[thirdparty/binutils-gdb.git] / sim / v850 / sim-main.h

#define WITH_CORE
#define WITH_MODULO_MEMORY 1
#define WITH_WATCHPOINTS 1
#define WITH_TARGET_WORD_MSB 31

#include "sim-basics.h"

#include <signal.h>
typedef address_word sim_cia;


/* This simulator doesn't cache state */
#define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
#define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)

/* Get the number of instructions.  FIXME: must be a more elegant way
   of doing this.  */
#include "itable.h"
#define MAX_INSNS (nr_itable_entries)
#define INSN_NAME(i) itable[(i)].name

#include "sim-base.h"

#include "simops.h"
#include "bfd.h"


typedef signed8 int8;
typedef unsigned8 uint8;
typedef signed16 int16;
typedef unsigned16 uint16;
typedef signed32 int32;
typedef unsigned32 uint32;
typedef unsigned32 reg_t;


/* The current state of the processor; registers, memory, etc.  */

typedef struct _v850_regs {
  reg_t regs[32];		/* general-purpose registers */
  reg_t sregs[32];		/* system registers, including psw */
  reg_t pc;
  int dummy_mem;		/* where invalid accesses go */
} v850_regs;

struct _sim_cpu
{
  /* ... simulator specific members ... */
  v850_regs reg;
  reg_t psw_mask;               /* only allow non-reserved bits to be set */
  sim_event *pending_nmi;
  /* ... base type ... */
  sim_cpu_base base;
};

#define CPU_CIA(CPU) ((CPU)->reg.pc)

struct sim_state {
  sim_cpu cpu[MAX_NR_PROCESSORS];
#if (WITH_SMP)
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
#else
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
#endif
#if 0
  SIM_ADDR rom_size;
  SIM_ADDR low_end;
  SIM_ADDR high_start;
  SIM_ADDR high_base;
  void *mem;
#endif
  sim_state_base base;
};

/* For compatibility, until all functions converted to passing
   SIM_DESC as an argument */
extern SIM_DESC simulator;


#define V850_ROM_SIZE 0x8000
#define V850_LOW_END 0x200000
#define V850_HIGH_START 0xffe000


#define SIG_V850_EXIT	-1	/* indication of a normal exit */


/* Because we are still using the old semantic table, provide compat
   macro's that store the instruction where the old simops expects
   it. */

extern uint32 OP[4];
#if 0
OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
OP[3] = inst;
#endif

#define SAVE_1 \
PC = cia; \
OP[0] = instruction_0 & 0x1f; \
OP[1] = (instruction_0 >> 11) & 0x1f; \
OP[2] = 0; \
OP[3] = instruction_0

#define COMPAT_1(CALL) \
SAVE_1; \
PC += (CALL); \
nia = PC

#define SAVE_2 \
PC = cia; \
OP[0] = instruction_0 & 0x1f; \
OP[1] = (instruction_0 >> 11) & 0x1f; \
OP[2] = instruction_1; \
OP[3] = (instruction_1 << 16) | instruction_0

#define COMPAT_2(CALL) \
SAVE_2; \
PC += (CALL); \
nia = PC


/* new */
#define GR  ((CPU)->reg.regs)
#define SR  ((CPU)->reg.sregs)

/* old */
#define State    (STATE_CPU (simulator, 0)->reg)
#define PC	(State.pc)
#define SP	(State.regs[3])
#define EP	(State.regs[30])

#define EIPC  (State.sregs[0])
#define EIPSW (State.sregs[1])
#define FEPC  (State.sregs[2])
#define FEPSW (State.sregs[3])
#define ECR   (State.sregs[4])
#define PSW   (State.sregs[5])
/* start-sanitize-v850e */
#define CTPC  (SR[16])
#define CTPSW (SR[17])
/* end-sanitize-v850e */
#define DBPC  (State.sregs[18])
#define DBPSW (State.sregs[19])
/* start-sanitize-v850e */
#define CTBP  (State.sregs[20])
/* end-sanitize-v850e */

/* start-sanitize-v850eq */
#define PSW_US BIT32 (8)
/* end-sanitize-v850eq */
#define PSW_NP 0x80
#define PSW_EP 0x40
#define PSW_ID 0x20
#define PSW_SAT 0x10
#define PSW_CY 0x8
#define PSW_OV 0x4
#define PSW_S 0x2
#define PSW_Z 0x1

#define SEXT3(x)	((((x)&0x7)^(~0x3))+0x4)	

/* sign-extend a 4-bit number */
#define SEXT4(x)	((((x)&0xf)^(~0x7))+0x8)	

/* sign-extend a 5-bit number */
#define SEXT5(x)	((((x)&0x1f)^(~0xf))+0x10)	

/* sign-extend a 9-bit number */
#define SEXT9(x)	((((x)&0x1ff)^(~0xff))+0x100)

/* sign-extend a 22-bit number */
#define SEXT22(x)	((((x)&0x3fffff)^(~0x1fffff))+0x200000)

/* sign extend a 40 bit number */
#define SEXT40(x)	((((x) & UNSIGNED64 (0xffffffffff)) \
			  ^ (~UNSIGNED64 (0x7fffffffff))) \
			 + UNSIGNED64 (0x8000000000))

/* sign extend a 44 bit number */
#define SEXT44(x)	((((x) & UNSIGNED64 (0xfffffffffff)) \
			  ^ (~ UNSIGNED64 (0x7ffffffffff))) \
			 + UNSIGNED64 (0x80000000000))

/* sign extend a 60 bit number */
#define SEXT60(x)	((((x) & UNSIGNED64 (0xfffffffffffffff)) \
			  ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
			 + UNSIGNED64 (0x800000000000000))

/* No sign extension */
#define NOP(x)		(x)

#define INC_ADDR(x,i)	x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))

#define RLW(x) load_mem (x, 4)

#ifdef _WIN32
#ifndef SIGTRAP
#define SIGTRAP 5
#endif
#ifndef SIGQUIT
#define SIGQUIT 3
#endif
#endif

/* Function declarations.  */

#define IMEM(EA) \
sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
			 PC, sim_core_execute_map, (EA))

#define IMEM_IMMED(EA,N) \
sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
			 PC, sim_core_execute_map, (EA) + (N) * 2)

#define load_mem(ADDR,LEN) \
sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
			       PC, sim_core_read_map, (ADDR))

#define store_mem(ADDR,LEN,DATA) \
sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
				PC, sim_core_write_map, (ADDR), (DATA))


/* compare cccc field against PSW */
int condition_met (unsigned code);


/* Debug/tracing calls */

enum op_types
{
  OP_UNKNOWN,
  OP_NONE,
  OP_TRAP,
  OP_REG,
  OP_REG_REG,
  OP_REG_REG_CMP,
  OP_REG_REG_MOVE,
  OP_IMM_REG,
  OP_IMM_REG_CMP,
  OP_IMM_REG_MOVE,
  OP_COND_BR,
  OP_LOAD16,
  OP_STORE16,
  OP_LOAD32,
  OP_STORE32,
  OP_JUMP,
  OP_IMM_REG_REG,
  OP_UIMM_REG_REG,
  OP_IMM16_REG_REG,
  OP_UIMM16_REG_REG,
  OP_BIT,
  OP_EX1,
  OP_EX2,
  OP_LDSR,
  OP_STSR,
/* start-sanitize-v850e */
  OP_BIT_CHANGE,
  OP_REG_REG_REG,
  OP_REG_REG3,
/* end-sanitize-v850e */
/* start-sanitize-v850eq */
  OP_IMM_REG_REG_REG,
  OP_PUSHPOP1,
  OP_PUSHPOP2,
  OP_PUSHPOP3,
/* end-sanitize-v850eq */
};

#ifdef DEBUG
void trace_input PARAMS ((char *name, enum op_types type, int size));
void trace_output PARAMS ((enum op_types result));
void trace_result PARAMS ((int has_result, unsigned32 result));

extern int trace_num_values;
extern unsigned32 trace_values[];
extern unsigned32 trace_pc;
extern const char *trace_name;
extern const char *trace_module;

#define TRACE_ALU_INPUT0() \
do { \
  if (TRACE_ALU_P (CPU)) { \
    trace_module = "alu"; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_num_values = 0; \
  } \
} while (0)

#define TRACE_ALU_INPUT1(IN1) \
do { \
  if (TRACE_ALU_P (CPU)) { \
    trace_module = "alu"; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_num_values = 1; \
  } \
} while (0)

#define TRACE_ALU_INPUT2(IN1, IN2) \
do { \
  if (TRACE_ALU_P (CPU)) { \
    trace_module = "alu"; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_values[1] = (IN2); \
    trace_num_values = 2; \
  } \
} while (0)

#define TRACE_ALU_INPUT3(IN0, IN1, IN2) \
do { \
  if (TRACE_ALU_P (CPU)) { \
    trace_module = "alu"; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN0); \
    trace_values[1] = (IN1); \
    trace_values[2] = (IN2); \
    trace_num_values = 3; \
  } \
} while (0)

#define TRACE_ALU_RESULT(RESULT) \
do { \
  if (TRACE_ALU_P (CPU)) { \
    trace_result (1, (RESULT)); \
  } \
} while (0)

#define TRACE_BRANCH0() \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = "branch"; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_num_values = 0; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_BRANCH1(IN1) \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = "branch"; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_num_values = 1; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_BRANCH2(IN1, IN2) \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = "branch"; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_values[1] = (IN2); \
    trace_num_values = 2; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_BRANCH3(IN1, IN2, IN3) \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = "branch"; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_values[1] = (IN2); \
    trace_values[2] = (IN3); \
    trace_num_values = 3; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_LD(ADDR,RESULT) \
do { \
  if (TRACE_MEMORY_P (CPU)) { \
    trace_module = "memory"; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (ADDR); \
    trace_num_values = 1; \
    trace_result (1, (RESULT)); \
  } \
} while (0)

/* start-sanitize-v850e */
#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
do { \
  if (TRACE_MEMORY_P (CPU)) { \
    trace_module = "memory"; \
    trace_pc = cia; \
    trace_name = (NAME); \
    trace_values[0] = (ADDR); \
    trace_num_values = 1; \
    trace_result (1, (RESULT)); \
  } \
} while (0)

/* end-sanitize-v850e */
#define TRACE_ST(ADDR,RESULT) \
do { \
  if (TRACE_MEMORY_P (CPU)) { \
    trace_module = "memory"; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (ADDR); \
    trace_num_values = 1; \
    trace_result (1, (RESULT)); \
  } \
} while (0)

#else
#define trace_input(NAME, IN1, IN2)
#define trace_output(RESULT)
#define trace_result(HAS_RESULT, RESULT)

#define TRACE_ALU_INPUT0()
#define TRACE_ALU_INPUT1(IN0)
#define TRACE_ALU_INPUT2(IN0, IN1)
#define TRACE_ALU_INPUT2(IN0, IN1)
#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
#define TRACE_ALU_RESULT(RESULT)

#define TRACE_BRANCH0()
#define TRACE_BRANCH1(IN1)
#define TRACE_BRANCH2(IN1, IN2)
#define TRACE_BRANCH2(IN1, IN2, IN3)

#define TRACE_LD(ADDR,RESULT)
#define TRACE_ST(ADDR,RESULT)

#endif


/* start-sanitize-v850eq */
extern void divun ( unsigned int       N,
		    unsigned long int  als,
		    unsigned long int  sfi,
		    unsigned long int *  quotient_ptr,
		    unsigned long int *  remainder_ptr,
		    boolean *          overflow_ptr
		    );
extern void divn ( unsigned int       N,
		   unsigned long int  als,
		   unsigned long int  sfi,
		   signed long int *  quotient_ptr,
		   signed long int *  remainder_ptr,
		   boolean *          overflow_ptr
		   );
/* end-sanitize-v850eq */
/* start-sanitize-v850e */
extern int type1_regs[];
extern int type2_regs[];
/* end-sanitize-v850e */
/* start-sanitize-v850eq */
extern int type3_regs[];
/* end-sanitize-v850eq */
Commit	Line	Data
93e7a1b5	1	#define WITH_CORE
5d37a07b AC	2	#define WITH_MODULO_MEMORY 1
	3	#define WITH_WATCHPOINTS 1
	4	#define WITH_TARGET_WORD_MSB 31
	5
cabedd58 AC	6	#include "sim-basics.h"
cabedd58 AC	7
410230cf	8	#include <signal.h>
cabedd58 AC	9	typedef address_word sim_cia;
cabedd58 AC	10
93e7a1b5	11
cabedd58 AC	12	/* This simulator doesn't cache state */
	13	#define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
	14	#define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)
	15
93e7a1b5 AC	16	/* Get the number of instructions. FIXME: must be a more elegant way
	17	of doing this. */
	18	#include "itable.h"
	19	#define MAX_INSNS (nr_itable_entries)
	20	#define INSN_NAME(i) itable[(i)].name
	21
cabedd58 AC	22	#include "sim-base.h"
cabedd58 AC	23
bda61639 AC	24	#include "simops.h"
	25	#include "bfd.h"
	26
	27
cabedd58 AC	28	typedef signed8 int8;
	29	typedef unsigned8 uint8;
	30	typedef signed16 int16;
	31	typedef unsigned16 uint16;
	32	typedef signed32 int32;
	33	typedef unsigned32 uint32;
	34	typedef unsigned32 reg_t;
	35
	36
	37	/* The current state of the processor; registers, memory, etc. */
	38
	39	typedef struct _v850_regs {
	40	reg_t regs[32]; /* general-purpose registers */
	41	reg_t sregs[32]; /* system registers, including psw */
	42	reg_t pc;
	43	int dummy_mem; /* where invalid accesses go */
cabedd58 AC	44	} v850_regs;
	45
	46	struct _sim_cpu
	47	{
	48	/* ... simulator specific members ... */
	49	v850_regs reg;
c7db488f	50	reg_t psw_mask; /* only allow non-reserved bits to be set */
a72f8fb4	51	sim_event *pending_nmi;
cabedd58 AC	52	/* ... base type ... */
	53	sim_cpu_base base;
	54	};
	55
5d37a07b AC	56	#define CPU_CIA(CPU) ((CPU)->reg.pc)
5d37a07b AC	57
cabedd58 AC	58	struct sim_state {
	59	sim_cpu cpu[MAX_NR_PROCESSORS];
	60	#if (WITH_SMP)
	61	#define STATE_CPU(sd,n) (&(sd)->cpu[n])
	62	#else
	63	#define STATE_CPU(sd,n) (&(sd)->cpu[0])
	64	#endif
da3a66e5	65	#if 0
cabedd58 AC	66	SIM_ADDR rom_size;
	67	SIM_ADDR low_end;
	68	SIM_ADDR high_start;
	69	SIM_ADDR high_base;
b5e935ae	70	void *mem;
da3a66e5	71	#endif
cabedd58 AC	72	sim_state_base base;
	73	};
	74
	75	/* For compatibility, until all functions converted to passing
	76	SIM_DESC as an argument */
	77	extern SIM_DESC simulator;
	78
	79
	80	#define V850_ROM_SIZE 0x8000
	81	#define V850_LOW_END 0x200000
	82	#define V850_HIGH_START 0xffe000
	83
	84
cabedd58 AC	85	#define SIG_V850_EXIT -1 /* indication of a normal exit */
cabedd58 AC	86
5d37a07b AC	87
	88	/* Because we are still using the old semantic table, provide compat
	89	macro's that store the instruction where the old simops expects
	90	it. */
	91
fb1fd475	92	extern uint32 OP[4];
5d37a07b	93	#if 0
bda61639 AC	94	OP[0] = inst & 0x1f; /* RRRRR -> reg1 */
bda61639 AC	95	OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */
fb1fd475	96	OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
5d37a07b AC	97	OP[3] = inst;
	98	#endif
	99
4dda50b0	100	#define SAVE_1 \
5d37a07b AC	101	PC = cia; \
	102	OP[0] = instruction_0 & 0x1f; \
	103	OP[1] = (instruction_0 >> 11) & 0x1f; \
	104	OP[2] = 0; \
4dda50b0 AC	105	OP[3] = instruction_0
	106
	107	#define COMPAT_1(CALL) \
	108	SAVE_1; \
5d37a07b AC	109	PC += (CALL); \
	110	nia = PC
	111
4dda50b0	112	#define SAVE_2 \
5d37a07b AC	113	PC = cia; \
	114	OP[0] = instruction_0 & 0x1f; \
	115	OP[1] = (instruction_0 >> 11) & 0x1f; \
	116	OP[2] = instruction_1; \
4dda50b0 AC	117	OP[3] = (instruction_1 << 16) \| instruction_0
	118
	119	#define COMPAT_2(CALL) \
	120	SAVE_2; \
5d37a07b AC	121	PC += (CALL); \
	122	nia = PC
	123
	124
fb1fd475 AC	125	/* new */
	126	#define GR ((CPU)->reg.regs)
	127	#define SR ((CPU)->reg.sregs)
cabedd58	128
fb1fd475	129	/* old */
cabedd58 AC	130	#define State (STATE_CPU (simulator, 0)->reg)
	131	#define PC (State.pc)
	132	#define SP (State.regs[3])
	133	#define EP (State.regs[30])
	134
	135	#define EIPC (State.sregs[0])
	136	#define EIPSW (State.sregs[1])
	137	#define FEPC (State.sregs[2])
	138	#define FEPSW (State.sregs[3])
	139	#define ECR (State.sregs[4])
	140	#define PSW (State.sregs[5])
	141	/* start-sanitize-v850e */
6aead89a AC	142	#define CTPC (SR[16])
6aead89a AC	143	#define CTPSW (SR[17])
cabedd58 AC	144	/* end-sanitize-v850e */
	145	#define DBPC (State.sregs[18])
	146	#define DBPSW (State.sregs[19])
	147	/* start-sanitize-v850e */
	148	#define CTBP (State.sregs[20])
	149	/* end-sanitize-v850e */
	150
658303f7 AC	151	/* start-sanitize-v850eq */
	152	#define PSW_US BIT32 (8)
	153	/* end-sanitize-v850eq */
cabedd58 AC	154	#define PSW_NP 0x80
	155	#define PSW_EP 0x40
	156	#define PSW_ID 0x20
	157	#define PSW_SAT 0x10
	158	#define PSW_CY 0x8
	159	#define PSW_OV 0x4
	160	#define PSW_S 0x2
	161	#define PSW_Z 0x1
	162
	163	#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
	164
	165	/* sign-extend a 4-bit number */
	166	#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
	167
	168	/* sign-extend a 5-bit number */
	169	#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
	170
cabedd58 AC	171	/* sign-extend a 9-bit number */
	172	#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
	173
cabedd58 AC	174	/* sign-extend a 22-bit number */
	175	#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
	176
cabedd58	177	/* sign extend a 40 bit number */
5d37a07b AC	178	#define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
	179	^ (~UNSIGNED64 (0x7fffffffff))) \
	180	+ UNSIGNED64 (0x8000000000))
cabedd58 AC	181
cabedd58 AC	182	/* sign extend a 44 bit number */
5d37a07b AC	183	#define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
	184	^ (~ UNSIGNED64 (0x7ffffffffff))) \
	185	+ UNSIGNED64 (0x80000000000))
cabedd58 AC	186
cabedd58 AC	187	/* sign extend a 60 bit number */
5d37a07b AC	188	#define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
	189	^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
	190	+ UNSIGNED64 (0x800000000000000))
cabedd58 AC	191
	192	/* No sign extension */
	193	#define NOP(x) (x)
	194
cabedd58 AC	195	#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
	196
	197	#define RLW(x) load_mem (x, 4)
	198
	199	#ifdef _WIN32
	200	#ifndef SIGTRAP
	201	#define SIGTRAP 5
	202	#endif
	203	#ifndef SIGQUIT
	204	#define SIGQUIT 3
	205	#endif
	206	#endif
	207
	208	/* Function declarations. */
	209
da3a66e5 AC	210	#define IMEM(EA) \
	211	sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
	212	PC, sim_core_execute_map, (EA))
	213
	214	#define IMEM_IMMED(EA,N) \
	215	sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
5d37a07b	216	PC, sim_core_execute_map, (EA) + (N) * 2)
cabedd58	217
da3a66e5 AC	218	#define load_mem(ADDR,LEN) \
	219	sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
	220	PC, sim_core_read_map, (ADDR))
cabedd58	221
da3a66e5 AC	222	#define store_mem(ADDR,LEN,DATA) \
	223	sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
	224	PC, sim_core_write_map, (ADDR), (DATA))
5d37a07b	225
658303f7	226
60fe0e06	227	/* compare cccc field against PSW */
bd4c35cc	228	int condition_met (unsigned code);
60fe0e06 AC	229
60fe0e06 AC	230
658303f7 AC	231	/* Debug/tracing calls */
	232
	233	enum op_types
	234	{
	235	OP_UNKNOWN,
	236	OP_NONE,
	237	OP_TRAP,
	238	OP_REG,
	239	OP_REG_REG,
	240	OP_REG_REG_CMP,
	241	OP_REG_REG_MOVE,
	242	OP_IMM_REG,
	243	OP_IMM_REG_CMP,
	244	OP_IMM_REG_MOVE,
	245	OP_COND_BR,
	246	OP_LOAD16,
	247	OP_STORE16,
	248	OP_LOAD32,
	249	OP_STORE32,
	250	OP_JUMP,
	251	OP_IMM_REG_REG,
	252	OP_UIMM_REG_REG,
fb1fd475 AC	253	OP_IMM16_REG_REG,
fb1fd475 AC	254	OP_UIMM16_REG_REG,
658303f7 AC	255	OP_BIT,
	256	OP_EX1,
	257	OP_EX2,
	258	OP_LDSR,
	259	OP_STSR,
	260	/* start-sanitize-v850e */
	261	OP_BIT_CHANGE,
	262	OP_REG_REG_REG,
	263	OP_REG_REG3,
	264	/* end-sanitize-v850e */
	265	/* start-sanitize-v850eq */
	266	OP_IMM_REG_REG_REG,
	267	OP_PUSHPOP1,
	268	OP_PUSHPOP2,
	269	OP_PUSHPOP3,
	270	/* end-sanitize-v850eq */
	271	};
	272
	273	#ifdef DEBUG
	274	void trace_input PARAMS ((char *name, enum op_types type, int size));
	275	void trace_output PARAMS ((enum op_types result));
fb1fd475 AC	276	void trace_result PARAMS ((int has_result, unsigned32 result));
	277
	278	extern int trace_num_values;
	279	extern unsigned32 trace_values[];
	280	extern unsigned32 trace_pc;
	281	extern const char *trace_name;
6aead89a	282	extern const char *trace_module;
fb1fd475 AC	283
	284	#define TRACE_ALU_INPUT0() \
	285	do { \
	286	if (TRACE_ALU_P (CPU)) { \
6aead89a AC	287	trace_module = "alu"; \
6aead89a AC	288	trace_pc = cia; \
fb1fd475 AC	289	trace_name = itable[MY_INDEX].name; \
	290	trace_num_values = 0; \
	291	} \
	292	} while (0)
	293
	294	#define TRACE_ALU_INPUT1(IN1) \
	295	do { \
	296	if (TRACE_ALU_P (CPU)) { \
6aead89a AC	297	trace_module = "alu"; \
6aead89a AC	298	trace_pc = cia; \
fb1fd475 AC	299	trace_name = itable[MY_INDEX].name; \
	300	trace_values[0] = (IN1); \
	301	trace_num_values = 1; \
	302	} \
	303	} while (0)
	304
	305	#define TRACE_ALU_INPUT2(IN1, IN2) \
	306	do { \
	307	if (TRACE_ALU_P (CPU)) { \
6aead89a AC	308	trace_module = "alu"; \
6aead89a AC	309	trace_pc = cia; \
fb1fd475 AC	310	trace_name = itable[MY_INDEX].name; \
	311	trace_values[0] = (IN1); \
	312	trace_values[1] = (IN2); \
	313	trace_num_values = 2; \
	314	} \
	315	} while (0)
	316
60fe0e06 AC	317	#define TRACE_ALU_INPUT3(IN0, IN1, IN2) \
	318	do { \
	319	if (TRACE_ALU_P (CPU)) { \
	320	trace_module = "alu"; \
	321	trace_pc = cia; \
	322	trace_name = itable[MY_INDEX].name; \
	323	trace_values[0] = (IN0); \
	324	trace_values[1] = (IN1); \
	325	trace_values[2] = (IN2); \
	326	trace_num_values = 3; \
	327	} \
	328	} while (0)
	329
fb1fd475 AC	330	#define TRACE_ALU_RESULT(RESULT) \
	331	do { \
	332	if (TRACE_ALU_P (CPU)) { \
	333	trace_result (1, (RESULT)); \
	334	} \
	335	} while (0)
	336
bd4c35cc AC	337	#define TRACE_BRANCH0() \
	338	do { \
	339	if (TRACE_BRANCH_P (CPU)) { \
	340	trace_module = "branch"; \
	341	trace_pc = cia; \
	342	trace_name = itable[MY_INDEX].name; \
	343	trace_num_values = 0; \
	344	trace_result (1, (nia)); \
	345	} \
	346	} while (0)
	347
6aead89a AC	348	#define TRACE_BRANCH1(IN1) \
	349	do { \
	350	if (TRACE_BRANCH_P (CPU)) { \
	351	trace_module = "branch"; \
	352	trace_pc = cia; \
	353	trace_name = itable[MY_INDEX].name; \
	354	trace_values[0] = (IN1); \
	355	trace_num_values = 1; \
	356	trace_result (1, (nia)); \
	357	} \
	358	} while (0)
	359
	360	#define TRACE_BRANCH2(IN1, IN2) \
	361	do { \
	362	if (TRACE_BRANCH_P (CPU)) { \
	363	trace_module = "branch"; \
	364	trace_pc = cia; \
	365	trace_name = itable[MY_INDEX].name; \
	366	trace_values[0] = (IN1); \
	367	trace_values[1] = (IN2); \
	368	trace_num_values = 2; \
	369	trace_result (1, (nia)); \
	370	} \
	371	} while (0)
	372
	373	#define TRACE_BRANCH3(IN1, IN2, IN3) \
	374	do { \
	375	if (TRACE_BRANCH_P (CPU)) { \
	376	trace_module = "branch"; \
	377	trace_pc = cia; \
	378	trace_name = itable[MY_INDEX].name; \
	379	trace_values[0] = (IN1); \
	380	trace_values[1] = (IN2); \
	381	trace_values[2] = (IN3); \
	382	trace_num_values = 3; \
	383	trace_result (1, (nia)); \
	384	} \
	385	} while (0)
	386
a276b6f0 AC	387	#define TRACE_LD(ADDR,RESULT) \
	388	do { \
	389	if (TRACE_MEMORY_P (CPU)) { \
	390	trace_module = "memory"; \
	391	trace_pc = cia; \
	392	trace_name = itable[MY_INDEX].name; \
	393	trace_values[0] = (ADDR); \
	394	trace_num_values = 1; \
	395	trace_result (1, (RESULT)); \
	396	} \
	397	} while (0)
	398
	399	/* start-sanitize-v850e */
	400	#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
	401	do { \
	402	if (TRACE_MEMORY_P (CPU)) { \
	403	trace_module = "memory"; \
	404	trace_pc = cia; \
	405	trace_name = (NAME); \
	406	trace_values[0] = (ADDR); \
	407	trace_num_values = 1; \
	408	trace_result (1, (RESULT)); \
	409	} \
	410	} while (0)
	411
	412	/* end-sanitize-v850e */
	413	#define TRACE_ST(ADDR,RESULT) \
	414	do { \
	415	if (TRACE_MEMORY_P (CPU)) { \
	416	trace_module = "memory"; \
	417	trace_pc = cia; \
	418	trace_name = itable[MY_INDEX].name; \
	419	trace_values[0] = (ADDR); \
	420	trace_num_values = 1; \
	421	trace_result (1, (RESULT)); \
	422	} \
	423	} while (0)
fb1fd475	424
658303f7 AC	425	#else
	426	#define trace_input(NAME, IN1, IN2)
	427	#define trace_output(RESULT)
fb1fd475 AC	428	#define trace_result(HAS_RESULT, RESULT)
	429
	430	#define TRACE_ALU_INPUT0()
bd4c35cc AC	431	#define TRACE_ALU_INPUT1(IN0)
	432	#define TRACE_ALU_INPUT2(IN0, IN1)
	433	#define TRACE_ALU_INPUT2(IN0, IN1)
	434	#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
fb1fd475	435	#define TRACE_ALU_RESULT(RESULT)
6aead89a	436
bd4c35cc	437	#define TRACE_BRANCH0()
6aead89a AC	438	#define TRACE_BRANCH1(IN1)
	439	#define TRACE_BRANCH2(IN1, IN2)
	440	#define TRACE_BRANCH2(IN1, IN2, IN3)
a276b6f0 AC	441
	442	#define TRACE_LD(ADDR,RESULT)
	443	#define TRACE_ST(ADDR,RESULT)
	444
658303f7 AC	445	#endif
658303f7 AC	446
bda61639 AC	447
	448	/* start-sanitize-v850eq */
	449	extern void divun ( unsigned int N,
	450	unsigned long int als,
	451	unsigned long int sfi,
	452	unsigned long int * quotient_ptr,
	453	unsigned long int * remainder_ptr,
	454	boolean * overflow_ptr
	455	);
	456	extern void divn ( unsigned int N,
	457	unsigned long int als,
	458	unsigned long int sfi,
	459	signed long int * quotient_ptr,
	460	signed long int * remainder_ptr,
	461	boolean * overflow_ptr
	462	);
	463	/* end-sanitize-v850eq */
	464	/* start-sanitize-v850e */
	465	extern int type1_regs[];
	466	extern int type2_regs[];
	467	/* end-sanitize-v850e */
	468	/* start-sanitize-v850eq */
	469	extern int type3_regs[];
	470	/* end-sanitize-v850eq */