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[PATCH] gas: arm: Fix IT-predicated MVE vcvt
[thirdparty/binutils-gdb.git] / gas / config / tc-arm.c
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1/* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
8
9 This file is part of GAS, the GNU Assembler.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
25
26#include "as.h"
27#include <limits.h>
28#include <stdarg.h>
29#define NO_RELOC 0
30#include "safe-ctype.h"
31#include "subsegs.h"
32#include "obstack.h"
33#include "libiberty.h"
34#include "opcode/arm.h"
35#include "cpu-arm.h"
36
37#ifdef OBJ_ELF
38#include "elf/arm.h"
39#include "dw2gencfi.h"
40#endif
41
42#include "dwarf2dbg.h"
43
44#ifdef OBJ_ELF
45/* Must be at least the size of the largest unwind opcode (currently two). */
46#define ARM_OPCODE_CHUNK_SIZE 8
47
48/* This structure holds the unwinding state. */
49
50static struct
51{
52 symbolS * proc_start;
53 symbolS * table_entry;
54 symbolS * personality_routine;
55 int personality_index;
56 /* The segment containing the function. */
57 segT saved_seg;
58 subsegT saved_subseg;
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes;
61 int opcode_count;
62 int opcode_alloc;
63 /* The number of bytes pushed to the stack. */
64 offsetT frame_size;
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
71 offsetT fp_offset;
72 int fp_reg;
73 /* Nonzero if an unwind_setfp directive has been seen. */
74 unsigned fp_used:1;
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored:1;
77} unwind;
78
79/* Whether --fdpic was given. */
80static int arm_fdpic;
81
82#endif /* OBJ_ELF */
83
84/* Results from operand parsing worker functions. */
85
86typedef enum
87{
88 PARSE_OPERAND_SUCCESS,
89 PARSE_OPERAND_FAIL,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91} parse_operand_result;
92
93enum arm_float_abi
94{
95 ARM_FLOAT_ABI_HARD,
96 ARM_FLOAT_ABI_SOFTFP,
97 ARM_FLOAT_ABI_SOFT
98};
99
100/* Types of processor to assemble for. */
101#ifndef CPU_DEFAULT
102/* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
105
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
108#endif
109
110/* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112static bfd_boolean out_of_range_p (offsetT value, offsetT bits)
113 {
114 gas_assert (bits < (offsetT)(sizeof (value) * 8));
115 return (value & ~((1 << bits)-1))
116 && ((value & ~((1 << bits)-1)) != ~((1 << bits)-1));
117}
118
119#ifndef FPU_DEFAULT
120# ifdef TE_LINUX
121# define FPU_DEFAULT FPU_ARCH_FPA
122# elif defined (TE_NetBSD)
123# ifdef OBJ_ELF
124# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
125# else
126 /* Legacy a.out format. */
127# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
128# endif
129# elif defined (TE_VXWORKS)
130# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
131# else
132 /* For backwards compatibility, default to FPA. */
133# define FPU_DEFAULT FPU_ARCH_FPA
134# endif
135#endif /* ifndef FPU_DEFAULT */
136
137#define streq(a, b) (strcmp (a, b) == 0)
138
139/* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142static arm_feature_set cpu_variant;
143/* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145static arm_feature_set arm_arch_used;
146static arm_feature_set thumb_arch_used;
147
148/* Flags stored in private area of BFD structure. */
149static int uses_apcs_26 = FALSE;
150static int atpcs = FALSE;
151static int support_interwork = FALSE;
152static int uses_apcs_float = FALSE;
153static int pic_code = FALSE;
154static int fix_v4bx = FALSE;
155/* Warn on using deprecated features. */
156static int warn_on_deprecated = TRUE;
157static int warn_on_restrict_it = FALSE;
158
159/* Understand CodeComposer Studio assembly syntax. */
160bfd_boolean codecomposer_syntax = FALSE;
161
162/* Variables that we set while parsing command-line options. Once all
163 options have been read we re-process these values to set the real
164 assembly flags. */
165
166/* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167 instead of -mcpu=arm1). */
168static const arm_feature_set *legacy_cpu = NULL;
169static const arm_feature_set *legacy_fpu = NULL;
170
171/* CPU, extension and FPU feature bits selected by -mcpu. */
172static const arm_feature_set *mcpu_cpu_opt = NULL;
173static arm_feature_set *mcpu_ext_opt = NULL;
174static const arm_feature_set *mcpu_fpu_opt = NULL;
175
176/* CPU, extension and FPU feature bits selected by -march. */
177static const arm_feature_set *march_cpu_opt = NULL;
178static arm_feature_set *march_ext_opt = NULL;
179static const arm_feature_set *march_fpu_opt = NULL;
180
181/* Feature bits selected by -mfpu. */
182static const arm_feature_set *mfpu_opt = NULL;
183
184/* Constants for known architecture features. */
185static const arm_feature_set fpu_default = FPU_DEFAULT;
186static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
187static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
188static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
189static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
190static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
191static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
192#ifdef OBJ_ELF
193static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
194#endif
195static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
196
197#ifdef CPU_DEFAULT
198static const arm_feature_set cpu_default = CPU_DEFAULT;
199#endif
200
201static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
202static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
203static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
204static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
205static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
206static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
207static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
208static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
209static const arm_feature_set arm_ext_v4t_5 =
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
211static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
212static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
213static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
214static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
215static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
216static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
217static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
218/* Only for compatability of hint instructions. */
219static const arm_feature_set arm_ext_v6k_v6t2 =
220 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2);
221static const arm_feature_set arm_ext_v6_notm =
222 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
223static const arm_feature_set arm_ext_v6_dsp =
224 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
225static const arm_feature_set arm_ext_barrier =
226 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
227static const arm_feature_set arm_ext_msr =
228 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
229static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
230static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
231static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
232static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
233static const arm_feature_set arm_ext_v8r = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R);
234#ifdef OBJ_ELF
235static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
236#endif
237static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
238static const arm_feature_set arm_ext_m =
239 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
240 ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
241static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
242static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
243static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
244static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
245static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
246static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
247static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
248static const arm_feature_set arm_ext_v8m_main =
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
250static const arm_feature_set arm_ext_v8_1m_main =
251ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
252/* Instructions in ARMv8-M only found in M profile architectures. */
253static const arm_feature_set arm_ext_v8m_m_only =
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
255static const arm_feature_set arm_ext_v6t2_v8m =
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
257/* Instructions shared between ARMv8-A and ARMv8-M. */
258static const arm_feature_set arm_ext_atomics =
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
260#ifdef OBJ_ELF
261/* DSP instructions Tag_DSP_extension refers to. */
262static const arm_feature_set arm_ext_dsp =
263 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
264#endif
265static const arm_feature_set arm_ext_ras =
266 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
267/* FP16 instructions. */
268static const arm_feature_set arm_ext_fp16 =
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
270static const arm_feature_set arm_ext_fp16_fml =
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
272static const arm_feature_set arm_ext_v8_2 =
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
274static const arm_feature_set arm_ext_v8_3 =
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
276static const arm_feature_set arm_ext_sb =
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
278static const arm_feature_set arm_ext_predres =
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
280static const arm_feature_set arm_ext_bf16 =
281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16);
282static const arm_feature_set arm_ext_i8mm =
283 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM);
284static const arm_feature_set arm_ext_crc =
285 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC);
286static const arm_feature_set arm_ext_cde =
287 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE);
288static const arm_feature_set arm_ext_cde0 =
289 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0);
290static const arm_feature_set arm_ext_cde1 =
291 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1);
292static const arm_feature_set arm_ext_cde2 =
293 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2);
294static const arm_feature_set arm_ext_cde3 =
295 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3);
296static const arm_feature_set arm_ext_cde4 =
297 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4);
298static const arm_feature_set arm_ext_cde5 =
299 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5);
300static const arm_feature_set arm_ext_cde6 =
301 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6);
302static const arm_feature_set arm_ext_cde7 =
303 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7);
304
305static const arm_feature_set arm_arch_any = ARM_ANY;
306static const arm_feature_set fpu_any = FPU_ANY;
307static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
308static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
309static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
310
311static const arm_feature_set arm_cext_iwmmxt2 =
312 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
313static const arm_feature_set arm_cext_iwmmxt =
314 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
315static const arm_feature_set arm_cext_xscale =
316 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
317static const arm_feature_set arm_cext_maverick =
318 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
319static const arm_feature_set fpu_fpa_ext_v1 =
320 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
321static const arm_feature_set fpu_fpa_ext_v2 =
322 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
323static const arm_feature_set fpu_vfp_ext_v1xd =
324 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
325static const arm_feature_set fpu_vfp_ext_v1 =
326 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
327static const arm_feature_set fpu_vfp_ext_v2 =
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
329static const arm_feature_set fpu_vfp_ext_v3xd =
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
331static const arm_feature_set fpu_vfp_ext_v3 =
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
333static const arm_feature_set fpu_vfp_ext_d32 =
334 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
335static const arm_feature_set fpu_neon_ext_v1 =
336 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
337static const arm_feature_set fpu_vfp_v3_or_neon_ext =
338 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
339static const arm_feature_set mve_ext =
340 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE);
341static const arm_feature_set mve_fp_ext =
342 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP);
343/* Note: This has more than one bit set, which means using it with
344 mark_feature_used (which returns if *any* of the bits are set in the current
345 cpu variant) can give surprising results. */
346static const arm_feature_set armv8m_fp =
347 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16);
348#ifdef OBJ_ELF
349static const arm_feature_set fpu_vfp_fp16 =
350 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
351static const arm_feature_set fpu_neon_ext_fma =
352 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
353#endif
354static const arm_feature_set fpu_vfp_ext_fma =
355 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
356static const arm_feature_set fpu_vfp_ext_armv8 =
357 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
358static const arm_feature_set fpu_vfp_ext_armv8xd =
359 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
360static const arm_feature_set fpu_neon_ext_armv8 =
361 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
362static const arm_feature_set fpu_crypto_ext_armv8 =
363 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
364static const arm_feature_set fpu_neon_ext_v8_1 =
365 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
366static const arm_feature_set fpu_neon_ext_dotprod =
367 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
368
369static int mfloat_abi_opt = -1;
370/* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
371 directive. */
372static arm_feature_set selected_arch = ARM_ARCH_NONE;
373/* Extension feature bits selected by the last -mcpu/-march or .arch_extension
374 directive. */
375static arm_feature_set selected_ext = ARM_ARCH_NONE;
376/* Feature bits selected by the last -mcpu/-march or by the combination of the
377 last .cpu/.arch directive .arch_extension directives since that
378 directive. */
379static arm_feature_set selected_cpu = ARM_ARCH_NONE;
380/* FPU feature bits selected by the last -mfpu or .fpu directive. */
381static arm_feature_set selected_fpu = FPU_NONE;
382/* Feature bits selected by the last .object_arch directive. */
383static arm_feature_set selected_object_arch = ARM_ARCH_NONE;
384/* Must be long enough to hold any of the names in arm_cpus. */
385static const struct arm_ext_table * selected_ctx_ext_table = NULL;
386static char selected_cpu_name[20];
387
388extern FLONUM_TYPE generic_floating_point_number;
389
390/* Return if no cpu was selected on command-line. */
391static bfd_boolean
392no_cpu_selected (void)
393{
394 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
395}
396
397#ifdef OBJ_ELF
398# ifdef EABI_DEFAULT
399static int meabi_flags = EABI_DEFAULT;
400# else
401static int meabi_flags = EF_ARM_EABI_UNKNOWN;
402# endif
403
404static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
405
406bfd_boolean
407arm_is_eabi (void)
408{
409 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
410}
411#endif
412
413#ifdef OBJ_ELF
414/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
415symbolS * GOT_symbol;
416#endif
417
418/* 0: assemble for ARM,
419 1: assemble for Thumb,
420 2: assemble for Thumb even though target CPU does not support thumb
421 instructions. */
422static int thumb_mode = 0;
423/* A value distinct from the possible values for thumb_mode that we
424 can use to record whether thumb_mode has been copied into the
425 tc_frag_data field of a frag. */
426#define MODE_RECORDED (1 << 4)
427
428/* Specifies the intrinsic IT insn behavior mode. */
429enum implicit_it_mode
430{
431 IMPLICIT_IT_MODE_NEVER = 0x00,
432 IMPLICIT_IT_MODE_ARM = 0x01,
433 IMPLICIT_IT_MODE_THUMB = 0x02,
434 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
435};
436static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
437
438/* If unified_syntax is true, we are processing the new unified
439 ARM/Thumb syntax. Important differences from the old ARM mode:
440
441 - Immediate operands do not require a # prefix.
442 - Conditional affixes always appear at the end of the
443 instruction. (For backward compatibility, those instructions
444 that formerly had them in the middle, continue to accept them
445 there.)
446 - The IT instruction may appear, and if it does is validated
447 against subsequent conditional affixes. It does not generate
448 machine code.
449
450 Important differences from the old Thumb mode:
451
452 - Immediate operands do not require a # prefix.
453 - Most of the V6T2 instructions are only available in unified mode.
454 - The .N and .W suffixes are recognized and honored (it is an error
455 if they cannot be honored).
456 - All instructions set the flags if and only if they have an 's' affix.
457 - Conditional affixes may be used. They are validated against
458 preceding IT instructions. Unlike ARM mode, you cannot use a
459 conditional affix except in the scope of an IT instruction. */
460
461static bfd_boolean unified_syntax = FALSE;
462
463/* An immediate operand can start with #, and ld*, st*, pld operands
464 can contain [ and ]. We need to tell APP not to elide whitespace
465 before a [, which can appear as the first operand for pld.
466 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
467const char arm_symbol_chars[] = "#[]{}";
468
469enum neon_el_type
470{
471 NT_invtype,
472 NT_untyped,
473 NT_integer,
474 NT_float,
475 NT_poly,
476 NT_signed,
477 NT_bfloat,
478 NT_unsigned
479};
480
481struct neon_type_el
482{
483 enum neon_el_type type;
484 unsigned size;
485};
486
487#define NEON_MAX_TYPE_ELS 5
488
489struct neon_type
490{
491 struct neon_type_el el[NEON_MAX_TYPE_ELS];
492 unsigned elems;
493};
494
495enum pred_instruction_type
496{
497 OUTSIDE_PRED_INSN,
498 INSIDE_VPT_INSN,
499 INSIDE_IT_INSN,
500 INSIDE_IT_LAST_INSN,
501 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
502 if inside, should be the last one. */
503 NEUTRAL_IT_INSN, /* This could be either inside or outside,
504 i.e. BKPT and NOP. */
505 IT_INSN, /* The IT insn has been parsed. */
506 VPT_INSN, /* The VPT/VPST insn has been parsed. */
507 MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
508 a predication code. */
509 MVE_UNPREDICABLE_INSN, /* MVE instruction that is non-predicable. */
510};
511
512/* The maximum number of operands we need. */
513#define ARM_IT_MAX_OPERANDS 6
514#define ARM_IT_MAX_RELOCS 3
515
516struct arm_it
517{
518 const char * error;
519 unsigned long instruction;
520 int size;
521 int size_req;
522 int cond;
523 /* "uncond_value" is set to the value in place of the conditional field in
524 unconditional versions of the instruction, or -1 if nothing is
525 appropriate. */
526 int uncond_value;
527 struct neon_type vectype;
528 /* This does not indicate an actual NEON instruction, only that
529 the mnemonic accepts neon-style type suffixes. */
530 int is_neon;
531 /* Set to the opcode if the instruction needs relaxation.
532 Zero if the instruction is not relaxed. */
533 unsigned long relax;
534 struct
535 {
536 bfd_reloc_code_real_type type;
537 expressionS exp;
538 int pc_rel;
539 } relocs[ARM_IT_MAX_RELOCS];
540
541 enum pred_instruction_type pred_insn_type;
542
543 struct
544 {
545 unsigned reg;
546 signed int imm;
547 struct neon_type_el vectype;
548 unsigned present : 1; /* Operand present. */
549 unsigned isreg : 1; /* Operand was a register. */
550 unsigned immisreg : 2; /* .imm field is a second register.
551 0: imm, 1: gpr, 2: MVE Q-register. */
552 unsigned isscalar : 2; /* Operand is a (SIMD) scalar:
553 0) not scalar,
554 1) Neon scalar,
555 2) MVE scalar. */
556 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
557 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
558 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
559 instructions. This allows us to disambiguate ARM <-> vector insns. */
560 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
561 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
562 unsigned isquad : 1; /* Operand is SIMD quad register. */
563 unsigned issingle : 1; /* Operand is VFP single-precision register. */
564 unsigned iszr : 1; /* Operand is ZR register. */
565 unsigned hasreloc : 1; /* Operand has relocation suffix. */
566 unsigned writeback : 1; /* Operand has trailing ! */
567 unsigned preind : 1; /* Preindexed address. */
568 unsigned postind : 1; /* Postindexed address. */
569 unsigned negative : 1; /* Index register was negated. */
570 unsigned shifted : 1; /* Shift applied to operation. */
571 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
572 } operands[ARM_IT_MAX_OPERANDS];
573};
574
575static struct arm_it inst;
576
577#define NUM_FLOAT_VALS 8
578
579const char * fp_const[] =
580{
581 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
582};
583
584LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
585
586#define FAIL (-1)
587#define SUCCESS (0)
588
589#define SUFF_S 1
590#define SUFF_D 2
591#define SUFF_E 3
592#define SUFF_P 4
593
594#define CP_T_X 0x00008000
595#define CP_T_Y 0x00400000
596
597#define CONDS_BIT 0x00100000
598#define LOAD_BIT 0x00100000
599
600#define DOUBLE_LOAD_FLAG 0x00000001
601
602struct asm_cond
603{
604 const char * template_name;
605 unsigned long value;
606};
607
608#define COND_ALWAYS 0xE
609
610struct asm_psr
611{
612 const char * template_name;
613 unsigned long field;
614};
615
616struct asm_barrier_opt
617{
618 const char * template_name;
619 unsigned long value;
620 const arm_feature_set arch;
621};
622
623/* The bit that distinguishes CPSR and SPSR. */
624#define SPSR_BIT (1 << 22)
625
626/* The individual PSR flag bits. */
627#define PSR_c (1 << 16)
628#define PSR_x (1 << 17)
629#define PSR_s (1 << 18)
630#define PSR_f (1 << 19)
631
632struct reloc_entry
633{
634 const char * name;
635 bfd_reloc_code_real_type reloc;
636};
637
638enum vfp_reg_pos
639{
640 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
641 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
642};
643
644enum vfp_ldstm_type
645{
646 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
647};
648
649/* Bits for DEFINED field in neon_typed_alias. */
650#define NTA_HASTYPE 1
651#define NTA_HASINDEX 2
652
653struct neon_typed_alias
654{
655 unsigned char defined;
656 unsigned char index;
657 struct neon_type_el eltype;
658};
659
660/* ARM register categories. This includes coprocessor numbers and various
661 architecture extensions' registers. Each entry should have an error message
662 in reg_expected_msgs below. */
663enum arm_reg_type
664{
665 REG_TYPE_RN,
666 REG_TYPE_CP,
667 REG_TYPE_CN,
668 REG_TYPE_FN,
669 REG_TYPE_VFS,
670 REG_TYPE_VFD,
671 REG_TYPE_NQ,
672 REG_TYPE_VFSD,
673 REG_TYPE_NDQ,
674 REG_TYPE_NSD,
675 REG_TYPE_NSDQ,
676 REG_TYPE_VFC,
677 REG_TYPE_MVF,
678 REG_TYPE_MVD,
679 REG_TYPE_MVFX,
680 REG_TYPE_MVDX,
681 REG_TYPE_MVAX,
682 REG_TYPE_MQ,
683 REG_TYPE_DSPSC,
684 REG_TYPE_MMXWR,
685 REG_TYPE_MMXWC,
686 REG_TYPE_MMXWCG,
687 REG_TYPE_XSCALE,
688 REG_TYPE_RNB,
689 REG_TYPE_ZR
690};
691
692/* Structure for a hash table entry for a register.
693 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
694 information which states whether a vector type or index is specified (for a
695 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
696struct reg_entry
697{
698 const char * name;
699 unsigned int number;
700 unsigned char type;
701 unsigned char builtin;
702 struct neon_typed_alias * neon;
703};
704
705/* Diagnostics used when we don't get a register of the expected type. */
706const char * const reg_expected_msgs[] =
707{
708 [REG_TYPE_RN] = N_("ARM register expected"),
709 [REG_TYPE_CP] = N_("bad or missing co-processor number"),
710 [REG_TYPE_CN] = N_("co-processor register expected"),
711 [REG_TYPE_FN] = N_("FPA register expected"),
712 [REG_TYPE_VFS] = N_("VFP single precision register expected"),
713 [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"),
714 [REG_TYPE_NQ] = N_("Neon quad precision register expected"),
715 [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"),
716 [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"),
717 [REG_TYPE_NSD] = N_("Neon single or double precision register expected"),
718 [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register"
719 " expected"),
720 [REG_TYPE_VFC] = N_("VFP system register expected"),
721 [REG_TYPE_MVF] = N_("Maverick MVF register expected"),
722 [REG_TYPE_MVD] = N_("Maverick MVD register expected"),
723 [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"),
724 [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"),
725 [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"),
726 [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"),
727 [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"),
728 [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"),
729 [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
730 [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
731 [REG_TYPE_MQ] = N_("MVE vector register expected"),
732 [REG_TYPE_RNB] = ""
733};
734
735/* Some well known registers that we refer to directly elsewhere. */
736#define REG_R12 12
737#define REG_SP 13
738#define REG_LR 14
739#define REG_PC 15
740
741/* ARM instructions take 4bytes in the object file, Thumb instructions
742 take 2: */
743#define INSN_SIZE 4
744
745struct asm_opcode
746{
747 /* Basic string to match. */
748 const char * template_name;
749
750 /* Parameters to instruction. */
751 unsigned int operands[8];
752
753 /* Conditional tag - see opcode_lookup. */
754 unsigned int tag : 4;
755
756 /* Basic instruction code. */
757 unsigned int avalue;
758
759 /* Thumb-format instruction code. */
760 unsigned int tvalue;
761
762 /* Which architecture variant provides this instruction. */
763 const arm_feature_set * avariant;
764 const arm_feature_set * tvariant;
765
766 /* Function to call to encode instruction in ARM format. */
767 void (* aencode) (void);
768
769 /* Function to call to encode instruction in Thumb format. */
770 void (* tencode) (void);
771
772 /* Indicates whether this instruction may be vector predicated. */
773 unsigned int mayBeVecPred : 1;
774};
775
776/* Defines for various bits that we will want to toggle. */
777#define INST_IMMEDIATE 0x02000000
778#define OFFSET_REG 0x02000000
779#define HWOFFSET_IMM 0x00400000
780#define SHIFT_BY_REG 0x00000010
781#define PRE_INDEX 0x01000000
782#define INDEX_UP 0x00800000
783#define WRITE_BACK 0x00200000
784#define LDM_TYPE_2_OR_3 0x00400000
785#define CPSI_MMOD 0x00020000
786
787#define LITERAL_MASK 0xf000f000
788#define OPCODE_MASK 0xfe1fffff
789#define V4_STR_BIT 0x00000020
790#define VLDR_VMOV_SAME 0x0040f000
791
792#define T2_SUBS_PC_LR 0xf3de8f00
793
794#define DATA_OP_SHIFT 21
795#define SBIT_SHIFT 20
796
797#define T2_OPCODE_MASK 0xfe1fffff
798#define T2_DATA_OP_SHIFT 21
799#define T2_SBIT_SHIFT 20
800
801#define A_COND_MASK 0xf0000000
802#define A_PUSH_POP_OP_MASK 0x0fff0000
803
804/* Opcodes for pushing/poping registers to/from the stack. */
805#define A1_OPCODE_PUSH 0x092d0000
806#define A2_OPCODE_PUSH 0x052d0004
807#define A2_OPCODE_POP 0x049d0004
808
809/* Codes to distinguish the arithmetic instructions. */
810#define OPCODE_AND 0
811#define OPCODE_EOR 1
812#define OPCODE_SUB 2
813#define OPCODE_RSB 3
814#define OPCODE_ADD 4
815#define OPCODE_ADC 5
816#define OPCODE_SBC 6
817#define OPCODE_RSC 7
818#define OPCODE_TST 8
819#define OPCODE_TEQ 9
820#define OPCODE_CMP 10
821#define OPCODE_CMN 11
822#define OPCODE_ORR 12
823#define OPCODE_MOV 13
824#define OPCODE_BIC 14
825#define OPCODE_MVN 15
826
827#define T2_OPCODE_AND 0
828#define T2_OPCODE_BIC 1
829#define T2_OPCODE_ORR 2
830#define T2_OPCODE_ORN 3
831#define T2_OPCODE_EOR 4
832#define T2_OPCODE_ADD 8
833#define T2_OPCODE_ADC 10
834#define T2_OPCODE_SBC 11
835#define T2_OPCODE_SUB 13
836#define T2_OPCODE_RSB 14
837
838#define T_OPCODE_MUL 0x4340
839#define T_OPCODE_TST 0x4200
840#define T_OPCODE_CMN 0x42c0
841#define T_OPCODE_NEG 0x4240
842#define T_OPCODE_MVN 0x43c0
843
844#define T_OPCODE_ADD_R3 0x1800
845#define T_OPCODE_SUB_R3 0x1a00
846#define T_OPCODE_ADD_HI 0x4400
847#define T_OPCODE_ADD_ST 0xb000
848#define T_OPCODE_SUB_ST 0xb080
849#define T_OPCODE_ADD_SP 0xa800
850#define T_OPCODE_ADD_PC 0xa000
851#define T_OPCODE_ADD_I8 0x3000
852#define T_OPCODE_SUB_I8 0x3800
853#define T_OPCODE_ADD_I3 0x1c00
854#define T_OPCODE_SUB_I3 0x1e00
855
856#define T_OPCODE_ASR_R 0x4100
857#define T_OPCODE_LSL_R 0x4080
858#define T_OPCODE_LSR_R 0x40c0
859#define T_OPCODE_ROR_R 0x41c0
860#define T_OPCODE_ASR_I 0x1000
861#define T_OPCODE_LSL_I 0x0000
862#define T_OPCODE_LSR_I 0x0800
863
864#define T_OPCODE_MOV_I8 0x2000
865#define T_OPCODE_CMP_I8 0x2800
866#define T_OPCODE_CMP_LR 0x4280
867#define T_OPCODE_MOV_HR 0x4600
868#define T_OPCODE_CMP_HR 0x4500
869
870#define T_OPCODE_LDR_PC 0x4800
871#define T_OPCODE_LDR_SP 0x9800
872#define T_OPCODE_STR_SP 0x9000
873#define T_OPCODE_LDR_IW 0x6800
874#define T_OPCODE_STR_IW 0x6000
875#define T_OPCODE_LDR_IH 0x8800
876#define T_OPCODE_STR_IH 0x8000
877#define T_OPCODE_LDR_IB 0x7800
878#define T_OPCODE_STR_IB 0x7000
879#define T_OPCODE_LDR_RW 0x5800
880#define T_OPCODE_STR_RW 0x5000
881#define T_OPCODE_LDR_RH 0x5a00
882#define T_OPCODE_STR_RH 0x5200
883#define T_OPCODE_LDR_RB 0x5c00
884#define T_OPCODE_STR_RB 0x5400
885
886#define T_OPCODE_PUSH 0xb400
887#define T_OPCODE_POP 0xbc00
888
889#define T_OPCODE_BRANCH 0xe000
890
891#define THUMB_SIZE 2 /* Size of thumb instruction. */
892#define THUMB_PP_PC_LR 0x0100
893#define THUMB_LOAD_BIT 0x0800
894#define THUMB2_LOAD_BIT 0x00100000
895
896#define BAD_SYNTAX _("syntax error")
897#define BAD_ARGS _("bad arguments to instruction")
898#define BAD_SP _("r13 not allowed here")
899#define BAD_PC _("r15 not allowed here")
900#define BAD_ODD _("Odd register not allowed here")
901#define BAD_EVEN _("Even register not allowed here")
902#define BAD_COND _("instruction cannot be conditional")
903#define BAD_OVERLAP _("registers may not be the same")
904#define BAD_HIREG _("lo register required")
905#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
906#define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
907#define BAD_BRANCH _("branch must be last instruction in IT block")
908#define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
909#define BAD_NO_VPT _("instruction not allowed in VPT block")
910#define BAD_NOT_IT _("instruction not allowed in IT block")
911#define BAD_NOT_VPT _("instruction missing MVE vector predication code")
912#define BAD_FPU _("selected FPU does not support instruction")
913#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
914#define BAD_OUT_VPT \
915 _("vector predicated instruction should be in VPT/VPST block")
916#define BAD_IT_COND _("incorrect condition in IT block")
917#define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
918#define BAD_IT_IT _("IT falling in the range of a previous IT block")
919#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
920#define BAD_PC_ADDRESSING \
921 _("cannot use register index with PC-relative addressing")
922#define BAD_PC_WRITEBACK \
923 _("cannot use writeback with PC-relative addressing")
924#define BAD_RANGE _("branch out of range")
925#define BAD_FP16 _("selected processor does not support fp16 instruction")
926#define BAD_BF16 _("selected processor does not support bf16 instruction")
927#define BAD_CDE _("selected processor does not support cde instruction")
928#define BAD_CDE_COPROC _("coprocessor for insn is not enabled for cde")
929#define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
930#define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
931#define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
932 "block")
933#define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
934 "block")
935#define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
936 " operand")
937#define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
938 " operand")
939#define BAD_SIMD_TYPE _("bad type in SIMD instruction")
940#define BAD_MVE_AUTO \
941 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
942 " use a valid -march or -mcpu option.")
943#define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
944 "and source operands makes instruction UNPREDICTABLE")
945#define BAD_EL_TYPE _("bad element type for instruction")
946#define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
947
948static struct hash_control * arm_ops_hsh;
949static struct hash_control * arm_cond_hsh;
950static struct hash_control * arm_vcond_hsh;
951static struct hash_control * arm_shift_hsh;
952static struct hash_control * arm_psr_hsh;
953static struct hash_control * arm_v7m_psr_hsh;
954static struct hash_control * arm_reg_hsh;
955static struct hash_control * arm_reloc_hsh;
956static struct hash_control * arm_barrier_opt_hsh;
957
958/* Stuff needed to resolve the label ambiguity
959 As:
960 ...
961 label: <insn>
962 may differ from:
963 ...
964 label:
965 <insn> */
966
967symbolS * last_label_seen;
968static int label_is_thumb_function_name = FALSE;
969
970/* Literal pool structure. Held on a per-section
971 and per-sub-section basis. */
972
973#define MAX_LITERAL_POOL_SIZE 1024
974typedef struct literal_pool
975{
976 expressionS literals [MAX_LITERAL_POOL_SIZE];
977 unsigned int next_free_entry;
978 unsigned int id;
979 symbolS * symbol;
980 segT section;
981 subsegT sub_section;
982#ifdef OBJ_ELF
983 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
984#endif
985 struct literal_pool * next;
986 unsigned int alignment;
987} literal_pool;
988
989/* Pointer to a linked list of literal pools. */
990literal_pool * list_of_pools = NULL;
991
992typedef enum asmfunc_states
993{
994 OUTSIDE_ASMFUNC,
995 WAITING_ASMFUNC_NAME,
996 WAITING_ENDASMFUNC
997} asmfunc_states;
998
999static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
1000
1001#ifdef OBJ_ELF
1002# define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
1003#else
1004static struct current_pred now_pred;
1005#endif
1006
1007static inline int
1008now_pred_compatible (int cond)
1009{
1010 return (cond & ~1) == (now_pred.cc & ~1);
1011}
1012
1013static inline int
1014conditional_insn (void)
1015{
1016 return inst.cond != COND_ALWAYS;
1017}
1018
1019static int in_pred_block (void);
1020
1021static int handle_pred_state (void);
1022
1023static void force_automatic_it_block_close (void);
1024
1025static void it_fsm_post_encode (void);
1026
1027#define set_pred_insn_type(type) \
1028 do \
1029 { \
1030 inst.pred_insn_type = type; \
1031 if (handle_pred_state () == FAIL) \
1032 return; \
1033 } \
1034 while (0)
1035
1036#define set_pred_insn_type_nonvoid(type, failret) \
1037 do \
1038 { \
1039 inst.pred_insn_type = type; \
1040 if (handle_pred_state () == FAIL) \
1041 return failret; \
1042 } \
1043 while(0)
1044
1045#define set_pred_insn_type_last() \
1046 do \
1047 { \
1048 if (inst.cond == COND_ALWAYS) \
1049 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1050 else \
1051 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1052 } \
1053 while (0)
1054
1055/* Toggle value[pos]. */
1056#define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1057
1058/* Pure syntax. */
1059
1060/* This array holds the chars that always start a comment. If the
1061 pre-processor is disabled, these aren't very useful. */
1062char arm_comment_chars[] = "@";
1063
1064/* This array holds the chars that only start a comment at the beginning of
1065 a line. If the line seems to have the form '# 123 filename'
1066 .line and .file directives will appear in the pre-processed output. */
1067/* Note that input_file.c hand checks for '#' at the beginning of the
1068 first line of the input file. This is because the compiler outputs
1069 #NO_APP at the beginning of its output. */
1070/* Also note that comments like this one will always work. */
1071const char line_comment_chars[] = "#";
1072
1073char arm_line_separator_chars[] = ";";
1074
1075/* Chars that can be used to separate mant
1076 from exp in floating point numbers. */
1077const char EXP_CHARS[] = "eE";
1078
1079/* Chars that mean this number is a floating point constant. */
1080/* As in 0f12.456 */
1081/* or 0d1.2345e12 */
1082
1083const char FLT_CHARS[] = "rRsSfFdDxXeEpPHh";
1084
1085/* Prefix characters that indicate the start of an immediate
1086 value. */
1087#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1088
1089/* Separator character handling. */
1090
1091#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1092
1093enum fp_16bit_format
1094{
1095 ARM_FP16_FORMAT_IEEE = 0x1,
1096 ARM_FP16_FORMAT_ALTERNATIVE = 0x2,
1097 ARM_FP16_FORMAT_DEFAULT = 0x3
1098};
1099
1100static enum fp_16bit_format fp16_format = ARM_FP16_FORMAT_DEFAULT;
1101
1102
1103static inline int
1104skip_past_char (char ** str, char c)
1105{
1106 /* PR gas/14987: Allow for whitespace before the expected character. */
1107 skip_whitespace (*str);
1108
1109 if (**str == c)
1110 {
1111 (*str)++;
1112 return SUCCESS;
1113 }
1114 else
1115 return FAIL;
1116}
1117
1118#define skip_past_comma(str) skip_past_char (str, ',')
1119
1120/* Arithmetic expressions (possibly involving symbols). */
1121
1122/* Return TRUE if anything in the expression is a bignum. */
1123
1124static bfd_boolean
1125walk_no_bignums (symbolS * sp)
1126{
1127 if (symbol_get_value_expression (sp)->X_op == O_big)
1128 return TRUE;
1129
1130 if (symbol_get_value_expression (sp)->X_add_symbol)
1131 {
1132 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
1133 || (symbol_get_value_expression (sp)->X_op_symbol
1134 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
1135 }
1136
1137 return FALSE;
1138}
1139
1140static bfd_boolean in_my_get_expression = FALSE;
1141
1142/* Third argument to my_get_expression. */
1143#define GE_NO_PREFIX 0
1144#define GE_IMM_PREFIX 1
1145#define GE_OPT_PREFIX 2
1146/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1147 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1148#define GE_OPT_PREFIX_BIG 3
1149
1150static int
1151my_get_expression (expressionS * ep, char ** str, int prefix_mode)
1152{
1153 char * save_in;
1154
1155 /* In unified syntax, all prefixes are optional. */
1156 if (unified_syntax)
1157 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
1158 : GE_OPT_PREFIX;
1159
1160 switch (prefix_mode)
1161 {
1162 case GE_NO_PREFIX: break;
1163 case GE_IMM_PREFIX:
1164 if (!is_immediate_prefix (**str))
1165 {
1166 inst.error = _("immediate expression requires a # prefix");
1167 return FAIL;
1168 }
1169 (*str)++;
1170 break;
1171 case GE_OPT_PREFIX:
1172 case GE_OPT_PREFIX_BIG:
1173 if (is_immediate_prefix (**str))
1174 (*str)++;
1175 break;
1176 default:
1177 abort ();
1178 }
1179
1180 memset (ep, 0, sizeof (expressionS));
1181
1182 save_in = input_line_pointer;
1183 input_line_pointer = *str;
1184 in_my_get_expression = TRUE;
1185 expression (ep);
1186 in_my_get_expression = FALSE;
1187
1188 if (ep->X_op == O_illegal || ep->X_op == O_absent)
1189 {
1190 /* We found a bad or missing expression in md_operand(). */
1191 *str = input_line_pointer;
1192 input_line_pointer = save_in;
1193 if (inst.error == NULL)
1194 inst.error = (ep->X_op == O_absent
1195 ? _("missing expression") :_("bad expression"));
1196 return 1;
1197 }
1198
1199 /* Get rid of any bignums now, so that we don't generate an error for which
1200 we can't establish a line number later on. Big numbers are never valid
1201 in instructions, which is where this routine is always called. */
1202 if (prefix_mode != GE_OPT_PREFIX_BIG
1203 && (ep->X_op == O_big
1204 || (ep->X_add_symbol
1205 && (walk_no_bignums (ep->X_add_symbol)
1206 || (ep->X_op_symbol
1207 && walk_no_bignums (ep->X_op_symbol))))))
1208 {
1209 inst.error = _("invalid constant");
1210 *str = input_line_pointer;
1211 input_line_pointer = save_in;
1212 return 1;
1213 }
1214
1215 *str = input_line_pointer;
1216 input_line_pointer = save_in;
1217 return SUCCESS;
1218}
1219
1220/* Turn a string in input_line_pointer into a floating point constant
1221 of type TYPE, and store the appropriate bytes in *LITP. The number
1222 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1223 returned, or NULL on OK.
1224
1225 Note that fp constants aren't represent in the normal way on the ARM.
1226 In big endian mode, things are as expected. However, in little endian
1227 mode fp constants are big-endian word-wise, and little-endian byte-wise
1228 within the words. For example, (double) 1.1 in big endian mode is
1229 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1230 the byte sequence 99 99 f1 3f 9a 99 99 99.
1231
1232 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1233
1234const char *
1235md_atof (int type, char * litP, int * sizeP)
1236{
1237 int prec;
1238 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1239 char *t;
1240 int i;
1241
1242 switch (type)
1243 {
1244 case 'H':
1245 case 'h':
1246 prec = 1;
1247 break;
1248
1249 /* If this is a bfloat16, then parse it slightly differently, as it
1250 does not follow the IEEE specification for floating point numbers
1251 exactly. */
1252 case 'b':
1253 {
1254 FLONUM_TYPE generic_float;
1255
1256 t = atof_ieee_detail (input_line_pointer, 1, 8, words, &generic_float);
1257
1258 if (t)
1259 input_line_pointer = t;
1260 else
1261 return _("invalid floating point number");
1262
1263 switch (generic_float.sign)
1264 {
1265 /* Is +Inf. */
1266 case 'P':
1267 words[0] = 0x7f80;
1268 break;
1269
1270 /* Is -Inf. */
1271 case 'N':
1272 words[0] = 0xff80;
1273 break;
1274
1275 /* Is NaN. */
1276 /* bfloat16 has two types of NaN - quiet and signalling.
1277 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1278 signalling NaN's have bit[0] == 0 && fraction != 0.
1279 Chosen this specific encoding as it is the same form
1280 as used by other IEEE 754 encodings in GAS. */
1281 case 0:
1282 words[0] = 0x7fff;
1283 break;
1284
1285 default:
1286 break;
1287 }
1288
1289 *sizeP = 2;
1290
1291 md_number_to_chars (litP, (valueT) words[0], sizeof (LITTLENUM_TYPE));
1292
1293 return NULL;
1294 }
1295 case 'f':
1296 case 'F':
1297 case 's':
1298 case 'S':
1299 prec = 2;
1300 break;
1301
1302 case 'd':
1303 case 'D':
1304 case 'r':
1305 case 'R':
1306 prec = 4;
1307 break;
1308
1309 case 'x':
1310 case 'X':
1311 prec = 5;
1312 break;
1313
1314 case 'p':
1315 case 'P':
1316 prec = 5;
1317 break;
1318
1319 default:
1320 *sizeP = 0;
1321 return _("Unrecognized or unsupported floating point constant");
1322 }
1323
1324 t = atof_ieee (input_line_pointer, type, words);
1325 if (t)
1326 input_line_pointer = t;
1327 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1328
1329 if (target_big_endian || prec == 1)
1330 for (i = 0; i < prec; i++)
1331 {
1332 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1333 litP += sizeof (LITTLENUM_TYPE);
1334 }
1335 else if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1336 for (i = prec - 1; i >= 0; i--)
1337 {
1338 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1339 litP += sizeof (LITTLENUM_TYPE);
1340 }
1341 else
1342 /* For a 4 byte float the order of elements in `words' is 1 0.
1343 For an 8 byte float the order is 1 0 3 2. */
1344 for (i = 0; i < prec; i += 2)
1345 {
1346 md_number_to_chars (litP, (valueT) words[i + 1],
1347 sizeof (LITTLENUM_TYPE));
1348 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1349 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1350 litP += 2 * sizeof (LITTLENUM_TYPE);
1351 }
1352
1353 return NULL;
1354}
1355
1356/* We handle all bad expressions here, so that we can report the faulty
1357 instruction in the error message. */
1358
1359void
1360md_operand (expressionS * exp)
1361{
1362 if (in_my_get_expression)
1363 exp->X_op = O_illegal;
1364}
1365
1366/* Immediate values. */
1367
1368#ifdef OBJ_ELF
1369/* Generic immediate-value read function for use in directives.
1370 Accepts anything that 'expression' can fold to a constant.
1371 *val receives the number. */
1372
1373static int
1374immediate_for_directive (int *val)
1375{
1376 expressionS exp;
1377 exp.X_op = O_illegal;
1378
1379 if (is_immediate_prefix (*input_line_pointer))
1380 {
1381 input_line_pointer++;
1382 expression (&exp);
1383 }
1384
1385 if (exp.X_op != O_constant)
1386 {
1387 as_bad (_("expected #constant"));
1388 ignore_rest_of_line ();
1389 return FAIL;
1390 }
1391 *val = exp.X_add_number;
1392 return SUCCESS;
1393}
1394#endif
1395
1396/* Register parsing. */
1397
1398/* Generic register parser. CCP points to what should be the
1399 beginning of a register name. If it is indeed a valid register
1400 name, advance CCP over it and return the reg_entry structure;
1401 otherwise return NULL. Does not issue diagnostics. */
1402
1403static struct reg_entry *
1404arm_reg_parse_multi (char **ccp)
1405{
1406 char *start = *ccp;
1407 char *p;
1408 struct reg_entry *reg;
1409
1410 skip_whitespace (start);
1411
1412#ifdef REGISTER_PREFIX
1413 if (*start != REGISTER_PREFIX)
1414 return NULL;
1415 start++;
1416#endif
1417#ifdef OPTIONAL_REGISTER_PREFIX
1418 if (*start == OPTIONAL_REGISTER_PREFIX)
1419 start++;
1420#endif
1421
1422 p = start;
1423 if (!ISALPHA (*p) || !is_name_beginner (*p))
1424 return NULL;
1425
1426 do
1427 p++;
1428 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1429
1430 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1431
1432 if (!reg)
1433 return NULL;
1434
1435 *ccp = p;
1436 return reg;
1437}
1438
1439static int
1440arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1441 enum arm_reg_type type)
1442{
1443 /* Alternative syntaxes are accepted for a few register classes. */
1444 switch (type)
1445 {
1446 case REG_TYPE_MVF:
1447 case REG_TYPE_MVD:
1448 case REG_TYPE_MVFX:
1449 case REG_TYPE_MVDX:
1450 /* Generic coprocessor register names are allowed for these. */
1451 if (reg && reg->type == REG_TYPE_CN)
1452 return reg->number;
1453 break;
1454
1455 case REG_TYPE_CP:
1456 /* For backward compatibility, a bare number is valid here. */
1457 {
1458 unsigned long processor = strtoul (start, ccp, 10);
1459 if (*ccp != start && processor <= 15)
1460 return processor;
1461 }
1462 /* Fall through. */
1463
1464 case REG_TYPE_MMXWC:
1465 /* WC includes WCG. ??? I'm not sure this is true for all
1466 instructions that take WC registers. */
1467 if (reg && reg->type == REG_TYPE_MMXWCG)
1468 return reg->number;
1469 break;
1470
1471 default:
1472 break;
1473 }
1474
1475 return FAIL;
1476}
1477
1478/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1479 return value is the register number or FAIL. */
1480
1481static int
1482arm_reg_parse (char **ccp, enum arm_reg_type type)
1483{
1484 char *start = *ccp;
1485 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1486 int ret;
1487
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1490 return FAIL;
1491
1492 if (reg && reg->type == type)
1493 return reg->number;
1494
1495 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1496 return ret;
1497
1498 *ccp = start;
1499 return FAIL;
1500}
1501
1502/* Parse a Neon type specifier. *STR should point at the leading '.'
1503 character. Does no verification at this stage that the type fits the opcode
1504 properly. E.g.,
1505
1506 .i32.i32.s16
1507 .s32.f32
1508 .u16
1509
1510 Can all be legally parsed by this function.
1511
1512 Fills in neon_type struct pointer with parsed information, and updates STR
1513 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1514 type, FAIL if not. */
1515
1516static int
1517parse_neon_type (struct neon_type *type, char **str)
1518{
1519 char *ptr = *str;
1520
1521 if (type)
1522 type->elems = 0;
1523
1524 while (type->elems < NEON_MAX_TYPE_ELS)
1525 {
1526 enum neon_el_type thistype = NT_untyped;
1527 unsigned thissize = -1u;
1528
1529 if (*ptr != '.')
1530 break;
1531
1532 ptr++;
1533
1534 /* Just a size without an explicit type. */
1535 if (ISDIGIT (*ptr))
1536 goto parsesize;
1537
1538 switch (TOLOWER (*ptr))
1539 {
1540 case 'i': thistype = NT_integer; break;
1541 case 'f': thistype = NT_float; break;
1542 case 'p': thistype = NT_poly; break;
1543 case 's': thistype = NT_signed; break;
1544 case 'u': thistype = NT_unsigned; break;
1545 case 'd':
1546 thistype = NT_float;
1547 thissize = 64;
1548 ptr++;
1549 goto done;
1550 case 'b':
1551 thistype = NT_bfloat;
1552 switch (TOLOWER (*(++ptr)))
1553 {
1554 case 'f':
1555 ptr += 1;
1556 thissize = strtoul (ptr, &ptr, 10);
1557 if (thissize != 16)
1558 {
1559 as_bad (_("bad size %d in type specifier"), thissize);
1560 return FAIL;
1561 }
1562 goto done;
1563 case '0': case '1': case '2': case '3': case '4':
1564 case '5': case '6': case '7': case '8': case '9':
1565 case ' ': case '.':
1566 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1567 return FAIL;
1568 default:
1569 break;
1570 }
1571 break;
1572 default:
1573 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1574 return FAIL;
1575 }
1576
1577 ptr++;
1578
1579 /* .f is an abbreviation for .f32. */
1580 if (thistype == NT_float && !ISDIGIT (*ptr))
1581 thissize = 32;
1582 else
1583 {
1584 parsesize:
1585 thissize = strtoul (ptr, &ptr, 10);
1586
1587 if (thissize != 8 && thissize != 16 && thissize != 32
1588 && thissize != 64)
1589 {
1590 as_bad (_("bad size %d in type specifier"), thissize);
1591 return FAIL;
1592 }
1593 }
1594
1595 done:
1596 if (type)
1597 {
1598 type->el[type->elems].type = thistype;
1599 type->el[type->elems].size = thissize;
1600 type->elems++;
1601 }
1602 }
1603
1604 /* Empty/missing type is not a successful parse. */
1605 if (type->elems == 0)
1606 return FAIL;
1607
1608 *str = ptr;
1609
1610 return SUCCESS;
1611}
1612
1613/* Errors may be set multiple times during parsing or bit encoding
1614 (particularly in the Neon bits), but usually the earliest error which is set
1615 will be the most meaningful. Avoid overwriting it with later (cascading)
1616 errors by calling this function. */
1617
1618static void
1619first_error (const char *err)
1620{
1621 if (!inst.error)
1622 inst.error = err;
1623}
1624
1625/* Parse a single type, e.g. ".s32", leading period included. */
1626static int
1627parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1628{
1629 char *str = *ccp;
1630 struct neon_type optype;
1631
1632 if (*str == '.')
1633 {
1634 if (parse_neon_type (&optype, &str) == SUCCESS)
1635 {
1636 if (optype.elems == 1)
1637 *vectype = optype.el[0];
1638 else
1639 {
1640 first_error (_("only one type should be specified for operand"));
1641 return FAIL;
1642 }
1643 }
1644 else
1645 {
1646 first_error (_("vector type expected"));
1647 return FAIL;
1648 }
1649 }
1650 else
1651 return FAIL;
1652
1653 *ccp = str;
1654
1655 return SUCCESS;
1656}
1657
1658/* Special meanings for indices (which have a range of 0-7), which will fit into
1659 a 4-bit integer. */
1660
1661#define NEON_ALL_LANES 15
1662#define NEON_INTERLEAVE_LANES 14
1663
1664/* Record a use of the given feature. */
1665static void
1666record_feature_use (const arm_feature_set *feature)
1667{
1668 if (thumb_mode)
1669 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
1670 else
1671 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
1672}
1673
1674/* If the given feature available in the selected CPU, mark it as used.
1675 Returns TRUE iff feature is available. */
1676static bfd_boolean
1677mark_feature_used (const arm_feature_set *feature)
1678{
1679
1680 /* Do not support the use of MVE only instructions when in auto-detection or
1681 -march=all. */
1682 if (((feature == &mve_ext) || (feature == &mve_fp_ext))
1683 && ARM_CPU_IS_ANY (cpu_variant))
1684 {
1685 first_error (BAD_MVE_AUTO);
1686 return FALSE;
1687 }
1688 /* Ensure the option is valid on the current architecture. */
1689 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
1690 return FALSE;
1691
1692 /* Add the appropriate architecture feature for the barrier option used.
1693 */
1694 record_feature_use (feature);
1695
1696 return TRUE;
1697}
1698
1699/* Parse either a register or a scalar, with an optional type. Return the
1700 register number, and optionally fill in the actual type of the register
1701 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1702 type/index information in *TYPEINFO. */
1703
1704static int
1705parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1706 enum arm_reg_type *rtype,
1707 struct neon_typed_alias *typeinfo)
1708{
1709 char *str = *ccp;
1710 struct reg_entry *reg = arm_reg_parse_multi (&str);
1711 struct neon_typed_alias atype;
1712 struct neon_type_el parsetype;
1713
1714 atype.defined = 0;
1715 atype.index = -1;
1716 atype.eltype.type = NT_invtype;
1717 atype.eltype.size = -1;
1718
1719 /* Try alternate syntax for some types of register. Note these are mutually
1720 exclusive with the Neon syntax extensions. */
1721 if (reg == NULL)
1722 {
1723 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1724 if (altreg != FAIL)
1725 *ccp = str;
1726 if (typeinfo)
1727 *typeinfo = atype;
1728 return altreg;
1729 }
1730
1731 /* Undo polymorphism when a set of register types may be accepted. */
1732 if ((type == REG_TYPE_NDQ
1733 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1734 || (type == REG_TYPE_VFSD
1735 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1736 || (type == REG_TYPE_NSDQ
1737 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1738 || reg->type == REG_TYPE_NQ))
1739 || (type == REG_TYPE_NSD
1740 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1741 || (type == REG_TYPE_MMXWC
1742 && (reg->type == REG_TYPE_MMXWCG)))
1743 type = (enum arm_reg_type) reg->type;
1744
1745 if (type == REG_TYPE_MQ)
1746 {
1747 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1748 return FAIL;
1749
1750 if (!reg || reg->type != REG_TYPE_NQ)
1751 return FAIL;
1752
1753 if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32))
1754 {
1755 first_error (_("expected MVE register [q0..q7]"));
1756 return FAIL;
1757 }
1758 type = REG_TYPE_NQ;
1759 }
1760 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
1761 && (type == REG_TYPE_NQ))
1762 return FAIL;
1763
1764
1765 if (type != reg->type)
1766 return FAIL;
1767
1768 if (reg->neon)
1769 atype = *reg->neon;
1770
1771 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1772 {
1773 if ((atype.defined & NTA_HASTYPE) != 0)
1774 {
1775 first_error (_("can't redefine type for operand"));
1776 return FAIL;
1777 }
1778 atype.defined |= NTA_HASTYPE;
1779 atype.eltype = parsetype;
1780 }
1781
1782 if (skip_past_char (&str, '[') == SUCCESS)
1783 {
1784 if (type != REG_TYPE_VFD
1785 && !(type == REG_TYPE_VFS
1786 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2))
1787 && !(type == REG_TYPE_NQ
1788 && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
1789 {
1790 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1791 first_error (_("only D and Q registers may be indexed"));
1792 else
1793 first_error (_("only D registers may be indexed"));
1794 return FAIL;
1795 }
1796
1797 if ((atype.defined & NTA_HASINDEX) != 0)
1798 {
1799 first_error (_("can't change index for operand"));
1800 return FAIL;
1801 }
1802
1803 atype.defined |= NTA_HASINDEX;
1804
1805 if (skip_past_char (&str, ']') == SUCCESS)
1806 atype.index = NEON_ALL_LANES;
1807 else
1808 {
1809 expressionS exp;
1810
1811 my_get_expression (&exp, &str, GE_NO_PREFIX);
1812
1813 if (exp.X_op != O_constant)
1814 {
1815 first_error (_("constant expression required"));
1816 return FAIL;
1817 }
1818
1819 if (skip_past_char (&str, ']') == FAIL)
1820 return FAIL;
1821
1822 atype.index = exp.X_add_number;
1823 }
1824 }
1825
1826 if (typeinfo)
1827 *typeinfo = atype;
1828
1829 if (rtype)
1830 *rtype = type;
1831
1832 *ccp = str;
1833
1834 return reg->number;
1835}
1836
1837/* Like arm_reg_parse, but also allow the following extra features:
1838 - If RTYPE is non-zero, return the (possibly restricted) type of the
1839 register (e.g. Neon double or quad reg when either has been requested).
1840 - If this is a Neon vector type with additional type information, fill
1841 in the struct pointed to by VECTYPE (if non-NULL).
1842 This function will fault on encountering a scalar. */
1843
1844static int
1845arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1846 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1847{
1848 struct neon_typed_alias atype;
1849 char *str = *ccp;
1850 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1851
1852 if (reg == FAIL)
1853 return FAIL;
1854
1855 /* Do not allow regname(... to parse as a register. */
1856 if (*str == '(')
1857 return FAIL;
1858
1859 /* Do not allow a scalar (reg+index) to parse as a register. */
1860 if ((atype.defined & NTA_HASINDEX) != 0)
1861 {
1862 first_error (_("register operand expected, but got scalar"));
1863 return FAIL;
1864 }
1865
1866 if (vectype)
1867 *vectype = atype.eltype;
1868
1869 *ccp = str;
1870
1871 return reg;
1872}
1873
1874#define NEON_SCALAR_REG(X) ((X) >> 4)
1875#define NEON_SCALAR_INDEX(X) ((X) & 15)
1876
1877/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1878 have enough information to be able to do a good job bounds-checking. So, we
1879 just do easy checks here, and do further checks later. */
1880
1881static int
1882parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum
1883 arm_reg_type reg_type)
1884{
1885 int reg;
1886 char *str = *ccp;
1887 struct neon_typed_alias atype;
1888 unsigned reg_size;
1889
1890 reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
1891
1892 switch (reg_type)
1893 {
1894 case REG_TYPE_VFS:
1895 reg_size = 32;
1896 break;
1897 case REG_TYPE_VFD:
1898 reg_size = 64;
1899 break;
1900 case REG_TYPE_MQ:
1901 reg_size = 128;
1902 break;
1903 default:
1904 gas_assert (0);
1905 return FAIL;
1906 }
1907
1908 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1909 return FAIL;
1910
1911 if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES)
1912 {
1913 first_error (_("scalar must have an index"));
1914 return FAIL;
1915 }
1916 else if (atype.index >= reg_size / elsize)
1917 {
1918 first_error (_("scalar index out of range"));
1919 return FAIL;
1920 }
1921
1922 if (type)
1923 *type = atype.eltype;
1924
1925 *ccp = str;
1926
1927 return reg * 16 + atype.index;
1928}
1929
1930/* Types of registers in a list. */
1931
1932enum reg_list_els
1933{
1934 REGLIST_RN,
1935 REGLIST_CLRM,
1936 REGLIST_VFP_S,
1937 REGLIST_VFP_S_VPR,
1938 REGLIST_VFP_D,
1939 REGLIST_VFP_D_VPR,
1940 REGLIST_NEON_D
1941};
1942
1943/* Parse an ARM register list. Returns the bitmask, or FAIL. */
1944
1945static long
1946parse_reg_list (char ** strp, enum reg_list_els etype)
1947{
1948 char *str = *strp;
1949 long range = 0;
1950 int another_range;
1951
1952 gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM);
1953
1954 /* We come back here if we get ranges concatenated by '+' or '|'. */
1955 do
1956 {
1957 skip_whitespace (str);
1958
1959 another_range = 0;
1960
1961 if (*str == '{')
1962 {
1963 int in_range = 0;
1964 int cur_reg = -1;
1965
1966 str++;
1967 do
1968 {
1969 int reg;
1970 const char apsr_str[] = "apsr";
1971 int apsr_str_len = strlen (apsr_str);
1972
1973 reg = arm_reg_parse (&str, REG_TYPE_RN);
1974 if (etype == REGLIST_CLRM)
1975 {
1976 if (reg == REG_SP || reg == REG_PC)
1977 reg = FAIL;
1978 else if (reg == FAIL
1979 && !strncasecmp (str, apsr_str, apsr_str_len)
1980 && !ISALPHA (*(str + apsr_str_len)))
1981 {
1982 reg = 15;
1983 str += apsr_str_len;
1984 }
1985
1986 if (reg == FAIL)
1987 {
1988 first_error (_("r0-r12, lr or APSR expected"));
1989 return FAIL;
1990 }
1991 }
1992 else /* etype == REGLIST_RN. */
1993 {
1994 if (reg == FAIL)
1995 {
1996 first_error (_(reg_expected_msgs[REGLIST_RN]));
1997 return FAIL;
1998 }
1999 }
2000
2001 if (in_range)
2002 {
2003 int i;
2004
2005 if (reg <= cur_reg)
2006 {
2007 first_error (_("bad range in register list"));
2008 return FAIL;
2009 }
2010
2011 for (i = cur_reg + 1; i < reg; i++)
2012 {
2013 if (range & (1 << i))
2014 as_tsktsk
2015 (_("Warning: duplicated register (r%d) in register list"),
2016 i);
2017 else
2018 range |= 1 << i;
2019 }
2020 in_range = 0;
2021 }
2022
2023 if (range & (1 << reg))
2024 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2025 reg);
2026 else if (reg <= cur_reg)
2027 as_tsktsk (_("Warning: register range not in ascending order"));
2028
2029 range |= 1 << reg;
2030 cur_reg = reg;
2031 }
2032 while (skip_past_comma (&str) != FAIL
2033 || (in_range = 1, *str++ == '-'));
2034 str--;
2035
2036 if (skip_past_char (&str, '}') == FAIL)
2037 {
2038 first_error (_("missing `}'"));
2039 return FAIL;
2040 }
2041 }
2042 else if (etype == REGLIST_RN)
2043 {
2044 expressionS exp;
2045
2046 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
2047 return FAIL;
2048
2049 if (exp.X_op == O_constant)
2050 {
2051 if (exp.X_add_number
2052 != (exp.X_add_number & 0x0000ffff))
2053 {
2054 inst.error = _("invalid register mask");
2055 return FAIL;
2056 }
2057
2058 if ((range & exp.X_add_number) != 0)
2059 {
2060 int regno = range & exp.X_add_number;
2061
2062 regno &= -regno;
2063 regno = (1 << regno) - 1;
2064 as_tsktsk
2065 (_("Warning: duplicated register (r%d) in register list"),
2066 regno);
2067 }
2068
2069 range |= exp.X_add_number;
2070 }
2071 else
2072 {
2073 if (inst.relocs[0].type != 0)
2074 {
2075 inst.error = _("expression too complex");
2076 return FAIL;
2077 }
2078
2079 memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
2080 inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
2081 inst.relocs[0].pc_rel = 0;
2082 }
2083 }
2084
2085 if (*str == '|' || *str == '+')
2086 {
2087 str++;
2088 another_range = 1;
2089 }
2090 }
2091 while (another_range);
2092
2093 *strp = str;
2094 return range;
2095}
2096
2097/* Parse a VFP register list. If the string is invalid return FAIL.
2098 Otherwise return the number of registers, and set PBASE to the first
2099 register. Parses registers of type ETYPE.
2100 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2101 - Q registers can be used to specify pairs of D registers
2102 - { } can be omitted from around a singleton register list
2103 FIXME: This is not implemented, as it would require backtracking in
2104 some cases, e.g.:
2105 vtbl.8 d3,d4,d5
2106 This could be done (the meaning isn't really ambiguous), but doesn't
2107 fit in well with the current parsing framework.
2108 - 32 D registers may be used (also true for VFPv3).
2109 FIXME: Types are ignored in these register lists, which is probably a
2110 bug. */
2111
2112static int
2113parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
2114 bfd_boolean *partial_match)
2115{
2116 char *str = *ccp;
2117 int base_reg;
2118 int new_base;
2119 enum arm_reg_type regtype = (enum arm_reg_type) 0;
2120 int max_regs = 0;
2121 int count = 0;
2122 int warned = 0;
2123 unsigned long mask = 0;
2124 int i;
2125 bfd_boolean vpr_seen = FALSE;
2126 bfd_boolean expect_vpr =
2127 (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
2128
2129 if (skip_past_char (&str, '{') == FAIL)
2130 {
2131 inst.error = _("expecting {");
2132 return FAIL;
2133 }
2134
2135 switch (etype)
2136 {
2137 case REGLIST_VFP_S:
2138 case REGLIST_VFP_S_VPR:
2139 regtype = REG_TYPE_VFS;
2140 max_regs = 32;
2141 break;
2142
2143 case REGLIST_VFP_D:
2144 case REGLIST_VFP_D_VPR:
2145 regtype = REG_TYPE_VFD;
2146 break;
2147
2148 case REGLIST_NEON_D:
2149 regtype = REG_TYPE_NDQ;
2150 break;
2151
2152 default:
2153 gas_assert (0);
2154 }
2155
2156 if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
2157 {
2158 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2159 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
2160 {
2161 max_regs = 32;
2162 if (thumb_mode)
2163 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
2164 fpu_vfp_ext_d32);
2165 else
2166 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
2167 fpu_vfp_ext_d32);
2168 }
2169 else
2170 max_regs = 16;
2171 }
2172
2173 base_reg = max_regs;
2174 *partial_match = FALSE;
2175
2176 do
2177 {
2178 int setmask = 1, addregs = 1;
2179 const char vpr_str[] = "vpr";
2180 int vpr_str_len = strlen (vpr_str);
2181
2182 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
2183
2184 if (expect_vpr)
2185 {
2186 if (new_base == FAIL
2187 && !strncasecmp (str, vpr_str, vpr_str_len)
2188 && !ISALPHA (*(str + vpr_str_len))
2189 && !vpr_seen)
2190 {
2191 vpr_seen = TRUE;
2192 str += vpr_str_len;
2193 if (count == 0)
2194 base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
2195 }
2196 else if (vpr_seen)
2197 {
2198 first_error (_("VPR expected last"));
2199 return FAIL;
2200 }
2201 else if (new_base == FAIL)
2202 {
2203 if (regtype == REG_TYPE_VFS)
2204 first_error (_("VFP single precision register or VPR "
2205 "expected"));
2206 else /* regtype == REG_TYPE_VFD. */
2207 first_error (_("VFP/Neon double precision register or VPR "
2208 "expected"));
2209 return FAIL;
2210 }
2211 }
2212 else if (new_base == FAIL)
2213 {
2214 first_error (_(reg_expected_msgs[regtype]));
2215 return FAIL;
2216 }
2217
2218 *partial_match = TRUE;
2219 if (vpr_seen)
2220 continue;
2221
2222 if (new_base >= max_regs)
2223 {
2224 first_error (_("register out of range in list"));
2225 return FAIL;
2226 }
2227
2228 /* Note: a value of 2 * n is returned for the register Q<n>. */
2229 if (regtype == REG_TYPE_NQ)
2230 {
2231 setmask = 3;
2232 addregs = 2;
2233 }
2234
2235 if (new_base < base_reg)
2236 base_reg = new_base;
2237
2238 if (mask & (setmask << new_base))
2239 {
2240 first_error (_("invalid register list"));
2241 return FAIL;
2242 }
2243
2244 if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
2245 {
2246 as_tsktsk (_("register list not in ascending order"));
2247 warned = 1;
2248 }
2249
2250 mask |= setmask << new_base;
2251 count += addregs;
2252
2253 if (*str == '-') /* We have the start of a range expression */
2254 {
2255 int high_range;
2256
2257 str++;
2258
2259 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
2260 == FAIL)
2261 {
2262 inst.error = gettext (reg_expected_msgs[regtype]);
2263 return FAIL;
2264 }
2265
2266 if (high_range >= max_regs)
2267 {
2268 first_error (_("register out of range in list"));
2269 return FAIL;
2270 }
2271
2272 if (regtype == REG_TYPE_NQ)
2273 high_range = high_range + 1;
2274
2275 if (high_range <= new_base)
2276 {
2277 inst.error = _("register range not in ascending order");
2278 return FAIL;
2279 }
2280
2281 for (new_base += addregs; new_base <= high_range; new_base += addregs)
2282 {
2283 if (mask & (setmask << new_base))
2284 {
2285 inst.error = _("invalid register list");
2286 return FAIL;
2287 }
2288
2289 mask |= setmask << new_base;
2290 count += addregs;
2291 }
2292 }
2293 }
2294 while (skip_past_comma (&str) != FAIL);
2295
2296 str++;
2297
2298 /* Sanity check -- should have raised a parse error above. */
2299 if ((!vpr_seen && count == 0) || count > max_regs)
2300 abort ();
2301
2302 *pbase = base_reg;
2303
2304 if (expect_vpr && !vpr_seen)
2305 {
2306 first_error (_("VPR expected last"));
2307 return FAIL;
2308 }
2309
2310 /* Final test -- the registers must be consecutive. */
2311 mask >>= base_reg;
2312 for (i = 0; i < count; i++)
2313 {
2314 if ((mask & (1u << i)) == 0)
2315 {
2316 inst.error = _("non-contiguous register range");
2317 return FAIL;
2318 }
2319 }
2320
2321 *ccp = str;
2322
2323 return count;
2324}
2325
2326/* True if two alias types are the same. */
2327
2328static bfd_boolean
2329neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
2330{
2331 if (!a && !b)
2332 return TRUE;
2333
2334 if (!a || !b)
2335 return FALSE;
2336
2337 if (a->defined != b->defined)
2338 return FALSE;
2339
2340 if ((a->defined & NTA_HASTYPE) != 0
2341 && (a->eltype.type != b->eltype.type
2342 || a->eltype.size != b->eltype.size))
2343 return FALSE;
2344
2345 if ((a->defined & NTA_HASINDEX) != 0
2346 && (a->index != b->index))
2347 return FALSE;
2348
2349 return TRUE;
2350}
2351
2352/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2353 The base register is put in *PBASE.
2354 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2355 the return value.
2356 The register stride (minus one) is put in bit 4 of the return value.
2357 Bits [6:5] encode the list length (minus one).
2358 The type of the list elements is put in *ELTYPE, if non-NULL. */
2359
2360#define NEON_LANE(X) ((X) & 0xf)
2361#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2362#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2363
2364static int
2365parse_neon_el_struct_list (char **str, unsigned *pbase,
2366 int mve,
2367 struct neon_type_el *eltype)
2368{
2369 char *ptr = *str;
2370 int base_reg = -1;
2371 int reg_incr = -1;
2372 int count = 0;
2373 int lane = -1;
2374 int leading_brace = 0;
2375 enum arm_reg_type rtype = REG_TYPE_NDQ;
2376 const char *const incr_error = mve ? _("register stride must be 1") :
2377 _("register stride must be 1 or 2");
2378 const char *const type_error = _("mismatched element/structure types in list");
2379 struct neon_typed_alias firsttype;
2380 firsttype.defined = 0;
2381 firsttype.eltype.type = NT_invtype;
2382 firsttype.eltype.size = -1;
2383 firsttype.index = -1;
2384
2385 if (skip_past_char (&ptr, '{') == SUCCESS)
2386 leading_brace = 1;
2387
2388 do
2389 {
2390 struct neon_typed_alias atype;
2391 if (mve)
2392 rtype = REG_TYPE_MQ;
2393 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2394
2395 if (getreg == FAIL)
2396 {
2397 first_error (_(reg_expected_msgs[rtype]));
2398 return FAIL;
2399 }
2400
2401 if (base_reg == -1)
2402 {
2403 base_reg = getreg;
2404 if (rtype == REG_TYPE_NQ)
2405 {
2406 reg_incr = 1;
2407 }
2408 firsttype = atype;
2409 }
2410 else if (reg_incr == -1)
2411 {
2412 reg_incr = getreg - base_reg;
2413 if (reg_incr < 1 || reg_incr > 2)
2414 {
2415 first_error (_(incr_error));
2416 return FAIL;
2417 }
2418 }
2419 else if (getreg != base_reg + reg_incr * count)
2420 {
2421 first_error (_(incr_error));
2422 return FAIL;
2423 }
2424
2425 if (! neon_alias_types_same (&atype, &firsttype))
2426 {
2427 first_error (_(type_error));
2428 return FAIL;
2429 }
2430
2431 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2432 modes. */
2433 if (ptr[0] == '-')
2434 {
2435 struct neon_typed_alias htype;
2436 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2437 if (lane == -1)
2438 lane = NEON_INTERLEAVE_LANES;
2439 else if (lane != NEON_INTERLEAVE_LANES)
2440 {
2441 first_error (_(type_error));
2442 return FAIL;
2443 }
2444 if (reg_incr == -1)
2445 reg_incr = 1;
2446 else if (reg_incr != 1)
2447 {
2448 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2449 return FAIL;
2450 }
2451 ptr++;
2452 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2453 if (hireg == FAIL)
2454 {
2455 first_error (_(reg_expected_msgs[rtype]));
2456 return FAIL;
2457 }
2458 if (! neon_alias_types_same (&htype, &firsttype))
2459 {
2460 first_error (_(type_error));
2461 return FAIL;
2462 }
2463 count += hireg + dregs - getreg;
2464 continue;
2465 }
2466
2467 /* If we're using Q registers, we can't use [] or [n] syntax. */
2468 if (rtype == REG_TYPE_NQ)
2469 {
2470 count += 2;
2471 continue;
2472 }
2473
2474 if ((atype.defined & NTA_HASINDEX) != 0)
2475 {
2476 if (lane == -1)
2477 lane = atype.index;
2478 else if (lane != atype.index)
2479 {
2480 first_error (_(type_error));
2481 return FAIL;
2482 }
2483 }
2484 else if (lane == -1)
2485 lane = NEON_INTERLEAVE_LANES;
2486 else if (lane != NEON_INTERLEAVE_LANES)
2487 {
2488 first_error (_(type_error));
2489 return FAIL;
2490 }
2491 count++;
2492 }
2493 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2494
2495 /* No lane set by [x]. We must be interleaving structures. */
2496 if (lane == -1)
2497 lane = NEON_INTERLEAVE_LANES;
2498
2499 /* Sanity check. */
2500 if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4)
2501 || (count > 1 && reg_incr == -1))
2502 {
2503 first_error (_("error parsing element/structure list"));
2504 return FAIL;
2505 }
2506
2507 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2508 {
2509 first_error (_("expected }"));
2510 return FAIL;
2511 }
2512
2513 if (reg_incr == -1)
2514 reg_incr = 1;
2515
2516 if (eltype)
2517 *eltype = firsttype.eltype;
2518
2519 *pbase = base_reg;
2520 *str = ptr;
2521
2522 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2523}
2524
2525/* Parse an explicit relocation suffix on an expression. This is
2526 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2527 arm_reloc_hsh contains no entries, so this function can only
2528 succeed if there is no () after the word. Returns -1 on error,
2529 BFD_RELOC_UNUSED if there wasn't any suffix. */
2530
2531static int
2532parse_reloc (char **str)
2533{
2534 struct reloc_entry *r;
2535 char *p, *q;
2536
2537 if (**str != '(')
2538 return BFD_RELOC_UNUSED;
2539
2540 p = *str + 1;
2541 q = p;
2542
2543 while (*q && *q != ')' && *q != ',')
2544 q++;
2545 if (*q != ')')
2546 return -1;
2547
2548 if ((r = (struct reloc_entry *)
2549 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2550 return -1;
2551
2552 *str = q + 1;
2553 return r->reloc;
2554}
2555
2556/* Directives: register aliases. */
2557
2558static struct reg_entry *
2559insert_reg_alias (char *str, unsigned number, int type)
2560{
2561 struct reg_entry *new_reg;
2562 const char *name;
2563
2564 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2565 {
2566 if (new_reg->builtin)
2567 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2568
2569 /* Only warn about a redefinition if it's not defined as the
2570 same register. */
2571 else if (new_reg->number != number || new_reg->type != type)
2572 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2573
2574 return NULL;
2575 }
2576
2577 name = xstrdup (str);
2578 new_reg = XNEW (struct reg_entry);
2579
2580 new_reg->name = name;
2581 new_reg->number = number;
2582 new_reg->type = type;
2583 new_reg->builtin = FALSE;
2584 new_reg->neon = NULL;
2585
2586 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2587 abort ();
2588
2589 return new_reg;
2590}
2591
2592static void
2593insert_neon_reg_alias (char *str, int number, int type,
2594 struct neon_typed_alias *atype)
2595{
2596 struct reg_entry *reg = insert_reg_alias (str, number, type);
2597
2598 if (!reg)
2599 {
2600 first_error (_("attempt to redefine typed alias"));
2601 return;
2602 }
2603
2604 if (atype)
2605 {
2606 reg->neon = XNEW (struct neon_typed_alias);
2607 *reg->neon = *atype;
2608 }
2609}
2610
2611/* Look for the .req directive. This is of the form:
2612
2613 new_register_name .req existing_register_name
2614
2615 If we find one, or if it looks sufficiently like one that we want to
2616 handle any error here, return TRUE. Otherwise return FALSE. */
2617
2618static bfd_boolean
2619create_register_alias (char * newname, char *p)
2620{
2621 struct reg_entry *old;
2622 char *oldname, *nbuf;
2623 size_t nlen;
2624
2625 /* The input scrubber ensures that whitespace after the mnemonic is
2626 collapsed to single spaces. */
2627 oldname = p;
2628 if (strncmp (oldname, " .req ", 6) != 0)
2629 return FALSE;
2630
2631 oldname += 6;
2632 if (*oldname == '\0')
2633 return FALSE;
2634
2635 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2636 if (!old)
2637 {
2638 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2639 return TRUE;
2640 }
2641
2642 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2643 the desired alias name, and p points to its end. If not, then
2644 the desired alias name is in the global original_case_string. */
2645#ifdef TC_CASE_SENSITIVE
2646 nlen = p - newname;
2647#else
2648 newname = original_case_string;
2649 nlen = strlen (newname);
2650#endif
2651
2652 nbuf = xmemdup0 (newname, nlen);
2653
2654 /* Create aliases under the new name as stated; an all-lowercase
2655 version of the new name; and an all-uppercase version of the new
2656 name. */
2657 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2658 {
2659 for (p = nbuf; *p; p++)
2660 *p = TOUPPER (*p);
2661
2662 if (strncmp (nbuf, newname, nlen))
2663 {
2664 /* If this attempt to create an additional alias fails, do not bother
2665 trying to create the all-lower case alias. We will fail and issue
2666 a second, duplicate error message. This situation arises when the
2667 programmer does something like:
2668 foo .req r0
2669 Foo .req r1
2670 The second .req creates the "Foo" alias but then fails to create
2671 the artificial FOO alias because it has already been created by the
2672 first .req. */
2673 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2674 {
2675 free (nbuf);
2676 return TRUE;
2677 }
2678 }
2679
2680 for (p = nbuf; *p; p++)
2681 *p = TOLOWER (*p);
2682
2683 if (strncmp (nbuf, newname, nlen))
2684 insert_reg_alias (nbuf, old->number, old->type);
2685 }
2686
2687 free (nbuf);
2688 return TRUE;
2689}
2690
2691/* Create a Neon typed/indexed register alias using directives, e.g.:
2692 X .dn d5.s32[1]
2693 Y .qn 6.s16
2694 Z .dn d7
2695 T .dn Z[0]
2696 These typed registers can be used instead of the types specified after the
2697 Neon mnemonic, so long as all operands given have types. Types can also be
2698 specified directly, e.g.:
2699 vadd d0.s32, d1.s32, d2.s32 */
2700
2701static bfd_boolean
2702create_neon_reg_alias (char *newname, char *p)
2703{
2704 enum arm_reg_type basetype;
2705 struct reg_entry *basereg;
2706 struct reg_entry mybasereg;
2707 struct neon_type ntype;
2708 struct neon_typed_alias typeinfo;
2709 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2710 int namelen;
2711
2712 typeinfo.defined = 0;
2713 typeinfo.eltype.type = NT_invtype;
2714 typeinfo.eltype.size = -1;
2715 typeinfo.index = -1;
2716
2717 nameend = p;
2718
2719 if (strncmp (p, " .dn ", 5) == 0)
2720 basetype = REG_TYPE_VFD;
2721 else if (strncmp (p, " .qn ", 5) == 0)
2722 basetype = REG_TYPE_NQ;
2723 else
2724 return FALSE;
2725
2726 p += 5;
2727
2728 if (*p == '\0')
2729 return FALSE;
2730
2731 basereg = arm_reg_parse_multi (&p);
2732
2733 if (basereg && basereg->type != basetype)
2734 {
2735 as_bad (_("bad type for register"));
2736 return FALSE;
2737 }
2738
2739 if (basereg == NULL)
2740 {
2741 expressionS exp;
2742 /* Try parsing as an integer. */
2743 my_get_expression (&exp, &p, GE_NO_PREFIX);
2744 if (exp.X_op != O_constant)
2745 {
2746 as_bad (_("expression must be constant"));
2747 return FALSE;
2748 }
2749 basereg = &mybasereg;
2750 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2751 : exp.X_add_number;
2752 basereg->neon = 0;
2753 }
2754
2755 if (basereg->neon)
2756 typeinfo = *basereg->neon;
2757
2758 if (parse_neon_type (&ntype, &p) == SUCCESS)
2759 {
2760 /* We got a type. */
2761 if (typeinfo.defined & NTA_HASTYPE)
2762 {
2763 as_bad (_("can't redefine the type of a register alias"));
2764 return FALSE;
2765 }
2766
2767 typeinfo.defined |= NTA_HASTYPE;
2768 if (ntype.elems != 1)
2769 {
2770 as_bad (_("you must specify a single type only"));
2771 return FALSE;
2772 }
2773 typeinfo.eltype = ntype.el[0];
2774 }
2775
2776 if (skip_past_char (&p, '[') == SUCCESS)
2777 {
2778 expressionS exp;
2779 /* We got a scalar index. */
2780
2781 if (typeinfo.defined & NTA_HASINDEX)
2782 {
2783 as_bad (_("can't redefine the index of a scalar alias"));
2784 return FALSE;
2785 }
2786
2787 my_get_expression (&exp, &p, GE_NO_PREFIX);
2788
2789 if (exp.X_op != O_constant)
2790 {
2791 as_bad (_("scalar index must be constant"));
2792 return FALSE;
2793 }
2794
2795 typeinfo.defined |= NTA_HASINDEX;
2796 typeinfo.index = exp.X_add_number;
2797
2798 if (skip_past_char (&p, ']') == FAIL)
2799 {
2800 as_bad (_("expecting ]"));
2801 return FALSE;
2802 }
2803 }
2804
2805 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2806 the desired alias name, and p points to its end. If not, then
2807 the desired alias name is in the global original_case_string. */
2808#ifdef TC_CASE_SENSITIVE
2809 namelen = nameend - newname;
2810#else
2811 newname = original_case_string;
2812 namelen = strlen (newname);
2813#endif
2814
2815 namebuf = xmemdup0 (newname, namelen);
2816
2817 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2818 typeinfo.defined != 0 ? &typeinfo : NULL);
2819
2820 /* Insert name in all uppercase. */
2821 for (p = namebuf; *p; p++)
2822 *p = TOUPPER (*p);
2823
2824 if (strncmp (namebuf, newname, namelen))
2825 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2826 typeinfo.defined != 0 ? &typeinfo : NULL);
2827
2828 /* Insert name in all lowercase. */
2829 for (p = namebuf; *p; p++)
2830 *p = TOLOWER (*p);
2831
2832 if (strncmp (namebuf, newname, namelen))
2833 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2834 typeinfo.defined != 0 ? &typeinfo : NULL);
2835
2836 free (namebuf);
2837 return TRUE;
2838}
2839
2840/* Should never be called, as .req goes between the alias and the
2841 register name, not at the beginning of the line. */
2842
2843static void
2844s_req (int a ATTRIBUTE_UNUSED)
2845{
2846 as_bad (_("invalid syntax for .req directive"));
2847}
2848
2849static void
2850s_dn (int a ATTRIBUTE_UNUSED)
2851{
2852 as_bad (_("invalid syntax for .dn directive"));
2853}
2854
2855static void
2856s_qn (int a ATTRIBUTE_UNUSED)
2857{
2858 as_bad (_("invalid syntax for .qn directive"));
2859}
2860
2861/* The .unreq directive deletes an alias which was previously defined
2862 by .req. For example:
2863
2864 my_alias .req r11
2865 .unreq my_alias */
2866
2867static void
2868s_unreq (int a ATTRIBUTE_UNUSED)
2869{
2870 char * name;
2871 char saved_char;
2872
2873 name = input_line_pointer;
2874
2875 while (*input_line_pointer != 0
2876 && *input_line_pointer != ' '
2877 && *input_line_pointer != '\n')
2878 ++input_line_pointer;
2879
2880 saved_char = *input_line_pointer;
2881 *input_line_pointer = 0;
2882
2883 if (!*name)
2884 as_bad (_("invalid syntax for .unreq directive"));
2885 else
2886 {
2887 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2888 name);
2889
2890 if (!reg)
2891 as_bad (_("unknown register alias '%s'"), name);
2892 else if (reg->builtin)
2893 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2894 name);
2895 else
2896 {
2897 char * p;
2898 char * nbuf;
2899
2900 hash_delete (arm_reg_hsh, name, FALSE);
2901 free ((char *) reg->name);
2902 free (reg->neon);
2903 free (reg);
2904
2905 /* Also locate the all upper case and all lower case versions.
2906 Do not complain if we cannot find one or the other as it
2907 was probably deleted above. */
2908
2909 nbuf = strdup (name);
2910 for (p = nbuf; *p; p++)
2911 *p = TOUPPER (*p);
2912 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2913 if (reg)
2914 {
2915 hash_delete (arm_reg_hsh, nbuf, FALSE);
2916 free ((char *) reg->name);
2917 free (reg->neon);
2918 free (reg);
2919 }
2920
2921 for (p = nbuf; *p; p++)
2922 *p = TOLOWER (*p);
2923 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2924 if (reg)
2925 {
2926 hash_delete (arm_reg_hsh, nbuf, FALSE);
2927 free ((char *) reg->name);
2928 free (reg->neon);
2929 free (reg);
2930 }
2931
2932 free (nbuf);
2933 }
2934 }
2935
2936 *input_line_pointer = saved_char;
2937 demand_empty_rest_of_line ();
2938}
2939
2940/* Directives: Instruction set selection. */
2941
2942#ifdef OBJ_ELF
2943/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2944 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2945 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2946 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2947
2948/* Create a new mapping symbol for the transition to STATE. */
2949
2950static void
2951make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2952{
2953 symbolS * symbolP;
2954 const char * symname;
2955 int type;
2956
2957 switch (state)
2958 {
2959 case MAP_DATA:
2960 symname = "$d";
2961 type = BSF_NO_FLAGS;
2962 break;
2963 case MAP_ARM:
2964 symname = "$a";
2965 type = BSF_NO_FLAGS;
2966 break;
2967 case MAP_THUMB:
2968 symname = "$t";
2969 type = BSF_NO_FLAGS;
2970 break;
2971 default:
2972 abort ();
2973 }
2974
2975 symbolP = symbol_new (symname, now_seg, value, frag);
2976 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2977
2978 switch (state)
2979 {
2980 case MAP_ARM:
2981 THUMB_SET_FUNC (symbolP, 0);
2982 ARM_SET_THUMB (symbolP, 0);
2983 ARM_SET_INTERWORK (symbolP, support_interwork);
2984 break;
2985
2986 case MAP_THUMB:
2987 THUMB_SET_FUNC (symbolP, 1);
2988 ARM_SET_THUMB (symbolP, 1);
2989 ARM_SET_INTERWORK (symbolP, support_interwork);
2990 break;
2991
2992 case MAP_DATA:
2993 default:
2994 break;
2995 }
2996
2997 /* Save the mapping symbols for future reference. Also check that
2998 we do not place two mapping symbols at the same offset within a
2999 frag. We'll handle overlap between frags in
3000 check_mapping_symbols.
3001
3002 If .fill or other data filling directive generates zero sized data,
3003 the mapping symbol for the following code will have the same value
3004 as the one generated for the data filling directive. In this case,
3005 we replace the old symbol with the new one at the same address. */
3006 if (value == 0)
3007 {
3008 if (frag->tc_frag_data.first_map != NULL)
3009 {
3010 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
3011 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
3012 }
3013 frag->tc_frag_data.first_map = symbolP;
3014 }
3015 if (frag->tc_frag_data.last_map != NULL)
3016 {
3017 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
3018 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
3019 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
3020 }
3021 frag->tc_frag_data.last_map = symbolP;
3022}
3023
3024/* We must sometimes convert a region marked as code to data during
3025 code alignment, if an odd number of bytes have to be padded. The
3026 code mapping symbol is pushed to an aligned address. */
3027
3028static void
3029insert_data_mapping_symbol (enum mstate state,
3030 valueT value, fragS *frag, offsetT bytes)
3031{
3032 /* If there was already a mapping symbol, remove it. */
3033 if (frag->tc_frag_data.last_map != NULL
3034 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
3035 {
3036 symbolS *symp = frag->tc_frag_data.last_map;
3037
3038 if (value == 0)
3039 {
3040 know (frag->tc_frag_data.first_map == symp);
3041 frag->tc_frag_data.first_map = NULL;
3042 }
3043 frag->tc_frag_data.last_map = NULL;
3044 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
3045 }
3046
3047 make_mapping_symbol (MAP_DATA, value, frag);
3048 make_mapping_symbol (state, value + bytes, frag);
3049}
3050
3051static void mapping_state_2 (enum mstate state, int max_chars);
3052
3053/* Set the mapping state to STATE. Only call this when about to
3054 emit some STATE bytes to the file. */
3055
3056#define TRANSITION(from, to) (mapstate == (from) && state == (to))
3057void
3058mapping_state (enum mstate state)
3059{
3060 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
3061
3062 if (mapstate == state)
3063 /* The mapping symbol has already been emitted.
3064 There is nothing else to do. */
3065 return;
3066
3067 if (state == MAP_ARM || state == MAP_THUMB)
3068 /* PR gas/12931
3069 All ARM instructions require 4-byte alignment.
3070 (Almost) all Thumb instructions require 2-byte alignment.
3071
3072 When emitting instructions into any section, mark the section
3073 appropriately.
3074
3075 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3076 but themselves require 2-byte alignment; this applies to some
3077 PC- relative forms. However, these cases will involve implicit
3078 literal pool generation or an explicit .align >=2, both of
3079 which will cause the section to me marked with sufficient
3080 alignment. Thus, we don't handle those cases here. */
3081 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
3082
3083 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
3084 /* This case will be evaluated later. */
3085 return;
3086
3087 mapping_state_2 (state, 0);
3088}
3089
3090/* Same as mapping_state, but MAX_CHARS bytes have already been
3091 allocated. Put the mapping symbol that far back. */
3092
3093static void
3094mapping_state_2 (enum mstate state, int max_chars)
3095{
3096 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
3097
3098 if (!SEG_NORMAL (now_seg))
3099 return;
3100
3101 if (mapstate == state)
3102 /* The mapping symbol has already been emitted.
3103 There is nothing else to do. */
3104 return;
3105
3106 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
3107 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
3108 {
3109 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
3110 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
3111
3112 if (add_symbol)
3113 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
3114 }
3115
3116 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
3117 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
3118}
3119#undef TRANSITION
3120#else
3121#define mapping_state(x) ((void)0)
3122#define mapping_state_2(x, y) ((void)0)
3123#endif
3124
3125/* Find the real, Thumb encoded start of a Thumb function. */
3126
3127#ifdef OBJ_COFF
3128static symbolS *
3129find_real_start (symbolS * symbolP)
3130{
3131 char * real_start;
3132 const char * name = S_GET_NAME (symbolP);
3133 symbolS * new_target;
3134
3135 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3136#define STUB_NAME ".real_start_of"
3137
3138 if (name == NULL)
3139 abort ();
3140
3141 /* The compiler may generate BL instructions to local labels because
3142 it needs to perform a branch to a far away location. These labels
3143 do not have a corresponding ".real_start_of" label. We check
3144 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3145 the ".real_start_of" convention for nonlocal branches. */
3146 if (S_IS_LOCAL (symbolP) || name[0] == '.')
3147 return symbolP;
3148
3149 real_start = concat (STUB_NAME, name, NULL);
3150 new_target = symbol_find (real_start);
3151 free (real_start);
3152
3153 if (new_target == NULL)
3154 {
3155 as_warn (_("Failed to find real start of function: %s\n"), name);
3156 new_target = symbolP;
3157 }
3158
3159 return new_target;
3160}
3161#endif
3162
3163static void
3164opcode_select (int width)
3165{
3166 switch (width)
3167 {
3168 case 16:
3169 if (! thumb_mode)
3170 {
3171 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
3172 as_bad (_("selected processor does not support THUMB opcodes"));
3173
3174 thumb_mode = 1;
3175 /* No need to force the alignment, since we will have been
3176 coming from ARM mode, which is word-aligned. */
3177 record_alignment (now_seg, 1);
3178 }
3179 break;
3180
3181 case 32:
3182 if (thumb_mode)
3183 {
3184 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
3185 as_bad (_("selected processor does not support ARM opcodes"));
3186
3187 thumb_mode = 0;
3188
3189 if (!need_pass_2)
3190 frag_align (2, 0, 0);
3191
3192 record_alignment (now_seg, 1);
3193 }
3194 break;
3195
3196 default:
3197 as_bad (_("invalid instruction size selected (%d)"), width);
3198 }
3199}
3200
3201static void
3202s_arm (int ignore ATTRIBUTE_UNUSED)
3203{
3204 opcode_select (32);
3205 demand_empty_rest_of_line ();
3206}
3207
3208static void
3209s_thumb (int ignore ATTRIBUTE_UNUSED)
3210{
3211 opcode_select (16);
3212 demand_empty_rest_of_line ();
3213}
3214
3215static void
3216s_code (int unused ATTRIBUTE_UNUSED)
3217{
3218 int temp;
3219
3220 temp = get_absolute_expression ();
3221 switch (temp)
3222 {
3223 case 16:
3224 case 32:
3225 opcode_select (temp);
3226 break;
3227
3228 default:
3229 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
3230 }
3231}
3232
3233static void
3234s_force_thumb (int ignore ATTRIBUTE_UNUSED)
3235{
3236 /* If we are not already in thumb mode go into it, EVEN if
3237 the target processor does not support thumb instructions.
3238 This is used by gcc/config/arm/lib1funcs.asm for example
3239 to compile interworking support functions even if the
3240 target processor should not support interworking. */
3241 if (! thumb_mode)
3242 {
3243 thumb_mode = 2;
3244 record_alignment (now_seg, 1);
3245 }
3246
3247 demand_empty_rest_of_line ();
3248}
3249
3250static void
3251s_thumb_func (int ignore ATTRIBUTE_UNUSED)
3252{
3253 s_thumb (0);
3254
3255 /* The following label is the name/address of the start of a Thumb function.
3256 We need to know this for the interworking support. */
3257 label_is_thumb_function_name = TRUE;
3258}
3259
3260/* Perform a .set directive, but also mark the alias as
3261 being a thumb function. */
3262
3263static void
3264s_thumb_set (int equiv)
3265{
3266 /* XXX the following is a duplicate of the code for s_set() in read.c
3267 We cannot just call that code as we need to get at the symbol that
3268 is created. */
3269 char * name;
3270 char delim;
3271 char * end_name;
3272 symbolS * symbolP;
3273
3274 /* Especial apologies for the random logic:
3275 This just grew, and could be parsed much more simply!
3276 Dean - in haste. */
3277 delim = get_symbol_name (& name);
3278 end_name = input_line_pointer;
3279 (void) restore_line_pointer (delim);
3280
3281 if (*input_line_pointer != ',')
3282 {
3283 *end_name = 0;
3284 as_bad (_("expected comma after name \"%s\""), name);
3285 *end_name = delim;
3286 ignore_rest_of_line ();
3287 return;
3288 }
3289
3290 input_line_pointer++;
3291 *end_name = 0;
3292
3293 if (name[0] == '.' && name[1] == '\0')
3294 {
3295 /* XXX - this should not happen to .thumb_set. */
3296 abort ();
3297 }
3298
3299 if ((symbolP = symbol_find (name)) == NULL
3300 && (symbolP = md_undefined_symbol (name)) == NULL)
3301 {
3302#ifndef NO_LISTING
3303 /* When doing symbol listings, play games with dummy fragments living
3304 outside the normal fragment chain to record the file and line info
3305 for this symbol. */
3306 if (listing & LISTING_SYMBOLS)
3307 {
3308 extern struct list_info_struct * listing_tail;
3309 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
3310
3311 memset (dummy_frag, 0, sizeof (fragS));
3312 dummy_frag->fr_type = rs_fill;
3313 dummy_frag->line = listing_tail;
3314 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
3315 dummy_frag->fr_symbol = symbolP;
3316 }
3317 else
3318#endif
3319 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
3320
3321#ifdef OBJ_COFF
3322 /* "set" symbols are local unless otherwise specified. */
3323 SF_SET_LOCAL (symbolP);
3324#endif /* OBJ_COFF */
3325 } /* Make a new symbol. */
3326
3327 symbol_table_insert (symbolP);
3328
3329 * end_name = delim;
3330
3331 if (equiv
3332 && S_IS_DEFINED (symbolP)
3333 && S_GET_SEGMENT (symbolP) != reg_section)
3334 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
3335
3336 pseudo_set (symbolP);
3337
3338 demand_empty_rest_of_line ();
3339
3340 /* XXX Now we come to the Thumb specific bit of code. */
3341
3342 THUMB_SET_FUNC (symbolP, 1);
3343 ARM_SET_THUMB (symbolP, 1);
3344#if defined OBJ_ELF || defined OBJ_COFF
3345 ARM_SET_INTERWORK (symbolP, support_interwork);
3346#endif
3347}
3348
3349/* Directives: Mode selection. */
3350
3351/* .syntax [unified|divided] - choose the new unified syntax
3352 (same for Arm and Thumb encoding, modulo slight differences in what
3353 can be represented) or the old divergent syntax for each mode. */
3354static void
3355s_syntax (int unused ATTRIBUTE_UNUSED)
3356{
3357 char *name, delim;
3358
3359 delim = get_symbol_name (& name);
3360
3361 if (!strcasecmp (name, "unified"))
3362 unified_syntax = TRUE;
3363 else if (!strcasecmp (name, "divided"))
3364 unified_syntax = FALSE;
3365 else
3366 {
3367 as_bad (_("unrecognized syntax mode \"%s\""), name);
3368 return;
3369 }
3370 (void) restore_line_pointer (delim);
3371 demand_empty_rest_of_line ();
3372}
3373
3374/* Directives: sectioning and alignment. */
3375
3376static void
3377s_bss (int ignore ATTRIBUTE_UNUSED)
3378{
3379 /* We don't support putting frags in the BSS segment, we fake it by
3380 marking in_bss, then looking at s_skip for clues. */
3381 subseg_set (bss_section, 0);
3382 demand_empty_rest_of_line ();
3383
3384#ifdef md_elf_section_change_hook
3385 md_elf_section_change_hook ();
3386#endif
3387}
3388
3389static void
3390s_even (int ignore ATTRIBUTE_UNUSED)
3391{
3392 /* Never make frag if expect extra pass. */
3393 if (!need_pass_2)
3394 frag_align (1, 0, 0);
3395
3396 record_alignment (now_seg, 1);
3397
3398 demand_empty_rest_of_line ();
3399}
3400
3401/* Directives: CodeComposer Studio. */
3402
3403/* .ref (for CodeComposer Studio syntax only). */
3404static void
3405s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3406{
3407 if (codecomposer_syntax)
3408 ignore_rest_of_line ();
3409 else
3410 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3411}
3412
3413/* If name is not NULL, then it is used for marking the beginning of a
3414 function, whereas if it is NULL then it means the function end. */
3415static void
3416asmfunc_debug (const char * name)
3417{
3418 static const char * last_name = NULL;
3419
3420 if (name != NULL)
3421 {
3422 gas_assert (last_name == NULL);
3423 last_name = name;
3424
3425 if (debug_type == DEBUG_STABS)
3426 stabs_generate_asm_func (name, name);
3427 }
3428 else
3429 {
3430 gas_assert (last_name != NULL);
3431
3432 if (debug_type == DEBUG_STABS)
3433 stabs_generate_asm_endfunc (last_name, last_name);
3434
3435 last_name = NULL;
3436 }
3437}
3438
3439static void
3440s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3441{
3442 if (codecomposer_syntax)
3443 {
3444 switch (asmfunc_state)
3445 {
3446 case OUTSIDE_ASMFUNC:
3447 asmfunc_state = WAITING_ASMFUNC_NAME;
3448 break;
3449
3450 case WAITING_ASMFUNC_NAME:
3451 as_bad (_(".asmfunc repeated."));
3452 break;
3453
3454 case WAITING_ENDASMFUNC:
3455 as_bad (_(".asmfunc without function."));
3456 break;
3457 }
3458 demand_empty_rest_of_line ();
3459 }
3460 else
3461 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3462}
3463
3464static void
3465s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3466{
3467 if (codecomposer_syntax)
3468 {
3469 switch (asmfunc_state)
3470 {
3471 case OUTSIDE_ASMFUNC:
3472 as_bad (_(".endasmfunc without a .asmfunc."));
3473 break;
3474
3475 case WAITING_ASMFUNC_NAME:
3476 as_bad (_(".endasmfunc without function."));
3477 break;
3478
3479 case WAITING_ENDASMFUNC:
3480 asmfunc_state = OUTSIDE_ASMFUNC;
3481 asmfunc_debug (NULL);
3482 break;
3483 }
3484 demand_empty_rest_of_line ();
3485 }
3486 else
3487 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3488}
3489
3490static void
3491s_ccs_def (int name)
3492{
3493 if (codecomposer_syntax)
3494 s_globl (name);
3495 else
3496 as_bad (_(".def pseudo-op only available with -mccs flag."));
3497}
3498
3499/* Directives: Literal pools. */
3500
3501static literal_pool *
3502find_literal_pool (void)
3503{
3504 literal_pool * pool;
3505
3506 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3507 {
3508 if (pool->section == now_seg
3509 && pool->sub_section == now_subseg)
3510 break;
3511 }
3512
3513 return pool;
3514}
3515
3516static literal_pool *
3517find_or_make_literal_pool (void)
3518{
3519 /* Next literal pool ID number. */
3520 static unsigned int latest_pool_num = 1;
3521 literal_pool * pool;
3522
3523 pool = find_literal_pool ();
3524
3525 if (pool == NULL)
3526 {
3527 /* Create a new pool. */
3528 pool = XNEW (literal_pool);
3529 if (! pool)
3530 return NULL;
3531
3532 pool->next_free_entry = 0;
3533 pool->section = now_seg;
3534 pool->sub_section = now_subseg;
3535 pool->next = list_of_pools;
3536 pool->symbol = NULL;
3537 pool->alignment = 2;
3538
3539 /* Add it to the list. */
3540 list_of_pools = pool;
3541 }
3542
3543 /* New pools, and emptied pools, will have a NULL symbol. */
3544 if (pool->symbol == NULL)
3545 {
3546 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3547 (valueT) 0, &zero_address_frag);
3548 pool->id = latest_pool_num ++;
3549 }
3550
3551 /* Done. */
3552 return pool;
3553}
3554
3555/* Add the literal in the global 'inst'
3556 structure to the relevant literal pool. */
3557
3558static int
3559add_to_lit_pool (unsigned int nbytes)
3560{
3561#define PADDING_SLOT 0x1
3562#define LIT_ENTRY_SIZE_MASK 0xFF
3563 literal_pool * pool;
3564 unsigned int entry, pool_size = 0;
3565 bfd_boolean padding_slot_p = FALSE;
3566 unsigned imm1 = 0;
3567 unsigned imm2 = 0;
3568
3569 if (nbytes == 8)
3570 {
3571 imm1 = inst.operands[1].imm;
3572 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3573 : inst.relocs[0].exp.X_unsigned ? 0
3574 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
3575 if (target_big_endian)
3576 {
3577 imm1 = imm2;
3578 imm2 = inst.operands[1].imm;
3579 }
3580 }
3581
3582 pool = find_or_make_literal_pool ();
3583
3584 /* Check if this literal value is already in the pool. */
3585 for (entry = 0; entry < pool->next_free_entry; entry ++)
3586 {
3587 if (nbytes == 4)
3588 {
3589 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3590 && (inst.relocs[0].exp.X_op == O_constant)
3591 && (pool->literals[entry].X_add_number
3592 == inst.relocs[0].exp.X_add_number)
3593 && (pool->literals[entry].X_md == nbytes)
3594 && (pool->literals[entry].X_unsigned
3595 == inst.relocs[0].exp.X_unsigned))
3596 break;
3597
3598 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3599 && (inst.relocs[0].exp.X_op == O_symbol)
3600 && (pool->literals[entry].X_add_number
3601 == inst.relocs[0].exp.X_add_number)
3602 && (pool->literals[entry].X_add_symbol
3603 == inst.relocs[0].exp.X_add_symbol)
3604 && (pool->literals[entry].X_op_symbol
3605 == inst.relocs[0].exp.X_op_symbol)
3606 && (pool->literals[entry].X_md == nbytes))
3607 break;
3608 }
3609 else if ((nbytes == 8)
3610 && !(pool_size & 0x7)
3611 && ((entry + 1) != pool->next_free_entry)
3612 && (pool->literals[entry].X_op == O_constant)
3613 && (pool->literals[entry].X_add_number == (offsetT) imm1)
3614 && (pool->literals[entry].X_unsigned
3615 == inst.relocs[0].exp.X_unsigned)
3616 && (pool->literals[entry + 1].X_op == O_constant)
3617 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
3618 && (pool->literals[entry + 1].X_unsigned
3619 == inst.relocs[0].exp.X_unsigned))
3620 break;
3621
3622 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3623 if (padding_slot_p && (nbytes == 4))
3624 break;
3625
3626 pool_size += 4;
3627 }
3628
3629 /* Do we need to create a new entry? */
3630 if (entry == pool->next_free_entry)
3631 {
3632 if (entry >= MAX_LITERAL_POOL_SIZE)
3633 {
3634 inst.error = _("literal pool overflow");
3635 return FAIL;
3636 }
3637
3638 if (nbytes == 8)
3639 {
3640 /* For 8-byte entries, we align to an 8-byte boundary,
3641 and split it into two 4-byte entries, because on 32-bit
3642 host, 8-byte constants are treated as big num, thus
3643 saved in "generic_bignum" which will be overwritten
3644 by later assignments.
3645
3646 We also need to make sure there is enough space for
3647 the split.
3648
3649 We also check to make sure the literal operand is a
3650 constant number. */
3651 if (!(inst.relocs[0].exp.X_op == O_constant
3652 || inst.relocs[0].exp.X_op == O_big))
3653 {
3654 inst.error = _("invalid type for literal pool");
3655 return FAIL;
3656 }
3657 else if (pool_size & 0x7)
3658 {
3659 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3660 {
3661 inst.error = _("literal pool overflow");
3662 return FAIL;
3663 }
3664
3665 pool->literals[entry] = inst.relocs[0].exp;
3666 pool->literals[entry].X_op = O_constant;
3667 pool->literals[entry].X_add_number = 0;
3668 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3669 pool->next_free_entry += 1;
3670 pool_size += 4;
3671 }
3672 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3673 {
3674 inst.error = _("literal pool overflow");
3675 return FAIL;
3676 }
3677
3678 pool->literals[entry] = inst.relocs[0].exp;
3679 pool->literals[entry].X_op = O_constant;
3680 pool->literals[entry].X_add_number = imm1;
3681 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3682 pool->literals[entry++].X_md = 4;
3683 pool->literals[entry] = inst.relocs[0].exp;
3684 pool->literals[entry].X_op = O_constant;
3685 pool->literals[entry].X_add_number = imm2;
3686 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3687 pool->literals[entry].X_md = 4;
3688 pool->alignment = 3;
3689 pool->next_free_entry += 1;
3690 }
3691 else
3692 {
3693 pool->literals[entry] = inst.relocs[0].exp;
3694 pool->literals[entry].X_md = 4;
3695 }
3696
3697#ifdef OBJ_ELF
3698 /* PR ld/12974: Record the location of the first source line to reference
3699 this entry in the literal pool. If it turns out during linking that the
3700 symbol does not exist we will be able to give an accurate line number for
3701 the (first use of the) missing reference. */
3702 if (debug_type == DEBUG_DWARF2)
3703 dwarf2_where (pool->locs + entry);
3704#endif
3705 pool->next_free_entry += 1;
3706 }
3707 else if (padding_slot_p)
3708 {
3709 pool->literals[entry] = inst.relocs[0].exp;
3710 pool->literals[entry].X_md = nbytes;
3711 }
3712
3713 inst.relocs[0].exp.X_op = O_symbol;
3714 inst.relocs[0].exp.X_add_number = pool_size;
3715 inst.relocs[0].exp.X_add_symbol = pool->symbol;
3716
3717 return SUCCESS;
3718}
3719
3720bfd_boolean
3721tc_start_label_without_colon (void)
3722{
3723 bfd_boolean ret = TRUE;
3724
3725 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3726 {
3727 const char *label = input_line_pointer;
3728
3729 while (!is_end_of_line[(int) label[-1]])
3730 --label;
3731
3732 if (*label == '.')
3733 {
3734 as_bad (_("Invalid label '%s'"), label);
3735 ret = FALSE;
3736 }
3737
3738 asmfunc_debug (label);
3739
3740 asmfunc_state = WAITING_ENDASMFUNC;
3741 }
3742
3743 return ret;
3744}
3745
3746/* Can't use symbol_new here, so have to create a symbol and then at
3747 a later date assign it a value. That's what these functions do. */
3748
3749static void
3750symbol_locate (symbolS * symbolP,
3751 const char * name, /* It is copied, the caller can modify. */
3752 segT segment, /* Segment identifier (SEG_<something>). */
3753 valueT valu, /* Symbol value. */
3754 fragS * frag) /* Associated fragment. */
3755{
3756 size_t name_length;
3757 char * preserved_copy_of_name;
3758
3759 name_length = strlen (name) + 1; /* +1 for \0. */
3760 obstack_grow (&notes, name, name_length);
3761 preserved_copy_of_name = (char *) obstack_finish (&notes);
3762
3763#ifdef tc_canonicalize_symbol_name
3764 preserved_copy_of_name =
3765 tc_canonicalize_symbol_name (preserved_copy_of_name);
3766#endif
3767
3768 S_SET_NAME (symbolP, preserved_copy_of_name);
3769
3770 S_SET_SEGMENT (symbolP, segment);
3771 S_SET_VALUE (symbolP, valu);
3772 symbol_clear_list_pointers (symbolP);
3773
3774 symbol_set_frag (symbolP, frag);
3775
3776 /* Link to end of symbol chain. */
3777 {
3778 extern int symbol_table_frozen;
3779
3780 if (symbol_table_frozen)
3781 abort ();
3782 }
3783
3784 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3785
3786 obj_symbol_new_hook (symbolP);
3787
3788#ifdef tc_symbol_new_hook
3789 tc_symbol_new_hook (symbolP);
3790#endif
3791
3792#ifdef DEBUG_SYMS
3793 verify_symbol_chain (symbol_rootP, symbol_lastP);
3794#endif /* DEBUG_SYMS */
3795}
3796
3797static void
3798s_ltorg (int ignored ATTRIBUTE_UNUSED)
3799{
3800 unsigned int entry;
3801 literal_pool * pool;
3802 char sym_name[20];
3803
3804 pool = find_literal_pool ();
3805 if (pool == NULL
3806 || pool->symbol == NULL
3807 || pool->next_free_entry == 0)
3808 return;
3809
3810 /* Align pool as you have word accesses.
3811 Only make a frag if we have to. */
3812 if (!need_pass_2)
3813 frag_align (pool->alignment, 0, 0);
3814
3815 record_alignment (now_seg, 2);
3816
3817#ifdef OBJ_ELF
3818 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3819 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
3820#endif
3821 sprintf (sym_name, "$$lit_\002%x", pool->id);
3822
3823 symbol_locate (pool->symbol, sym_name, now_seg,
3824 (valueT) frag_now_fix (), frag_now);
3825 symbol_table_insert (pool->symbol);
3826
3827 ARM_SET_THUMB (pool->symbol, thumb_mode);
3828
3829#if defined OBJ_COFF || defined OBJ_ELF
3830 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3831#endif
3832
3833 for (entry = 0; entry < pool->next_free_entry; entry ++)
3834 {
3835#ifdef OBJ_ELF
3836 if (debug_type == DEBUG_DWARF2)
3837 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3838#endif
3839 /* First output the expression in the instruction to the pool. */
3840 emit_expr (&(pool->literals[entry]),
3841 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
3842 }
3843
3844 /* Mark the pool as empty. */
3845 pool->next_free_entry = 0;
3846 pool->symbol = NULL;
3847}
3848
3849#ifdef OBJ_ELF
3850/* Forward declarations for functions below, in the MD interface
3851 section. */
3852static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3853static valueT create_unwind_entry (int);
3854static void start_unwind_section (const segT, int);
3855static void add_unwind_opcode (valueT, int);
3856static void flush_pending_unwind (void);
3857
3858/* Directives: Data. */
3859
3860static void
3861s_arm_elf_cons (int nbytes)
3862{
3863 expressionS exp;
3864
3865#ifdef md_flush_pending_output
3866 md_flush_pending_output ();
3867#endif
3868
3869 if (is_it_end_of_statement ())
3870 {
3871 demand_empty_rest_of_line ();
3872 return;
3873 }
3874
3875#ifdef md_cons_align
3876 md_cons_align (nbytes);
3877#endif
3878
3879 mapping_state (MAP_DATA);
3880 do
3881 {
3882 int reloc;
3883 char *base = input_line_pointer;
3884
3885 expression (& exp);
3886
3887 if (exp.X_op != O_symbol)
3888 emit_expr (&exp, (unsigned int) nbytes);
3889 else
3890 {
3891 char *before_reloc = input_line_pointer;
3892 reloc = parse_reloc (&input_line_pointer);
3893 if (reloc == -1)
3894 {
3895 as_bad (_("unrecognized relocation suffix"));
3896 ignore_rest_of_line ();
3897 return;
3898 }
3899 else if (reloc == BFD_RELOC_UNUSED)
3900 emit_expr (&exp, (unsigned int) nbytes);
3901 else
3902 {
3903 reloc_howto_type *howto = (reloc_howto_type *)
3904 bfd_reloc_type_lookup (stdoutput,
3905 (bfd_reloc_code_real_type) reloc);
3906 int size = bfd_get_reloc_size (howto);
3907
3908 if (reloc == BFD_RELOC_ARM_PLT32)
3909 {
3910 as_bad (_("(plt) is only valid on branch targets"));
3911 reloc = BFD_RELOC_UNUSED;
3912 size = 0;
3913 }
3914
3915 if (size > nbytes)
3916 as_bad (ngettext ("%s relocations do not fit in %d byte",
3917 "%s relocations do not fit in %d bytes",
3918 nbytes),
3919 howto->name, nbytes);
3920 else
3921 {
3922 /* We've parsed an expression stopping at O_symbol.
3923 But there may be more expression left now that we
3924 have parsed the relocation marker. Parse it again.
3925 XXX Surely there is a cleaner way to do this. */
3926 char *p = input_line_pointer;
3927 int offset;
3928 char *save_buf = XNEWVEC (char, input_line_pointer - base);
3929
3930 memcpy (save_buf, base, input_line_pointer - base);
3931 memmove (base + (input_line_pointer - before_reloc),
3932 base, before_reloc - base);
3933
3934 input_line_pointer = base + (input_line_pointer-before_reloc);
3935 expression (&exp);
3936 memcpy (base, save_buf, p - base);
3937
3938 offset = nbytes - size;
3939 p = frag_more (nbytes);
3940 memset (p, 0, nbytes);
3941 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3942 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3943 free (save_buf);
3944 }
3945 }
3946 }
3947 }
3948 while (*input_line_pointer++ == ',');
3949
3950 /* Put terminator back into stream. */
3951 input_line_pointer --;
3952 demand_empty_rest_of_line ();
3953}
3954
3955/* Emit an expression containing a 32-bit thumb instruction.
3956 Implementation based on put_thumb32_insn. */
3957
3958static void
3959emit_thumb32_expr (expressionS * exp)
3960{
3961 expressionS exp_high = *exp;
3962
3963 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3964 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3965 exp->X_add_number &= 0xffff;
3966 emit_expr (exp, (unsigned int) THUMB_SIZE);
3967}
3968
3969/* Guess the instruction size based on the opcode. */
3970
3971static int
3972thumb_insn_size (int opcode)
3973{
3974 if ((unsigned int) opcode < 0xe800u)
3975 return 2;
3976 else if ((unsigned int) opcode >= 0xe8000000u)
3977 return 4;
3978 else
3979 return 0;
3980}
3981
3982static bfd_boolean
3983emit_insn (expressionS *exp, int nbytes)
3984{
3985 int size = 0;
3986
3987 if (exp->X_op == O_constant)
3988 {
3989 size = nbytes;
3990
3991 if (size == 0)
3992 size = thumb_insn_size (exp->X_add_number);
3993
3994 if (size != 0)
3995 {
3996 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3997 {
3998 as_bad (_(".inst.n operand too big. "\
3999 "Use .inst.w instead"));
4000 size = 0;
4001 }
4002 else
4003 {
4004 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
4005 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0);
4006 else
4007 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
4008
4009 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
4010 emit_thumb32_expr (exp);
4011 else
4012 emit_expr (exp, (unsigned int) size);
4013
4014 it_fsm_post_encode ();
4015 }
4016 }
4017 else
4018 as_bad (_("cannot determine Thumb instruction size. " \
4019 "Use .inst.n/.inst.w instead"));
4020 }
4021 else
4022 as_bad (_("constant expression required"));
4023
4024 return (size != 0);
4025}
4026
4027/* Like s_arm_elf_cons but do not use md_cons_align and
4028 set the mapping state to MAP_ARM/MAP_THUMB. */
4029
4030static void
4031s_arm_elf_inst (int nbytes)
4032{
4033 if (is_it_end_of_statement ())
4034 {
4035 demand_empty_rest_of_line ();
4036 return;
4037 }
4038
4039 /* Calling mapping_state () here will not change ARM/THUMB,
4040 but will ensure not to be in DATA state. */
4041
4042 if (thumb_mode)
4043 mapping_state (MAP_THUMB);
4044 else
4045 {
4046 if (nbytes != 0)
4047 {
4048 as_bad (_("width suffixes are invalid in ARM mode"));
4049 ignore_rest_of_line ();
4050 return;
4051 }
4052
4053 nbytes = 4;
4054
4055 mapping_state (MAP_ARM);
4056 }
4057
4058 do
4059 {
4060 expressionS exp;
4061
4062 expression (& exp);
4063
4064 if (! emit_insn (& exp, nbytes))
4065 {
4066 ignore_rest_of_line ();
4067 return;
4068 }
4069 }
4070 while (*input_line_pointer++ == ',');
4071
4072 /* Put terminator back into stream. */
4073 input_line_pointer --;
4074 demand_empty_rest_of_line ();
4075}
4076
4077/* Parse a .rel31 directive. */
4078
4079static void
4080s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
4081{
4082 expressionS exp;
4083 char *p;
4084 valueT highbit;
4085
4086 highbit = 0;
4087 if (*input_line_pointer == '1')
4088 highbit = 0x80000000;
4089 else if (*input_line_pointer != '0')
4090 as_bad (_("expected 0 or 1"));
4091
4092 input_line_pointer++;
4093 if (*input_line_pointer != ',')
4094 as_bad (_("missing comma"));
4095 input_line_pointer++;
4096
4097#ifdef md_flush_pending_output
4098 md_flush_pending_output ();
4099#endif
4100
4101#ifdef md_cons_align
4102 md_cons_align (4);
4103#endif
4104
4105 mapping_state (MAP_DATA);
4106
4107 expression (&exp);
4108
4109 p = frag_more (4);
4110 md_number_to_chars (p, highbit, 4);
4111 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
4112 BFD_RELOC_ARM_PREL31);
4113
4114 demand_empty_rest_of_line ();
4115}
4116
4117/* Directives: AEABI stack-unwind tables. */
4118
4119/* Parse an unwind_fnstart directive. Simply records the current location. */
4120
4121static void
4122s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
4123{
4124 demand_empty_rest_of_line ();
4125 if (unwind.proc_start)
4126 {
4127 as_bad (_("duplicate .fnstart directive"));
4128 return;
4129 }
4130
4131 /* Mark the start of the function. */
4132 unwind.proc_start = expr_build_dot ();
4133
4134 /* Reset the rest of the unwind info. */
4135 unwind.opcode_count = 0;
4136 unwind.table_entry = NULL;
4137 unwind.personality_routine = NULL;
4138 unwind.personality_index = -1;
4139 unwind.frame_size = 0;
4140 unwind.fp_offset = 0;
4141 unwind.fp_reg = REG_SP;
4142 unwind.fp_used = 0;
4143 unwind.sp_restored = 0;
4144}
4145
4146
4147/* Parse a handlerdata directive. Creates the exception handling table entry
4148 for the function. */
4149
4150static void
4151s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
4152{
4153 demand_empty_rest_of_line ();
4154 if (!unwind.proc_start)
4155 as_bad (MISSING_FNSTART);
4156
4157 if (unwind.table_entry)
4158 as_bad (_("duplicate .handlerdata directive"));
4159
4160 create_unwind_entry (1);
4161}
4162
4163/* Parse an unwind_fnend directive. Generates the index table entry. */
4164
4165static void
4166s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
4167{
4168 long where;
4169 char *ptr;
4170 valueT val;
4171 unsigned int marked_pr_dependency;
4172
4173 demand_empty_rest_of_line ();
4174
4175 if (!unwind.proc_start)
4176 {
4177 as_bad (_(".fnend directive without .fnstart"));
4178 return;
4179 }
4180
4181 /* Add eh table entry. */
4182 if (unwind.table_entry == NULL)
4183 val = create_unwind_entry (0);
4184 else
4185 val = 0;
4186
4187 /* Add index table entry. This is two words. */
4188 start_unwind_section (unwind.saved_seg, 1);
4189 frag_align (2, 0, 0);
4190 record_alignment (now_seg, 2);
4191
4192 ptr = frag_more (8);
4193 memset (ptr, 0, 8);
4194 where = frag_now_fix () - 8;
4195
4196 /* Self relative offset of the function start. */
4197 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
4198 BFD_RELOC_ARM_PREL31);
4199
4200 /* Indicate dependency on EHABI-defined personality routines to the
4201 linker, if it hasn't been done already. */
4202 marked_pr_dependency
4203 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
4204 if (unwind.personality_index >= 0 && unwind.personality_index < 3
4205 && !(marked_pr_dependency & (1 << unwind.personality_index)))
4206 {
4207 static const char *const name[] =
4208 {
4209 "__aeabi_unwind_cpp_pr0",
4210 "__aeabi_unwind_cpp_pr1",
4211 "__aeabi_unwind_cpp_pr2"
4212 };
4213 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
4214 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
4215 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
4216 |= 1 << unwind.personality_index;
4217 }
4218
4219 if (val)
4220 /* Inline exception table entry. */
4221 md_number_to_chars (ptr + 4, val, 4);
4222 else
4223 /* Self relative offset of the table entry. */
4224 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
4225 BFD_RELOC_ARM_PREL31);
4226
4227 /* Restore the original section. */
4228 subseg_set (unwind.saved_seg, unwind.saved_subseg);
4229
4230 unwind.proc_start = NULL;
4231}
4232
4233
4234/* Parse an unwind_cantunwind directive. */
4235
4236static void
4237s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
4238{
4239 demand_empty_rest_of_line ();
4240 if (!unwind.proc_start)
4241 as_bad (MISSING_FNSTART);
4242
4243 if (unwind.personality_routine || unwind.personality_index != -1)
4244 as_bad (_("personality routine specified for cantunwind frame"));
4245
4246 unwind.personality_index = -2;
4247}
4248
4249
4250/* Parse a personalityindex directive. */
4251
4252static void
4253s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
4254{
4255 expressionS exp;
4256
4257 if (!unwind.proc_start)
4258 as_bad (MISSING_FNSTART);
4259
4260 if (unwind.personality_routine || unwind.personality_index != -1)
4261 as_bad (_("duplicate .personalityindex directive"));
4262
4263 expression (&exp);
4264
4265 if (exp.X_op != O_constant
4266 || exp.X_add_number < 0 || exp.X_add_number > 15)
4267 {
4268 as_bad (_("bad personality routine number"));
4269 ignore_rest_of_line ();
4270 return;
4271 }
4272
4273 unwind.personality_index = exp.X_add_number;
4274
4275 demand_empty_rest_of_line ();
4276}
4277
4278
4279/* Parse a personality directive. */
4280
4281static void
4282s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
4283{
4284 char *name, *p, c;
4285
4286 if (!unwind.proc_start)
4287 as_bad (MISSING_FNSTART);
4288
4289 if (unwind.personality_routine || unwind.personality_index != -1)
4290 as_bad (_("duplicate .personality directive"));
4291
4292 c = get_symbol_name (& name);
4293 p = input_line_pointer;
4294 if (c == '"')
4295 ++ input_line_pointer;
4296 unwind.personality_routine = symbol_find_or_make (name);
4297 *p = c;
4298 demand_empty_rest_of_line ();
4299}
4300
4301
4302/* Parse a directive saving core registers. */
4303
4304static void
4305s_arm_unwind_save_core (void)
4306{
4307 valueT op;
4308 long range;
4309 int n;
4310
4311 range = parse_reg_list (&input_line_pointer, REGLIST_RN);
4312 if (range == FAIL)
4313 {
4314 as_bad (_("expected register list"));
4315 ignore_rest_of_line ();
4316 return;
4317 }
4318
4319 demand_empty_rest_of_line ();
4320
4321 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4322 into .unwind_save {..., sp...}. We aren't bothered about the value of
4323 ip because it is clobbered by calls. */
4324 if (unwind.sp_restored && unwind.fp_reg == 12
4325 && (range & 0x3000) == 0x1000)
4326 {
4327 unwind.opcode_count--;
4328 unwind.sp_restored = 0;
4329 range = (range | 0x2000) & ~0x1000;
4330 unwind.pending_offset = 0;
4331 }
4332
4333 /* Pop r4-r15. */
4334 if (range & 0xfff0)
4335 {
4336 /* See if we can use the short opcodes. These pop a block of up to 8
4337 registers starting with r4, plus maybe r14. */
4338 for (n = 0; n < 8; n++)
4339 {
4340 /* Break at the first non-saved register. */
4341 if ((range & (1 << (n + 4))) == 0)
4342 break;
4343 }
4344 /* See if there are any other bits set. */
4345 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
4346 {
4347 /* Use the long form. */
4348 op = 0x8000 | ((range >> 4) & 0xfff);
4349 add_unwind_opcode (op, 2);
4350 }
4351 else
4352 {
4353 /* Use the short form. */
4354 if (range & 0x4000)
4355 op = 0xa8; /* Pop r14. */
4356 else
4357 op = 0xa0; /* Do not pop r14. */
4358 op |= (n - 1);
4359 add_unwind_opcode (op, 1);
4360 }
4361 }
4362
4363 /* Pop r0-r3. */
4364 if (range & 0xf)
4365 {
4366 op = 0xb100 | (range & 0xf);
4367 add_unwind_opcode (op, 2);
4368 }
4369
4370 /* Record the number of bytes pushed. */
4371 for (n = 0; n < 16; n++)
4372 {
4373 if (range & (1 << n))
4374 unwind.frame_size += 4;
4375 }
4376}
4377
4378
4379/* Parse a directive saving FPA registers. */
4380
4381static void
4382s_arm_unwind_save_fpa (int reg)
4383{
4384 expressionS exp;
4385 int num_regs;
4386 valueT op;
4387
4388 /* Get Number of registers to transfer. */
4389 if (skip_past_comma (&input_line_pointer) != FAIL)
4390 expression (&exp);
4391 else
4392 exp.X_op = O_illegal;
4393
4394 if (exp.X_op != O_constant)
4395 {
4396 as_bad (_("expected , <constant>"));
4397 ignore_rest_of_line ();
4398 return;
4399 }
4400
4401 num_regs = exp.X_add_number;
4402
4403 if (num_regs < 1 || num_regs > 4)
4404 {
4405 as_bad (_("number of registers must be in the range [1:4]"));
4406 ignore_rest_of_line ();
4407 return;
4408 }
4409
4410 demand_empty_rest_of_line ();
4411
4412 if (reg == 4)
4413 {
4414 /* Short form. */
4415 op = 0xb4 | (num_regs - 1);
4416 add_unwind_opcode (op, 1);
4417 }
4418 else
4419 {
4420 /* Long form. */
4421 op = 0xc800 | (reg << 4) | (num_regs - 1);
4422 add_unwind_opcode (op, 2);
4423 }
4424 unwind.frame_size += num_regs * 12;
4425}
4426
4427
4428/* Parse a directive saving VFP registers for ARMv6 and above. */
4429
4430static void
4431s_arm_unwind_save_vfp_armv6 (void)
4432{
4433 int count;
4434 unsigned int start;
4435 valueT op;
4436 int num_vfpv3_regs = 0;
4437 int num_regs_below_16;
4438 bfd_boolean partial_match;
4439
4440 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
4441 &partial_match);
4442 if (count == FAIL)
4443 {
4444 as_bad (_("expected register list"));
4445 ignore_rest_of_line ();
4446 return;
4447 }
4448
4449 demand_empty_rest_of_line ();
4450
4451 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4452 than FSTMX/FLDMX-style ones). */
4453
4454 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4455 if (start >= 16)
4456 num_vfpv3_regs = count;
4457 else if (start + count > 16)
4458 num_vfpv3_regs = start + count - 16;
4459
4460 if (num_vfpv3_regs > 0)
4461 {
4462 int start_offset = start > 16 ? start - 16 : 0;
4463 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4464 add_unwind_opcode (op, 2);
4465 }
4466
4467 /* Generate opcode for registers numbered in the range 0 .. 15. */
4468 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
4469 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
4470 if (num_regs_below_16 > 0)
4471 {
4472 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4473 add_unwind_opcode (op, 2);
4474 }
4475
4476 unwind.frame_size += count * 8;
4477}
4478
4479
4480/* Parse a directive saving VFP registers for pre-ARMv6. */
4481
4482static void
4483s_arm_unwind_save_vfp (void)
4484{
4485 int count;
4486 unsigned int reg;
4487 valueT op;
4488 bfd_boolean partial_match;
4489
4490 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D,
4491 &partial_match);
4492 if (count == FAIL)
4493 {
4494 as_bad (_("expected register list"));
4495 ignore_rest_of_line ();
4496 return;
4497 }
4498
4499 demand_empty_rest_of_line ();
4500
4501 if (reg == 8)
4502 {
4503 /* Short form. */
4504 op = 0xb8 | (count - 1);
4505 add_unwind_opcode (op, 1);
4506 }
4507 else
4508 {
4509 /* Long form. */
4510 op = 0xb300 | (reg << 4) | (count - 1);
4511 add_unwind_opcode (op, 2);
4512 }
4513 unwind.frame_size += count * 8 + 4;
4514}
4515
4516
4517/* Parse a directive saving iWMMXt data registers. */
4518
4519static void
4520s_arm_unwind_save_mmxwr (void)
4521{
4522 int reg;
4523 int hi_reg;
4524 int i;
4525 unsigned mask = 0;
4526 valueT op;
4527
4528 if (*input_line_pointer == '{')
4529 input_line_pointer++;
4530
4531 do
4532 {
4533 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4534
4535 if (reg == FAIL)
4536 {
4537 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4538 goto error;
4539 }
4540
4541 if (mask >> reg)
4542 as_tsktsk (_("register list not in ascending order"));
4543 mask |= 1 << reg;
4544
4545 if (*input_line_pointer == '-')
4546 {
4547 input_line_pointer++;
4548 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4549 if (hi_reg == FAIL)
4550 {
4551 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4552 goto error;
4553 }
4554 else if (reg >= hi_reg)
4555 {
4556 as_bad (_("bad register range"));
4557 goto error;
4558 }
4559 for (; reg < hi_reg; reg++)
4560 mask |= 1 << reg;
4561 }
4562 }
4563 while (skip_past_comma (&input_line_pointer) != FAIL);
4564
4565 skip_past_char (&input_line_pointer, '}');
4566
4567 demand_empty_rest_of_line ();
4568
4569 /* Generate any deferred opcodes because we're going to be looking at
4570 the list. */
4571 flush_pending_unwind ();
4572
4573 for (i = 0; i < 16; i++)
4574 {
4575 if (mask & (1 << i))
4576 unwind.frame_size += 8;
4577 }
4578
4579 /* Attempt to combine with a previous opcode. We do this because gcc
4580 likes to output separate unwind directives for a single block of
4581 registers. */
4582 if (unwind.opcode_count > 0)
4583 {
4584 i = unwind.opcodes[unwind.opcode_count - 1];
4585 if ((i & 0xf8) == 0xc0)
4586 {
4587 i &= 7;
4588 /* Only merge if the blocks are contiguous. */
4589 if (i < 6)
4590 {
4591 if ((mask & 0xfe00) == (1 << 9))
4592 {
4593 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4594 unwind.opcode_count--;
4595 }
4596 }
4597 else if (i == 6 && unwind.opcode_count >= 2)
4598 {
4599 i = unwind.opcodes[unwind.opcode_count - 2];
4600 reg = i >> 4;
4601 i &= 0xf;
4602
4603 op = 0xffff << (reg - 1);
4604 if (reg > 0
4605 && ((mask & op) == (1u << (reg - 1))))
4606 {
4607 op = (1 << (reg + i + 1)) - 1;
4608 op &= ~((1 << reg) - 1);
4609 mask |= op;
4610 unwind.opcode_count -= 2;
4611 }
4612 }
4613 }
4614 }
4615
4616 hi_reg = 15;
4617 /* We want to generate opcodes in the order the registers have been
4618 saved, ie. descending order. */
4619 for (reg = 15; reg >= -1; reg--)
4620 {
4621 /* Save registers in blocks. */
4622 if (reg < 0
4623 || !(mask & (1 << reg)))
4624 {
4625 /* We found an unsaved reg. Generate opcodes to save the
4626 preceding block. */
4627 if (reg != hi_reg)
4628 {
4629 if (reg == 9)
4630 {
4631 /* Short form. */
4632 op = 0xc0 | (hi_reg - 10);
4633 add_unwind_opcode (op, 1);
4634 }
4635 else
4636 {
4637 /* Long form. */
4638 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4639 add_unwind_opcode (op, 2);
4640 }
4641 }
4642 hi_reg = reg - 1;
4643 }
4644 }
4645
4646 return;
4647 error:
4648 ignore_rest_of_line ();
4649}
4650
4651static void
4652s_arm_unwind_save_mmxwcg (void)
4653{
4654 int reg;
4655 int hi_reg;
4656 unsigned mask = 0;
4657 valueT op;
4658
4659 if (*input_line_pointer == '{')
4660 input_line_pointer++;
4661
4662 skip_whitespace (input_line_pointer);
4663
4664 do
4665 {
4666 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4667
4668 if (reg == FAIL)
4669 {
4670 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4671 goto error;
4672 }
4673
4674 reg -= 8;
4675 if (mask >> reg)
4676 as_tsktsk (_("register list not in ascending order"));
4677 mask |= 1 << reg;
4678
4679 if (*input_line_pointer == '-')
4680 {
4681 input_line_pointer++;
4682 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4683 if (hi_reg == FAIL)
4684 {
4685 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4686 goto error;
4687 }
4688 else if (reg >= hi_reg)
4689 {
4690 as_bad (_("bad register range"));
4691 goto error;
4692 }
4693 for (; reg < hi_reg; reg++)
4694 mask |= 1 << reg;
4695 }
4696 }
4697 while (skip_past_comma (&input_line_pointer) != FAIL);
4698
4699 skip_past_char (&input_line_pointer, '}');
4700
4701 demand_empty_rest_of_line ();
4702
4703 /* Generate any deferred opcodes because we're going to be looking at
4704 the list. */
4705 flush_pending_unwind ();
4706
4707 for (reg = 0; reg < 16; reg++)
4708 {
4709 if (mask & (1 << reg))
4710 unwind.frame_size += 4;
4711 }
4712 op = 0xc700 | mask;
4713 add_unwind_opcode (op, 2);
4714 return;
4715 error:
4716 ignore_rest_of_line ();
4717}
4718
4719
4720/* Parse an unwind_save directive.
4721 If the argument is non-zero, this is a .vsave directive. */
4722
4723static void
4724s_arm_unwind_save (int arch_v6)
4725{
4726 char *peek;
4727 struct reg_entry *reg;
4728 bfd_boolean had_brace = FALSE;
4729
4730 if (!unwind.proc_start)
4731 as_bad (MISSING_FNSTART);
4732
4733 /* Figure out what sort of save we have. */
4734 peek = input_line_pointer;
4735
4736 if (*peek == '{')
4737 {
4738 had_brace = TRUE;
4739 peek++;
4740 }
4741
4742 reg = arm_reg_parse_multi (&peek);
4743
4744 if (!reg)
4745 {
4746 as_bad (_("register expected"));
4747 ignore_rest_of_line ();
4748 return;
4749 }
4750
4751 switch (reg->type)
4752 {
4753 case REG_TYPE_FN:
4754 if (had_brace)
4755 {
4756 as_bad (_("FPA .unwind_save does not take a register list"));
4757 ignore_rest_of_line ();
4758 return;
4759 }
4760 input_line_pointer = peek;
4761 s_arm_unwind_save_fpa (reg->number);
4762 return;
4763
4764 case REG_TYPE_RN:
4765 s_arm_unwind_save_core ();
4766 return;
4767
4768 case REG_TYPE_VFD:
4769 if (arch_v6)
4770 s_arm_unwind_save_vfp_armv6 ();
4771 else
4772 s_arm_unwind_save_vfp ();
4773 return;
4774
4775 case REG_TYPE_MMXWR:
4776 s_arm_unwind_save_mmxwr ();
4777 return;
4778
4779 case REG_TYPE_MMXWCG:
4780 s_arm_unwind_save_mmxwcg ();
4781 return;
4782
4783 default:
4784 as_bad (_(".unwind_save does not support this kind of register"));
4785 ignore_rest_of_line ();
4786 }
4787}
4788
4789
4790/* Parse an unwind_movsp directive. */
4791
4792static void
4793s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4794{
4795 int reg;
4796 valueT op;
4797 int offset;
4798
4799 if (!unwind.proc_start)
4800 as_bad (MISSING_FNSTART);
4801
4802 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4803 if (reg == FAIL)
4804 {
4805 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4806 ignore_rest_of_line ();
4807 return;
4808 }
4809
4810 /* Optional constant. */
4811 if (skip_past_comma (&input_line_pointer) != FAIL)
4812 {
4813 if (immediate_for_directive (&offset) == FAIL)
4814 return;
4815 }
4816 else
4817 offset = 0;
4818
4819 demand_empty_rest_of_line ();
4820
4821 if (reg == REG_SP || reg == REG_PC)
4822 {
4823 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4824 return;
4825 }
4826
4827 if (unwind.fp_reg != REG_SP)
4828 as_bad (_("unexpected .unwind_movsp directive"));
4829
4830 /* Generate opcode to restore the value. */
4831 op = 0x90 | reg;
4832 add_unwind_opcode (op, 1);
4833
4834 /* Record the information for later. */
4835 unwind.fp_reg = reg;
4836 unwind.fp_offset = unwind.frame_size - offset;
4837 unwind.sp_restored = 1;
4838}
4839
4840/* Parse an unwind_pad directive. */
4841
4842static void
4843s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4844{
4845 int offset;
4846
4847 if (!unwind.proc_start)
4848 as_bad (MISSING_FNSTART);
4849
4850 if (immediate_for_directive (&offset) == FAIL)
4851 return;
4852
4853 if (offset & 3)
4854 {
4855 as_bad (_("stack increment must be multiple of 4"));
4856 ignore_rest_of_line ();
4857 return;
4858 }
4859
4860 /* Don't generate any opcodes, just record the details for later. */
4861 unwind.frame_size += offset;
4862 unwind.pending_offset += offset;
4863
4864 demand_empty_rest_of_line ();
4865}
4866
4867/* Parse an unwind_setfp directive. */
4868
4869static void
4870s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4871{
4872 int sp_reg;
4873 int fp_reg;
4874 int offset;
4875
4876 if (!unwind.proc_start)
4877 as_bad (MISSING_FNSTART);
4878
4879 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4880 if (skip_past_comma (&input_line_pointer) == FAIL)
4881 sp_reg = FAIL;
4882 else
4883 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4884
4885 if (fp_reg == FAIL || sp_reg == FAIL)
4886 {
4887 as_bad (_("expected <reg>, <reg>"));
4888 ignore_rest_of_line ();
4889 return;
4890 }
4891
4892 /* Optional constant. */
4893 if (skip_past_comma (&input_line_pointer) != FAIL)
4894 {
4895 if (immediate_for_directive (&offset) == FAIL)
4896 return;
4897 }
4898 else
4899 offset = 0;
4900
4901 demand_empty_rest_of_line ();
4902
4903 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4904 {
4905 as_bad (_("register must be either sp or set by a previous"
4906 "unwind_movsp directive"));
4907 return;
4908 }
4909
4910 /* Don't generate any opcodes, just record the information for later. */
4911 unwind.fp_reg = fp_reg;
4912 unwind.fp_used = 1;
4913 if (sp_reg == REG_SP)
4914 unwind.fp_offset = unwind.frame_size - offset;
4915 else
4916 unwind.fp_offset -= offset;
4917}
4918
4919/* Parse an unwind_raw directive. */
4920
4921static void
4922s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4923{
4924 expressionS exp;
4925 /* This is an arbitrary limit. */
4926 unsigned char op[16];
4927 int count;
4928
4929 if (!unwind.proc_start)
4930 as_bad (MISSING_FNSTART);
4931
4932 expression (&exp);
4933 if (exp.X_op == O_constant
4934 && skip_past_comma (&input_line_pointer) != FAIL)
4935 {
4936 unwind.frame_size += exp.X_add_number;
4937 expression (&exp);
4938 }
4939 else
4940 exp.X_op = O_illegal;
4941
4942 if (exp.X_op != O_constant)
4943 {
4944 as_bad (_("expected <offset>, <opcode>"));
4945 ignore_rest_of_line ();
4946 return;
4947 }
4948
4949 count = 0;
4950
4951 /* Parse the opcode. */
4952 for (;;)
4953 {
4954 if (count >= 16)
4955 {
4956 as_bad (_("unwind opcode too long"));
4957 ignore_rest_of_line ();
4958 }
4959 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4960 {
4961 as_bad (_("invalid unwind opcode"));
4962 ignore_rest_of_line ();
4963 return;
4964 }
4965 op[count++] = exp.X_add_number;
4966
4967 /* Parse the next byte. */
4968 if (skip_past_comma (&input_line_pointer) == FAIL)
4969 break;
4970
4971 expression (&exp);
4972 }
4973
4974 /* Add the opcode bytes in reverse order. */
4975 while (count--)
4976 add_unwind_opcode (op[count], 1);
4977
4978 demand_empty_rest_of_line ();
4979}
4980
4981
4982/* Parse a .eabi_attribute directive. */
4983
4984static void
4985s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4986{
4987 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4988
4989 if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4990 attributes_set_explicitly[tag] = 1;
4991}
4992
4993/* Emit a tls fix for the symbol. */
4994
4995static void
4996s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4997{
4998 char *p;
4999 expressionS exp;
5000#ifdef md_flush_pending_output
5001 md_flush_pending_output ();
5002#endif
5003
5004#ifdef md_cons_align
5005 md_cons_align (4);
5006#endif
5007
5008 /* Since we're just labelling the code, there's no need to define a
5009 mapping symbol. */
5010 expression (&exp);
5011 p = obstack_next_free (&frchain_now->frch_obstack);
5012 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
5013 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
5014 : BFD_RELOC_ARM_TLS_DESCSEQ);
5015}
5016#endif /* OBJ_ELF */
5017
5018static void s_arm_arch (int);
5019static void s_arm_object_arch (int);
5020static void s_arm_cpu (int);
5021static void s_arm_fpu (int);
5022static void s_arm_arch_extension (int);
5023
5024#ifdef TE_PE
5025
5026static void
5027pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
5028{
5029 expressionS exp;
5030
5031 do
5032 {
5033 expression (&exp);
5034 if (exp.X_op == O_symbol)
5035 exp.X_op = O_secrel;
5036
5037 emit_expr (&exp, 4);
5038 }
5039 while (*input_line_pointer++ == ',');
5040
5041 input_line_pointer--;
5042 demand_empty_rest_of_line ();
5043}
5044#endif /* TE_PE */
5045
5046int
5047arm_is_largest_exponent_ok (int precision)
5048{
5049 /* precision == 1 ensures that this will only return
5050 true for 16 bit floats. */
5051 return (precision == 1) && (fp16_format == ARM_FP16_FORMAT_ALTERNATIVE);
5052}
5053
5054static void
5055set_fp16_format (int dummy ATTRIBUTE_UNUSED)
5056{
5057 char saved_char;
5058 char* name;
5059 enum fp_16bit_format new_format;
5060
5061 new_format = ARM_FP16_FORMAT_DEFAULT;
5062
5063 name = input_line_pointer;
5064 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
5065 input_line_pointer++;
5066
5067 saved_char = *input_line_pointer;
5068 *input_line_pointer = 0;
5069
5070 if (strcasecmp (name, "ieee") == 0)
5071 new_format = ARM_FP16_FORMAT_IEEE;
5072 else if (strcasecmp (name, "alternative") == 0)
5073 new_format = ARM_FP16_FORMAT_ALTERNATIVE;
5074 else
5075 {
5076 as_bad (_("unrecognised float16 format \"%s\""), name);
5077 goto cleanup;
5078 }
5079
5080 /* Only set fp16_format if it is still the default (aka not already
5081 been set yet). */
5082 if (fp16_format == ARM_FP16_FORMAT_DEFAULT)
5083 fp16_format = new_format;
5084 else
5085 {
5086 if (new_format != fp16_format)
5087 as_warn (_("float16 format cannot be set more than once, ignoring."));
5088 }
5089
5090 cleanup:
5091 *input_line_pointer = saved_char;
5092 ignore_rest_of_line ();
5093}
5094
5095/* This table describes all the machine specific pseudo-ops the assembler
5096 has to support. The fields are:
5097 pseudo-op name without dot
5098 function to call to execute this pseudo-op
5099 Integer arg to pass to the function. */
5100
5101const pseudo_typeS md_pseudo_table[] =
5102{
5103 /* Never called because '.req' does not start a line. */
5104 { "req", s_req, 0 },
5105 /* Following two are likewise never called. */
5106 { "dn", s_dn, 0 },
5107 { "qn", s_qn, 0 },
5108 { "unreq", s_unreq, 0 },
5109 { "bss", s_bss, 0 },
5110 { "align", s_align_ptwo, 2 },
5111 { "arm", s_arm, 0 },
5112 { "thumb", s_thumb, 0 },
5113 { "code", s_code, 0 },
5114 { "force_thumb", s_force_thumb, 0 },
5115 { "thumb_func", s_thumb_func, 0 },
5116 { "thumb_set", s_thumb_set, 0 },
5117 { "even", s_even, 0 },
5118 { "ltorg", s_ltorg, 0 },
5119 { "pool", s_ltorg, 0 },
5120 { "syntax", s_syntax, 0 },
5121 { "cpu", s_arm_cpu, 0 },
5122 { "arch", s_arm_arch, 0 },
5123 { "object_arch", s_arm_object_arch, 0 },
5124 { "fpu", s_arm_fpu, 0 },
5125 { "arch_extension", s_arm_arch_extension, 0 },
5126#ifdef OBJ_ELF
5127 { "word", s_arm_elf_cons, 4 },
5128 { "long", s_arm_elf_cons, 4 },
5129 { "inst.n", s_arm_elf_inst, 2 },
5130 { "inst.w", s_arm_elf_inst, 4 },
5131 { "inst", s_arm_elf_inst, 0 },
5132 { "rel31", s_arm_rel31, 0 },
5133 { "fnstart", s_arm_unwind_fnstart, 0 },
5134 { "fnend", s_arm_unwind_fnend, 0 },
5135 { "cantunwind", s_arm_unwind_cantunwind, 0 },
5136 { "personality", s_arm_unwind_personality, 0 },
5137 { "personalityindex", s_arm_unwind_personalityindex, 0 },
5138 { "handlerdata", s_arm_unwind_handlerdata, 0 },
5139 { "save", s_arm_unwind_save, 0 },
5140 { "vsave", s_arm_unwind_save, 1 },
5141 { "movsp", s_arm_unwind_movsp, 0 },
5142 { "pad", s_arm_unwind_pad, 0 },
5143 { "setfp", s_arm_unwind_setfp, 0 },
5144 { "unwind_raw", s_arm_unwind_raw, 0 },
5145 { "eabi_attribute", s_arm_eabi_attribute, 0 },
5146 { "tlsdescseq", s_arm_tls_descseq, 0 },
5147#else
5148 { "word", cons, 4},
5149
5150 /* These are used for dwarf. */
5151 {"2byte", cons, 2},
5152 {"4byte", cons, 4},
5153 {"8byte", cons, 8},
5154 /* These are used for dwarf2. */
5155 { "file", dwarf2_directive_file, 0 },
5156 { "loc", dwarf2_directive_loc, 0 },
5157 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
5158#endif
5159 { "extend", float_cons, 'x' },
5160 { "ldouble", float_cons, 'x' },
5161 { "packed", float_cons, 'p' },
5162 { "bfloat16", float_cons, 'b' },
5163#ifdef TE_PE
5164 {"secrel32", pe_directive_secrel, 0},
5165#endif
5166
5167 /* These are for compatibility with CodeComposer Studio. */
5168 {"ref", s_ccs_ref, 0},
5169 {"def", s_ccs_def, 0},
5170 {"asmfunc", s_ccs_asmfunc, 0},
5171 {"endasmfunc", s_ccs_endasmfunc, 0},
5172
5173 {"float16", float_cons, 'h' },
5174 {"float16_format", set_fp16_format, 0 },
5175
5176 { 0, 0, 0 }
5177};
5178
5179/* Parser functions used exclusively in instruction operands. */
5180
5181/* Generic immediate-value read function for use in insn parsing.
5182 STR points to the beginning of the immediate (the leading #);
5183 VAL receives the value; if the value is outside [MIN, MAX]
5184 issue an error. PREFIX_OPT is true if the immediate prefix is
5185 optional. */
5186
5187static int
5188parse_immediate (char **str, int *val, int min, int max,
5189 bfd_boolean prefix_opt)
5190{
5191 expressionS exp;
5192
5193 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
5194 if (exp.X_op != O_constant)
5195 {
5196 inst.error = _("constant expression required");
5197 return FAIL;
5198 }
5199
5200 if (exp.X_add_number < min || exp.X_add_number > max)
5201 {
5202 inst.error = _("immediate value out of range");
5203 return FAIL;
5204 }
5205
5206 *val = exp.X_add_number;
5207 return SUCCESS;
5208}
5209
5210/* Less-generic immediate-value read function with the possibility of loading a
5211 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5212 instructions. Puts the result directly in inst.operands[i]. */
5213
5214static int
5215parse_big_immediate (char **str, int i, expressionS *in_exp,
5216 bfd_boolean allow_symbol_p)
5217{
5218 expressionS exp;
5219 expressionS *exp_p = in_exp ? in_exp : &exp;
5220 char *ptr = *str;
5221
5222 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5223
5224 if (exp_p->X_op == O_constant)
5225 {
5226 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
5227 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5228 O_constant. We have to be careful not to break compilation for
5229 32-bit X_add_number, though. */
5230 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
5231 {
5232 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5233 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5234 & 0xffffffff);
5235 inst.operands[i].regisimm = 1;
5236 }
5237 }
5238 else if (exp_p->X_op == O_big
5239 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5240 {
5241 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
5242
5243 /* Bignums have their least significant bits in
5244 generic_bignum[0]. Make sure we put 32 bits in imm and
5245 32 bits in reg, in a (hopefully) portable way. */
5246 gas_assert (parts != 0);
5247
5248 /* Make sure that the number is not too big.
5249 PR 11972: Bignums can now be sign-extended to the
5250 size of a .octa so check that the out of range bits
5251 are all zero or all one. */
5252 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
5253 {
5254 LITTLENUM_TYPE m = -1;
5255
5256 if (generic_bignum[parts * 2] != 0
5257 && generic_bignum[parts * 2] != m)
5258 return FAIL;
5259
5260 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
5261 if (generic_bignum[j] != generic_bignum[j-1])
5262 return FAIL;
5263 }
5264
5265 inst.operands[i].imm = 0;
5266 for (j = 0; j < parts; j++, idx++)
5267 inst.operands[i].imm |= generic_bignum[idx]
5268 << (LITTLENUM_NUMBER_OF_BITS * j);
5269 inst.operands[i].reg = 0;
5270 for (j = 0; j < parts; j++, idx++)
5271 inst.operands[i].reg |= generic_bignum[idx]
5272 << (LITTLENUM_NUMBER_OF_BITS * j);
5273 inst.operands[i].regisimm = 1;
5274 }
5275 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5276 return FAIL;
5277
5278 *str = ptr;
5279
5280 return SUCCESS;
5281}
5282
5283/* Returns the pseudo-register number of an FPA immediate constant,
5284 or FAIL if there isn't a valid constant here. */
5285
5286static int
5287parse_fpa_immediate (char ** str)
5288{
5289 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5290 char * save_in;
5291 expressionS exp;
5292 int i;
5293 int j;
5294
5295 /* First try and match exact strings, this is to guarantee
5296 that some formats will work even for cross assembly. */
5297
5298 for (i = 0; fp_const[i]; i++)
5299 {
5300 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
5301 {
5302 char *start = *str;
5303
5304 *str += strlen (fp_const[i]);
5305 if (is_end_of_line[(unsigned char) **str])
5306 return i + 8;
5307 *str = start;
5308 }
5309 }
5310
5311 /* Just because we didn't get a match doesn't mean that the constant
5312 isn't valid, just that it is in a format that we don't
5313 automatically recognize. Try parsing it with the standard
5314 expression routines. */
5315
5316 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
5317
5318 /* Look for a raw floating point number. */
5319 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
5320 && is_end_of_line[(unsigned char) *save_in])
5321 {
5322 for (i = 0; i < NUM_FLOAT_VALS; i++)
5323 {
5324 for (j = 0; j < MAX_LITTLENUMS; j++)
5325 {
5326 if (words[j] != fp_values[i][j])
5327 break;
5328 }
5329
5330 if (j == MAX_LITTLENUMS)
5331 {
5332 *str = save_in;
5333 return i + 8;
5334 }
5335 }
5336 }
5337
5338 /* Try and parse a more complex expression, this will probably fail
5339 unless the code uses a floating point prefix (eg "0f"). */
5340 save_in = input_line_pointer;
5341 input_line_pointer = *str;
5342 if (expression (&exp) == absolute_section
5343 && exp.X_op == O_big
5344 && exp.X_add_number < 0)
5345 {
5346 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5347 Ditto for 15. */
5348#define X_PRECISION 5
5349#define E_PRECISION 15L
5350 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
5351 {
5352 for (i = 0; i < NUM_FLOAT_VALS; i++)
5353 {
5354 for (j = 0; j < MAX_LITTLENUMS; j++)
5355 {
5356 if (words[j] != fp_values[i][j])
5357 break;
5358 }
5359
5360 if (j == MAX_LITTLENUMS)
5361 {
5362 *str = input_line_pointer;
5363 input_line_pointer = save_in;
5364 return i + 8;
5365 }
5366 }
5367 }
5368 }
5369
5370 *str = input_line_pointer;
5371 input_line_pointer = save_in;
5372 inst.error = _("invalid FPA immediate expression");
5373 return FAIL;
5374}
5375
5376/* Returns 1 if a number has "quarter-precision" float format
5377 0baBbbbbbc defgh000 00000000 00000000. */
5378
5379static int
5380is_quarter_float (unsigned imm)
5381{
5382 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
5383 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
5384}
5385
5386
5387/* Detect the presence of a floating point or integer zero constant,
5388 i.e. #0.0 or #0. */
5389
5390static bfd_boolean
5391parse_ifimm_zero (char **in)
5392{
5393 int error_code;
5394
5395 if (!is_immediate_prefix (**in))
5396 {
5397 /* In unified syntax, all prefixes are optional. */
5398 if (!unified_syntax)
5399 return FALSE;
5400 }
5401 else
5402 ++*in;
5403
5404 /* Accept #0x0 as a synonym for #0. */
5405 if (strncmp (*in, "0x", 2) == 0)
5406 {
5407 int val;
5408 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
5409 return FALSE;
5410 return TRUE;
5411 }
5412
5413 error_code = atof_generic (in, ".", EXP_CHARS,
5414 &generic_floating_point_number);
5415
5416 if (!error_code
5417 && generic_floating_point_number.sign == '+'
5418 && (generic_floating_point_number.low
5419 > generic_floating_point_number.leader))
5420 return TRUE;
5421
5422 return FALSE;
5423}
5424
5425/* Parse an 8-bit "quarter-precision" floating point number of the form:
5426 0baBbbbbbc defgh000 00000000 00000000.
5427 The zero and minus-zero cases need special handling, since they can't be
5428 encoded in the "quarter-precision" float format, but can nonetheless be
5429 loaded as integer constants. */
5430
5431static unsigned
5432parse_qfloat_immediate (char **ccp, int *immed)
5433{
5434 char *str = *ccp;
5435 char *fpnum;
5436 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5437 int found_fpchar = 0;
5438
5439 skip_past_char (&str, '#');
5440
5441 /* We must not accidentally parse an integer as a floating-point number. Make
5442 sure that the value we parse is not an integer by checking for special
5443 characters '.' or 'e'.
5444 FIXME: This is a horrible hack, but doing better is tricky because type
5445 information isn't in a very usable state at parse time. */
5446 fpnum = str;
5447 skip_whitespace (fpnum);
5448
5449 if (strncmp (fpnum, "0x", 2) == 0)
5450 return FAIL;
5451 else
5452 {
5453 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
5454 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5455 {
5456 found_fpchar = 1;
5457 break;
5458 }
5459
5460 if (!found_fpchar)
5461 return FAIL;
5462 }
5463
5464 if ((str = atof_ieee (str, 's', words)) != NULL)
5465 {
5466 unsigned fpword = 0;
5467 int i;
5468
5469 /* Our FP word must be 32 bits (single-precision FP). */
5470 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
5471 {
5472 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5473 fpword |= words[i];
5474 }
5475
5476 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
5477 *immed = fpword;
5478 else
5479 return FAIL;
5480
5481 *ccp = str;
5482
5483 return SUCCESS;
5484 }
5485
5486 return FAIL;
5487}
5488
5489/* Shift operands. */
5490enum shift_kind
5491{
5492 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW
5493};
5494
5495struct asm_shift_name
5496{
5497 const char *name;
5498 enum shift_kind kind;
5499};
5500
5501/* Third argument to parse_shift. */
5502enum parse_shift_mode
5503{
5504 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5505 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5506 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5507 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5508 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
5509 SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */
5510};
5511
5512/* Parse a <shift> specifier on an ARM data processing instruction.
5513 This has three forms:
5514
5515 (LSL|LSR|ASL|ASR|ROR) Rs
5516 (LSL|LSR|ASL|ASR|ROR) #imm
5517 RRX
5518
5519 Note that ASL is assimilated to LSL in the instruction encoding, and
5520 RRX to ROR #0 (which cannot be written as such). */
5521
5522static int
5523parse_shift (char **str, int i, enum parse_shift_mode mode)
5524{
5525 const struct asm_shift_name *shift_name;
5526 enum shift_kind shift;
5527 char *s = *str;
5528 char *p = s;
5529 int reg;
5530
5531 for (p = *str; ISALPHA (*p); p++)
5532 ;
5533
5534 if (p == *str)
5535 {
5536 inst.error = _("shift expression expected");
5537 return FAIL;
5538 }
5539
5540 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
5541 p - *str);
5542
5543 if (shift_name == NULL)
5544 {
5545 inst.error = _("shift expression expected");
5546 return FAIL;
5547 }
5548
5549 shift = shift_name->kind;
5550
5551 switch (mode)
5552 {
5553 case NO_SHIFT_RESTRICT:
5554 case SHIFT_IMMEDIATE:
5555 if (shift == SHIFT_UXTW)
5556 {
5557 inst.error = _("'UXTW' not allowed here");
5558 return FAIL;
5559 }
5560 break;
5561
5562 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5563 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5564 {
5565 inst.error = _("'LSL' or 'ASR' required");
5566 return FAIL;
5567 }
5568 break;
5569
5570 case SHIFT_LSL_IMMEDIATE:
5571 if (shift != SHIFT_LSL)
5572 {
5573 inst.error = _("'LSL' required");
5574 return FAIL;
5575 }
5576 break;
5577
5578 case SHIFT_ASR_IMMEDIATE:
5579 if (shift != SHIFT_ASR)
5580 {
5581 inst.error = _("'ASR' required");
5582 return FAIL;
5583 }
5584 break;
5585 case SHIFT_UXTW_IMMEDIATE:
5586 if (shift != SHIFT_UXTW)
5587 {
5588 inst.error = _("'UXTW' required");
5589 return FAIL;
5590 }
5591 break;
5592
5593 default: abort ();
5594 }
5595
5596 if (shift != SHIFT_RRX)
5597 {
5598 /* Whitespace can appear here if the next thing is a bare digit. */
5599 skip_whitespace (p);
5600
5601 if (mode == NO_SHIFT_RESTRICT
5602 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5603 {
5604 inst.operands[i].imm = reg;
5605 inst.operands[i].immisreg = 1;
5606 }
5607 else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
5608 return FAIL;
5609 }
5610 inst.operands[i].shift_kind = shift;
5611 inst.operands[i].shifted = 1;
5612 *str = p;
5613 return SUCCESS;
5614}
5615
5616/* Parse a <shifter_operand> for an ARM data processing instruction:
5617
5618 #<immediate>
5619 #<immediate>, <rotate>
5620 <Rm>
5621 <Rm>, <shift>
5622
5623 where <shift> is defined by parse_shift above, and <rotate> is a
5624 multiple of 2 between 0 and 30. Validation of immediate operands
5625 is deferred to md_apply_fix. */
5626
5627static int
5628parse_shifter_operand (char **str, int i)
5629{
5630 int value;
5631 expressionS exp;
5632
5633 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
5634 {
5635 inst.operands[i].reg = value;
5636 inst.operands[i].isreg = 1;
5637
5638 /* parse_shift will override this if appropriate */
5639 inst.relocs[0].exp.X_op = O_constant;
5640 inst.relocs[0].exp.X_add_number = 0;
5641
5642 if (skip_past_comma (str) == FAIL)
5643 return SUCCESS;
5644
5645 /* Shift operation on register. */
5646 return parse_shift (str, i, NO_SHIFT_RESTRICT);
5647 }
5648
5649 if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
5650 return FAIL;
5651
5652 if (skip_past_comma (str) == SUCCESS)
5653 {
5654 /* #x, y -- ie explicit rotation by Y. */
5655 if (my_get_expression (&exp, str, GE_NO_PREFIX))
5656 return FAIL;
5657
5658 if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
5659 {
5660 inst.error = _("constant expression expected");
5661 return FAIL;
5662 }
5663
5664 value = exp.X_add_number;
5665 if (value < 0 || value > 30 || value % 2 != 0)
5666 {
5667 inst.error = _("invalid rotation");
5668 return FAIL;
5669 }
5670 if (inst.relocs[0].exp.X_add_number < 0
5671 || inst.relocs[0].exp.X_add_number > 255)
5672 {
5673 inst.error = _("invalid constant");
5674 return FAIL;
5675 }
5676
5677 /* Encode as specified. */
5678 inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
5679 return SUCCESS;
5680 }
5681
5682 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5683 inst.relocs[0].pc_rel = 0;
5684 return SUCCESS;
5685}
5686
5687/* Group relocation information. Each entry in the table contains the
5688 textual name of the relocation as may appear in assembler source
5689 and must end with a colon.
5690 Along with this textual name are the relocation codes to be used if
5691 the corresponding instruction is an ALU instruction (ADD or SUB only),
5692 an LDR, an LDRS, or an LDC. */
5693
5694struct group_reloc_table_entry
5695{
5696 const char *name;
5697 int alu_code;
5698 int ldr_code;
5699 int ldrs_code;
5700 int ldc_code;
5701};
5702
5703typedef enum
5704{
5705 /* Varieties of non-ALU group relocation. */
5706
5707 GROUP_LDR,
5708 GROUP_LDRS,
5709 GROUP_LDC,
5710 GROUP_MVE
5711} group_reloc_type;
5712
5713static struct group_reloc_table_entry group_reloc_table[] =
5714 { /* Program counter relative: */
5715 { "pc_g0_nc",
5716 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5717 0, /* LDR */
5718 0, /* LDRS */
5719 0 }, /* LDC */
5720 { "pc_g0",
5721 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5722 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5723 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5724 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5725 { "pc_g1_nc",
5726 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5727 0, /* LDR */
5728 0, /* LDRS */
5729 0 }, /* LDC */
5730 { "pc_g1",
5731 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5732 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5733 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5734 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5735 { "pc_g2",
5736 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5737 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5738 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5739 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5740 /* Section base relative */
5741 { "sb_g0_nc",
5742 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5743 0, /* LDR */
5744 0, /* LDRS */
5745 0 }, /* LDC */
5746 { "sb_g0",
5747 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5748 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5749 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5750 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5751 { "sb_g1_nc",
5752 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5753 0, /* LDR */
5754 0, /* LDRS */
5755 0 }, /* LDC */
5756 { "sb_g1",
5757 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5758 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5759 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5760 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5761 { "sb_g2",
5762 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5763 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5764 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5765 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5766 /* Absolute thumb alu relocations. */
5767 { "lower0_7",
5768 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5769 0, /* LDR. */
5770 0, /* LDRS. */
5771 0 }, /* LDC. */
5772 { "lower8_15",
5773 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5774 0, /* LDR. */
5775 0, /* LDRS. */
5776 0 }, /* LDC. */
5777 { "upper0_7",
5778 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5779 0, /* LDR. */
5780 0, /* LDRS. */
5781 0 }, /* LDC. */
5782 { "upper8_15",
5783 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5784 0, /* LDR. */
5785 0, /* LDRS. */
5786 0 } }; /* LDC. */
5787
5788/* Given the address of a pointer pointing to the textual name of a group
5789 relocation as may appear in assembler source, attempt to find its details
5790 in group_reloc_table. The pointer will be updated to the character after
5791 the trailing colon. On failure, FAIL will be returned; SUCCESS
5792 otherwise. On success, *entry will be updated to point at the relevant
5793 group_reloc_table entry. */
5794
5795static int
5796find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5797{
5798 unsigned int i;
5799 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5800 {
5801 int length = strlen (group_reloc_table[i].name);
5802
5803 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5804 && (*str)[length] == ':')
5805 {
5806 *out = &group_reloc_table[i];
5807 *str += (length + 1);
5808 return SUCCESS;
5809 }
5810 }
5811
5812 return FAIL;
5813}
5814
5815/* Parse a <shifter_operand> for an ARM data processing instruction
5816 (as for parse_shifter_operand) where group relocations are allowed:
5817
5818 #<immediate>
5819 #<immediate>, <rotate>
5820 #:<group_reloc>:<expression>
5821 <Rm>
5822 <Rm>, <shift>
5823
5824 where <group_reloc> is one of the strings defined in group_reloc_table.
5825 The hashes are optional.
5826
5827 Everything else is as for parse_shifter_operand. */
5828
5829static parse_operand_result
5830parse_shifter_operand_group_reloc (char **str, int i)
5831{
5832 /* Determine if we have the sequence of characters #: or just :
5833 coming next. If we do, then we check for a group relocation.
5834 If we don't, punt the whole lot to parse_shifter_operand. */
5835
5836 if (((*str)[0] == '#' && (*str)[1] == ':')
5837 || (*str)[0] == ':')
5838 {
5839 struct group_reloc_table_entry *entry;
5840
5841 if ((*str)[0] == '#')
5842 (*str) += 2;
5843 else
5844 (*str)++;
5845
5846 /* Try to parse a group relocation. Anything else is an error. */
5847 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5848 {
5849 inst.error = _("unknown group relocation");
5850 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5851 }
5852
5853 /* We now have the group relocation table entry corresponding to
5854 the name in the assembler source. Next, we parse the expression. */
5855 if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
5856 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5857
5858 /* Record the relocation type (always the ALU variant here). */
5859 inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5860 gas_assert (inst.relocs[0].type != 0);
5861
5862 return PARSE_OPERAND_SUCCESS;
5863 }
5864 else
5865 return parse_shifter_operand (str, i) == SUCCESS
5866 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5867
5868 /* Never reached. */
5869}
5870
5871/* Parse a Neon alignment expression. Information is written to
5872 inst.operands[i]. We assume the initial ':' has been skipped.
5873
5874 align .imm = align << 8, .immisalign=1, .preind=0 */
5875static parse_operand_result
5876parse_neon_alignment (char **str, int i)
5877{
5878 char *p = *str;
5879 expressionS exp;
5880
5881 my_get_expression (&exp, &p, GE_NO_PREFIX);
5882
5883 if (exp.X_op != O_constant)
5884 {
5885 inst.error = _("alignment must be constant");
5886 return PARSE_OPERAND_FAIL;
5887 }
5888
5889 inst.operands[i].imm = exp.X_add_number << 8;
5890 inst.operands[i].immisalign = 1;
5891 /* Alignments are not pre-indexes. */
5892 inst.operands[i].preind = 0;
5893
5894 *str = p;
5895 return PARSE_OPERAND_SUCCESS;
5896}
5897
5898/* Parse all forms of an ARM address expression. Information is written
5899 to inst.operands[i] and/or inst.relocs[0].
5900
5901 Preindexed addressing (.preind=1):
5902
5903 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5904 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5905 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5906 .shift_kind=shift .relocs[0].exp=shift_imm
5907
5908 These three may have a trailing ! which causes .writeback to be set also.
5909
5910 Postindexed addressing (.postind=1, .writeback=1):
5911
5912 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5913 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5914 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5915 .shift_kind=shift .relocs[0].exp=shift_imm
5916
5917 Unindexed addressing (.preind=0, .postind=0):
5918
5919 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5920
5921 Other:
5922
5923 [Rn]{!} shorthand for [Rn,#0]{!}
5924 =immediate .isreg=0 .relocs[0].exp=immediate
5925 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5926
5927 It is the caller's responsibility to check for addressing modes not
5928 supported by the instruction, and to set inst.relocs[0].type. */
5929
5930static parse_operand_result
5931parse_address_main (char **str, int i, int group_relocations,
5932 group_reloc_type group_type)
5933{
5934 char *p = *str;
5935 int reg;
5936
5937 if (skip_past_char (&p, '[') == FAIL)
5938 {
5939 if (skip_past_char (&p, '=') == FAIL)
5940 {
5941 /* Bare address - translate to PC-relative offset. */
5942 inst.relocs[0].pc_rel = 1;
5943 inst.operands[i].reg = REG_PC;
5944 inst.operands[i].isreg = 1;
5945 inst.operands[i].preind = 1;
5946
5947 if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
5948 return PARSE_OPERAND_FAIL;
5949 }
5950 else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
5951 /*allow_symbol_p=*/TRUE))
5952 return PARSE_OPERAND_FAIL;
5953
5954 *str = p;
5955 return PARSE_OPERAND_SUCCESS;
5956 }
5957
5958 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5959 skip_whitespace (p);
5960
5961 if (group_type == GROUP_MVE)
5962 {
5963 enum arm_reg_type rtype = REG_TYPE_MQ;
5964 struct neon_type_el et;
5965 if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5966 {
5967 inst.operands[i].isquad = 1;
5968 }
5969 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5970 {
5971 inst.error = BAD_ADDR_MODE;
5972 return PARSE_OPERAND_FAIL;
5973 }
5974 }
5975 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5976 {
5977 if (group_type == GROUP_MVE)
5978 inst.error = BAD_ADDR_MODE;
5979 else
5980 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5981 return PARSE_OPERAND_FAIL;
5982 }
5983 inst.operands[i].reg = reg;
5984 inst.operands[i].isreg = 1;
5985
5986 if (skip_past_comma (&p) == SUCCESS)
5987 {
5988 inst.operands[i].preind = 1;
5989
5990 if (*p == '+') p++;
5991 else if (*p == '-') p++, inst.operands[i].negative = 1;
5992
5993 enum arm_reg_type rtype = REG_TYPE_MQ;
5994 struct neon_type_el et;
5995 if (group_type == GROUP_MVE
5996 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5997 {
5998 inst.operands[i].immisreg = 2;
5999 inst.operands[i].imm = reg;
6000
6001 if (skip_past_comma (&p) == SUCCESS)
6002 {
6003 if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS)
6004 {
6005 inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
6006 inst.relocs[0].exp.X_add_number = 0;
6007 }
6008 else
6009 return PARSE_OPERAND_FAIL;
6010 }
6011 }
6012 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
6013 {
6014 inst.operands[i].imm = reg;
6015 inst.operands[i].immisreg = 1;
6016
6017 if (skip_past_comma (&p) == SUCCESS)
6018 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
6019 return PARSE_OPERAND_FAIL;
6020 }
6021 else if (skip_past_char (&p, ':') == SUCCESS)
6022 {
6023 /* FIXME: '@' should be used here, but it's filtered out by generic
6024 code before we get to see it here. This may be subject to
6025 change. */
6026 parse_operand_result result = parse_neon_alignment (&p, i);
6027
6028 if (result != PARSE_OPERAND_SUCCESS)
6029 return result;
6030 }
6031 else
6032 {
6033 if (inst.operands[i].negative)
6034 {
6035 inst.operands[i].negative = 0;
6036 p--;
6037 }
6038
6039 if (group_relocations
6040 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
6041 {
6042 struct group_reloc_table_entry *entry;
6043
6044 /* Skip over the #: or : sequence. */
6045 if (*p == '#')
6046 p += 2;
6047 else
6048 p++;
6049
6050 /* Try to parse a group relocation. Anything else is an
6051 error. */
6052 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
6053 {
6054 inst.error = _("unknown group relocation");
6055 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
6056 }
6057
6058 /* We now have the group relocation table entry corresponding to
6059 the name in the assembler source. Next, we parse the
6060 expression. */
6061 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
6062 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
6063
6064 /* Record the relocation type. */
6065 switch (group_type)
6066 {
6067 case GROUP_LDR:
6068 inst.relocs[0].type
6069 = (bfd_reloc_code_real_type) entry->ldr_code;
6070 break;
6071
6072 case GROUP_LDRS:
6073 inst.relocs[0].type
6074 = (bfd_reloc_code_real_type) entry->ldrs_code;
6075 break;
6076
6077 case GROUP_LDC:
6078 inst.relocs[0].type
6079 = (bfd_reloc_code_real_type) entry->ldc_code;
6080 break;
6081
6082 default:
6083 gas_assert (0);
6084 }
6085
6086 if (inst.relocs[0].type == 0)
6087 {
6088 inst.error = _("this group relocation is not allowed on this instruction");
6089 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
6090 }
6091 }
6092 else
6093 {
6094 char *q = p;
6095
6096 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6097 return PARSE_OPERAND_FAIL;
6098 /* If the offset is 0, find out if it's a +0 or -0. */
6099 if (inst.relocs[0].exp.X_op == O_constant
6100 && inst.relocs[0].exp.X_add_number == 0)
6101 {
6102 skip_whitespace (q);
6103 if (*q == '#')
6104 {
6105 q++;
6106 skip_whitespace (q);
6107 }
6108 if (*q == '-')
6109 inst.operands[i].negative = 1;
6110 }
6111 }
6112 }
6113 }
6114 else if (skip_past_char (&p, ':') == SUCCESS)
6115 {
6116 /* FIXME: '@' should be used here, but it's filtered out by generic code
6117 before we get to see it here. This may be subject to change. */
6118 parse_operand_result result = parse_neon_alignment (&p, i);
6119
6120 if (result != PARSE_OPERAND_SUCCESS)
6121 return result;
6122 }
6123
6124 if (skip_past_char (&p, ']') == FAIL)
6125 {
6126 inst.error = _("']' expected");
6127 return PARSE_OPERAND_FAIL;
6128 }
6129
6130 if (skip_past_char (&p, '!') == SUCCESS)
6131 inst.operands[i].writeback = 1;
6132
6133 else if (skip_past_comma (&p) == SUCCESS)
6134 {
6135 if (skip_past_char (&p, '{') == SUCCESS)
6136 {
6137 /* [Rn], {expr} - unindexed, with option */
6138 if (parse_immediate (&p, &inst.operands[i].imm,
6139 0, 255, TRUE) == FAIL)
6140 return PARSE_OPERAND_FAIL;
6141
6142 if (skip_past_char (&p, '}') == FAIL)
6143 {
6144 inst.error = _("'}' expected at end of 'option' field");
6145 return PARSE_OPERAND_FAIL;
6146 }
6147 if (inst.operands[i].preind)
6148 {
6149 inst.error = _("cannot combine index with option");
6150 return PARSE_OPERAND_FAIL;
6151 }
6152 *str = p;
6153 return PARSE_OPERAND_SUCCESS;
6154 }
6155 else
6156 {
6157 inst.operands[i].postind = 1;
6158 inst.operands[i].writeback = 1;
6159
6160 if (inst.operands[i].preind)
6161 {
6162 inst.error = _("cannot combine pre- and post-indexing");
6163 return PARSE_OPERAND_FAIL;
6164 }
6165
6166 if (*p == '+') p++;
6167 else if (*p == '-') p++, inst.operands[i].negative = 1;
6168
6169 enum arm_reg_type rtype = REG_TYPE_MQ;
6170 struct neon_type_el et;
6171 if (group_type == GROUP_MVE
6172 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6173 {
6174 inst.operands[i].immisreg = 2;
6175 inst.operands[i].imm = reg;
6176 }
6177 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
6178 {
6179 /* We might be using the immediate for alignment already. If we
6180 are, OR the register number into the low-order bits. */
6181 if (inst.operands[i].immisalign)
6182 inst.operands[i].imm |= reg;
6183 else
6184 inst.operands[i].imm = reg;
6185 inst.operands[i].immisreg = 1;
6186
6187 if (skip_past_comma (&p) == SUCCESS)
6188 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
6189 return PARSE_OPERAND_FAIL;
6190 }
6191 else
6192 {
6193 char *q = p;
6194
6195 if (inst.operands[i].negative)
6196 {
6197 inst.operands[i].negative = 0;
6198 p--;
6199 }
6200 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6201 return PARSE_OPERAND_FAIL;
6202 /* If the offset is 0, find out if it's a +0 or -0. */
6203 if (inst.relocs[0].exp.X_op == O_constant
6204 && inst.relocs[0].exp.X_add_number == 0)
6205 {
6206 skip_whitespace (q);
6207 if (*q == '#')
6208 {
6209 q++;
6210 skip_whitespace (q);
6211 }
6212 if (*q == '-')
6213 inst.operands[i].negative = 1;
6214 }
6215 }
6216 }
6217 }
6218
6219 /* If at this point neither .preind nor .postind is set, we have a
6220 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6221 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6222 {
6223 inst.operands[i].preind = 1;
6224 inst.relocs[0].exp.X_op = O_constant;
6225 inst.relocs[0].exp.X_add_number = 0;
6226 }
6227 *str = p;
6228 return PARSE_OPERAND_SUCCESS;
6229}
6230
6231static int
6232parse_address (char **str, int i)
6233{
6234 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
6235 ? SUCCESS : FAIL;
6236}
6237
6238static parse_operand_result
6239parse_address_group_reloc (char **str, int i, group_reloc_type type)
6240{
6241 return parse_address_main (str, i, 1, type);
6242}
6243
6244/* Parse an operand for a MOVW or MOVT instruction. */
6245static int
6246parse_half (char **str)
6247{
6248 char * p;
6249
6250 p = *str;
6251 skip_past_char (&p, '#');
6252 if (strncasecmp (p, ":lower16:", 9) == 0)
6253 inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
6254 else if (strncasecmp (p, ":upper16:", 9) == 0)
6255 inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
6256
6257 if (inst.relocs[0].type != BFD_RELOC_UNUSED)
6258 {
6259 p += 9;
6260 skip_whitespace (p);
6261 }
6262
6263 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
6264 return FAIL;
6265
6266 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
6267 {
6268 if (inst.relocs[0].exp.X_op != O_constant)
6269 {
6270 inst.error = _("constant expression expected");
6271 return FAIL;
6272 }
6273 if (inst.relocs[0].exp.X_add_number < 0
6274 || inst.relocs[0].exp.X_add_number > 0xffff)
6275 {
6276 inst.error = _("immediate value out of range");
6277 return FAIL;
6278 }
6279 }
6280 *str = p;
6281 return SUCCESS;
6282}
6283
6284/* Miscellaneous. */
6285
6286/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6287 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6288static int
6289parse_psr (char **str, bfd_boolean lhs)
6290{
6291 char *p;
6292 unsigned long psr_field;
6293 const struct asm_psr *psr;
6294 char *start;
6295 bfd_boolean is_apsr = FALSE;
6296 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
6297
6298 /* PR gas/12698: If the user has specified -march=all then m_profile will
6299 be TRUE, but we want to ignore it in this case as we are building for any
6300 CPU type, including non-m variants. */
6301 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
6302 m_profile = FALSE;
6303
6304 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6305 feature for ease of use and backwards compatibility. */
6306 p = *str;
6307 if (strncasecmp (p, "SPSR", 4) == 0)
6308 {
6309 if (m_profile)
6310 goto unsupported_psr;
6311
6312 psr_field = SPSR_BIT;
6313 }
6314 else if (strncasecmp (p, "CPSR", 4) == 0)
6315 {
6316 if (m_profile)
6317 goto unsupported_psr;
6318
6319 psr_field = 0;
6320 }
6321 else if (strncasecmp (p, "APSR", 4) == 0)
6322 {
6323 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6324 and ARMv7-R architecture CPUs. */
6325 is_apsr = TRUE;
6326 psr_field = 0;
6327 }
6328 else if (m_profile)
6329 {
6330 start = p;
6331 do
6332 p++;
6333 while (ISALNUM (*p) || *p == '_');
6334
6335 if (strncasecmp (start, "iapsr", 5) == 0
6336 || strncasecmp (start, "eapsr", 5) == 0
6337 || strncasecmp (start, "xpsr", 4) == 0
6338 || strncasecmp (start, "psr", 3) == 0)
6339 p = start + strcspn (start, "rR") + 1;
6340
6341 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
6342 p - start);
6343
6344 if (!psr)
6345 return FAIL;
6346
6347 /* If APSR is being written, a bitfield may be specified. Note that
6348 APSR itself is handled above. */
6349 if (psr->field <= 3)
6350 {
6351 psr_field = psr->field;
6352 is_apsr = TRUE;
6353 goto check_suffix;
6354 }
6355
6356 *str = p;
6357 /* M-profile MSR instructions have the mask field set to "10", except
6358 *PSR variants which modify APSR, which may use a different mask (and
6359 have been handled already). Do that by setting the PSR_f field
6360 here. */
6361 return psr->field | (lhs ? PSR_f : 0);
6362 }
6363 else
6364 goto unsupported_psr;
6365
6366 p += 4;
6367 check_suffix:
6368 if (*p == '_')
6369 {
6370 /* A suffix follows. */
6371 p++;
6372 start = p;
6373
6374 do
6375 p++;
6376 while (ISALNUM (*p) || *p == '_');
6377
6378 if (is_apsr)
6379 {
6380 /* APSR uses a notation for bits, rather than fields. */
6381 unsigned int nzcvq_bits = 0;
6382 unsigned int g_bit = 0;
6383 char *bit;
6384
6385 for (bit = start; bit != p; bit++)
6386 {
6387 switch (TOLOWER (*bit))
6388 {
6389 case 'n':
6390 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
6391 break;
6392
6393 case 'z':
6394 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
6395 break;
6396
6397 case 'c':
6398 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
6399 break;
6400
6401 case 'v':
6402 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
6403 break;
6404
6405 case 'q':
6406 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
6407 break;
6408
6409 case 'g':
6410 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
6411 break;
6412
6413 default:
6414 inst.error = _("unexpected bit specified after APSR");
6415 return FAIL;
6416 }
6417 }
6418
6419 if (nzcvq_bits == 0x1f)
6420 psr_field |= PSR_f;
6421
6422 if (g_bit == 0x1)
6423 {
6424 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
6425 {
6426 inst.error = _("selected processor does not "
6427 "support DSP extension");
6428 return FAIL;
6429 }
6430
6431 psr_field |= PSR_s;
6432 }
6433
6434 if ((nzcvq_bits & 0x20) != 0
6435 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
6436 || (g_bit & 0x2) != 0)
6437 {
6438 inst.error = _("bad bitmask specified after APSR");
6439 return FAIL;
6440 }
6441 }
6442 else
6443 {
6444 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
6445 p - start);
6446 if (!psr)
6447 goto error;
6448
6449 psr_field |= psr->field;
6450 }
6451 }
6452 else
6453 {
6454 if (ISALNUM (*p))
6455 goto error; /* Garbage after "[CS]PSR". */
6456
6457 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6458 is deprecated, but allow it anyway. */
6459 if (is_apsr && lhs)
6460 {
6461 psr_field |= PSR_f;
6462 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6463 "deprecated"));
6464 }
6465 else if (!m_profile)
6466 /* These bits are never right for M-profile devices: don't set them
6467 (only code paths which read/write APSR reach here). */
6468 psr_field |= (PSR_c | PSR_f);
6469 }
6470 *str = p;
6471 return psr_field;
6472
6473 unsupported_psr:
6474 inst.error = _("selected processor does not support requested special "
6475 "purpose register");
6476 return FAIL;
6477
6478 error:
6479 inst.error = _("flag for {c}psr instruction expected");
6480 return FAIL;
6481}
6482
6483static int
6484parse_sys_vldr_vstr (char **str)
6485{
6486 unsigned i;
6487 int val = FAIL;
6488 struct {
6489 const char *name;
6490 int regl;
6491 int regh;
6492 } sysregs[] = {
6493 {"FPSCR", 0x1, 0x0},
6494 {"FPSCR_nzcvqc", 0x2, 0x0},
6495 {"VPR", 0x4, 0x1},
6496 {"P0", 0x5, 0x1},
6497 {"FPCXTNS", 0x6, 0x1},
6498 {"FPCXTS", 0x7, 0x1}
6499 };
6500 char *op_end = strchr (*str, ',');
6501 size_t op_strlen = op_end - *str;
6502
6503 for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
6504 {
6505 if (!strncmp (*str, sysregs[i].name, op_strlen))
6506 {
6507 val = sysregs[i].regl | (sysregs[i].regh << 3);
6508 *str = op_end;
6509 break;
6510 }
6511 }
6512
6513 return val;
6514}
6515
6516/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6517 value suitable for splatting into the AIF field of the instruction. */
6518
6519static int
6520parse_cps_flags (char **str)
6521{
6522 int val = 0;
6523 int saw_a_flag = 0;
6524 char *s = *str;
6525
6526 for (;;)
6527 switch (*s++)
6528 {
6529 case '\0': case ',':
6530 goto done;
6531
6532 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
6533 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
6534 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
6535
6536 default:
6537 inst.error = _("unrecognized CPS flag");
6538 return FAIL;
6539 }
6540
6541 done:
6542 if (saw_a_flag == 0)
6543 {
6544 inst.error = _("missing CPS flags");
6545 return FAIL;
6546 }
6547
6548 *str = s - 1;
6549 return val;
6550}
6551
6552/* Parse an endian specifier ("BE" or "LE", case insensitive);
6553 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6554
6555static int
6556parse_endian_specifier (char **str)
6557{
6558 int little_endian;
6559 char *s = *str;
6560
6561 if (strncasecmp (s, "BE", 2))
6562 little_endian = 0;
6563 else if (strncasecmp (s, "LE", 2))
6564 little_endian = 1;
6565 else
6566 {
6567 inst.error = _("valid endian specifiers are be or le");
6568 return FAIL;
6569 }
6570
6571 if (ISALNUM (s[2]) || s[2] == '_')
6572 {
6573 inst.error = _("valid endian specifiers are be or le");
6574 return FAIL;
6575 }
6576
6577 *str = s + 2;
6578 return little_endian;
6579}
6580
6581/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6582 value suitable for poking into the rotate field of an sxt or sxta
6583 instruction, or FAIL on error. */
6584
6585static int
6586parse_ror (char **str)
6587{
6588 int rot;
6589 char *s = *str;
6590
6591 if (strncasecmp (s, "ROR", 3) == 0)
6592 s += 3;
6593 else
6594 {
6595 inst.error = _("missing rotation field after comma");
6596 return FAIL;
6597 }
6598
6599 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6600 return FAIL;
6601
6602 switch (rot)
6603 {
6604 case 0: *str = s; return 0x0;
6605 case 8: *str = s; return 0x1;
6606 case 16: *str = s; return 0x2;
6607 case 24: *str = s; return 0x3;
6608
6609 default:
6610 inst.error = _("rotation can only be 0, 8, 16, or 24");
6611 return FAIL;
6612 }
6613}
6614
6615/* Parse a conditional code (from conds[] below). The value returned is in the
6616 range 0 .. 14, or FAIL. */
6617static int
6618parse_cond (char **str)
6619{
6620 char *q;
6621 const struct asm_cond *c;
6622 int n;
6623 /* Condition codes are always 2 characters, so matching up to
6624 3 characters is sufficient. */
6625 char cond[3];
6626
6627 q = *str;
6628 n = 0;
6629 while (ISALPHA (*q) && n < 3)
6630 {
6631 cond[n] = TOLOWER (*q);
6632 q++;
6633 n++;
6634 }
6635
6636 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
6637 if (!c)
6638 {
6639 inst.error = _("condition required");
6640 return FAIL;
6641 }
6642
6643 *str = q;
6644 return c->value;
6645}
6646
6647/* Parse an option for a barrier instruction. Returns the encoding for the
6648 option, or FAIL. */
6649static int
6650parse_barrier (char **str)
6651{
6652 char *p, *q;
6653 const struct asm_barrier_opt *o;
6654
6655 p = q = *str;
6656 while (ISALPHA (*q))
6657 q++;
6658
6659 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
6660 q - p);
6661 if (!o)
6662 return FAIL;
6663
6664 if (!mark_feature_used (&o->arch))
6665 return FAIL;
6666
6667 *str = q;
6668 return o->value;
6669}
6670
6671/* Parse the operands of a table branch instruction. Similar to a memory
6672 operand. */
6673static int
6674parse_tb (char **str)
6675{
6676 char * p = *str;
6677 int reg;
6678
6679 if (skip_past_char (&p, '[') == FAIL)
6680 {
6681 inst.error = _("'[' expected");
6682 return FAIL;
6683 }
6684
6685 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6686 {
6687 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6688 return FAIL;
6689 }
6690 inst.operands[0].reg = reg;
6691
6692 if (skip_past_comma (&p) == FAIL)
6693 {
6694 inst.error = _("',' expected");
6695 return FAIL;
6696 }
6697
6698 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6699 {
6700 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6701 return FAIL;
6702 }
6703 inst.operands[0].imm = reg;
6704
6705 if (skip_past_comma (&p) == SUCCESS)
6706 {
6707 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6708 return FAIL;
6709 if (inst.relocs[0].exp.X_add_number != 1)
6710 {
6711 inst.error = _("invalid shift");
6712 return FAIL;
6713 }
6714 inst.operands[0].shifted = 1;
6715 }
6716
6717 if (skip_past_char (&p, ']') == FAIL)
6718 {
6719 inst.error = _("']' expected");
6720 return FAIL;
6721 }
6722 *str = p;
6723 return SUCCESS;
6724}
6725
6726/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6727 information on the types the operands can take and how they are encoded.
6728 Up to four operands may be read; this function handles setting the
6729 ".present" field for each read operand itself.
6730 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6731 else returns FAIL. */
6732
6733static int
6734parse_neon_mov (char **str, int *which_operand)
6735{
6736 int i = *which_operand, val;
6737 enum arm_reg_type rtype;
6738 char *ptr = *str;
6739 struct neon_type_el optype;
6740
6741 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6742 {
6743 /* Cases 17 or 19. */
6744 inst.operands[i].reg = val;
6745 inst.operands[i].isvec = 1;
6746 inst.operands[i].isscalar = 2;
6747 inst.operands[i].vectype = optype;
6748 inst.operands[i++].present = 1;
6749
6750 if (skip_past_comma (&ptr) == FAIL)
6751 goto wanted_comma;
6752
6753 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6754 {
6755 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6756 inst.operands[i].reg = val;
6757 inst.operands[i].isreg = 1;
6758 inst.operands[i].present = 1;
6759 }
6760 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6761 {
6762 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6763 inst.operands[i].reg = val;
6764 inst.operands[i].isvec = 1;
6765 inst.operands[i].isscalar = 2;
6766 inst.operands[i].vectype = optype;
6767 inst.operands[i++].present = 1;
6768
6769 if (skip_past_comma (&ptr) == FAIL)
6770 goto wanted_comma;
6771
6772 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6773 goto wanted_arm;
6774
6775 inst.operands[i].reg = val;
6776 inst.operands[i].isreg = 1;
6777 inst.operands[i++].present = 1;
6778
6779 if (skip_past_comma (&ptr) == FAIL)
6780 goto wanted_comma;
6781
6782 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6783 goto wanted_arm;
6784
6785 inst.operands[i].reg = val;
6786 inst.operands[i].isreg = 1;
6787 inst.operands[i].present = 1;
6788 }
6789 else
6790 {
6791 first_error (_("expected ARM or MVE vector register"));
6792 return FAIL;
6793 }
6794 }
6795 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
6796 {
6797 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6798 inst.operands[i].reg = val;
6799 inst.operands[i].isscalar = 1;
6800 inst.operands[i].vectype = optype;
6801 inst.operands[i++].present = 1;
6802
6803 if (skip_past_comma (&ptr) == FAIL)
6804 goto wanted_comma;
6805
6806 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6807 goto wanted_arm;
6808
6809 inst.operands[i].reg = val;
6810 inst.operands[i].isreg = 1;
6811 inst.operands[i].present = 1;
6812 }
6813 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6814 != FAIL)
6815 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype))
6816 != FAIL))
6817 {
6818 /* Cases 0, 1, 2, 3, 5 (D only). */
6819 if (skip_past_comma (&ptr) == FAIL)
6820 goto wanted_comma;
6821
6822 inst.operands[i].reg = val;
6823 inst.operands[i].isreg = 1;
6824 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6825 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6826 inst.operands[i].isvec = 1;
6827 inst.operands[i].vectype = optype;
6828 inst.operands[i++].present = 1;
6829
6830 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6831 {
6832 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6833 Case 13: VMOV <Sd>, <Rm> */
6834 inst.operands[i].reg = val;
6835 inst.operands[i].isreg = 1;
6836 inst.operands[i].present = 1;
6837
6838 if (rtype == REG_TYPE_NQ)
6839 {
6840 first_error (_("can't use Neon quad register here"));
6841 return FAIL;
6842 }
6843 else if (rtype != REG_TYPE_VFS)
6844 {
6845 i++;
6846 if (skip_past_comma (&ptr) == FAIL)
6847 goto wanted_comma;
6848 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6849 goto wanted_arm;
6850 inst.operands[i].reg = val;
6851 inst.operands[i].isreg = 1;
6852 inst.operands[i].present = 1;
6853 }
6854 }
6855 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6856 &optype)) != FAIL)
6857 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype,
6858 &optype)) != FAIL))
6859 {
6860 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6861 Case 1: VMOV<c><q> <Dd>, <Dm>
6862 Case 8: VMOV.F32 <Sd>, <Sm>
6863 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6864
6865 inst.operands[i].reg = val;
6866 inst.operands[i].isreg = 1;
6867 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6868 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6869 inst.operands[i].isvec = 1;
6870 inst.operands[i].vectype = optype;
6871 inst.operands[i].present = 1;
6872
6873 if (skip_past_comma (&ptr) == SUCCESS)
6874 {
6875 /* Case 15. */
6876 i++;
6877
6878 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6879 goto wanted_arm;
6880
6881 inst.operands[i].reg = val;
6882 inst.operands[i].isreg = 1;
6883 inst.operands[i++].present = 1;
6884
6885 if (skip_past_comma (&ptr) == FAIL)
6886 goto wanted_comma;
6887
6888 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6889 goto wanted_arm;
6890
6891 inst.operands[i].reg = val;
6892 inst.operands[i].isreg = 1;
6893 inst.operands[i].present = 1;
6894 }
6895 }
6896 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6897 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6898 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6899 Case 10: VMOV.F32 <Sd>, #<imm>
6900 Case 11: VMOV.F64 <Dd>, #<imm> */
6901 inst.operands[i].immisfloat = 1;
6902 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6903 == SUCCESS)
6904 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6905 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6906 ;
6907 else
6908 {
6909 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6910 return FAIL;
6911 }
6912 }
6913 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6914 {
6915 /* Cases 6, 7, 16, 18. */
6916 inst.operands[i].reg = val;
6917 inst.operands[i].isreg = 1;
6918 inst.operands[i++].present = 1;
6919
6920 if (skip_past_comma (&ptr) == FAIL)
6921 goto wanted_comma;
6922
6923 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6924 {
6925 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6926 inst.operands[i].reg = val;
6927 inst.operands[i].isscalar = 2;
6928 inst.operands[i].present = 1;
6929 inst.operands[i].vectype = optype;
6930 }
6931 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
6932 {
6933 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6934 inst.operands[i].reg = val;
6935 inst.operands[i].isscalar = 1;
6936 inst.operands[i].present = 1;
6937 inst.operands[i].vectype = optype;
6938 }
6939 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6940 {
6941 inst.operands[i].reg = val;
6942 inst.operands[i].isreg = 1;
6943 inst.operands[i++].present = 1;
6944
6945 if (skip_past_comma (&ptr) == FAIL)
6946 goto wanted_comma;
6947
6948 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6949 != FAIL)
6950 {
6951 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6952
6953 inst.operands[i].reg = val;
6954 inst.operands[i].isreg = 1;
6955 inst.operands[i].isvec = 1;
6956 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6957 inst.operands[i].vectype = optype;
6958 inst.operands[i].present = 1;
6959
6960 if (rtype == REG_TYPE_VFS)
6961 {
6962 /* Case 14. */
6963 i++;
6964 if (skip_past_comma (&ptr) == FAIL)
6965 goto wanted_comma;
6966 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6967 &optype)) == FAIL)
6968 {
6969 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6970 return FAIL;
6971 }
6972 inst.operands[i].reg = val;
6973 inst.operands[i].isreg = 1;
6974 inst.operands[i].isvec = 1;
6975 inst.operands[i].issingle = 1;
6976 inst.operands[i].vectype = optype;
6977 inst.operands[i].present = 1;
6978 }
6979 }
6980 else
6981 {
6982 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6983 != FAIL)
6984 {
6985 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6986 inst.operands[i].reg = val;
6987 inst.operands[i].isvec = 1;
6988 inst.operands[i].isscalar = 2;
6989 inst.operands[i].vectype = optype;
6990 inst.operands[i++].present = 1;
6991
6992 if (skip_past_comma (&ptr) == FAIL)
6993 goto wanted_comma;
6994
6995 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6996 == FAIL)
6997 {
6998 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
6999 return FAIL;
7000 }
7001 inst.operands[i].reg = val;
7002 inst.operands[i].isvec = 1;
7003 inst.operands[i].isscalar = 2;
7004 inst.operands[i].vectype = optype;
7005 inst.operands[i].present = 1;
7006 }
7007 else
7008 {
7009 first_error (_("VFP single, double or MVE vector register"
7010 " expected"));
7011 return FAIL;
7012 }
7013 }
7014 }
7015 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
7016 != FAIL)
7017 {
7018 /* Case 13. */
7019 inst.operands[i].reg = val;
7020 inst.operands[i].isreg = 1;
7021 inst.operands[i].isvec = 1;
7022 inst.operands[i].issingle = 1;
7023 inst.operands[i].vectype = optype;
7024 inst.operands[i].present = 1;
7025 }
7026 }
7027 else
7028 {
7029 first_error (_("parse error"));
7030 return FAIL;
7031 }
7032
7033 /* Successfully parsed the operands. Update args. */
7034 *which_operand = i;
7035 *str = ptr;
7036 return SUCCESS;
7037
7038 wanted_comma:
7039 first_error (_("expected comma"));
7040 return FAIL;
7041
7042 wanted_arm:
7043 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
7044 return FAIL;
7045}
7046
7047/* Use this macro when the operand constraints are different
7048 for ARM and THUMB (e.g. ldrd). */
7049#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7050 ((arm_operand) | ((thumb_operand) << 16))
7051
7052/* Matcher codes for parse_operands. */
7053enum operand_parse_code
7054{
7055 OP_stop, /* end of line */
7056
7057 OP_RR, /* ARM register */
7058 OP_RRnpc, /* ARM register, not r15 */
7059 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7060 OP_RRnpcb, /* ARM register, not r15, in square brackets */
7061 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
7062 optional trailing ! */
7063 OP_RRw, /* ARM register, not r15, optional trailing ! */
7064 OP_RCP, /* Coprocessor number */
7065 OP_RCN, /* Coprocessor register */
7066 OP_RF, /* FPA register */
7067 OP_RVS, /* VFP single precision register */
7068 OP_RVD, /* VFP double precision register (0..15) */
7069 OP_RND, /* Neon double precision register (0..31) */
7070 OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
7071 OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
7072 */
7073 OP_RNSDMQR, /* Neon single or double precision, MVE vector or ARM register.
7074 */
7075 OP_RNQ, /* Neon quad precision register */
7076 OP_RNQMQ, /* Neon quad or MVE vector register. */
7077 OP_RVSD, /* VFP single or double precision register */
7078 OP_RVSD_COND, /* VFP single, double precision register or condition code. */
7079 OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */
7080 OP_RNSD, /* Neon single or double precision register */
7081 OP_RNDQ, /* Neon double or quad precision register */
7082 OP_RNDQMQ, /* Neon double, quad or MVE vector register. */
7083 OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */
7084 OP_RNSDQ, /* Neon single, double or quad precision register */
7085 OP_RNSC, /* Neon scalar D[X] */
7086 OP_RVC, /* VFP control register */
7087 OP_RMF, /* Maverick F register */
7088 OP_RMD, /* Maverick D register */
7089 OP_RMFX, /* Maverick FX register */
7090 OP_RMDX, /* Maverick DX register */
7091 OP_RMAX, /* Maverick AX register */
7092 OP_RMDS, /* Maverick DSPSC register */
7093 OP_RIWR, /* iWMMXt wR register */
7094 OP_RIWC, /* iWMMXt wC register */
7095 OP_RIWG, /* iWMMXt wCG register */
7096 OP_RXA, /* XScale accumulator register */
7097
7098 OP_RNSDMQ, /* Neon single, double or MVE vector register */
7099 OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register
7100 */
7101 OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or
7102 GPR (no SP/SP) */
7103 OP_RMQ, /* MVE vector register. */
7104 OP_RMQRZ, /* MVE vector or ARM register including ZR. */
7105 OP_RMQRR, /* MVE vector or ARM register. */
7106
7107 /* New operands for Armv8.1-M Mainline. */
7108 OP_LR, /* ARM LR register */
7109 OP_RRe, /* ARM register, only even numbered. */
7110 OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
7111 OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
7112 OP_RR_ZR, /* ARM register or ZR but no PC */
7113
7114 OP_REGLST, /* ARM register list */
7115 OP_CLRMLST, /* CLRM register list */
7116 OP_VRSLST, /* VFP single-precision register list */
7117 OP_VRDLST, /* VFP double-precision register list */
7118 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
7119 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
7120 OP_NSTRLST, /* Neon element/structure list */
7121 OP_VRSDVLST, /* VFP single or double-precision register list and VPR */
7122 OP_MSTRLST2, /* MVE vector list with two elements. */
7123 OP_MSTRLST4, /* MVE vector list with four elements. */
7124
7125 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
7126 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
7127 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
7128 OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate
7129 zero. */
7130 OP_RR_RNSC, /* ARM reg or Neon scalar. */
7131 OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
7132 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
7133 OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7134 */
7135 OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7136 scalar, or ARM register. */
7137 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
7138 OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register. */
7139 OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7140 register. */
7141 OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7142 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
7143 OP_VMOV, /* Neon VMOV operands. */
7144 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7145 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7146 OP_RNDQMQ_Ibig,
7147 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
7148 OP_RNDQMQ_I63b_RR, /* Neon D or Q reg, immediate for shift, MVE vector or
7149 ARM register. */
7150 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7151 OP_VLDR, /* VLDR operand. */
7152
7153 OP_I0, /* immediate zero */
7154 OP_I7, /* immediate value 0 .. 7 */
7155 OP_I15, /* 0 .. 15 */
7156 OP_I16, /* 1 .. 16 */
7157 OP_I16z, /* 0 .. 16 */
7158 OP_I31, /* 0 .. 31 */
7159 OP_I31w, /* 0 .. 31, optional trailing ! */
7160 OP_I32, /* 1 .. 32 */
7161 OP_I32z, /* 0 .. 32 */
7162 OP_I48_I64, /* 48 or 64 */
7163 OP_I63, /* 0 .. 63 */
7164 OP_I63s, /* -64 .. 63 */
7165 OP_I64, /* 1 .. 64 */
7166 OP_I64z, /* 0 .. 64 */
7167 OP_I127, /* 0 .. 127 */
7168 OP_I255, /* 0 .. 255 */
7169 OP_I511, /* 0 .. 511 */
7170 OP_I4095, /* 0 .. 4095 */
7171 OP_I8191, /* 0 .. 8191 */
7172 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
7173 OP_I7b, /* 0 .. 7 */
7174 OP_I15b, /* 0 .. 15 */
7175 OP_I31b, /* 0 .. 31 */
7176
7177 OP_SH, /* shifter operand */
7178 OP_SHG, /* shifter operand with possible group relocation */
7179 OP_ADDR, /* Memory address expression (any mode) */
7180 OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */
7181 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
7182 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
7183 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
7184 OP_EXP, /* arbitrary expression */
7185 OP_EXPi, /* same, with optional immediate prefix */
7186 OP_EXPr, /* same, with optional relocation suffix */
7187 OP_EXPs, /* same, with optional non-first operand relocation suffix */
7188 OP_HALF, /* 0 .. 65535 or low/high reloc. */
7189 OP_IROT1, /* VCADD rotate immediate: 90, 270. */
7190 OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7191
7192 OP_CPSF, /* CPS flags */
7193 OP_ENDI, /* Endianness specifier */
7194 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
7195 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
7196 OP_COND, /* conditional code */
7197 OP_TB, /* Table branch. */
7198
7199 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
7200
7201 OP_RRnpc_I0, /* ARM register or literal 0 */
7202 OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
7203 OP_RR_EXi, /* ARM register or expression with imm prefix */
7204 OP_RF_IF, /* FPA register or immediate */
7205 OP_RIWR_RIWC, /* iWMMXt R or C reg */
7206 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
7207
7208 /* Optional operands. */
7209 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
7210 OP_oI31b, /* 0 .. 31 */
7211 OP_oI32b, /* 1 .. 32 */
7212 OP_oI32z, /* 0 .. 32 */
7213 OP_oIffffb, /* 0 .. 65535 */
7214 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
7215
7216 OP_oRR, /* ARM register */
7217 OP_oLR, /* ARM LR register */
7218 OP_oRRnpc, /* ARM register, not the PC */
7219 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7220 OP_oRRw, /* ARM register, not r15, optional trailing ! */
7221 OP_oRND, /* Optional Neon double precision register */
7222 OP_oRNQ, /* Optional Neon quad precision register */
7223 OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */
7224 OP_oRNDQ, /* Optional Neon double or quad precision register */
7225 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
7226 OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
7227 register. */
7228 OP_oRNSDMQ, /* Optional single, double register or MVE vector
7229 register. */
7230 OP_oSHll, /* LSL immediate */
7231 OP_oSHar, /* ASR immediate */
7232 OP_oSHllar, /* LSL or ASR immediate */
7233 OP_oROR, /* ROR 0/8/16/24 */
7234 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
7235
7236 OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */
7237
7238 /* Some pre-defined mixed (ARM/THUMB) operands. */
7239 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
7240 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
7241 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
7242
7243 OP_FIRST_OPTIONAL = OP_oI7b
7244};
7245
7246/* Generic instruction operand parser. This does no encoding and no
7247 semantic validation; it merely squirrels values away in the inst
7248 structure. Returns SUCCESS or FAIL depending on whether the
7249 specified grammar matched. */
7250static int
7251parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
7252{
7253 unsigned const int *upat = pattern;
7254 char *backtrack_pos = 0;
7255 const char *backtrack_error = 0;
7256 int i, val = 0, backtrack_index = 0;
7257 enum arm_reg_type rtype;
7258 parse_operand_result result;
7259 unsigned int op_parse_code;
7260 bfd_boolean partial_match;
7261
7262#define po_char_or_fail(chr) \
7263 do \
7264 { \
7265 if (skip_past_char (&str, chr) == FAIL) \
7266 goto bad_args; \
7267 } \
7268 while (0)
7269
7270#define po_reg_or_fail(regtype) \
7271 do \
7272 { \
7273 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7274 & inst.operands[i].vectype); \
7275 if (val == FAIL) \
7276 { \
7277 first_error (_(reg_expected_msgs[regtype])); \
7278 goto failure; \
7279 } \
7280 inst.operands[i].reg = val; \
7281 inst.operands[i].isreg = 1; \
7282 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7283 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7284 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7285 || rtype == REG_TYPE_VFD \
7286 || rtype == REG_TYPE_NQ); \
7287 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7288 } \
7289 while (0)
7290
7291#define po_reg_or_goto(regtype, label) \
7292 do \
7293 { \
7294 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7295 & inst.operands[i].vectype); \
7296 if (val == FAIL) \
7297 goto label; \
7298 \
7299 inst.operands[i].reg = val; \
7300 inst.operands[i].isreg = 1; \
7301 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7302 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7303 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7304 || rtype == REG_TYPE_VFD \
7305 || rtype == REG_TYPE_NQ); \
7306 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7307 } \
7308 while (0)
7309
7310#define po_imm_or_fail(min, max, popt) \
7311 do \
7312 { \
7313 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7314 goto failure; \
7315 inst.operands[i].imm = val; \
7316 } \
7317 while (0)
7318
7319#define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7320 do \
7321 { \
7322 expressionS exp; \
7323 my_get_expression (&exp, &str, popt); \
7324 if (exp.X_op != O_constant) \
7325 { \
7326 inst.error = _("constant expression required"); \
7327 goto failure; \
7328 } \
7329 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7330 { \
7331 inst.error = _("immediate value 48 or 64 expected"); \
7332 goto failure; \
7333 } \
7334 inst.operands[i].imm = exp.X_add_number; \
7335 } \
7336 while (0)
7337
7338#define po_scalar_or_goto(elsz, label, reg_type) \
7339 do \
7340 { \
7341 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7342 reg_type); \
7343 if (val == FAIL) \
7344 goto label; \
7345 inst.operands[i].reg = val; \
7346 inst.operands[i].isscalar = 1; \
7347 } \
7348 while (0)
7349
7350#define po_misc_or_fail(expr) \
7351 do \
7352 { \
7353 if (expr) \
7354 goto failure; \
7355 } \
7356 while (0)
7357
7358#define po_misc_or_fail_no_backtrack(expr) \
7359 do \
7360 { \
7361 result = expr; \
7362 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7363 backtrack_pos = 0; \
7364 if (result != PARSE_OPERAND_SUCCESS) \
7365 goto failure; \
7366 } \
7367 while (0)
7368
7369#define po_barrier_or_imm(str) \
7370 do \
7371 { \
7372 val = parse_barrier (&str); \
7373 if (val == FAIL && ! ISALPHA (*str)) \
7374 goto immediate; \
7375 if (val == FAIL \
7376 /* ISB can only take SY as an option. */ \
7377 || ((inst.instruction & 0xf0) == 0x60 \
7378 && val != 0xf)) \
7379 { \
7380 inst.error = _("invalid barrier type"); \
7381 backtrack_pos = 0; \
7382 goto failure; \
7383 } \
7384 } \
7385 while (0)
7386
7387 skip_whitespace (str);
7388
7389 for (i = 0; upat[i] != OP_stop; i++)
7390 {
7391 op_parse_code = upat[i];
7392 if (op_parse_code >= 1<<16)
7393 op_parse_code = thumb ? (op_parse_code >> 16)
7394 : (op_parse_code & ((1<<16)-1));
7395
7396 if (op_parse_code >= OP_FIRST_OPTIONAL)
7397 {
7398 /* Remember where we are in case we need to backtrack. */
7399 backtrack_pos = str;
7400 backtrack_error = inst.error;
7401 backtrack_index = i;
7402 }
7403
7404 if (i > 0 && (i > 1 || inst.operands[0].present))
7405 po_char_or_fail (',');
7406
7407 switch (op_parse_code)
7408 {
7409 /* Registers */
7410 case OP_oRRnpc:
7411 case OP_oRRnpcsp:
7412 case OP_RRnpc:
7413 case OP_RRnpcsp:
7414 case OP_oRR:
7415 case OP_RRe:
7416 case OP_RRo:
7417 case OP_LR:
7418 case OP_oLR:
7419 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
7420 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
7421 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
7422 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
7423 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
7424 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
7425 case OP_oRND:
7426 case OP_RNSDMQR:
7427 po_reg_or_goto (REG_TYPE_VFS, try_rndmqr);
7428 break;
7429 try_rndmqr:
7430 case OP_RNDMQR:
7431 po_reg_or_goto (REG_TYPE_RN, try_rndmq);
7432 break;
7433 try_rndmq:
7434 case OP_RNDMQ:
7435 po_reg_or_goto (REG_TYPE_MQ, try_rnd);
7436 break;
7437 try_rnd:
7438 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
7439 case OP_RVC:
7440 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
7441 break;
7442 /* Also accept generic coprocessor regs for unknown registers. */
7443 coproc_reg:
7444 po_reg_or_goto (REG_TYPE_CN, vpr_po);
7445 break;
7446 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7447 existing register with a value of 0, this seems like the
7448 best way to parse P0. */
7449 vpr_po:
7450 if (strncasecmp (str, "P0", 2) == 0)
7451 {
7452 str += 2;
7453 inst.operands[i].isreg = 1;
7454 inst.operands[i].reg = 13;
7455 }
7456 else
7457 goto failure;
7458 break;
7459 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
7460 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
7461 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
7462 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
7463 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
7464 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
7465 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
7466 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
7467 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
7468 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
7469 case OP_oRNQ:
7470 case OP_RNQMQ:
7471 po_reg_or_goto (REG_TYPE_MQ, try_nq);
7472 break;
7473 try_nq:
7474 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
7475 case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
7476 case OP_RNDQMQR:
7477 po_reg_or_goto (REG_TYPE_RN, try_rndqmq);
7478 break;
7479 try_rndqmq:
7480 case OP_oRNDQMQ:
7481 case OP_RNDQMQ:
7482 po_reg_or_goto (REG_TYPE_MQ, try_rndq);
7483 break;
7484 try_rndq:
7485 case OP_oRNDQ:
7486 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
7487 case OP_RVSDMQ:
7488 po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
7489 break;
7490 try_rvsd:
7491 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
7492 case OP_RVSD_COND:
7493 po_reg_or_goto (REG_TYPE_VFSD, try_cond);
7494 break;
7495 case OP_oRNSDMQ:
7496 case OP_RNSDMQ:
7497 po_reg_or_goto (REG_TYPE_NSD, try_mq2);
7498 break;
7499 try_mq2:
7500 po_reg_or_fail (REG_TYPE_MQ);
7501 break;
7502 case OP_oRNSDQ:
7503 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
7504 case OP_RNSDQMQR:
7505 po_reg_or_goto (REG_TYPE_RN, try_mq);
7506 break;
7507 try_mq:
7508 case OP_oRNSDQMQ:
7509 case OP_RNSDQMQ:
7510 po_reg_or_goto (REG_TYPE_MQ, try_nsdq2);
7511 break;
7512 try_nsdq2:
7513 po_reg_or_fail (REG_TYPE_NSDQ);
7514 inst.error = 0;
7515 break;
7516 case OP_RMQRR:
7517 po_reg_or_goto (REG_TYPE_RN, try_rmq);
7518 break;
7519 try_rmq:
7520 case OP_RMQ:
7521 po_reg_or_fail (REG_TYPE_MQ);
7522 break;
7523 /* Neon scalar. Using an element size of 8 means that some invalid
7524 scalars are accepted here, so deal with those in later code. */
7525 case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break;
7526
7527 case OP_RNDQ_I0:
7528 {
7529 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
7530 break;
7531 try_imm0:
7532 po_imm_or_fail (0, 0, TRUE);
7533 }
7534 break;
7535
7536 case OP_RVSD_I0:
7537 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
7538 break;
7539
7540 case OP_RSVDMQ_FI0:
7541 po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0);
7542 break;
7543 try_rsvd_fi0:
7544 case OP_RSVD_FI0:
7545 {
7546 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
7547 break;
7548 try_ifimm0:
7549 if (parse_ifimm_zero (&str))
7550 inst.operands[i].imm = 0;
7551 else
7552 {
7553 inst.error
7554 = _("only floating point zero is allowed as immediate value");
7555 goto failure;
7556 }
7557 }
7558 break;
7559
7560 case OP_RR_RNSC:
7561 {
7562 po_scalar_or_goto (8, try_rr, REG_TYPE_VFD);
7563 break;
7564 try_rr:
7565 po_reg_or_fail (REG_TYPE_RN);
7566 }
7567 break;
7568
7569 case OP_RNSDQ_RNSC_MQ_RR:
7570 po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq);
7571 break;
7572 try_rnsdq_rnsc_mq:
7573 case OP_RNSDQ_RNSC_MQ:
7574 po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc);
7575 break;
7576 try_rnsdq_rnsc:
7577 case OP_RNSDQ_RNSC:
7578 {
7579 po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD);
7580 inst.error = 0;
7581 break;
7582 try_nsdq:
7583 po_reg_or_fail (REG_TYPE_NSDQ);
7584 inst.error = 0;
7585 }
7586 break;
7587
7588 case OP_RNSD_RNSC:
7589 {
7590 po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD);
7591 break;
7592 try_s_scalar:
7593 po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS);
7594 break;
7595 try_nsd:
7596 po_reg_or_fail (REG_TYPE_NSD);
7597 }
7598 break;
7599
7600 case OP_RNDQMQ_RNSC_RR:
7601 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr);
7602 break;
7603 try_rndq_rnsc_rr:
7604 case OP_RNDQ_RNSC_RR:
7605 po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc);
7606 break;
7607 case OP_RNDQMQ_RNSC:
7608 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
7609 break;
7610 try_rndq_rnsc:
7611 case OP_RNDQ_RNSC:
7612 {
7613 po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
7614 break;
7615 try_ndq:
7616 po_reg_or_fail (REG_TYPE_NDQ);
7617 }
7618 break;
7619
7620 case OP_RND_RNSC:
7621 {
7622 po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD);
7623 break;
7624 try_vfd:
7625 po_reg_or_fail (REG_TYPE_VFD);
7626 }
7627 break;
7628
7629 case OP_VMOV:
7630 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7631 not careful then bad things might happen. */
7632 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
7633 break;
7634
7635 case OP_RNDQMQ_Ibig:
7636 po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig);
7637 break;
7638 try_rndq_ibig:
7639 case OP_RNDQ_Ibig:
7640 {
7641 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
7642 break;
7643 try_immbig:
7644 /* There's a possibility of getting a 64-bit immediate here, so
7645 we need special handling. */
7646 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
7647 == FAIL)
7648 {
7649 inst.error = _("immediate value is out of range");
7650 goto failure;
7651 }
7652 }
7653 break;
7654
7655 case OP_RNDQMQ_I63b_RR:
7656 po_reg_or_goto (REG_TYPE_MQ, try_rndq_i63b_rr);
7657 break;
7658 try_rndq_i63b_rr:
7659 po_reg_or_goto (REG_TYPE_RN, try_rndq_i63b);
7660 break;
7661 try_rndq_i63b:
7662 case OP_RNDQ_I63b:
7663 {
7664 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
7665 break;
7666 try_shimm:
7667 po_imm_or_fail (0, 63, TRUE);
7668 }
7669 break;
7670
7671 case OP_RRnpcb:
7672 po_char_or_fail ('[');
7673 po_reg_or_fail (REG_TYPE_RN);
7674 po_char_or_fail (']');
7675 break;
7676
7677 case OP_RRnpctw:
7678 case OP_RRw:
7679 case OP_oRRw:
7680 po_reg_or_fail (REG_TYPE_RN);
7681 if (skip_past_char (&str, '!') == SUCCESS)
7682 inst.operands[i].writeback = 1;
7683 break;
7684
7685 /* Immediates */
7686 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
7687 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
7688 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
7689 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
7690 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
7691 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
7692 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
7693 case OP_I48_I64: po_imm1_or_imm2_or_fail (48, 64, FALSE); break;
7694 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
7695 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
7696 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
7697 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
7698 case OP_I127: po_imm_or_fail ( 0, 127, FALSE); break;
7699 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
7700 case OP_I511: po_imm_or_fail ( 0, 511, FALSE); break;
7701 case OP_I4095: po_imm_or_fail ( 0, 4095, FALSE); break;
7702 case OP_I8191: po_imm_or_fail ( 0, 8191, FALSE); break;
7703 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
7704 case OP_oI7b:
7705 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
7706 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
7707 case OP_oI31b:
7708 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
7709 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
7710 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
7711 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
7712
7713 /* Immediate variants */
7714 case OP_oI255c:
7715 po_char_or_fail ('{');
7716 po_imm_or_fail (0, 255, TRUE);
7717 po_char_or_fail ('}');
7718 break;
7719
7720 case OP_I31w:
7721 /* The expression parser chokes on a trailing !, so we have
7722 to find it first and zap it. */
7723 {
7724 char *s = str;
7725 while (*s && *s != ',')
7726 s++;
7727 if (s[-1] == '!')
7728 {
7729 s[-1] = '\0';
7730 inst.operands[i].writeback = 1;
7731 }
7732 po_imm_or_fail (0, 31, TRUE);
7733 if (str == s - 1)
7734 str = s;
7735 }
7736 break;
7737
7738 /* Expressions */
7739 case OP_EXPi: EXPi:
7740 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7741 GE_OPT_PREFIX));
7742 break;
7743
7744 case OP_EXP:
7745 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7746 GE_NO_PREFIX));
7747 break;
7748
7749 case OP_EXPr: EXPr:
7750 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7751 GE_NO_PREFIX));
7752 if (inst.relocs[0].exp.X_op == O_symbol)
7753 {
7754 val = parse_reloc (&str);
7755 if (val == -1)
7756 {
7757 inst.error = _("unrecognized relocation suffix");
7758 goto failure;
7759 }
7760 else if (val != BFD_RELOC_UNUSED)
7761 {
7762 inst.operands[i].imm = val;
7763 inst.operands[i].hasreloc = 1;
7764 }
7765 }
7766 break;
7767
7768 case OP_EXPs:
7769 po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7770 GE_NO_PREFIX));
7771 if (inst.relocs[i].exp.X_op == O_symbol)
7772 {
7773 inst.operands[i].hasreloc = 1;
7774 }
7775 else if (inst.relocs[i].exp.X_op == O_constant)
7776 {
7777 inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7778 inst.operands[i].hasreloc = 0;
7779 }
7780 break;
7781
7782 /* Operand for MOVW or MOVT. */
7783 case OP_HALF:
7784 po_misc_or_fail (parse_half (&str));
7785 break;
7786
7787 /* Register or expression. */
7788 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
7789 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
7790
7791 /* Register or immediate. */
7792 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
7793 I0: po_imm_or_fail (0, 0, FALSE); break;
7794
7795 case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32); break;
7796 I32: po_imm_or_fail (1, 32, FALSE); break;
7797
7798 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
7799 IF:
7800 if (!is_immediate_prefix (*str))
7801 goto bad_args;
7802 str++;
7803 val = parse_fpa_immediate (&str);
7804 if (val == FAIL)
7805 goto failure;
7806 /* FPA immediates are encoded as registers 8-15.
7807 parse_fpa_immediate has already applied the offset. */
7808 inst.operands[i].reg = val;
7809 inst.operands[i].isreg = 1;
7810 break;
7811
7812 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
7813 I32z: po_imm_or_fail (0, 32, FALSE); break;
7814
7815 /* Two kinds of register. */
7816 case OP_RIWR_RIWC:
7817 {
7818 struct reg_entry *rege = arm_reg_parse_multi (&str);
7819 if (!rege
7820 || (rege->type != REG_TYPE_MMXWR
7821 && rege->type != REG_TYPE_MMXWC
7822 && rege->type != REG_TYPE_MMXWCG))
7823 {
7824 inst.error = _("iWMMXt data or control register expected");
7825 goto failure;
7826 }
7827 inst.operands[i].reg = rege->number;
7828 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7829 }
7830 break;
7831
7832 case OP_RIWC_RIWG:
7833 {
7834 struct reg_entry *rege = arm_reg_parse_multi (&str);
7835 if (!rege
7836 || (rege->type != REG_TYPE_MMXWC
7837 && rege->type != REG_TYPE_MMXWCG))
7838 {
7839 inst.error = _("iWMMXt control register expected");
7840 goto failure;
7841 }
7842 inst.operands[i].reg = rege->number;
7843 inst.operands[i].isreg = 1;
7844 }
7845 break;
7846
7847 /* Misc */
7848 case OP_CPSF: val = parse_cps_flags (&str); break;
7849 case OP_ENDI: val = parse_endian_specifier (&str); break;
7850 case OP_oROR: val = parse_ror (&str); break;
7851 try_cond:
7852 case OP_COND: val = parse_cond (&str); break;
7853 case OP_oBARRIER_I15:
7854 po_barrier_or_imm (str); break;
7855 immediate:
7856 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
7857 goto failure;
7858 break;
7859
7860 case OP_wPSR:
7861 case OP_rPSR:
7862 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7863 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7864 {
7865 inst.error = _("Banked registers are not available with this "
7866 "architecture.");
7867 goto failure;
7868 }
7869 break;
7870 try_psr:
7871 val = parse_psr (&str, op_parse_code == OP_wPSR);
7872 break;
7873
7874 case OP_VLDR:
7875 po_reg_or_goto (REG_TYPE_VFSD, try_sysreg);
7876 break;
7877 try_sysreg:
7878 val = parse_sys_vldr_vstr (&str);
7879 break;
7880
7881 case OP_APSR_RR:
7882 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7883 break;
7884 try_apsr:
7885 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7886 instruction). */
7887 if (strncasecmp (str, "APSR_", 5) == 0)
7888 {
7889 unsigned found = 0;
7890 str += 5;
7891 while (found < 15)
7892 switch (*str++)
7893 {
7894 case 'c': found = (found & 1) ? 16 : found | 1; break;
7895 case 'n': found = (found & 2) ? 16 : found | 2; break;
7896 case 'z': found = (found & 4) ? 16 : found | 4; break;
7897 case 'v': found = (found & 8) ? 16 : found | 8; break;
7898 default: found = 16;
7899 }
7900 if (found != 15)
7901 goto failure;
7902 inst.operands[i].isvec = 1;
7903 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7904 inst.operands[i].reg = REG_PC;
7905 }
7906 else
7907 goto failure;
7908 break;
7909
7910 case OP_TB:
7911 po_misc_or_fail (parse_tb (&str));
7912 break;
7913
7914 /* Register lists. */
7915 case OP_REGLST:
7916 val = parse_reg_list (&str, REGLIST_RN);
7917 if (*str == '^')
7918 {
7919 inst.operands[i].writeback = 1;
7920 str++;
7921 }
7922 break;
7923
7924 case OP_CLRMLST:
7925 val = parse_reg_list (&str, REGLIST_CLRM);
7926 break;
7927
7928 case OP_VRSLST:
7929 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7930 &partial_match);
7931 break;
7932
7933 case OP_VRDLST:
7934 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7935 &partial_match);
7936 break;
7937
7938 case OP_VRSDLST:
7939 /* Allow Q registers too. */
7940 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7941 REGLIST_NEON_D, &partial_match);
7942 if (val == FAIL)
7943 {
7944 inst.error = NULL;
7945 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7946 REGLIST_VFP_S, &partial_match);
7947 inst.operands[i].issingle = 1;
7948 }
7949 break;
7950
7951 case OP_VRSDVLST:
7952 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7953 REGLIST_VFP_D_VPR, &partial_match);
7954 if (val == FAIL && !partial_match)
7955 {
7956 inst.error = NULL;
7957 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7958 REGLIST_VFP_S_VPR, &partial_match);
7959 inst.operands[i].issingle = 1;
7960 }
7961 break;
7962
7963 case OP_NRDLST:
7964 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7965 REGLIST_NEON_D, &partial_match);
7966 break;
7967
7968 case OP_MSTRLST4:
7969 case OP_MSTRLST2:
7970 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7971 1, &inst.operands[i].vectype);
7972 if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe))
7973 goto failure;
7974 break;
7975 case OP_NSTRLST:
7976 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7977 0, &inst.operands[i].vectype);
7978 break;
7979
7980 /* Addressing modes */
7981 case OP_ADDRMVE:
7982 po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE));
7983 break;
7984
7985 case OP_ADDR:
7986 po_misc_or_fail (parse_address (&str, i));
7987 break;
7988
7989 case OP_ADDRGLDR:
7990 po_misc_or_fail_no_backtrack (
7991 parse_address_group_reloc (&str, i, GROUP_LDR));
7992 break;
7993
7994 case OP_ADDRGLDRS:
7995 po_misc_or_fail_no_backtrack (
7996 parse_address_group_reloc (&str, i, GROUP_LDRS));
7997 break;
7998
7999 case OP_ADDRGLDC:
8000 po_misc_or_fail_no_backtrack (
8001 parse_address_group_reloc (&str, i, GROUP_LDC));
8002 break;
8003
8004 case OP_SH:
8005 po_misc_or_fail (parse_shifter_operand (&str, i));
8006 break;
8007
8008 case OP_SHG:
8009 po_misc_or_fail_no_backtrack (
8010 parse_shifter_operand_group_reloc (&str, i));
8011 break;
8012
8013 case OP_oSHll:
8014 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
8015 break;
8016
8017 case OP_oSHar:
8018 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
8019 break;
8020
8021 case OP_oSHllar:
8022 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
8023 break;
8024
8025 case OP_RMQRZ:
8026 case OP_oRMQRZ:
8027 po_reg_or_goto (REG_TYPE_MQ, try_rr_zr);
8028 break;
8029
8030 case OP_RR_ZR:
8031 try_rr_zr:
8032 po_reg_or_goto (REG_TYPE_RN, ZR);
8033 break;
8034 ZR:
8035 po_reg_or_fail (REG_TYPE_ZR);
8036 break;
8037
8038 default:
8039 as_fatal (_("unhandled operand code %d"), op_parse_code);
8040 }
8041
8042 /* Various value-based sanity checks and shared operations. We
8043 do not signal immediate failures for the register constraints;
8044 this allows a syntax error to take precedence. */
8045 switch (op_parse_code)
8046 {
8047 case OP_oRRnpc:
8048 case OP_RRnpc:
8049 case OP_RRnpcb:
8050 case OP_RRw:
8051 case OP_oRRw:
8052 case OP_RRnpc_I0:
8053 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
8054 inst.error = BAD_PC;
8055 break;
8056
8057 case OP_oRRnpcsp:
8058 case OP_RRnpcsp:
8059 case OP_RRnpcsp_I32:
8060 if (inst.operands[i].isreg)
8061 {
8062 if (inst.operands[i].reg == REG_PC)
8063 inst.error = BAD_PC;
8064 else if (inst.operands[i].reg == REG_SP
8065 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8066 relaxed since ARMv8-A. */
8067 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8068 {
8069 gas_assert (thumb);
8070 inst.error = BAD_SP;
8071 }
8072 }
8073 break;
8074
8075 case OP_RRnpctw:
8076 if (inst.operands[i].isreg
8077 && inst.operands[i].reg == REG_PC
8078 && (inst.operands[i].writeback || thumb))
8079 inst.error = BAD_PC;
8080 break;
8081
8082 case OP_RVSD_COND:
8083 case OP_VLDR:
8084 if (inst.operands[i].isreg)
8085 break;
8086 /* fall through. */
8087
8088 case OP_CPSF:
8089 case OP_ENDI:
8090 case OP_oROR:
8091 case OP_wPSR:
8092 case OP_rPSR:
8093 case OP_COND:
8094 case OP_oBARRIER_I15:
8095 case OP_REGLST:
8096 case OP_CLRMLST:
8097 case OP_VRSLST:
8098 case OP_VRDLST:
8099 case OP_VRSDLST:
8100 case OP_VRSDVLST:
8101 case OP_NRDLST:
8102 case OP_NSTRLST:
8103 case OP_MSTRLST2:
8104 case OP_MSTRLST4:
8105 if (val == FAIL)
8106 goto failure;
8107 inst.operands[i].imm = val;
8108 break;
8109
8110 case OP_LR:
8111 case OP_oLR:
8112 if (inst.operands[i].reg != REG_LR)
8113 inst.error = _("operand must be LR register");
8114 break;
8115
8116 case OP_RMQRZ:
8117 case OP_oRMQRZ:
8118 case OP_RR_ZR:
8119 if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
8120 inst.error = BAD_PC;
8121 break;
8122
8123 case OP_RRe:
8124 if (inst.operands[i].isreg
8125 && (inst.operands[i].reg & 0x00000001) != 0)
8126 inst.error = BAD_ODD;
8127 break;
8128
8129 case OP_RRo:
8130 if (inst.operands[i].isreg)
8131 {
8132 if ((inst.operands[i].reg & 0x00000001) != 1)
8133 inst.error = BAD_EVEN;
8134 else if (inst.operands[i].reg == REG_SP)
8135 as_tsktsk (MVE_BAD_SP);
8136 else if (inst.operands[i].reg == REG_PC)
8137 inst.error = BAD_PC;
8138 }
8139 break;
8140
8141 default:
8142 break;
8143 }
8144
8145 /* If we get here, this operand was successfully parsed. */
8146 inst.operands[i].present = 1;
8147 continue;
8148
8149 bad_args:
8150 inst.error = BAD_ARGS;
8151
8152 failure:
8153 if (!backtrack_pos)
8154 {
8155 /* The parse routine should already have set inst.error, but set a
8156 default here just in case. */
8157 if (!inst.error)
8158 inst.error = BAD_SYNTAX;
8159 return FAIL;
8160 }
8161
8162 /* Do not backtrack over a trailing optional argument that
8163 absorbed some text. We will only fail again, with the
8164 'garbage following instruction' error message, which is
8165 probably less helpful than the current one. */
8166 if (backtrack_index == i && backtrack_pos != str
8167 && upat[i+1] == OP_stop)
8168 {
8169 if (!inst.error)
8170 inst.error = BAD_SYNTAX;
8171 return FAIL;
8172 }
8173
8174 /* Try again, skipping the optional argument at backtrack_pos. */
8175 str = backtrack_pos;
8176 inst.error = backtrack_error;
8177 inst.operands[backtrack_index].present = 0;
8178 i = backtrack_index;
8179 backtrack_pos = 0;
8180 }
8181
8182 /* Check that we have parsed all the arguments. */
8183 if (*str != '\0' && !inst.error)
8184 inst.error = _("garbage following instruction");
8185
8186 return inst.error ? FAIL : SUCCESS;
8187}
8188
8189#undef po_char_or_fail
8190#undef po_reg_or_fail
8191#undef po_reg_or_goto
8192#undef po_imm_or_fail
8193#undef po_scalar_or_fail
8194#undef po_barrier_or_imm
8195
8196/* Shorthand macro for instruction encoding functions issuing errors. */
8197#define constraint(expr, err) \
8198 do \
8199 { \
8200 if (expr) \
8201 { \
8202 inst.error = err; \
8203 return; \
8204 } \
8205 } \
8206 while (0)
8207
8208/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8209 instructions are unpredictable if these registers are used. This
8210 is the BadReg predicate in ARM's Thumb-2 documentation.
8211
8212 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8213 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8214#define reject_bad_reg(reg) \
8215 do \
8216 if (reg == REG_PC) \
8217 { \
8218 inst.error = BAD_PC; \
8219 return; \
8220 } \
8221 else if (reg == REG_SP \
8222 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8223 { \
8224 inst.error = BAD_SP; \
8225 return; \
8226 } \
8227 while (0)
8228
8229/* If REG is R13 (the stack pointer), warn that its use is
8230 deprecated. */
8231#define warn_deprecated_sp(reg) \
8232 do \
8233 if (warn_on_deprecated && reg == REG_SP) \
8234 as_tsktsk (_("use of r13 is deprecated")); \
8235 while (0)
8236
8237/* Functions for operand encoding. ARM, then Thumb. */
8238
8239#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8240
8241/* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8242
8243 The only binary encoding difference is the Coprocessor number. Coprocessor
8244 9 is used for half-precision calculations or conversions. The format of the
8245 instruction is the same as the equivalent Coprocessor 10 instruction that
8246 exists for Single-Precision operation. */
8247
8248static void
8249do_scalar_fp16_v82_encode (void)
8250{
8251 if (inst.cond < COND_ALWAYS)
8252 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8253 " the behaviour is UNPREDICTABLE"));
8254 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
8255 _(BAD_FP16));
8256
8257 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
8258 mark_feature_used (&arm_ext_fp16);
8259}
8260
8261/* If VAL can be encoded in the immediate field of an ARM instruction,
8262 return the encoded form. Otherwise, return FAIL. */
8263
8264static unsigned int
8265encode_arm_immediate (unsigned int val)
8266{
8267 unsigned int a, i;
8268
8269 if (val <= 0xff)
8270 return val;
8271
8272 for (i = 2; i < 32; i += 2)
8273 if ((a = rotate_left (val, i)) <= 0xff)
8274 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
8275
8276 return FAIL;
8277}
8278
8279/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8280 return the encoded form. Otherwise, return FAIL. */
8281static unsigned int
8282encode_thumb32_immediate (unsigned int val)
8283{
8284 unsigned int a, i;
8285
8286 if (val <= 0xff)
8287 return val;
8288
8289 for (i = 1; i <= 24; i++)
8290 {
8291 a = val >> i;
8292 if ((val & ~(0xff << i)) == 0)
8293 return ((val >> i) & 0x7f) | ((32 - i) << 7);
8294 }
8295
8296 a = val & 0xff;
8297 if (val == ((a << 16) | a))
8298 return 0x100 | a;
8299 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
8300 return 0x300 | a;
8301
8302 a = val & 0xff00;
8303 if (val == ((a << 16) | a))
8304 return 0x200 | (a >> 8);
8305
8306 return FAIL;
8307}
8308/* Encode a VFP SP or DP register number into inst.instruction. */
8309
8310static void
8311encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
8312{
8313 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
8314 && reg > 15)
8315 {
8316 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
8317 {
8318 if (thumb_mode)
8319 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8320 fpu_vfp_ext_d32);
8321 else
8322 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8323 fpu_vfp_ext_d32);
8324 }
8325 else
8326 {
8327 first_error (_("D register out of range for selected VFP version"));
8328 return;
8329 }
8330 }
8331
8332 switch (pos)
8333 {
8334 case VFP_REG_Sd:
8335 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8336 break;
8337
8338 case VFP_REG_Sn:
8339 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8340 break;
8341
8342 case VFP_REG_Sm:
8343 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8344 break;
8345
8346 case VFP_REG_Dd:
8347 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8348 break;
8349
8350 case VFP_REG_Dn:
8351 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8352 break;
8353
8354 case VFP_REG_Dm:
8355 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8356 break;
8357
8358 default:
8359 abort ();
8360 }
8361}
8362
8363/* Encode a <shift> in an ARM-format instruction. The immediate,
8364 if any, is handled by md_apply_fix. */
8365static void
8366encode_arm_shift (int i)
8367{
8368 /* register-shifted register. */
8369 if (inst.operands[i].immisreg)
8370 {
8371 int op_index;
8372 for (op_index = 0; op_index <= i; ++op_index)
8373 {
8374 /* Check the operand only when it's presented. In pre-UAL syntax,
8375 if the destination register is the same as the first operand, two
8376 register form of the instruction can be used. */
8377 if (inst.operands[op_index].present && inst.operands[op_index].isreg
8378 && inst.operands[op_index].reg == REG_PC)
8379 as_warn (UNPRED_REG ("r15"));
8380 }
8381
8382 if (inst.operands[i].imm == REG_PC)
8383 as_warn (UNPRED_REG ("r15"));
8384 }
8385
8386 if (inst.operands[i].shift_kind == SHIFT_RRX)
8387 inst.instruction |= SHIFT_ROR << 5;
8388 else
8389 {
8390 inst.instruction |= inst.operands[i].shift_kind << 5;
8391 if (inst.operands[i].immisreg)
8392 {
8393 inst.instruction |= SHIFT_BY_REG;
8394 inst.instruction |= inst.operands[i].imm << 8;
8395 }
8396 else
8397 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8398 }
8399}
8400
8401static void
8402encode_arm_shifter_operand (int i)
8403{
8404 if (inst.operands[i].isreg)
8405 {
8406 inst.instruction |= inst.operands[i].reg;
8407 encode_arm_shift (i);
8408 }
8409 else
8410 {
8411 inst.instruction |= INST_IMMEDIATE;
8412 if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
8413 inst.instruction |= inst.operands[i].imm;
8414 }
8415}
8416
8417/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8418static void
8419encode_arm_addr_mode_common (int i, bfd_boolean is_t)
8420{
8421 /* PR 14260:
8422 Generate an error if the operand is not a register. */
8423 constraint (!inst.operands[i].isreg,
8424 _("Instruction does not support =N addresses"));
8425
8426 inst.instruction |= inst.operands[i].reg << 16;
8427
8428 if (inst.operands[i].preind)
8429 {
8430 if (is_t)
8431 {
8432 inst.error = _("instruction does not accept preindexed addressing");
8433 return;
8434 }
8435 inst.instruction |= PRE_INDEX;
8436 if (inst.operands[i].writeback)
8437 inst.instruction |= WRITE_BACK;
8438
8439 }
8440 else if (inst.operands[i].postind)
8441 {
8442 gas_assert (inst.operands[i].writeback);
8443 if (is_t)
8444 inst.instruction |= WRITE_BACK;
8445 }
8446 else /* unindexed - only for coprocessor */
8447 {
8448 inst.error = _("instruction does not accept unindexed addressing");
8449 return;
8450 }
8451
8452 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8453 && (((inst.instruction & 0x000f0000) >> 16)
8454 == ((inst.instruction & 0x0000f000) >> 12)))
8455 as_warn ((inst.instruction & LOAD_BIT)
8456 ? _("destination register same as write-back base")
8457 : _("source register same as write-back base"));
8458}
8459
8460/* inst.operands[i] was set up by parse_address. Encode it into an
8461 ARM-format mode 2 load or store instruction. If is_t is true,
8462 reject forms that cannot be used with a T instruction (i.e. not
8463 post-indexed). */
8464static void
8465encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
8466{
8467 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8468
8469 encode_arm_addr_mode_common (i, is_t);
8470
8471 if (inst.operands[i].immisreg)
8472 {
8473 constraint ((inst.operands[i].imm == REG_PC
8474 || (is_pc && inst.operands[i].writeback)),
8475 BAD_PC_ADDRESSING);
8476 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
8477 inst.instruction |= inst.operands[i].imm;
8478 if (!inst.operands[i].negative)
8479 inst.instruction |= INDEX_UP;
8480 if (inst.operands[i].shifted)
8481 {
8482 if (inst.operands[i].shift_kind == SHIFT_RRX)
8483 inst.instruction |= SHIFT_ROR << 5;
8484 else
8485 {
8486 inst.instruction |= inst.operands[i].shift_kind << 5;
8487 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8488 }
8489 }
8490 }
8491 else /* immediate offset in inst.relocs[0] */
8492 {
8493 if (is_pc && !inst.relocs[0].pc_rel)
8494 {
8495 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
8496
8497 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8498 cannot use PC in addressing.
8499 PC cannot be used in writeback addressing, either. */
8500 constraint ((is_t || inst.operands[i].writeback),
8501 BAD_PC_ADDRESSING);
8502
8503 /* Use of PC in str is deprecated for ARMv7. */
8504 if (warn_on_deprecated
8505 && !is_load
8506 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
8507 as_tsktsk (_("use of PC in this instruction is deprecated"));
8508 }
8509
8510 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8511 {
8512 /* Prefer + for zero encoded value. */
8513 if (!inst.operands[i].negative)
8514 inst.instruction |= INDEX_UP;
8515 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
8516 }
8517 }
8518}
8519
8520/* inst.operands[i] was set up by parse_address. Encode it into an
8521 ARM-format mode 3 load or store instruction. Reject forms that
8522 cannot be used with such instructions. If is_t is true, reject
8523 forms that cannot be used with a T instruction (i.e. not
8524 post-indexed). */
8525static void
8526encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
8527{
8528 if (inst.operands[i].immisreg && inst.operands[i].shifted)
8529 {
8530 inst.error = _("instruction does not accept scaled register index");
8531 return;
8532 }
8533
8534 encode_arm_addr_mode_common (i, is_t);
8535
8536 if (inst.operands[i].immisreg)
8537 {
8538 constraint ((inst.operands[i].imm == REG_PC
8539 || (is_t && inst.operands[i].reg == REG_PC)),
8540 BAD_PC_ADDRESSING);
8541 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8542 BAD_PC_WRITEBACK);
8543 inst.instruction |= inst.operands[i].imm;
8544 if (!inst.operands[i].negative)
8545 inst.instruction |= INDEX_UP;
8546 }
8547 else /* immediate offset in inst.relocs[0] */
8548 {
8549 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
8550 && inst.operands[i].writeback),
8551 BAD_PC_WRITEBACK);
8552 inst.instruction |= HWOFFSET_IMM;
8553 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8554 {
8555 /* Prefer + for zero encoded value. */
8556 if (!inst.operands[i].negative)
8557 inst.instruction |= INDEX_UP;
8558
8559 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
8560 }
8561 }
8562}
8563
8564/* Write immediate bits [7:0] to the following locations:
8565
8566 |28/24|23 19|18 16|15 4|3 0|
8567 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8568
8569 This function is used by VMOV/VMVN/VORR/VBIC. */
8570
8571static void
8572neon_write_immbits (unsigned immbits)
8573{
8574 inst.instruction |= immbits & 0xf;
8575 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8576 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8577}
8578
8579/* Invert low-order SIZE bits of XHI:XLO. */
8580
8581static void
8582neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
8583{
8584 unsigned immlo = xlo ? *xlo : 0;
8585 unsigned immhi = xhi ? *xhi : 0;
8586
8587 switch (size)
8588 {
8589 case 8:
8590 immlo = (~immlo) & 0xff;
8591 break;
8592
8593 case 16:
8594 immlo = (~immlo) & 0xffff;
8595 break;
8596
8597 case 64:
8598 immhi = (~immhi) & 0xffffffff;
8599 /* fall through. */
8600
8601 case 32:
8602 immlo = (~immlo) & 0xffffffff;
8603 break;
8604
8605 default:
8606 abort ();
8607 }
8608
8609 if (xlo)
8610 *xlo = immlo;
8611
8612 if (xhi)
8613 *xhi = immhi;
8614}
8615
8616/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8617 A, B, C, D. */
8618
8619static int
8620neon_bits_same_in_bytes (unsigned imm)
8621{
8622 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
8623 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
8624 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
8625 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
8626}
8627
8628/* For immediate of above form, return 0bABCD. */
8629
8630static unsigned
8631neon_squash_bits (unsigned imm)
8632{
8633 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
8634 | ((imm & 0x01000000) >> 21);
8635}
8636
8637/* Compress quarter-float representation to 0b...000 abcdefgh. */
8638
8639static unsigned
8640neon_qfloat_bits (unsigned imm)
8641{
8642 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
8643}
8644
8645/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8646 the instruction. *OP is passed as the initial value of the op field, and
8647 may be set to a different value depending on the constant (i.e.
8648 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8649 MVN). If the immediate looks like a repeated pattern then also
8650 try smaller element sizes. */
8651
8652static int
8653neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
8654 unsigned *immbits, int *op, int size,
8655 enum neon_el_type type)
8656{
8657 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8658 float. */
8659 if (type == NT_float && !float_p)
8660 return FAIL;
8661
8662 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
8663 {
8664 if (size != 32 || *op == 1)
8665 return FAIL;
8666 *immbits = neon_qfloat_bits (immlo);
8667 return 0xf;
8668 }
8669
8670 if (size == 64)
8671 {
8672 if (neon_bits_same_in_bytes (immhi)
8673 && neon_bits_same_in_bytes (immlo))
8674 {
8675 if (*op == 1)
8676 return FAIL;
8677 *immbits = (neon_squash_bits (immhi) << 4)
8678 | neon_squash_bits (immlo);
8679 *op = 1;
8680 return 0xe;
8681 }
8682
8683 if (immhi != immlo)
8684 return FAIL;
8685 }
8686
8687 if (size >= 32)
8688 {
8689 if (immlo == (immlo & 0x000000ff))
8690 {
8691 *immbits = immlo;
8692 return 0x0;
8693 }
8694 else if (immlo == (immlo & 0x0000ff00))
8695 {
8696 *immbits = immlo >> 8;
8697 return 0x2;
8698 }
8699 else if (immlo == (immlo & 0x00ff0000))
8700 {
8701 *immbits = immlo >> 16;
8702 return 0x4;
8703 }
8704 else if (immlo == (immlo & 0xff000000))
8705 {
8706 *immbits = immlo >> 24;
8707 return 0x6;
8708 }
8709 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
8710 {
8711 *immbits = (immlo >> 8) & 0xff;
8712 return 0xc;
8713 }
8714 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
8715 {
8716 *immbits = (immlo >> 16) & 0xff;
8717 return 0xd;
8718 }
8719
8720 if ((immlo & 0xffff) != (immlo >> 16))
8721 return FAIL;
8722 immlo &= 0xffff;
8723 }
8724
8725 if (size >= 16)
8726 {
8727 if (immlo == (immlo & 0x000000ff))
8728 {
8729 *immbits = immlo;
8730 return 0x8;
8731 }
8732 else if (immlo == (immlo & 0x0000ff00))
8733 {
8734 *immbits = immlo >> 8;
8735 return 0xa;
8736 }
8737
8738 if ((immlo & 0xff) != (immlo >> 8))
8739 return FAIL;
8740 immlo &= 0xff;
8741 }
8742
8743 if (immlo == (immlo & 0x000000ff))
8744 {
8745 /* Don't allow MVN with 8-bit immediate. */
8746 if (*op == 1)
8747 return FAIL;
8748 *immbits = immlo;
8749 return 0xe;
8750 }
8751
8752 return FAIL;
8753}
8754
8755#if defined BFD_HOST_64_BIT
8756/* Returns TRUE if double precision value V may be cast
8757 to single precision without loss of accuracy. */
8758
8759static bfd_boolean
8760is_double_a_single (bfd_int64_t v)
8761{
8762 int exp = (int)((v >> 52) & 0x7FF);
8763 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
8764
8765 return (exp == 0 || exp == 0x7FF
8766 || (exp >= 1023 - 126 && exp <= 1023 + 127))
8767 && (mantissa & 0x1FFFFFFFl) == 0;
8768}
8769
8770/* Returns a double precision value casted to single precision
8771 (ignoring the least significant bits in exponent and mantissa). */
8772
8773static int
8774double_to_single (bfd_int64_t v)
8775{
8776 int sign = (int) ((v >> 63) & 1l);
8777 int exp = (int) ((v >> 52) & 0x7FF);
8778 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
8779
8780 if (exp == 0x7FF)
8781 exp = 0xFF;
8782 else
8783 {
8784 exp = exp - 1023 + 127;
8785 if (exp >= 0xFF)
8786 {
8787 /* Infinity. */
8788 exp = 0x7F;
8789 mantissa = 0;
8790 }
8791 else if (exp < 0)
8792 {
8793 /* No denormalized numbers. */
8794 exp = 0;
8795 mantissa = 0;
8796 }
8797 }
8798 mantissa >>= 29;
8799 return (sign << 31) | (exp << 23) | mantissa;
8800}
8801#endif /* BFD_HOST_64_BIT */
8802
8803enum lit_type
8804{
8805 CONST_THUMB,
8806 CONST_ARM,
8807 CONST_VEC
8808};
8809
8810static void do_vfp_nsyn_opcode (const char *);
8811
8812/* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8813 Determine whether it can be performed with a move instruction; if
8814 it can, convert inst.instruction to that move instruction and
8815 return TRUE; if it can't, convert inst.instruction to a literal-pool
8816 load and return FALSE. If this is not a valid thing to do in the
8817 current context, set inst.error and return TRUE.
8818
8819 inst.operands[i] describes the destination register. */
8820
8821static bfd_boolean
8822move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
8823{
8824 unsigned long tbit;
8825 bfd_boolean thumb_p = (t == CONST_THUMB);
8826 bfd_boolean arm_p = (t == CONST_ARM);
8827
8828 if (thumb_p)
8829 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8830 else
8831 tbit = LOAD_BIT;
8832
8833 if ((inst.instruction & tbit) == 0)
8834 {
8835 inst.error = _("invalid pseudo operation");
8836 return TRUE;
8837 }
8838
8839 if (inst.relocs[0].exp.X_op != O_constant
8840 && inst.relocs[0].exp.X_op != O_symbol
8841 && inst.relocs[0].exp.X_op != O_big)
8842 {
8843 inst.error = _("constant expression expected");
8844 return TRUE;
8845 }
8846
8847 if (inst.relocs[0].exp.X_op == O_constant
8848 || inst.relocs[0].exp.X_op == O_big)
8849 {
8850#if defined BFD_HOST_64_BIT
8851 bfd_int64_t v;
8852#else
8853 offsetT v;
8854#endif
8855 if (inst.relocs[0].exp.X_op == O_big)
8856 {
8857 LITTLENUM_TYPE w[X_PRECISION];
8858 LITTLENUM_TYPE * l;
8859
8860 if (inst.relocs[0].exp.X_add_number == -1)
8861 {
8862 gen_to_words (w, X_PRECISION, E_PRECISION);
8863 l = w;
8864 /* FIXME: Should we check words w[2..5] ? */
8865 }
8866 else
8867 l = generic_bignum;
8868
8869#if defined BFD_HOST_64_BIT
8870 v =
8871 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
8872 << LITTLENUM_NUMBER_OF_BITS)
8873 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
8874 << LITTLENUM_NUMBER_OF_BITS)
8875 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
8876 << LITTLENUM_NUMBER_OF_BITS)
8877 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
8878#else
8879 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
8880 | (l[0] & LITTLENUM_MASK);
8881#endif
8882 }
8883 else
8884 v = inst.relocs[0].exp.X_add_number;
8885
8886 if (!inst.operands[i].issingle)
8887 {
8888 if (thumb_p)
8889 {
8890 /* LDR should not use lead in a flag-setting instruction being
8891 chosen so we do not check whether movs can be used. */
8892
8893 if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
8894 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8895 && inst.operands[i].reg != 13
8896 && inst.operands[i].reg != 15)
8897 {
8898 /* Check if on thumb2 it can be done with a mov.w, mvn or
8899 movw instruction. */
8900 unsigned int newimm;
8901 bfd_boolean isNegated;
8902
8903 newimm = encode_thumb32_immediate (v);
8904 if (newimm != (unsigned int) FAIL)
8905 isNegated = FALSE;
8906 else
8907 {
8908 newimm = encode_thumb32_immediate (~v);
8909 if (newimm != (unsigned int) FAIL)
8910 isNegated = TRUE;
8911 }
8912
8913 /* The number can be loaded with a mov.w or mvn
8914 instruction. */
8915 if (newimm != (unsigned int) FAIL
8916 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
8917 {
8918 inst.instruction = (0xf04f0000 /* MOV.W. */
8919 | (inst.operands[i].reg << 8));
8920 /* Change to MOVN. */
8921 inst.instruction |= (isNegated ? 0x200000 : 0);
8922 inst.instruction |= (newimm & 0x800) << 15;
8923 inst.instruction |= (newimm & 0x700) << 4;
8924 inst.instruction |= (newimm & 0x0ff);
8925 return TRUE;
8926 }
8927 /* The number can be loaded with a movw instruction. */
8928 else if ((v & ~0xFFFF) == 0
8929 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8930 {
8931 int imm = v & 0xFFFF;
8932
8933 inst.instruction = 0xf2400000; /* MOVW. */
8934 inst.instruction |= (inst.operands[i].reg << 8);
8935 inst.instruction |= (imm & 0xf000) << 4;
8936 inst.instruction |= (imm & 0x0800) << 15;
8937 inst.instruction |= (imm & 0x0700) << 4;
8938 inst.instruction |= (imm & 0x00ff);
8939 /* In case this replacement is being done on Armv8-M
8940 Baseline we need to make sure to disable the
8941 instruction size check, as otherwise GAS will reject
8942 the use of this T32 instruction. */
8943 inst.size_req = 0;
8944 return TRUE;
8945 }
8946 }
8947 }
8948 else if (arm_p)
8949 {
8950 int value = encode_arm_immediate (v);
8951
8952 if (value != FAIL)
8953 {
8954 /* This can be done with a mov instruction. */
8955 inst.instruction &= LITERAL_MASK;
8956 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8957 inst.instruction |= value & 0xfff;
8958 return TRUE;
8959 }
8960
8961 value = encode_arm_immediate (~ v);
8962 if (value != FAIL)
8963 {
8964 /* This can be done with a mvn instruction. */
8965 inst.instruction &= LITERAL_MASK;
8966 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8967 inst.instruction |= value & 0xfff;
8968 return TRUE;
8969 }
8970 }
8971 else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
8972 {
8973 int op = 0;
8974 unsigned immbits = 0;
8975 unsigned immlo = inst.operands[1].imm;
8976 unsigned immhi = inst.operands[1].regisimm
8977 ? inst.operands[1].reg
8978 : inst.relocs[0].exp.X_unsigned
8979 ? 0
8980 : ((bfd_int64_t)((int) immlo)) >> 32;
8981 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8982 &op, 64, NT_invtype);
8983
8984 if (cmode == FAIL)
8985 {
8986 neon_invert_size (&immlo, &immhi, 64);
8987 op = !op;
8988 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8989 &op, 64, NT_invtype);
8990 }
8991
8992 if (cmode != FAIL)
8993 {
8994 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8995 | (1 << 23)
8996 | (cmode << 8)
8997 | (op << 5)
8998 | (1 << 4);
8999
9000 /* Fill other bits in vmov encoding for both thumb and arm. */
9001 if (thumb_mode)
9002 inst.instruction |= (0x7U << 29) | (0xF << 24);
9003 else
9004 inst.instruction |= (0xFU << 28) | (0x1 << 25);
9005 neon_write_immbits (immbits);
9006 return TRUE;
9007 }
9008 }
9009 }
9010
9011 if (t == CONST_VEC)
9012 {
9013 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
9014 if (inst.operands[i].issingle
9015 && is_quarter_float (inst.operands[1].imm)
9016 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
9017 {
9018 inst.operands[1].imm =
9019 neon_qfloat_bits (v);
9020 do_vfp_nsyn_opcode ("fconsts");
9021 return TRUE;
9022 }
9023
9024 /* If our host does not support a 64-bit type then we cannot perform
9025 the following optimization. This mean that there will be a
9026 discrepancy between the output produced by an assembler built for
9027 a 32-bit-only host and the output produced from a 64-bit host, but
9028 this cannot be helped. */
9029#if defined BFD_HOST_64_BIT
9030 else if (!inst.operands[1].issingle
9031 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
9032 {
9033 if (is_double_a_single (v)
9034 && is_quarter_float (double_to_single (v)))
9035 {
9036 inst.operands[1].imm =
9037 neon_qfloat_bits (double_to_single (v));
9038 do_vfp_nsyn_opcode ("fconstd");
9039 return TRUE;
9040 }
9041 }
9042#endif
9043 }
9044 }
9045
9046 if (add_to_lit_pool ((!inst.operands[i].isvec
9047 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
9048 return TRUE;
9049
9050 inst.operands[1].reg = REG_PC;
9051 inst.operands[1].isreg = 1;
9052 inst.operands[1].preind = 1;
9053 inst.relocs[0].pc_rel = 1;
9054 inst.relocs[0].type = (thumb_p
9055 ? BFD_RELOC_ARM_THUMB_OFFSET
9056 : (mode_3
9057 ? BFD_RELOC_ARM_HWLITERAL
9058 : BFD_RELOC_ARM_LITERAL));
9059 return FALSE;
9060}
9061
9062/* inst.operands[i] was set up by parse_address. Encode it into an
9063 ARM-format instruction. Reject all forms which cannot be encoded
9064 into a coprocessor load/store instruction. If wb_ok is false,
9065 reject use of writeback; if unind_ok is false, reject use of
9066 unindexed addressing. If reloc_override is not 0, use it instead
9067 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9068 (in which case it is preserved). */
9069
9070static int
9071encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
9072{
9073 if (!inst.operands[i].isreg)
9074 {
9075 /* PR 18256 */
9076 if (! inst.operands[0].isvec)
9077 {
9078 inst.error = _("invalid co-processor operand");
9079 return FAIL;
9080 }
9081 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
9082 return SUCCESS;
9083 }
9084
9085 inst.instruction |= inst.operands[i].reg << 16;
9086
9087 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
9088
9089 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
9090 {
9091 gas_assert (!inst.operands[i].writeback);
9092 if (!unind_ok)
9093 {
9094 inst.error = _("instruction does not support unindexed addressing");
9095 return FAIL;
9096 }
9097 inst.instruction |= inst.operands[i].imm;
9098 inst.instruction |= INDEX_UP;
9099 return SUCCESS;
9100 }
9101
9102 if (inst.operands[i].preind)
9103 inst.instruction |= PRE_INDEX;
9104
9105 if (inst.operands[i].writeback)
9106 {
9107 if (inst.operands[i].reg == REG_PC)
9108 {
9109 inst.error = _("pc may not be used with write-back");
9110 return FAIL;
9111 }
9112 if (!wb_ok)
9113 {
9114 inst.error = _("instruction does not support writeback");
9115 return FAIL;
9116 }
9117 inst.instruction |= WRITE_BACK;
9118 }
9119
9120 if (reloc_override)
9121 inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
9122 else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
9123 || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
9124 && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
9125 {
9126 if (thumb_mode)
9127 inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
9128 else
9129 inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
9130 }
9131
9132 /* Prefer + for zero encoded value. */
9133 if (!inst.operands[i].negative)
9134 inst.instruction |= INDEX_UP;
9135
9136 return SUCCESS;
9137}
9138
9139/* Functions for instruction encoding, sorted by sub-architecture.
9140 First some generics; their names are taken from the conventional
9141 bit positions for register arguments in ARM format instructions. */
9142
9143static void
9144do_noargs (void)
9145{
9146}
9147
9148static void
9149do_rd (void)
9150{
9151 inst.instruction |= inst.operands[0].reg << 12;
9152}
9153
9154static void
9155do_rn (void)
9156{
9157 inst.instruction |= inst.operands[0].reg << 16;
9158}
9159
9160static void
9161do_rd_rm (void)
9162{
9163 inst.instruction |= inst.operands[0].reg << 12;
9164 inst.instruction |= inst.operands[1].reg;
9165}
9166
9167static void
9168do_rm_rn (void)
9169{
9170 inst.instruction |= inst.operands[0].reg;
9171 inst.instruction |= inst.operands[1].reg << 16;
9172}
9173
9174static void
9175do_rd_rn (void)
9176{
9177 inst.instruction |= inst.operands[0].reg << 12;
9178 inst.instruction |= inst.operands[1].reg << 16;
9179}
9180
9181static void
9182do_rn_rd (void)
9183{
9184 inst.instruction |= inst.operands[0].reg << 16;
9185 inst.instruction |= inst.operands[1].reg << 12;
9186}
9187
9188static void
9189do_tt (void)
9190{
9191 inst.instruction |= inst.operands[0].reg << 8;
9192 inst.instruction |= inst.operands[1].reg << 16;
9193}
9194
9195static bfd_boolean
9196check_obsolete (const arm_feature_set *feature, const char *msg)
9197{
9198 if (ARM_CPU_IS_ANY (cpu_variant))
9199 {
9200 as_tsktsk ("%s", msg);
9201 return TRUE;
9202 }
9203 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
9204 {
9205 as_bad ("%s", msg);
9206 return TRUE;
9207 }
9208
9209 return FALSE;
9210}
9211
9212static void
9213do_rd_rm_rn (void)
9214{
9215 unsigned Rn = inst.operands[2].reg;
9216 /* Enforce restrictions on SWP instruction. */
9217 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
9218 {
9219 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
9220 _("Rn must not overlap other operands"));
9221
9222 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9223 */
9224 if (!check_obsolete (&arm_ext_v8,
9225 _("swp{b} use is obsoleted for ARMv8 and later"))
9226 && warn_on_deprecated
9227 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
9228 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9229 }
9230
9231 inst.instruction |= inst.operands[0].reg << 12;
9232 inst.instruction |= inst.operands[1].reg;
9233 inst.instruction |= Rn << 16;
9234}
9235
9236static void
9237do_rd_rn_rm (void)
9238{
9239 inst.instruction |= inst.operands[0].reg << 12;
9240 inst.instruction |= inst.operands[1].reg << 16;
9241 inst.instruction |= inst.operands[2].reg;
9242}
9243
9244static void
9245do_rm_rd_rn (void)
9246{
9247 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
9248 constraint (((inst.relocs[0].exp.X_op != O_constant
9249 && inst.relocs[0].exp.X_op != O_illegal)
9250 || inst.relocs[0].exp.X_add_number != 0),
9251 BAD_ADDR_MODE);
9252 inst.instruction |= inst.operands[0].reg;
9253 inst.instruction |= inst.operands[1].reg << 12;
9254 inst.instruction |= inst.operands[2].reg << 16;
9255}
9256
9257static void
9258do_imm0 (void)
9259{
9260 inst.instruction |= inst.operands[0].imm;
9261}
9262
9263static void
9264do_rd_cpaddr (void)
9265{
9266 inst.instruction |= inst.operands[0].reg << 12;
9267 encode_arm_cp_address (1, TRUE, TRUE, 0);
9268}
9269
9270/* ARM instructions, in alphabetical order by function name (except
9271 that wrapper functions appear immediately after the function they
9272 wrap). */
9273
9274/* This is a pseudo-op of the form "adr rd, label" to be converted
9275 into a relative address of the form "add rd, pc, #label-.-8". */
9276
9277static void
9278do_adr (void)
9279{
9280 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9281
9282 /* Frag hacking will turn this into a sub instruction if the offset turns
9283 out to be negative. */
9284 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9285 inst.relocs[0].pc_rel = 1;
9286 inst.relocs[0].exp.X_add_number -= 8;
9287
9288 if (support_interwork
9289 && inst.relocs[0].exp.X_op == O_symbol
9290 && inst.relocs[0].exp.X_add_symbol != NULL
9291 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9292 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9293 inst.relocs[0].exp.X_add_number |= 1;
9294}
9295
9296/* This is a pseudo-op of the form "adrl rd, label" to be converted
9297 into a relative address of the form:
9298 add rd, pc, #low(label-.-8)"
9299 add rd, rd, #high(label-.-8)" */
9300
9301static void
9302do_adrl (void)
9303{
9304 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9305
9306 /* Frag hacking will turn this into a sub instruction if the offset turns
9307 out to be negative. */
9308 inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9309 inst.relocs[0].pc_rel = 1;
9310 inst.size = INSN_SIZE * 2;
9311 inst.relocs[0].exp.X_add_number -= 8;
9312
9313 if (support_interwork
9314 && inst.relocs[0].exp.X_op == O_symbol
9315 && inst.relocs[0].exp.X_add_symbol != NULL
9316 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9317 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9318 inst.relocs[0].exp.X_add_number |= 1;
9319}
9320
9321static void
9322do_arit (void)
9323{
9324 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9325 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9326 THUMB1_RELOC_ONLY);
9327 if (!inst.operands[1].present)
9328 inst.operands[1].reg = inst.operands[0].reg;
9329 inst.instruction |= inst.operands[0].reg << 12;
9330 inst.instruction |= inst.operands[1].reg << 16;
9331 encode_arm_shifter_operand (2);
9332}
9333
9334static void
9335do_barrier (void)
9336{
9337 if (inst.operands[0].present)
9338 inst.instruction |= inst.operands[0].imm;
9339 else
9340 inst.instruction |= 0xf;
9341}
9342
9343static void
9344do_bfc (void)
9345{
9346 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9347 constraint (msb > 32, _("bit-field extends past end of register"));
9348 /* The instruction encoding stores the LSB and MSB,
9349 not the LSB and width. */
9350 inst.instruction |= inst.operands[0].reg << 12;
9351 inst.instruction |= inst.operands[1].imm << 7;
9352 inst.instruction |= (msb - 1) << 16;
9353}
9354
9355static void
9356do_bfi (void)
9357{
9358 unsigned int msb;
9359
9360 /* #0 in second position is alternative syntax for bfc, which is
9361 the same instruction but with REG_PC in the Rm field. */
9362 if (!inst.operands[1].isreg)
9363 inst.operands[1].reg = REG_PC;
9364
9365 msb = inst.operands[2].imm + inst.operands[3].imm;
9366 constraint (msb > 32, _("bit-field extends past end of register"));
9367 /* The instruction encoding stores the LSB and MSB,
9368 not the LSB and width. */
9369 inst.instruction |= inst.operands[0].reg << 12;
9370 inst.instruction |= inst.operands[1].reg;
9371 inst.instruction |= inst.operands[2].imm << 7;
9372 inst.instruction |= (msb - 1) << 16;
9373}
9374
9375static void
9376do_bfx (void)
9377{
9378 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9379 _("bit-field extends past end of register"));
9380 inst.instruction |= inst.operands[0].reg << 12;
9381 inst.instruction |= inst.operands[1].reg;
9382 inst.instruction |= inst.operands[2].imm << 7;
9383 inst.instruction |= (inst.operands[3].imm - 1) << 16;
9384}
9385
9386/* ARM V5 breakpoint instruction (argument parse)
9387 BKPT <16 bit unsigned immediate>
9388 Instruction is not conditional.
9389 The bit pattern given in insns[] has the COND_ALWAYS condition,
9390 and it is an error if the caller tried to override that. */
9391
9392static void
9393do_bkpt (void)
9394{
9395 /* Top 12 of 16 bits to bits 19:8. */
9396 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
9397
9398 /* Bottom 4 of 16 bits to bits 3:0. */
9399 inst.instruction |= inst.operands[0].imm & 0xf;
9400}
9401
9402static void
9403encode_branch (int default_reloc)
9404{
9405 if (inst.operands[0].hasreloc)
9406 {
9407 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
9408 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9409 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9410 inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
9411 ? BFD_RELOC_ARM_PLT32
9412 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
9413 }
9414 else
9415 inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9416 inst.relocs[0].pc_rel = 1;
9417}
9418
9419static void
9420do_branch (void)
9421{
9422#ifdef OBJ_ELF
9423 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9424 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9425 else
9426#endif
9427 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9428}
9429
9430static void
9431do_bl (void)
9432{
9433#ifdef OBJ_ELF
9434 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9435 {
9436 if (inst.cond == COND_ALWAYS)
9437 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
9438 else
9439 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9440 }
9441 else
9442#endif
9443 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9444}
9445
9446/* ARM V5 branch-link-exchange instruction (argument parse)
9447 BLX <target_addr> ie BLX(1)
9448 BLX{<condition>} <Rm> ie BLX(2)
9449 Unfortunately, there are two different opcodes for this mnemonic.
9450 So, the insns[].value is not used, and the code here zaps values
9451 into inst.instruction.
9452 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9453
9454static void
9455do_blx (void)
9456{
9457 if (inst.operands[0].isreg)
9458 {
9459 /* Arg is a register; the opcode provided by insns[] is correct.
9460 It is not illegal to do "blx pc", just useless. */
9461 if (inst.operands[0].reg == REG_PC)
9462 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9463
9464 inst.instruction |= inst.operands[0].reg;
9465 }
9466 else
9467 {
9468 /* Arg is an address; this instruction cannot be executed
9469 conditionally, and the opcode must be adjusted.
9470 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9471 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9472 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9473 inst.instruction = 0xfa000000;
9474 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
9475 }
9476}
9477
9478static void
9479do_bx (void)
9480{
9481 bfd_boolean want_reloc;
9482
9483 if (inst.operands[0].reg == REG_PC)
9484 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9485
9486 inst.instruction |= inst.operands[0].reg;
9487 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9488 it is for ARMv4t or earlier. */
9489 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
9490 if (!ARM_FEATURE_ZERO (selected_object_arch)
9491 && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
9492 want_reloc = TRUE;
9493
9494#ifdef OBJ_ELF
9495 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
9496#endif
9497 want_reloc = FALSE;
9498
9499 if (want_reloc)
9500 inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
9501}
9502
9503
9504/* ARM v5TEJ. Jump to Jazelle code. */
9505
9506static void
9507do_bxj (void)
9508{
9509 if (inst.operands[0].reg == REG_PC)
9510 as_tsktsk (_("use of r15 in bxj is not really useful"));
9511
9512 inst.instruction |= inst.operands[0].reg;
9513}
9514
9515/* Co-processor data operation:
9516 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9517 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9518static void
9519do_cdp (void)
9520{
9521 inst.instruction |= inst.operands[0].reg << 8;
9522 inst.instruction |= inst.operands[1].imm << 20;
9523 inst.instruction |= inst.operands[2].reg << 12;
9524 inst.instruction |= inst.operands[3].reg << 16;
9525 inst.instruction |= inst.operands[4].reg;
9526 inst.instruction |= inst.operands[5].imm << 5;
9527}
9528
9529static void
9530do_cmp (void)
9531{
9532 inst.instruction |= inst.operands[0].reg << 16;
9533 encode_arm_shifter_operand (1);
9534}
9535
9536/* Transfer between coprocessor and ARM registers.
9537 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9538 MRC2
9539 MCR{cond}
9540 MCR2
9541
9542 No special properties. */
9543
9544struct deprecated_coproc_regs_s
9545{
9546 unsigned cp;
9547 int opc1;
9548 unsigned crn;
9549 unsigned crm;
9550 int opc2;
9551 arm_feature_set deprecated;
9552 arm_feature_set obsoleted;
9553 const char *dep_msg;
9554 const char *obs_msg;
9555};
9556
9557#define DEPR_ACCESS_V8 \
9558 N_("This coprocessor register access is deprecated in ARMv8")
9559
9560/* Table of all deprecated coprocessor registers. */
9561static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
9562{
9563 {15, 0, 7, 10, 5, /* CP15DMB. */
9564 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9565 DEPR_ACCESS_V8, NULL},
9566 {15, 0, 7, 10, 4, /* CP15DSB. */
9567 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9568 DEPR_ACCESS_V8, NULL},
9569 {15, 0, 7, 5, 4, /* CP15ISB. */
9570 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9571 DEPR_ACCESS_V8, NULL},
9572 {14, 6, 1, 0, 0, /* TEEHBR. */
9573 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9574 DEPR_ACCESS_V8, NULL},
9575 {14, 6, 0, 0, 0, /* TEECR. */
9576 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9577 DEPR_ACCESS_V8, NULL},
9578};
9579
9580#undef DEPR_ACCESS_V8
9581
9582static const size_t deprecated_coproc_reg_count =
9583 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
9584
9585static void
9586do_co_reg (void)
9587{
9588 unsigned Rd;
9589 size_t i;
9590
9591 Rd = inst.operands[2].reg;
9592 if (thumb_mode)
9593 {
9594 if (inst.instruction == 0xee000010
9595 || inst.instruction == 0xfe000010)
9596 /* MCR, MCR2 */
9597 reject_bad_reg (Rd);
9598 else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
9599 /* MRC, MRC2 */
9600 constraint (Rd == REG_SP, BAD_SP);
9601 }
9602 else
9603 {
9604 /* MCR */
9605 if (inst.instruction == 0xe000010)
9606 constraint (Rd == REG_PC, BAD_PC);
9607 }
9608
9609 for (i = 0; i < deprecated_coproc_reg_count; ++i)
9610 {
9611 const struct deprecated_coproc_regs_s *r =
9612 deprecated_coproc_regs + i;
9613
9614 if (inst.operands[0].reg == r->cp
9615 && inst.operands[1].imm == r->opc1
9616 && inst.operands[3].reg == r->crn
9617 && inst.operands[4].reg == r->crm
9618 && inst.operands[5].imm == r->opc2)
9619 {
9620 if (! ARM_CPU_IS_ANY (cpu_variant)
9621 && warn_on_deprecated
9622 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
9623 as_tsktsk ("%s", r->dep_msg);
9624 }
9625 }
9626
9627 inst.instruction |= inst.operands[0].reg << 8;
9628 inst.instruction |= inst.operands[1].imm << 21;
9629 inst.instruction |= Rd << 12;
9630 inst.instruction |= inst.operands[3].reg << 16;
9631 inst.instruction |= inst.operands[4].reg;
9632 inst.instruction |= inst.operands[5].imm << 5;
9633}
9634
9635/* Transfer between coprocessor register and pair of ARM registers.
9636 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9637 MCRR2
9638 MRRC{cond}
9639 MRRC2
9640
9641 Two XScale instructions are special cases of these:
9642
9643 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9644 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9645
9646 Result unpredictable if Rd or Rn is R15. */
9647
9648static void
9649do_co_reg2c (void)
9650{
9651 unsigned Rd, Rn;
9652
9653 Rd = inst.operands[2].reg;
9654 Rn = inst.operands[3].reg;
9655
9656 if (thumb_mode)
9657 {
9658 reject_bad_reg (Rd);
9659 reject_bad_reg (Rn);
9660 }
9661 else
9662 {
9663 constraint (Rd == REG_PC, BAD_PC);
9664 constraint (Rn == REG_PC, BAD_PC);
9665 }
9666
9667 /* Only check the MRRC{2} variants. */
9668 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9669 {
9670 /* If Rd == Rn, error that the operation is
9671 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9672 constraint (Rd == Rn, BAD_OVERLAP);
9673 }
9674
9675 inst.instruction |= inst.operands[0].reg << 8;
9676 inst.instruction |= inst.operands[1].imm << 4;
9677 inst.instruction |= Rd << 12;
9678 inst.instruction |= Rn << 16;
9679 inst.instruction |= inst.operands[4].reg;
9680}
9681
9682static void
9683do_cpsi (void)
9684{
9685 inst.instruction |= inst.operands[0].imm << 6;
9686 if (inst.operands[1].present)
9687 {
9688 inst.instruction |= CPSI_MMOD;
9689 inst.instruction |= inst.operands[1].imm;
9690 }
9691}
9692
9693static void
9694do_dbg (void)
9695{
9696 inst.instruction |= inst.operands[0].imm;
9697}
9698
9699static void
9700do_div (void)
9701{
9702 unsigned Rd, Rn, Rm;
9703
9704 Rd = inst.operands[0].reg;
9705 Rn = (inst.operands[1].present
9706 ? inst.operands[1].reg : Rd);
9707 Rm = inst.operands[2].reg;
9708
9709 constraint ((Rd == REG_PC), BAD_PC);
9710 constraint ((Rn == REG_PC), BAD_PC);
9711 constraint ((Rm == REG_PC), BAD_PC);
9712
9713 inst.instruction |= Rd << 16;
9714 inst.instruction |= Rn << 0;
9715 inst.instruction |= Rm << 8;
9716}
9717
9718static void
9719do_it (void)
9720{
9721 /* There is no IT instruction in ARM mode. We
9722 process it to do the validation as if in
9723 thumb mode, just in case the code gets
9724 assembled for thumb using the unified syntax. */
9725
9726 inst.size = 0;
9727 if (unified_syntax)
9728 {
9729 set_pred_insn_type (IT_INSN);
9730 now_pred.mask = (inst.instruction & 0xf) | 0x10;
9731 now_pred.cc = inst.operands[0].imm;
9732 }
9733}
9734
9735/* If there is only one register in the register list,
9736 then return its register number. Otherwise return -1. */
9737static int
9738only_one_reg_in_list (int range)
9739{
9740 int i = ffs (range) - 1;
9741 return (i > 15 || range != (1 << i)) ? -1 : i;
9742}
9743
9744static void
9745encode_ldmstm(int from_push_pop_mnem)
9746{
9747 int base_reg = inst.operands[0].reg;
9748 int range = inst.operands[1].imm;
9749 int one_reg;
9750
9751 inst.instruction |= base_reg << 16;
9752 inst.instruction |= range;
9753
9754 if (inst.operands[1].writeback)
9755 inst.instruction |= LDM_TYPE_2_OR_3;
9756
9757 if (inst.operands[0].writeback)
9758 {
9759 inst.instruction |= WRITE_BACK;
9760 /* Check for unpredictable uses of writeback. */
9761 if (inst.instruction & LOAD_BIT)
9762 {
9763 /* Not allowed in LDM type 2. */
9764 if ((inst.instruction & LDM_TYPE_2_OR_3)
9765 && ((range & (1 << REG_PC)) == 0))
9766 as_warn (_("writeback of base register is UNPREDICTABLE"));
9767 /* Only allowed if base reg not in list for other types. */
9768 else if (range & (1 << base_reg))
9769 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9770 }
9771 else /* STM. */
9772 {
9773 /* Not allowed for type 2. */
9774 if (inst.instruction & LDM_TYPE_2_OR_3)
9775 as_warn (_("writeback of base register is UNPREDICTABLE"));
9776 /* Only allowed if base reg not in list, or first in list. */
9777 else if ((range & (1 << base_reg))
9778 && (range & ((1 << base_reg) - 1)))
9779 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9780 }
9781 }
9782
9783 /* If PUSH/POP has only one register, then use the A2 encoding. */
9784 one_reg = only_one_reg_in_list (range);
9785 if (from_push_pop_mnem && one_reg >= 0)
9786 {
9787 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9788
9789 if (is_push && one_reg == 13 /* SP */)
9790 /* PR 22483: The A2 encoding cannot be used when
9791 pushing the stack pointer as this is UNPREDICTABLE. */
9792 return;
9793
9794 inst.instruction &= A_COND_MASK;
9795 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9796 inst.instruction |= one_reg << 12;
9797 }
9798}
9799
9800static void
9801do_ldmstm (void)
9802{
9803 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
9804}
9805
9806/* ARMv5TE load-consecutive (argument parse)
9807 Mode is like LDRH.
9808
9809 LDRccD R, mode
9810 STRccD R, mode. */
9811
9812static void
9813do_ldrd (void)
9814{
9815 constraint (inst.operands[0].reg % 2 != 0,
9816 _("first transfer register must be even"));
9817 constraint (inst.operands[1].present
9818 && inst.operands[1].reg != inst.operands[0].reg + 1,
9819 _("can only transfer two consecutive registers"));
9820 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9821 constraint (!inst.operands[2].isreg, _("'[' expected"));
9822
9823 if (!inst.operands[1].present)
9824 inst.operands[1].reg = inst.operands[0].reg + 1;
9825
9826 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9827 register and the first register written; we have to diagnose
9828 overlap between the base and the second register written here. */
9829
9830 if (inst.operands[2].reg == inst.operands[1].reg
9831 && (inst.operands[2].writeback || inst.operands[2].postind))
9832 as_warn (_("base register written back, and overlaps "
9833 "second transfer register"));
9834
9835 if (!(inst.instruction & V4_STR_BIT))
9836 {
9837 /* For an index-register load, the index register must not overlap the
9838 destination (even if not write-back). */
9839 if (inst.operands[2].immisreg
9840 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9841 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9842 as_warn (_("index register overlaps transfer register"));
9843 }
9844 inst.instruction |= inst.operands[0].reg << 12;
9845 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
9846}
9847
9848static void
9849do_ldrex (void)
9850{
9851 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9852 || inst.operands[1].postind || inst.operands[1].writeback
9853 || inst.operands[1].immisreg || inst.operands[1].shifted
9854 || inst.operands[1].negative
9855 /* This can arise if the programmer has written
9856 strex rN, rM, foo
9857 or if they have mistakenly used a register name as the last
9858 operand, eg:
9859 strex rN, rM, rX
9860 It is very difficult to distinguish between these two cases
9861 because "rX" might actually be a label. ie the register
9862 name has been occluded by a symbol of the same name. So we
9863 just generate a general 'bad addressing mode' type error
9864 message and leave it up to the programmer to discover the
9865 true cause and fix their mistake. */
9866 || (inst.operands[1].reg == REG_PC),
9867 BAD_ADDR_MODE);
9868
9869 constraint (inst.relocs[0].exp.X_op != O_constant
9870 || inst.relocs[0].exp.X_add_number != 0,
9871 _("offset must be zero in ARM encoding"));
9872
9873 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9874
9875 inst.instruction |= inst.operands[0].reg << 12;
9876 inst.instruction |= inst.operands[1].reg << 16;
9877 inst.relocs[0].type = BFD_RELOC_UNUSED;
9878}
9879
9880static void
9881do_ldrexd (void)
9882{
9883 constraint (inst.operands[0].reg % 2 != 0,
9884 _("even register required"));
9885 constraint (inst.operands[1].present
9886 && inst.operands[1].reg != inst.operands[0].reg + 1,
9887 _("can only load two consecutive registers"));
9888 /* If op 1 were present and equal to PC, this function wouldn't
9889 have been called in the first place. */
9890 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9891
9892 inst.instruction |= inst.operands[0].reg << 12;
9893 inst.instruction |= inst.operands[2].reg << 16;
9894}
9895
9896/* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9897 which is not a multiple of four is UNPREDICTABLE. */
9898static void
9899check_ldr_r15_aligned (void)
9900{
9901 constraint (!(inst.operands[1].immisreg)
9902 && (inst.operands[0].reg == REG_PC
9903 && inst.operands[1].reg == REG_PC
9904 && (inst.relocs[0].exp.X_add_number & 0x3)),
9905 _("ldr to register 15 must be 4-byte aligned"));
9906}
9907
9908static void
9909do_ldst (void)
9910{
9911 inst.instruction |= inst.operands[0].reg << 12;
9912 if (!inst.operands[1].isreg)
9913 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
9914 return;
9915 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
9916 check_ldr_r15_aligned ();
9917}
9918
9919static void
9920do_ldstt (void)
9921{
9922 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9923 reject [Rn,...]. */
9924 if (inst.operands[1].preind)
9925 {
9926 constraint (inst.relocs[0].exp.X_op != O_constant
9927 || inst.relocs[0].exp.X_add_number != 0,
9928 _("this instruction requires a post-indexed address"));
9929
9930 inst.operands[1].preind = 0;
9931 inst.operands[1].postind = 1;
9932 inst.operands[1].writeback = 1;
9933 }
9934 inst.instruction |= inst.operands[0].reg << 12;
9935 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
9936}
9937
9938/* Halfword and signed-byte load/store operations. */
9939
9940static void
9941do_ldstv4 (void)
9942{
9943 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9944 inst.instruction |= inst.operands[0].reg << 12;
9945 if (!inst.operands[1].isreg)
9946 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
9947 return;
9948 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
9949}
9950
9951static void
9952do_ldsttv4 (void)
9953{
9954 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9955 reject [Rn,...]. */
9956 if (inst.operands[1].preind)
9957 {
9958 constraint (inst.relocs[0].exp.X_op != O_constant
9959 || inst.relocs[0].exp.X_add_number != 0,
9960 _("this instruction requires a post-indexed address"));
9961
9962 inst.operands[1].preind = 0;
9963 inst.operands[1].postind = 1;
9964 inst.operands[1].writeback = 1;
9965 }
9966 inst.instruction |= inst.operands[0].reg << 12;
9967 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
9968}
9969
9970/* Co-processor register load/store.
9971 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9972static void
9973do_lstc (void)
9974{
9975 inst.instruction |= inst.operands[0].reg << 8;
9976 inst.instruction |= inst.operands[1].reg << 12;
9977 encode_arm_cp_address (2, TRUE, TRUE, 0);
9978}
9979
9980static void
9981do_mlas (void)
9982{
9983 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9984 if (inst.operands[0].reg == inst.operands[1].reg
9985 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
9986 && !(inst.instruction & 0x00400000))
9987 as_tsktsk (_("Rd and Rm should be different in mla"));
9988
9989 inst.instruction |= inst.operands[0].reg << 16;
9990 inst.instruction |= inst.operands[1].reg;
9991 inst.instruction |= inst.operands[2].reg << 8;
9992 inst.instruction |= inst.operands[3].reg << 12;
9993}
9994
9995static void
9996do_mov (void)
9997{
9998 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9999 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
10000 THUMB1_RELOC_ONLY);
10001 inst.instruction |= inst.operands[0].reg << 12;
10002 encode_arm_shifter_operand (1);
10003}
10004
10005/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
10006static void
10007do_mov16 (void)
10008{
10009 bfd_vma imm;
10010 bfd_boolean top;
10011
10012 top = (inst.instruction & 0x00400000) != 0;
10013 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
10014 _(":lower16: not allowed in this instruction"));
10015 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
10016 _(":upper16: not allowed in this instruction"));
10017 inst.instruction |= inst.operands[0].reg << 12;
10018 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
10019 {
10020 imm = inst.relocs[0].exp.X_add_number;
10021 /* The value is in two pieces: 0:11, 16:19. */
10022 inst.instruction |= (imm & 0x00000fff);
10023 inst.instruction |= (imm & 0x0000f000) << 4;
10024 }
10025}
10026
10027static int
10028do_vfp_nsyn_mrs (void)
10029{
10030 if (inst.operands[0].isvec)
10031 {
10032 if (inst.operands[1].reg != 1)
10033 first_error (_("operand 1 must be FPSCR"));
10034 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
10035 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
10036 do_vfp_nsyn_opcode ("fmstat");
10037 }
10038 else if (inst.operands[1].isvec)
10039 do_vfp_nsyn_opcode ("fmrx");
10040 else
10041 return FAIL;
10042
10043 return SUCCESS;
10044}
10045
10046static int
10047do_vfp_nsyn_msr (void)
10048{
10049 if (inst.operands[0].isvec)
10050 do_vfp_nsyn_opcode ("fmxr");
10051 else
10052 return FAIL;
10053
10054 return SUCCESS;
10055}
10056
10057static void
10058do_vmrs (void)
10059{
10060 unsigned Rt = inst.operands[0].reg;
10061
10062 if (thumb_mode && Rt == REG_SP)
10063 {
10064 inst.error = BAD_SP;
10065 return;
10066 }
10067
10068 switch (inst.operands[1].reg)
10069 {
10070 /* MVFR2 is only valid for Armv8-A. */
10071 case 5:
10072 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
10073 _(BAD_FPU));
10074 break;
10075
10076 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10077 case 1: /* fpscr. */
10078 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10079 || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10080 _(BAD_FPU));
10081 break;
10082
10083 case 14: /* fpcxt_ns. */
10084 case 15: /* fpcxt_s. */
10085 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
10086 _("selected processor does not support instruction"));
10087 break;
10088
10089 case 2: /* fpscr_nzcvqc. */
10090 case 12: /* vpr. */
10091 case 13: /* p0. */
10092 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
10093 || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10094 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10095 _("selected processor does not support instruction"));
10096 if (inst.operands[0].reg != 2
10097 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
10098 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10099 break;
10100
10101 default:
10102 break;
10103 }
10104
10105 /* APSR_ sets isvec. All other refs to PC are illegal. */
10106 if (!inst.operands[0].isvec && Rt == REG_PC)
10107 {
10108 inst.error = BAD_PC;
10109 return;
10110 }
10111
10112 /* If we get through parsing the register name, we just insert the number
10113 generated into the instruction without further validation. */
10114 inst.instruction |= (inst.operands[1].reg << 16);
10115 inst.instruction |= (Rt << 12);
10116}
10117
10118static void
10119do_vmsr (void)
10120{
10121 unsigned Rt = inst.operands[1].reg;
10122
10123 if (thumb_mode)
10124 reject_bad_reg (Rt);
10125 else if (Rt == REG_PC)
10126 {
10127 inst.error = BAD_PC;
10128 return;
10129 }
10130
10131 switch (inst.operands[0].reg)
10132 {
10133 /* MVFR2 is only valid for Armv8-A. */
10134 case 5:
10135 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
10136 _(BAD_FPU));
10137 break;
10138
10139 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10140 case 1: /* fpcr. */
10141 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10142 || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10143 _(BAD_FPU));
10144 break;
10145
10146 case 14: /* fpcxt_ns. */
10147 case 15: /* fpcxt_s. */
10148 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
10149 _("selected processor does not support instruction"));
10150 break;
10151
10152 case 2: /* fpscr_nzcvqc. */
10153 case 12: /* vpr. */
10154 case 13: /* p0. */
10155 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
10156 || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10157 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10158 _("selected processor does not support instruction"));
10159 if (inst.operands[0].reg != 2
10160 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
10161 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10162 break;
10163
10164 default:
10165 break;
10166 }
10167
10168 /* If we get through parsing the register name, we just insert the number
10169 generated into the instruction without further validation. */
10170 inst.instruction |= (inst.operands[0].reg << 16);
10171 inst.instruction |= (Rt << 12);
10172}
10173
10174static void
10175do_mrs (void)
10176{
10177 unsigned br;
10178
10179 if (do_vfp_nsyn_mrs () == SUCCESS)
10180 return;
10181
10182 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10183 inst.instruction |= inst.operands[0].reg << 12;
10184
10185 if (inst.operands[1].isreg)
10186 {
10187 br = inst.operands[1].reg;
10188 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000))
10189 as_bad (_("bad register for mrs"));
10190 }
10191 else
10192 {
10193 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10194 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
10195 != (PSR_c|PSR_f),
10196 _("'APSR', 'CPSR' or 'SPSR' expected"));
10197 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
10198 }
10199
10200 inst.instruction |= br;
10201}
10202
10203/* Two possible forms:
10204 "{C|S}PSR_<field>, Rm",
10205 "{C|S}PSR_f, #expression". */
10206
10207static void
10208do_msr (void)
10209{
10210 if (do_vfp_nsyn_msr () == SUCCESS)
10211 return;
10212
10213 inst.instruction |= inst.operands[0].imm;
10214 if (inst.operands[1].isreg)
10215 inst.instruction |= inst.operands[1].reg;
10216 else
10217 {
10218 inst.instruction |= INST_IMMEDIATE;
10219 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
10220 inst.relocs[0].pc_rel = 0;
10221 }
10222}
10223
10224static void
10225do_mul (void)
10226{
10227 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
10228
10229 if (!inst.operands[2].present)
10230 inst.operands[2].reg = inst.operands[0].reg;
10231 inst.instruction |= inst.operands[0].reg << 16;
10232 inst.instruction |= inst.operands[1].reg;
10233 inst.instruction |= inst.operands[2].reg << 8;
10234
10235 if (inst.operands[0].reg == inst.operands[1].reg
10236 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
10237 as_tsktsk (_("Rd and Rm should be different in mul"));
10238}
10239
10240/* Long Multiply Parser
10241 UMULL RdLo, RdHi, Rm, Rs
10242 SMULL RdLo, RdHi, Rm, Rs
10243 UMLAL RdLo, RdHi, Rm, Rs
10244 SMLAL RdLo, RdHi, Rm, Rs. */
10245
10246static void
10247do_mull (void)
10248{
10249 inst.instruction |= inst.operands[0].reg << 12;
10250 inst.instruction |= inst.operands[1].reg << 16;
10251 inst.instruction |= inst.operands[2].reg;
10252 inst.instruction |= inst.operands[3].reg << 8;
10253
10254 /* rdhi and rdlo must be different. */
10255 if (inst.operands[0].reg == inst.operands[1].reg)
10256 as_tsktsk (_("rdhi and rdlo must be different"));
10257
10258 /* rdhi, rdlo and rm must all be different before armv6. */
10259 if ((inst.operands[0].reg == inst.operands[2].reg
10260 || inst.operands[1].reg == inst.operands[2].reg)
10261 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
10262 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10263}
10264
10265static void
10266do_nop (void)
10267{
10268 if (inst.operands[0].present
10269 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
10270 {
10271 /* Architectural NOP hints are CPSR sets with no bits selected. */
10272 inst.instruction &= 0xf0000000;
10273 inst.instruction |= 0x0320f000;
10274 if (inst.operands[0].present)
10275 inst.instruction |= inst.operands[0].imm;
10276 }
10277}
10278
10279/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10280 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10281 Condition defaults to COND_ALWAYS.
10282 Error if Rd, Rn or Rm are R15. */
10283
10284static void
10285do_pkhbt (void)
10286{
10287 inst.instruction |= inst.operands[0].reg << 12;
10288 inst.instruction |= inst.operands[1].reg << 16;
10289 inst.instruction |= inst.operands[2].reg;
10290 if (inst.operands[3].present)
10291 encode_arm_shift (3);
10292}
10293
10294/* ARM V6 PKHTB (Argument Parse). */
10295
10296static void
10297do_pkhtb (void)
10298{
10299 if (!inst.operands[3].present)
10300 {
10301 /* If the shift specifier is omitted, turn the instruction
10302 into pkhbt rd, rm, rn. */
10303 inst.instruction &= 0xfff00010;
10304 inst.instruction |= inst.operands[0].reg << 12;
10305 inst.instruction |= inst.operands[1].reg;
10306 inst.instruction |= inst.operands[2].reg << 16;
10307 }
10308 else
10309 {
10310 inst.instruction |= inst.operands[0].reg << 12;
10311 inst.instruction |= inst.operands[1].reg << 16;
10312 inst.instruction |= inst.operands[2].reg;
10313 encode_arm_shift (3);
10314 }
10315}
10316
10317/* ARMv5TE: Preload-Cache
10318 MP Extensions: Preload for write
10319
10320 PLD(W) <addr_mode>
10321
10322 Syntactically, like LDR with B=1, W=0, L=1. */
10323
10324static void
10325do_pld (void)
10326{
10327 constraint (!inst.operands[0].isreg,
10328 _("'[' expected after PLD mnemonic"));
10329 constraint (inst.operands[0].postind,
10330 _("post-indexed expression used in preload instruction"));
10331 constraint (inst.operands[0].writeback,
10332 _("writeback used in preload instruction"));
10333 constraint (!inst.operands[0].preind,
10334 _("unindexed addressing used in preload instruction"));
10335 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10336}
10337
10338/* ARMv7: PLI <addr_mode> */
10339static void
10340do_pli (void)
10341{
10342 constraint (!inst.operands[0].isreg,
10343 _("'[' expected after PLI mnemonic"));
10344 constraint (inst.operands[0].postind,
10345 _("post-indexed expression used in preload instruction"));
10346 constraint (inst.operands[0].writeback,
10347 _("writeback used in preload instruction"));
10348 constraint (!inst.operands[0].preind,
10349 _("unindexed addressing used in preload instruction"));
10350 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10351 inst.instruction &= ~PRE_INDEX;
10352}
10353
10354static void
10355do_push_pop (void)
10356{
10357 constraint (inst.operands[0].writeback,
10358 _("push/pop do not support {reglist}^"));
10359 inst.operands[1] = inst.operands[0];
10360 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10361 inst.operands[0].isreg = 1;
10362 inst.operands[0].writeback = 1;
10363 inst.operands[0].reg = REG_SP;
10364 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
10365}
10366
10367/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10368 word at the specified address and the following word
10369 respectively.
10370 Unconditionally executed.
10371 Error if Rn is R15. */
10372
10373static void
10374do_rfe (void)
10375{
10376 inst.instruction |= inst.operands[0].reg << 16;
10377 if (inst.operands[0].writeback)
10378 inst.instruction |= WRITE_BACK;
10379}
10380
10381/* ARM V6 ssat (argument parse). */
10382
10383static void
10384do_ssat (void)
10385{
10386 inst.instruction |= inst.operands[0].reg << 12;
10387 inst.instruction |= (inst.operands[1].imm - 1) << 16;
10388 inst.instruction |= inst.operands[2].reg;
10389
10390 if (inst.operands[3].present)
10391 encode_arm_shift (3);
10392}
10393
10394/* ARM V6 usat (argument parse). */
10395
10396static void
10397do_usat (void)
10398{
10399 inst.instruction |= inst.operands[0].reg << 12;
10400 inst.instruction |= inst.operands[1].imm << 16;
10401 inst.instruction |= inst.operands[2].reg;
10402
10403 if (inst.operands[3].present)
10404 encode_arm_shift (3);
10405}
10406
10407/* ARM V6 ssat16 (argument parse). */
10408
10409static void
10410do_ssat16 (void)
10411{
10412 inst.instruction |= inst.operands[0].reg << 12;
10413 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10414 inst.instruction |= inst.operands[2].reg;
10415}
10416
10417static void
10418do_usat16 (void)
10419{
10420 inst.instruction |= inst.operands[0].reg << 12;
10421 inst.instruction |= inst.operands[1].imm << 16;
10422 inst.instruction |= inst.operands[2].reg;
10423}
10424
10425/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10426 preserving the other bits.
10427
10428 setend <endian_specifier>, where <endian_specifier> is either
10429 BE or LE. */
10430
10431static void
10432do_setend (void)
10433{
10434 if (warn_on_deprecated
10435 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
10436 as_tsktsk (_("setend use is deprecated for ARMv8"));
10437
10438 if (inst.operands[0].imm)
10439 inst.instruction |= 0x200;
10440}
10441
10442static void
10443do_shift (void)
10444{
10445 unsigned int Rm = (inst.operands[1].present
10446 ? inst.operands[1].reg
10447 : inst.operands[0].reg);
10448
10449 inst.instruction |= inst.operands[0].reg << 12;
10450 inst.instruction |= Rm;
10451 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
10452 {
10453 inst.instruction |= inst.operands[2].reg << 8;
10454 inst.instruction |= SHIFT_BY_REG;
10455 /* PR 12854: Error on extraneous shifts. */
10456 constraint (inst.operands[2].shifted,
10457 _("extraneous shift as part of operand to shift insn"));
10458 }
10459 else
10460 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
10461}
10462
10463static void
10464do_smc (void)
10465{
10466 unsigned int value = inst.relocs[0].exp.X_add_number;
10467 constraint (value > 0xf, _("immediate too large (bigger than 0xF)"));
10468
10469 inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10470 inst.relocs[0].pc_rel = 0;
10471}
10472
10473static void
10474do_hvc (void)
10475{
10476 inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10477 inst.relocs[0].pc_rel = 0;
10478}
10479
10480static void
10481do_swi (void)
10482{
10483 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10484 inst.relocs[0].pc_rel = 0;
10485}
10486
10487static void
10488do_setpan (void)
10489{
10490 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10491 _("selected processor does not support SETPAN instruction"));
10492
10493 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10494}
10495
10496static void
10497do_t_setpan (void)
10498{
10499 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10500 _("selected processor does not support SETPAN instruction"));
10501
10502 inst.instruction |= (inst.operands[0].imm << 3);
10503}
10504
10505/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10506 SMLAxy{cond} Rd,Rm,Rs,Rn
10507 SMLAWy{cond} Rd,Rm,Rs,Rn
10508 Error if any register is R15. */
10509
10510static void
10511do_smla (void)
10512{
10513 inst.instruction |= inst.operands[0].reg << 16;
10514 inst.instruction |= inst.operands[1].reg;
10515 inst.instruction |= inst.operands[2].reg << 8;
10516 inst.instruction |= inst.operands[3].reg << 12;
10517}
10518
10519/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10520 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10521 Error if any register is R15.
10522 Warning if Rdlo == Rdhi. */
10523
10524static void
10525do_smlal (void)
10526{
10527 inst.instruction |= inst.operands[0].reg << 12;
10528 inst.instruction |= inst.operands[1].reg << 16;
10529 inst.instruction |= inst.operands[2].reg;
10530 inst.instruction |= inst.operands[3].reg << 8;
10531
10532 if (inst.operands[0].reg == inst.operands[1].reg)
10533 as_tsktsk (_("rdhi and rdlo must be different"));
10534}
10535
10536/* ARM V5E (El Segundo) signed-multiply (argument parse)
10537 SMULxy{cond} Rd,Rm,Rs
10538 Error if any register is R15. */
10539
10540static void
10541do_smul (void)
10542{
10543 inst.instruction |= inst.operands[0].reg << 16;
10544 inst.instruction |= inst.operands[1].reg;
10545 inst.instruction |= inst.operands[2].reg << 8;
10546}
10547
10548/* ARM V6 srs (argument parse). The variable fields in the encoding are
10549 the same for both ARM and Thumb-2. */
10550
10551static void
10552do_srs (void)
10553{
10554 int reg;
10555
10556 if (inst.operands[0].present)
10557 {
10558 reg = inst.operands[0].reg;
10559 constraint (reg != REG_SP, _("SRS base register must be r13"));
10560 }
10561 else
10562 reg = REG_SP;
10563
10564 inst.instruction |= reg << 16;
10565 inst.instruction |= inst.operands[1].imm;
10566 if (inst.operands[0].writeback || inst.operands[1].writeback)
10567 inst.instruction |= WRITE_BACK;
10568}
10569
10570/* ARM V6 strex (argument parse). */
10571
10572static void
10573do_strex (void)
10574{
10575 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10576 || inst.operands[2].postind || inst.operands[2].writeback
10577 || inst.operands[2].immisreg || inst.operands[2].shifted
10578 || inst.operands[2].negative
10579 /* See comment in do_ldrex(). */
10580 || (inst.operands[2].reg == REG_PC),
10581 BAD_ADDR_MODE);
10582
10583 constraint (inst.operands[0].reg == inst.operands[1].reg
10584 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10585
10586 constraint (inst.relocs[0].exp.X_op != O_constant
10587 || inst.relocs[0].exp.X_add_number != 0,
10588 _("offset must be zero in ARM encoding"));
10589
10590 inst.instruction |= inst.operands[0].reg << 12;
10591 inst.instruction |= inst.operands[1].reg;
10592 inst.instruction |= inst.operands[2].reg << 16;
10593 inst.relocs[0].type = BFD_RELOC_UNUSED;
10594}
10595
10596static void
10597do_t_strexbh (void)
10598{
10599 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10600 || inst.operands[2].postind || inst.operands[2].writeback
10601 || inst.operands[2].immisreg || inst.operands[2].shifted
10602 || inst.operands[2].negative,
10603 BAD_ADDR_MODE);
10604
10605 constraint (inst.operands[0].reg == inst.operands[1].reg
10606 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10607
10608 do_rm_rd_rn ();
10609}
10610
10611static void
10612do_strexd (void)
10613{
10614 constraint (inst.operands[1].reg % 2 != 0,
10615 _("even register required"));
10616 constraint (inst.operands[2].present
10617 && inst.operands[2].reg != inst.operands[1].reg + 1,
10618 _("can only store two consecutive registers"));
10619 /* If op 2 were present and equal to PC, this function wouldn't
10620 have been called in the first place. */
10621 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
10622
10623 constraint (inst.operands[0].reg == inst.operands[1].reg
10624 || inst.operands[0].reg == inst.operands[1].reg + 1
10625 || inst.operands[0].reg == inst.operands[3].reg,
10626 BAD_OVERLAP);
10627
10628 inst.instruction |= inst.operands[0].reg << 12;
10629 inst.instruction |= inst.operands[1].reg;
10630 inst.instruction |= inst.operands[3].reg << 16;
10631}
10632
10633/* ARM V8 STRL. */
10634static void
10635do_stlex (void)
10636{
10637 constraint (inst.operands[0].reg == inst.operands[1].reg
10638 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10639
10640 do_rd_rm_rn ();
10641}
10642
10643static void
10644do_t_stlex (void)
10645{
10646 constraint (inst.operands[0].reg == inst.operands[1].reg
10647 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10648
10649 do_rm_rd_rn ();
10650}
10651
10652/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10653 extends it to 32-bits, and adds the result to a value in another
10654 register. You can specify a rotation by 0, 8, 16, or 24 bits
10655 before extracting the 16-bit value.
10656 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10657 Condition defaults to COND_ALWAYS.
10658 Error if any register uses R15. */
10659
10660static void
10661do_sxtah (void)
10662{
10663 inst.instruction |= inst.operands[0].reg << 12;
10664 inst.instruction |= inst.operands[1].reg << 16;
10665 inst.instruction |= inst.operands[2].reg;
10666 inst.instruction |= inst.operands[3].imm << 10;
10667}
10668
10669/* ARM V6 SXTH.
10670
10671 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10672 Condition defaults to COND_ALWAYS.
10673 Error if any register uses R15. */
10674
10675static void
10676do_sxth (void)
10677{
10678 inst.instruction |= inst.operands[0].reg << 12;
10679 inst.instruction |= inst.operands[1].reg;
10680 inst.instruction |= inst.operands[2].imm << 10;
10681}
10682\f
10683/* VFP instructions. In a logical order: SP variant first, monad
10684 before dyad, arithmetic then move then load/store. */
10685
10686static void
10687do_vfp_sp_monadic (void)
10688{
10689 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10690 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10691 _(BAD_FPU));
10692
10693 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10694 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10695}
10696
10697static void
10698do_vfp_sp_dyadic (void)
10699{
10700 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10701 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10702 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10703}
10704
10705static void
10706do_vfp_sp_compare_z (void)
10707{
10708 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10709}
10710
10711static void
10712do_vfp_dp_sp_cvt (void)
10713{
10714 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10715 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10716}
10717
10718static void
10719do_vfp_sp_dp_cvt (void)
10720{
10721 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10722 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10723}
10724
10725static void
10726do_vfp_reg_from_sp (void)
10727{
10728 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10729 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10730 _(BAD_FPU));
10731
10732 inst.instruction |= inst.operands[0].reg << 12;
10733 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10734}
10735
10736static void
10737do_vfp_reg2_from_sp2 (void)
10738{
10739 constraint (inst.operands[2].imm != 2,
10740 _("only two consecutive VFP SP registers allowed here"));
10741 inst.instruction |= inst.operands[0].reg << 12;
10742 inst.instruction |= inst.operands[1].reg << 16;
10743 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10744}
10745
10746static void
10747do_vfp_sp_from_reg (void)
10748{
10749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10750 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10751 _(BAD_FPU));
10752
10753 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
10754 inst.instruction |= inst.operands[1].reg << 12;
10755}
10756
10757static void
10758do_vfp_sp2_from_reg2 (void)
10759{
10760 constraint (inst.operands[0].imm != 2,
10761 _("only two consecutive VFP SP registers allowed here"));
10762 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
10763 inst.instruction |= inst.operands[1].reg << 12;
10764 inst.instruction |= inst.operands[2].reg << 16;
10765}
10766
10767static void
10768do_vfp_sp_ldst (void)
10769{
10770 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10771 encode_arm_cp_address (1, FALSE, TRUE, 0);
10772}
10773
10774static void
10775do_vfp_dp_ldst (void)
10776{
10777 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10778 encode_arm_cp_address (1, FALSE, TRUE, 0);
10779}
10780
10781
10782static void
10783vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
10784{
10785 if (inst.operands[0].writeback)
10786 inst.instruction |= WRITE_BACK;
10787 else
10788 constraint (ldstm_type != VFP_LDSTMIA,
10789 _("this addressing mode requires base-register writeback"));
10790 inst.instruction |= inst.operands[0].reg << 16;
10791 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
10792 inst.instruction |= inst.operands[1].imm;
10793}
10794
10795static void
10796vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
10797{
10798 int count;
10799
10800 if (inst.operands[0].writeback)
10801 inst.instruction |= WRITE_BACK;
10802 else
10803 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
10804 _("this addressing mode requires base-register writeback"));
10805
10806 inst.instruction |= inst.operands[0].reg << 16;
10807 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10808
10809 count = inst.operands[1].imm << 1;
10810 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
10811 count += 1;
10812
10813 inst.instruction |= count;
10814}
10815
10816static void
10817do_vfp_sp_ldstmia (void)
10818{
10819 vfp_sp_ldstm (VFP_LDSTMIA);
10820}
10821
10822static void
10823do_vfp_sp_ldstmdb (void)
10824{
10825 vfp_sp_ldstm (VFP_LDSTMDB);
10826}
10827
10828static void
10829do_vfp_dp_ldstmia (void)
10830{
10831 vfp_dp_ldstm (VFP_LDSTMIA);
10832}
10833
10834static void
10835do_vfp_dp_ldstmdb (void)
10836{
10837 vfp_dp_ldstm (VFP_LDSTMDB);
10838}
10839
10840static void
10841do_vfp_xp_ldstmia (void)
10842{
10843 vfp_dp_ldstm (VFP_LDSTMIAX);
10844}
10845
10846static void
10847do_vfp_xp_ldstmdb (void)
10848{
10849 vfp_dp_ldstm (VFP_LDSTMDBX);
10850}
10851
10852static void
10853do_vfp_dp_rd_rm (void)
10854{
10855 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
10856 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10857 _(BAD_FPU));
10858
10859 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10860 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10861}
10862
10863static void
10864do_vfp_dp_rn_rd (void)
10865{
10866 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10867 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10868}
10869
10870static void
10871do_vfp_dp_rd_rn (void)
10872{
10873 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10874 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10875}
10876
10877static void
10878do_vfp_dp_rd_rn_rm (void)
10879{
10880 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10881 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10882 _(BAD_FPU));
10883
10884 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10885 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10886 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10887}
10888
10889static void
10890do_vfp_dp_rd (void)
10891{
10892 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10893}
10894
10895static void
10896do_vfp_dp_rm_rd_rn (void)
10897{
10898 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10899 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10900 _(BAD_FPU));
10901
10902 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10903 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10904 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10905}
10906
10907/* VFPv3 instructions. */
10908static void
10909do_vfp_sp_const (void)
10910{
10911 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10912 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10913 inst.instruction |= (inst.operands[1].imm & 0x0f);
10914}
10915
10916static void
10917do_vfp_dp_const (void)
10918{
10919 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10920 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10921 inst.instruction |= (inst.operands[1].imm & 0x0f);
10922}
10923
10924static void
10925vfp_conv (int srcsize)
10926{
10927 int immbits = srcsize - inst.operands[1].imm;
10928
10929 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
10930 {
10931 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10932 i.e. immbits must be in range 0 - 16. */
10933 inst.error = _("immediate value out of range, expected range [0, 16]");
10934 return;
10935 }
10936 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
10937 {
10938 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10939 i.e. immbits must be in range 0 - 31. */
10940 inst.error = _("immediate value out of range, expected range [1, 32]");
10941 return;
10942 }
10943
10944 inst.instruction |= (immbits & 1) << 5;
10945 inst.instruction |= (immbits >> 1);
10946}
10947
10948static void
10949do_vfp_sp_conv_16 (void)
10950{
10951 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10952 vfp_conv (16);
10953}
10954
10955static void
10956do_vfp_dp_conv_16 (void)
10957{
10958 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10959 vfp_conv (16);
10960}
10961
10962static void
10963do_vfp_sp_conv_32 (void)
10964{
10965 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10966 vfp_conv (32);
10967}
10968
10969static void
10970do_vfp_dp_conv_32 (void)
10971{
10972 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10973 vfp_conv (32);
10974}
10975\f
10976/* FPA instructions. Also in a logical order. */
10977
10978static void
10979do_fpa_cmp (void)
10980{
10981 inst.instruction |= inst.operands[0].reg << 16;
10982 inst.instruction |= inst.operands[1].reg;
10983}
10984
10985static void
10986do_fpa_ldmstm (void)
10987{
10988 inst.instruction |= inst.operands[0].reg << 12;
10989 switch (inst.operands[1].imm)
10990 {
10991 case 1: inst.instruction |= CP_T_X; break;
10992 case 2: inst.instruction |= CP_T_Y; break;
10993 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
10994 case 4: break;
10995 default: abort ();
10996 }
10997
10998 if (inst.instruction & (PRE_INDEX | INDEX_UP))
10999 {
11000 /* The instruction specified "ea" or "fd", so we can only accept
11001 [Rn]{!}. The instruction does not really support stacking or
11002 unstacking, so we have to emulate these by setting appropriate
11003 bits and offsets. */
11004 constraint (inst.relocs[0].exp.X_op != O_constant
11005 || inst.relocs[0].exp.X_add_number != 0,
11006 _("this instruction does not support indexing"));
11007
11008 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
11009 inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
11010
11011 if (!(inst.instruction & INDEX_UP))
11012 inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
11013
11014 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
11015 {
11016 inst.operands[2].preind = 0;
11017 inst.operands[2].postind = 1;
11018 }
11019 }
11020
11021 encode_arm_cp_address (2, TRUE, TRUE, 0);
11022}
11023\f
11024/* iWMMXt instructions: strictly in alphabetical order. */
11025
11026static void
11027do_iwmmxt_tandorc (void)
11028{
11029 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
11030}
11031
11032static void
11033do_iwmmxt_textrc (void)
11034{
11035 inst.instruction |= inst.operands[0].reg << 12;
11036 inst.instruction |= inst.operands[1].imm;
11037}
11038
11039static void
11040do_iwmmxt_textrm (void)
11041{
11042 inst.instruction |= inst.operands[0].reg << 12;
11043 inst.instruction |= inst.operands[1].reg << 16;
11044 inst.instruction |= inst.operands[2].imm;
11045}
11046
11047static void
11048do_iwmmxt_tinsr (void)
11049{
11050 inst.instruction |= inst.operands[0].reg << 16;
11051 inst.instruction |= inst.operands[1].reg << 12;
11052 inst.instruction |= inst.operands[2].imm;
11053}
11054
11055static void
11056do_iwmmxt_tmia (void)
11057{
11058 inst.instruction |= inst.operands[0].reg << 5;
11059 inst.instruction |= inst.operands[1].reg;
11060 inst.instruction |= inst.operands[2].reg << 12;
11061}
11062
11063static void
11064do_iwmmxt_waligni (void)
11065{
11066 inst.instruction |= inst.operands[0].reg << 12;
11067 inst.instruction |= inst.operands[1].reg << 16;
11068 inst.instruction |= inst.operands[2].reg;
11069 inst.instruction |= inst.operands[3].imm << 20;
11070}
11071
11072static void
11073do_iwmmxt_wmerge (void)
11074{
11075 inst.instruction |= inst.operands[0].reg << 12;
11076 inst.instruction |= inst.operands[1].reg << 16;
11077 inst.instruction |= inst.operands[2].reg;
11078 inst.instruction |= inst.operands[3].imm << 21;
11079}
11080
11081static void
11082do_iwmmxt_wmov (void)
11083{
11084 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11085 inst.instruction |= inst.operands[0].reg << 12;
11086 inst.instruction |= inst.operands[1].reg << 16;
11087 inst.instruction |= inst.operands[1].reg;
11088}
11089
11090static void
11091do_iwmmxt_wldstbh (void)
11092{
11093 int reloc;
11094 inst.instruction |= inst.operands[0].reg << 12;
11095 if (thumb_mode)
11096 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
11097 else
11098 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
11099 encode_arm_cp_address (1, TRUE, FALSE, reloc);
11100}
11101
11102static void
11103do_iwmmxt_wldstw (void)
11104{
11105 /* RIWR_RIWC clears .isreg for a control register. */
11106 if (!inst.operands[0].isreg)
11107 {
11108 constraint (inst.cond != COND_ALWAYS, BAD_COND);
11109 inst.instruction |= 0xf0000000;
11110 }
11111
11112 inst.instruction |= inst.operands[0].reg << 12;
11113 encode_arm_cp_address (1, TRUE, TRUE, 0);
11114}
11115
11116static void
11117do_iwmmxt_wldstd (void)
11118{
11119 inst.instruction |= inst.operands[0].reg << 12;
11120 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
11121 && inst.operands[1].immisreg)
11122 {
11123 inst.instruction &= ~0x1a000ff;
11124 inst.instruction |= (0xfU << 28);
11125 if (inst.operands[1].preind)
11126 inst.instruction |= PRE_INDEX;
11127 if (!inst.operands[1].negative)
11128 inst.instruction |= INDEX_UP;
11129 if (inst.operands[1].writeback)
11130 inst.instruction |= WRITE_BACK;
11131 inst.instruction |= inst.operands[1].reg << 16;
11132 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
11133 inst.instruction |= inst.operands[1].imm;
11134 }
11135 else
11136 encode_arm_cp_address (1, TRUE, FALSE, 0);
11137}
11138
11139static void
11140do_iwmmxt_wshufh (void)
11141{
11142 inst.instruction |= inst.operands[0].reg << 12;
11143 inst.instruction |= inst.operands[1].reg << 16;
11144 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
11145 inst.instruction |= (inst.operands[2].imm & 0x0f);
11146}
11147
11148static void
11149do_iwmmxt_wzero (void)
11150{
11151 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11152 inst.instruction |= inst.operands[0].reg;
11153 inst.instruction |= inst.operands[0].reg << 12;
11154 inst.instruction |= inst.operands[0].reg << 16;
11155}
11156
11157static void
11158do_iwmmxt_wrwrwr_or_imm5 (void)
11159{
11160 if (inst.operands[2].isreg)
11161 do_rd_rn_rm ();
11162 else {
11163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
11164 _("immediate operand requires iWMMXt2"));
11165 do_rd_rn ();
11166 if (inst.operands[2].imm == 0)
11167 {
11168 switch ((inst.instruction >> 20) & 0xf)
11169 {
11170 case 4:
11171 case 5:
11172 case 6:
11173 case 7:
11174 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11175 inst.operands[2].imm = 16;
11176 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
11177 break;
11178 case 8:
11179 case 9:
11180 case 10:
11181 case 11:
11182 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11183 inst.operands[2].imm = 32;
11184 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
11185 break;
11186 case 12:
11187 case 13:
11188 case 14:
11189 case 15:
11190 {
11191 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11192 unsigned long wrn;
11193 wrn = (inst.instruction >> 16) & 0xf;
11194 inst.instruction &= 0xff0fff0f;
11195 inst.instruction |= wrn;
11196 /* Bail out here; the instruction is now assembled. */
11197 return;
11198 }
11199 }
11200 }
11201 /* Map 32 -> 0, etc. */
11202 inst.operands[2].imm &= 0x1f;
11203 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
11204 }
11205}
11206\f
11207/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11208 operations first, then control, shift, and load/store. */
11209
11210/* Insns like "foo X,Y,Z". */
11211
11212static void
11213do_mav_triple (void)
11214{
11215 inst.instruction |= inst.operands[0].reg << 16;
11216 inst.instruction |= inst.operands[1].reg;
11217 inst.instruction |= inst.operands[2].reg << 12;
11218}
11219
11220/* Insns like "foo W,X,Y,Z".
11221 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11222
11223static void
11224do_mav_quad (void)
11225{
11226 inst.instruction |= inst.operands[0].reg << 5;
11227 inst.instruction |= inst.operands[1].reg << 12;
11228 inst.instruction |= inst.operands[2].reg << 16;
11229 inst.instruction |= inst.operands[3].reg;
11230}
11231
11232/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11233static void
11234do_mav_dspsc (void)
11235{
11236 inst.instruction |= inst.operands[1].reg << 12;
11237}
11238
11239/* Maverick shift immediate instructions.
11240 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11241 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11242
11243static void
11244do_mav_shift (void)
11245{
11246 int imm = inst.operands[2].imm;
11247
11248 inst.instruction |= inst.operands[0].reg << 12;
11249 inst.instruction |= inst.operands[1].reg << 16;
11250
11251 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11252 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11253 Bit 4 should be 0. */
11254 imm = (imm & 0xf) | ((imm & 0x70) << 1);
11255
11256 inst.instruction |= imm;
11257}
11258\f
11259/* XScale instructions. Also sorted arithmetic before move. */
11260
11261/* Xscale multiply-accumulate (argument parse)
11262 MIAcc acc0,Rm,Rs
11263 MIAPHcc acc0,Rm,Rs
11264 MIAxycc acc0,Rm,Rs. */
11265
11266static void
11267do_xsc_mia (void)
11268{
11269 inst.instruction |= inst.operands[1].reg;
11270 inst.instruction |= inst.operands[2].reg << 12;
11271}
11272
11273/* Xscale move-accumulator-register (argument parse)
11274
11275 MARcc acc0,RdLo,RdHi. */
11276
11277static void
11278do_xsc_mar (void)
11279{
11280 inst.instruction |= inst.operands[1].reg << 12;
11281 inst.instruction |= inst.operands[2].reg << 16;
11282}
11283
11284/* Xscale move-register-accumulator (argument parse)
11285
11286 MRAcc RdLo,RdHi,acc0. */
11287
11288static void
11289do_xsc_mra (void)
11290{
11291 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
11292 inst.instruction |= inst.operands[0].reg << 12;
11293 inst.instruction |= inst.operands[1].reg << 16;
11294}
11295\f
11296/* Encoding functions relevant only to Thumb. */
11297
11298/* inst.operands[i] is a shifted-register operand; encode
11299 it into inst.instruction in the format used by Thumb32. */
11300
11301static void
11302encode_thumb32_shifted_operand (int i)
11303{
11304 unsigned int value = inst.relocs[0].exp.X_add_number;
11305 unsigned int shift = inst.operands[i].shift_kind;
11306
11307 constraint (inst.operands[i].immisreg,
11308 _("shift by register not allowed in thumb mode"));
11309 inst.instruction |= inst.operands[i].reg;
11310 if (shift == SHIFT_RRX)
11311 inst.instruction |= SHIFT_ROR << 4;
11312 else
11313 {
11314 constraint (inst.relocs[0].exp.X_op != O_constant,
11315 _("expression too complex"));
11316
11317 constraint (value > 32
11318 || (value == 32 && (shift == SHIFT_LSL
11319 || shift == SHIFT_ROR)),
11320 _("shift expression is too large"));
11321
11322 if (value == 0)
11323 shift = SHIFT_LSL;
11324 else if (value == 32)
11325 value = 0;
11326
11327 inst.instruction |= shift << 4;
11328 inst.instruction |= (value & 0x1c) << 10;
11329 inst.instruction |= (value & 0x03) << 6;
11330 }
11331}
11332
11333
11334/* inst.operands[i] was set up by parse_address. Encode it into a
11335 Thumb32 format load or store instruction. Reject forms that cannot
11336 be used with such instructions. If is_t is true, reject forms that
11337 cannot be used with a T instruction; if is_d is true, reject forms
11338 that cannot be used with a D instruction. If it is a store insn,
11339 reject PC in Rn. */
11340
11341static void
11342encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
11343{
11344 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
11345
11346 constraint (!inst.operands[i].isreg,
11347 _("Instruction does not support =N addresses"));
11348
11349 inst.instruction |= inst.operands[i].reg << 16;
11350 if (inst.operands[i].immisreg)
11351 {
11352 constraint (is_pc, BAD_PC_ADDRESSING);
11353 constraint (is_t || is_d, _("cannot use register index with this instruction"));
11354 constraint (inst.operands[i].negative,
11355 _("Thumb does not support negative register indexing"));
11356 constraint (inst.operands[i].postind,
11357 _("Thumb does not support register post-indexing"));
11358 constraint (inst.operands[i].writeback,
11359 _("Thumb does not support register indexing with writeback"));
11360 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11361 _("Thumb supports only LSL in shifted register indexing"));
11362
11363 inst.instruction |= inst.operands[i].imm;
11364 if (inst.operands[i].shifted)
11365 {
11366 constraint (inst.relocs[0].exp.X_op != O_constant,
11367 _("expression too complex"));
11368 constraint (inst.relocs[0].exp.X_add_number < 0
11369 || inst.relocs[0].exp.X_add_number > 3,
11370 _("shift out of range"));
11371 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
11372 }
11373 inst.relocs[0].type = BFD_RELOC_UNUSED;
11374 }
11375 else if (inst.operands[i].preind)
11376 {
11377 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
11378 constraint (is_t && inst.operands[i].writeback,
11379 _("cannot use writeback with this instruction"));
11380 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11381 BAD_PC_ADDRESSING);
11382
11383 if (is_d)
11384 {
11385 inst.instruction |= 0x01000000;
11386 if (inst.operands[i].writeback)
11387 inst.instruction |= 0x00200000;
11388 }
11389 else
11390 {
11391 inst.instruction |= 0x00000c00;
11392 if (inst.operands[i].writeback)
11393 inst.instruction |= 0x00000100;
11394 }
11395 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11396 }
11397 else if (inst.operands[i].postind)
11398 {
11399 gas_assert (inst.operands[i].writeback);
11400 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
11401 constraint (is_t, _("cannot use post-indexing with this instruction"));
11402
11403 if (is_d)
11404 inst.instruction |= 0x00200000;
11405 else
11406 inst.instruction |= 0x00000900;
11407 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11408 }
11409 else /* unindexed - only for coprocessor */
11410 inst.error = _("instruction does not accept unindexed addressing");
11411}
11412
11413/* Table of Thumb instructions which exist in 16- and/or 32-bit
11414 encodings (the latter only in post-V6T2 cores). The index is the
11415 value used in the insns table below. When there is more than one
11416 possible 16-bit encoding for the instruction, this table always
11417 holds variant (1).
11418 Also contains several pseudo-instructions used during relaxation. */
11419#define T16_32_TAB \
11420 X(_adc, 4140, eb400000), \
11421 X(_adcs, 4140, eb500000), \
11422 X(_add, 1c00, eb000000), \
11423 X(_adds, 1c00, eb100000), \
11424 X(_addi, 0000, f1000000), \
11425 X(_addis, 0000, f1100000), \
11426 X(_add_pc,000f, f20f0000), \
11427 X(_add_sp,000d, f10d0000), \
11428 X(_adr, 000f, f20f0000), \
11429 X(_and, 4000, ea000000), \
11430 X(_ands, 4000, ea100000), \
11431 X(_asr, 1000, fa40f000), \
11432 X(_asrs, 1000, fa50f000), \
11433 X(_b, e000, f000b000), \
11434 X(_bcond, d000, f0008000), \
11435 X(_bf, 0000, f040e001), \
11436 X(_bfcsel,0000, f000e001), \
11437 X(_bfx, 0000, f060e001), \
11438 X(_bfl, 0000, f000c001), \
11439 X(_bflx, 0000, f070e001), \
11440 X(_bic, 4380, ea200000), \
11441 X(_bics, 4380, ea300000), \
11442 X(_cinc, 0000, ea509000), \
11443 X(_cinv, 0000, ea50a000), \
11444 X(_cmn, 42c0, eb100f00), \
11445 X(_cmp, 2800, ebb00f00), \
11446 X(_cneg, 0000, ea50b000), \
11447 X(_cpsie, b660, f3af8400), \
11448 X(_cpsid, b670, f3af8600), \
11449 X(_cpy, 4600, ea4f0000), \
11450 X(_csel, 0000, ea508000), \
11451 X(_cset, 0000, ea5f900f), \
11452 X(_csetm, 0000, ea5fa00f), \
11453 X(_csinc, 0000, ea509000), \
11454 X(_csinv, 0000, ea50a000), \
11455 X(_csneg, 0000, ea50b000), \
11456 X(_dec_sp,80dd, f1ad0d00), \
11457 X(_dls, 0000, f040e001), \
11458 X(_dlstp, 0000, f000e001), \
11459 X(_eor, 4040, ea800000), \
11460 X(_eors, 4040, ea900000), \
11461 X(_inc_sp,00dd, f10d0d00), \
11462 X(_lctp, 0000, f00fe001), \
11463 X(_ldmia, c800, e8900000), \
11464 X(_ldr, 6800, f8500000), \
11465 X(_ldrb, 7800, f8100000), \
11466 X(_ldrh, 8800, f8300000), \
11467 X(_ldrsb, 5600, f9100000), \
11468 X(_ldrsh, 5e00, f9300000), \
11469 X(_ldr_pc,4800, f85f0000), \
11470 X(_ldr_pc2,4800, f85f0000), \
11471 X(_ldr_sp,9800, f85d0000), \
11472 X(_le, 0000, f00fc001), \
11473 X(_letp, 0000, f01fc001), \
11474 X(_lsl, 0000, fa00f000), \
11475 X(_lsls, 0000, fa10f000), \
11476 X(_lsr, 0800, fa20f000), \
11477 X(_lsrs, 0800, fa30f000), \
11478 X(_mov, 2000, ea4f0000), \
11479 X(_movs, 2000, ea5f0000), \
11480 X(_mul, 4340, fb00f000), \
11481 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11482 X(_mvn, 43c0, ea6f0000), \
11483 X(_mvns, 43c0, ea7f0000), \
11484 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11485 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11486 X(_orr, 4300, ea400000), \
11487 X(_orrs, 4300, ea500000), \
11488 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11489 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11490 X(_rev, ba00, fa90f080), \
11491 X(_rev16, ba40, fa90f090), \
11492 X(_revsh, bac0, fa90f0b0), \
11493 X(_ror, 41c0, fa60f000), \
11494 X(_rors, 41c0, fa70f000), \
11495 X(_sbc, 4180, eb600000), \
11496 X(_sbcs, 4180, eb700000), \
11497 X(_stmia, c000, e8800000), \
11498 X(_str, 6000, f8400000), \
11499 X(_strb, 7000, f8000000), \
11500 X(_strh, 8000, f8200000), \
11501 X(_str_sp,9000, f84d0000), \
11502 X(_sub, 1e00, eba00000), \
11503 X(_subs, 1e00, ebb00000), \
11504 X(_subi, 8000, f1a00000), \
11505 X(_subis, 8000, f1b00000), \
11506 X(_sxtb, b240, fa4ff080), \
11507 X(_sxth, b200, fa0ff080), \
11508 X(_tst, 4200, ea100f00), \
11509 X(_uxtb, b2c0, fa5ff080), \
11510 X(_uxth, b280, fa1ff080), \
11511 X(_nop, bf00, f3af8000), \
11512 X(_yield, bf10, f3af8001), \
11513 X(_wfe, bf20, f3af8002), \
11514 X(_wfi, bf30, f3af8003), \
11515 X(_wls, 0000, f040c001), \
11516 X(_wlstp, 0000, f000c001), \
11517 X(_sev, bf40, f3af8004), \
11518 X(_sevl, bf50, f3af8005), \
11519 X(_udf, de00, f7f0a000)
11520
11521/* To catch errors in encoding functions, the codes are all offset by
11522 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11523 as 16-bit instructions. */
11524#define X(a,b,c) T_MNEM##a
11525enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
11526#undef X
11527
11528#define X(a,b,c) 0x##b
11529static const unsigned short thumb_op16[] = { T16_32_TAB };
11530#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11531#undef X
11532
11533#define X(a,b,c) 0x##c
11534static const unsigned int thumb_op32[] = { T16_32_TAB };
11535#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11536#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11537#undef X
11538#undef T16_32_TAB
11539
11540/* Thumb instruction encoders, in alphabetical order. */
11541
11542/* ADDW or SUBW. */
11543
11544static void
11545do_t_add_sub_w (void)
11546{
11547 int Rd, Rn;
11548
11549 Rd = inst.operands[0].reg;
11550 Rn = inst.operands[1].reg;
11551
11552 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11553 is the SP-{plus,minus}-immediate form of the instruction. */
11554 if (Rn == REG_SP)
11555 constraint (Rd == REG_PC, BAD_PC);
11556 else
11557 reject_bad_reg (Rd);
11558
11559 inst.instruction |= (Rn << 16) | (Rd << 8);
11560 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11561}
11562
11563/* Parse an add or subtract instruction. We get here with inst.instruction
11564 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11565
11566static void
11567do_t_add_sub (void)
11568{
11569 int Rd, Rs, Rn;
11570
11571 Rd = inst.operands[0].reg;
11572 Rs = (inst.operands[1].present
11573 ? inst.operands[1].reg /* Rd, Rs, foo */
11574 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11575
11576 if (Rd == REG_PC)
11577 set_pred_insn_type_last ();
11578
11579 if (unified_syntax)
11580 {
11581 bfd_boolean flags;
11582 bfd_boolean narrow;
11583 int opcode;
11584
11585 flags = (inst.instruction == T_MNEM_adds
11586 || inst.instruction == T_MNEM_subs);
11587 if (flags)
11588 narrow = !in_pred_block ();
11589 else
11590 narrow = in_pred_block ();
11591 if (!inst.operands[2].isreg)
11592 {
11593 int add;
11594
11595 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11596 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
11597
11598 add = (inst.instruction == T_MNEM_add
11599 || inst.instruction == T_MNEM_adds);
11600 opcode = 0;
11601 if (inst.size_req != 4)
11602 {
11603 /* Attempt to use a narrow opcode, with relaxation if
11604 appropriate. */
11605 if (Rd == REG_SP && Rs == REG_SP && !flags)
11606 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
11607 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
11608 opcode = T_MNEM_add_sp;
11609 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
11610 opcode = T_MNEM_add_pc;
11611 else if (Rd <= 7 && Rs <= 7 && narrow)
11612 {
11613 if (flags)
11614 opcode = add ? T_MNEM_addis : T_MNEM_subis;
11615 else
11616 opcode = add ? T_MNEM_addi : T_MNEM_subi;
11617 }
11618 if (opcode)
11619 {
11620 inst.instruction = THUMB_OP16(opcode);
11621 inst.instruction |= (Rd << 4) | Rs;
11622 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11623 || (inst.relocs[0].type
11624 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC))
11625 {
11626 if (inst.size_req == 2)
11627 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11628 else
11629 inst.relax = opcode;
11630 }
11631 }
11632 else
11633 constraint (inst.size_req == 2, BAD_HIREG);
11634 }
11635 if (inst.size_req == 4
11636 || (inst.size_req != 2 && !opcode))
11637 {
11638 constraint ((inst.relocs[0].type
11639 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
11640 && (inst.relocs[0].type
11641 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
11642 THUMB1_RELOC_ONLY);
11643 if (Rd == REG_PC)
11644 {
11645 constraint (add, BAD_PC);
11646 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11647 _("only SUBS PC, LR, #const allowed"));
11648 constraint (inst.relocs[0].exp.X_op != O_constant,
11649 _("expression too complex"));
11650 constraint (inst.relocs[0].exp.X_add_number < 0
11651 || inst.relocs[0].exp.X_add_number > 0xff,
11652 _("immediate value out of range"));
11653 inst.instruction = T2_SUBS_PC_LR
11654 | inst.relocs[0].exp.X_add_number;
11655 inst.relocs[0].type = BFD_RELOC_UNUSED;
11656 return;
11657 }
11658 else if (Rs == REG_PC)
11659 {
11660 /* Always use addw/subw. */
11661 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
11662 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11663 }
11664 else
11665 {
11666 inst.instruction = THUMB_OP32 (inst.instruction);
11667 inst.instruction = (inst.instruction & 0xe1ffffff)
11668 | 0x10000000;
11669 if (flags)
11670 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11671 else
11672 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
11673 }
11674 inst.instruction |= Rd << 8;
11675 inst.instruction |= Rs << 16;
11676 }
11677 }
11678 else
11679 {
11680 unsigned int value = inst.relocs[0].exp.X_add_number;
11681 unsigned int shift = inst.operands[2].shift_kind;
11682
11683 Rn = inst.operands[2].reg;
11684 /* See if we can do this with a 16-bit instruction. */
11685 if (!inst.operands[2].shifted && inst.size_req != 4)
11686 {
11687 if (Rd > 7 || Rs > 7 || Rn > 7)
11688 narrow = FALSE;
11689
11690 if (narrow)
11691 {
11692 inst.instruction = ((inst.instruction == T_MNEM_adds
11693 || inst.instruction == T_MNEM_add)
11694 ? T_OPCODE_ADD_R3
11695 : T_OPCODE_SUB_R3);
11696 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11697 return;
11698 }
11699
11700 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
11701 {
11702 /* Thumb-1 cores (except v6-M) require at least one high
11703 register in a narrow non flag setting add. */
11704 if (Rd > 7 || Rn > 7
11705 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
11706 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
11707 {
11708 if (Rd == Rn)
11709 {
11710 Rn = Rs;
11711 Rs = Rd;
11712 }
11713 inst.instruction = T_OPCODE_ADD_HI;
11714 inst.instruction |= (Rd & 8) << 4;
11715 inst.instruction |= (Rd & 7);
11716 inst.instruction |= Rn << 3;
11717 return;
11718 }
11719 }
11720 }
11721
11722 constraint (Rd == REG_PC, BAD_PC);
11723 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11724 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
11725 constraint (Rs == REG_PC, BAD_PC);
11726 reject_bad_reg (Rn);
11727
11728 /* If we get here, it can't be done in 16 bits. */
11729 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11730 _("shift must be constant"));
11731 inst.instruction = THUMB_OP32 (inst.instruction);
11732 inst.instruction |= Rd << 8;
11733 inst.instruction |= Rs << 16;
11734 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
11735 _("shift value over 3 not allowed in thumb mode"));
11736 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
11737 _("only LSL shift allowed in thumb mode"));
11738 encode_thumb32_shifted_operand (2);
11739 }
11740 }
11741 else
11742 {
11743 constraint (inst.instruction == T_MNEM_adds
11744 || inst.instruction == T_MNEM_subs,
11745 BAD_THUMB32);
11746
11747 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
11748 {
11749 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
11750 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
11751 BAD_HIREG);
11752
11753 inst.instruction = (inst.instruction == T_MNEM_add
11754 ? 0x0000 : 0x8000);
11755 inst.instruction |= (Rd << 4) | Rs;
11756 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11757 return;
11758 }
11759
11760 Rn = inst.operands[2].reg;
11761 constraint (inst.operands[2].shifted, _("unshifted register required"));
11762
11763 /* We now have Rd, Rs, and Rn set to registers. */
11764 if (Rd > 7 || Rs > 7 || Rn > 7)
11765 {
11766 /* Can't do this for SUB. */
11767 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11768 inst.instruction = T_OPCODE_ADD_HI;
11769 inst.instruction |= (Rd & 8) << 4;
11770 inst.instruction |= (Rd & 7);
11771 if (Rs == Rd)
11772 inst.instruction |= Rn << 3;
11773 else if (Rn == Rd)
11774 inst.instruction |= Rs << 3;
11775 else
11776 constraint (1, _("dest must overlap one source register"));
11777 }
11778 else
11779 {
11780 inst.instruction = (inst.instruction == T_MNEM_add
11781 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
11782 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11783 }
11784 }
11785}
11786
11787static void
11788do_t_adr (void)
11789{
11790 unsigned Rd;
11791
11792 Rd = inst.operands[0].reg;
11793 reject_bad_reg (Rd);
11794
11795 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
11796 {
11797 /* Defer to section relaxation. */
11798 inst.relax = inst.instruction;
11799 inst.instruction = THUMB_OP16 (inst.instruction);
11800 inst.instruction |= Rd << 4;
11801 }
11802 else if (unified_syntax && inst.size_req != 2)
11803 {
11804 /* Generate a 32-bit opcode. */
11805 inst.instruction = THUMB_OP32 (inst.instruction);
11806 inst.instruction |= Rd << 8;
11807 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11808 inst.relocs[0].pc_rel = 1;
11809 }
11810 else
11811 {
11812 /* Generate a 16-bit opcode. */
11813 inst.instruction = THUMB_OP16 (inst.instruction);
11814 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11815 inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
11816 inst.relocs[0].pc_rel = 1;
11817 inst.instruction |= Rd << 4;
11818 }
11819
11820 if (inst.relocs[0].exp.X_op == O_symbol
11821 && inst.relocs[0].exp.X_add_symbol != NULL
11822 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11823 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11824 inst.relocs[0].exp.X_add_number += 1;
11825}
11826
11827/* Arithmetic instructions for which there is just one 16-bit
11828 instruction encoding, and it allows only two low registers.
11829 For maximal compatibility with ARM syntax, we allow three register
11830 operands even when Thumb-32 instructions are not available, as long
11831 as the first two are identical. For instance, both "sbc r0,r1" and
11832 "sbc r0,r0,r1" are allowed. */
11833static void
11834do_t_arit3 (void)
11835{
11836 int Rd, Rs, Rn;
11837
11838 Rd = inst.operands[0].reg;
11839 Rs = (inst.operands[1].present
11840 ? inst.operands[1].reg /* Rd, Rs, foo */
11841 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11842 Rn = inst.operands[2].reg;
11843
11844 reject_bad_reg (Rd);
11845 reject_bad_reg (Rs);
11846 if (inst.operands[2].isreg)
11847 reject_bad_reg (Rn);
11848
11849 if (unified_syntax)
11850 {
11851 if (!inst.operands[2].isreg)
11852 {
11853 /* For an immediate, we always generate a 32-bit opcode;
11854 section relaxation will shrink it later if possible. */
11855 inst.instruction = THUMB_OP32 (inst.instruction);
11856 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11857 inst.instruction |= Rd << 8;
11858 inst.instruction |= Rs << 16;
11859 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11860 }
11861 else
11862 {
11863 bfd_boolean narrow;
11864
11865 /* See if we can do this with a 16-bit instruction. */
11866 if (THUMB_SETS_FLAGS (inst.instruction))
11867 narrow = !in_pred_block ();
11868 else
11869 narrow = in_pred_block ();
11870
11871 if (Rd > 7 || Rn > 7 || Rs > 7)
11872 narrow = FALSE;
11873 if (inst.operands[2].shifted)
11874 narrow = FALSE;
11875 if (inst.size_req == 4)
11876 narrow = FALSE;
11877
11878 if (narrow
11879 && Rd == Rs)
11880 {
11881 inst.instruction = THUMB_OP16 (inst.instruction);
11882 inst.instruction |= Rd;
11883 inst.instruction |= Rn << 3;
11884 return;
11885 }
11886
11887 /* If we get here, it can't be done in 16 bits. */
11888 constraint (inst.operands[2].shifted
11889 && inst.operands[2].immisreg,
11890 _("shift must be constant"));
11891 inst.instruction = THUMB_OP32 (inst.instruction);
11892 inst.instruction |= Rd << 8;
11893 inst.instruction |= Rs << 16;
11894 encode_thumb32_shifted_operand (2);
11895 }
11896 }
11897 else
11898 {
11899 /* On its face this is a lie - the instruction does set the
11900 flags. However, the only supported mnemonic in this mode
11901 says it doesn't. */
11902 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11903
11904 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11905 _("unshifted register required"));
11906 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11907 constraint (Rd != Rs,
11908 _("dest and source1 must be the same register"));
11909
11910 inst.instruction = THUMB_OP16 (inst.instruction);
11911 inst.instruction |= Rd;
11912 inst.instruction |= Rn << 3;
11913 }
11914}
11915
11916/* Similarly, but for instructions where the arithmetic operation is
11917 commutative, so we can allow either of them to be different from
11918 the destination operand in a 16-bit instruction. For instance, all
11919 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11920 accepted. */
11921static void
11922do_t_arit3c (void)
11923{
11924 int Rd, Rs, Rn;
11925
11926 Rd = inst.operands[0].reg;
11927 Rs = (inst.operands[1].present
11928 ? inst.operands[1].reg /* Rd, Rs, foo */
11929 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11930 Rn = inst.operands[2].reg;
11931
11932 reject_bad_reg (Rd);
11933 reject_bad_reg (Rs);
11934 if (inst.operands[2].isreg)
11935 reject_bad_reg (Rn);
11936
11937 if (unified_syntax)
11938 {
11939 if (!inst.operands[2].isreg)
11940 {
11941 /* For an immediate, we always generate a 32-bit opcode;
11942 section relaxation will shrink it later if possible. */
11943 inst.instruction = THUMB_OP32 (inst.instruction);
11944 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11945 inst.instruction |= Rd << 8;
11946 inst.instruction |= Rs << 16;
11947 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11948 }
11949 else
11950 {
11951 bfd_boolean narrow;
11952
11953 /* See if we can do this with a 16-bit instruction. */
11954 if (THUMB_SETS_FLAGS (inst.instruction))
11955 narrow = !in_pred_block ();
11956 else
11957 narrow = in_pred_block ();
11958
11959 if (Rd > 7 || Rn > 7 || Rs > 7)
11960 narrow = FALSE;
11961 if (inst.operands[2].shifted)
11962 narrow = FALSE;
11963 if (inst.size_req == 4)
11964 narrow = FALSE;
11965
11966 if (narrow)
11967 {
11968 if (Rd == Rs)
11969 {
11970 inst.instruction = THUMB_OP16 (inst.instruction);
11971 inst.instruction |= Rd;
11972 inst.instruction |= Rn << 3;
11973 return;
11974 }
11975 if (Rd == Rn)
11976 {
11977 inst.instruction = THUMB_OP16 (inst.instruction);
11978 inst.instruction |= Rd;
11979 inst.instruction |= Rs << 3;
11980 return;
11981 }
11982 }
11983
11984 /* If we get here, it can't be done in 16 bits. */
11985 constraint (inst.operands[2].shifted
11986 && inst.operands[2].immisreg,
11987 _("shift must be constant"));
11988 inst.instruction = THUMB_OP32 (inst.instruction);
11989 inst.instruction |= Rd << 8;
11990 inst.instruction |= Rs << 16;
11991 encode_thumb32_shifted_operand (2);
11992 }
11993 }
11994 else
11995 {
11996 /* On its face this is a lie - the instruction does set the
11997 flags. However, the only supported mnemonic in this mode
11998 says it doesn't. */
11999 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12000
12001 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
12002 _("unshifted register required"));
12003 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
12004
12005 inst.instruction = THUMB_OP16 (inst.instruction);
12006 inst.instruction |= Rd;
12007
12008 if (Rd == Rs)
12009 inst.instruction |= Rn << 3;
12010 else if (Rd == Rn)
12011 inst.instruction |= Rs << 3;
12012 else
12013 constraint (1, _("dest must overlap one source register"));
12014 }
12015}
12016
12017static void
12018do_t_bfc (void)
12019{
12020 unsigned Rd;
12021 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
12022 constraint (msb > 32, _("bit-field extends past end of register"));
12023 /* The instruction encoding stores the LSB and MSB,
12024 not the LSB and width. */
12025 Rd = inst.operands[0].reg;
12026 reject_bad_reg (Rd);
12027 inst.instruction |= Rd << 8;
12028 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
12029 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
12030 inst.instruction |= msb - 1;
12031}
12032
12033static void
12034do_t_bfi (void)
12035{
12036 int Rd, Rn;
12037 unsigned int msb;
12038
12039 Rd = inst.operands[0].reg;
12040 reject_bad_reg (Rd);
12041
12042 /* #0 in second position is alternative syntax for bfc, which is
12043 the same instruction but with REG_PC in the Rm field. */
12044 if (!inst.operands[1].isreg)
12045 Rn = REG_PC;
12046 else
12047 {
12048 Rn = inst.operands[1].reg;
12049 reject_bad_reg (Rn);
12050 }
12051
12052 msb = inst.operands[2].imm + inst.operands[3].imm;
12053 constraint (msb > 32, _("bit-field extends past end of register"));
12054 /* The instruction encoding stores the LSB and MSB,
12055 not the LSB and width. */
12056 inst.instruction |= Rd << 8;
12057 inst.instruction |= Rn << 16;
12058 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
12059 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
12060 inst.instruction |= msb - 1;
12061}
12062
12063static void
12064do_t_bfx (void)
12065{
12066 unsigned Rd, Rn;
12067
12068 Rd = inst.operands[0].reg;
12069 Rn = inst.operands[1].reg;
12070
12071 reject_bad_reg (Rd);
12072 reject_bad_reg (Rn);
12073
12074 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
12075 _("bit-field extends past end of register"));
12076 inst.instruction |= Rd << 8;
12077 inst.instruction |= Rn << 16;
12078 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
12079 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
12080 inst.instruction |= inst.operands[3].imm - 1;
12081}
12082
12083/* ARM V5 Thumb BLX (argument parse)
12084 BLX <target_addr> which is BLX(1)
12085 BLX <Rm> which is BLX(2)
12086 Unfortunately, there are two different opcodes for this mnemonic.
12087 So, the insns[].value is not used, and the code here zaps values
12088 into inst.instruction.
12089
12090 ??? How to take advantage of the additional two bits of displacement
12091 available in Thumb32 mode? Need new relocation? */
12092
12093static void
12094do_t_blx (void)
12095{
12096 set_pred_insn_type_last ();
12097
12098 if (inst.operands[0].isreg)
12099 {
12100 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
12101 /* We have a register, so this is BLX(2). */
12102 inst.instruction |= inst.operands[0].reg << 3;
12103 }
12104 else
12105 {
12106 /* No register. This must be BLX(1). */
12107 inst.instruction = 0xf000e800;
12108 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
12109 }
12110}
12111
12112static void
12113do_t_branch (void)
12114{
12115 int opcode;
12116 int cond;
12117 bfd_reloc_code_real_type reloc;
12118
12119 cond = inst.cond;
12120 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN);
12121
12122 if (in_pred_block ())
12123 {
12124 /* Conditional branches inside IT blocks are encoded as unconditional
12125 branches. */
12126 cond = COND_ALWAYS;
12127 }
12128 else
12129 cond = inst.cond;
12130
12131 if (cond != COND_ALWAYS)
12132 opcode = T_MNEM_bcond;
12133 else
12134 opcode = inst.instruction;
12135
12136 if (unified_syntax
12137 && (inst.size_req == 4
12138 || (inst.size_req != 2
12139 && (inst.operands[0].hasreloc
12140 || inst.relocs[0].exp.X_op == O_constant))))
12141 {
12142 inst.instruction = THUMB_OP32(opcode);
12143 if (cond == COND_ALWAYS)
12144 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
12145 else
12146 {
12147 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
12148 _("selected architecture does not support "
12149 "wide conditional branch instruction"));
12150
12151 gas_assert (cond != 0xF);
12152 inst.instruction |= cond << 22;
12153 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
12154 }
12155 }
12156 else
12157 {
12158 inst.instruction = THUMB_OP16(opcode);
12159 if (cond == COND_ALWAYS)
12160 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
12161 else
12162 {
12163 inst.instruction |= cond << 8;
12164 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
12165 }
12166 /* Allow section relaxation. */
12167 if (unified_syntax && inst.size_req != 2)
12168 inst.relax = opcode;
12169 }
12170 inst.relocs[0].type = reloc;
12171 inst.relocs[0].pc_rel = 1;
12172}
12173
12174/* Actually do the work for Thumb state bkpt and hlt. The only difference
12175 between the two is the maximum immediate allowed - which is passed in
12176 RANGE. */
12177static void
12178do_t_bkpt_hlt1 (int range)
12179{
12180 constraint (inst.cond != COND_ALWAYS,
12181 _("instruction is always unconditional"));
12182 if (inst.operands[0].present)
12183 {
12184 constraint (inst.operands[0].imm > range,
12185 _("immediate value out of range"));
12186 inst.instruction |= inst.operands[0].imm;
12187 }
12188
12189 set_pred_insn_type (NEUTRAL_IT_INSN);
12190}
12191
12192static void
12193do_t_hlt (void)
12194{
12195 do_t_bkpt_hlt1 (63);
12196}
12197
12198static void
12199do_t_bkpt (void)
12200{
12201 do_t_bkpt_hlt1 (255);
12202}
12203
12204static void
12205do_t_branch23 (void)
12206{
12207 set_pred_insn_type_last ();
12208 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
12209
12210 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12211 this file. We used to simply ignore the PLT reloc type here --
12212 the branch encoding is now needed to deal with TLSCALL relocs.
12213 So if we see a PLT reloc now, put it back to how it used to be to
12214 keep the preexisting behaviour. */
12215 if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
12216 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
12217
12218#if defined(OBJ_COFF)
12219 /* If the destination of the branch is a defined symbol which does not have
12220 the THUMB_FUNC attribute, then we must be calling a function which has
12221 the (interfacearm) attribute. We look for the Thumb entry point to that
12222 function and change the branch to refer to that function instead. */
12223 if ( inst.relocs[0].exp.X_op == O_symbol
12224 && inst.relocs[0].exp.X_add_symbol != NULL
12225 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
12226 && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
12227 inst.relocs[0].exp.X_add_symbol
12228 = find_real_start (inst.relocs[0].exp.X_add_symbol);
12229#endif
12230}
12231
12232static void
12233do_t_bx (void)
12234{
12235 set_pred_insn_type_last ();
12236 inst.instruction |= inst.operands[0].reg << 3;
12237 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12238 should cause the alignment to be checked once it is known. This is
12239 because BX PC only works if the instruction is word aligned. */
12240}
12241
12242static void
12243do_t_bxj (void)
12244{
12245 int Rm;
12246
12247 set_pred_insn_type_last ();
12248 Rm = inst.operands[0].reg;
12249 reject_bad_reg (Rm);
12250 inst.instruction |= Rm << 16;
12251}
12252
12253static void
12254do_t_clz (void)
12255{
12256 unsigned Rd;
12257 unsigned Rm;
12258
12259 Rd = inst.operands[0].reg;
12260 Rm = inst.operands[1].reg;
12261
12262 reject_bad_reg (Rd);
12263 reject_bad_reg (Rm);
12264
12265 inst.instruction |= Rd << 8;
12266 inst.instruction |= Rm << 16;
12267 inst.instruction |= Rm;
12268}
12269
12270/* For the Armv8.1-M conditional instructions. */
12271static void
12272do_t_cond (void)
12273{
12274 unsigned Rd, Rn, Rm;
12275 signed int cond;
12276
12277 constraint (inst.cond != COND_ALWAYS, BAD_COND);
12278
12279 Rd = inst.operands[0].reg;
12280 switch (inst.instruction)
12281 {
12282 case T_MNEM_csinc:
12283 case T_MNEM_csinv:
12284 case T_MNEM_csneg:
12285 case T_MNEM_csel:
12286 Rn = inst.operands[1].reg;
12287 Rm = inst.operands[2].reg;
12288 cond = inst.operands[3].imm;
12289 constraint (Rn == REG_SP, BAD_SP);
12290 constraint (Rm == REG_SP, BAD_SP);
12291 break;
12292
12293 case T_MNEM_cinc:
12294 case T_MNEM_cinv:
12295 case T_MNEM_cneg:
12296 Rn = inst.operands[1].reg;
12297 cond = inst.operands[2].imm;
12298 /* Invert the last bit to invert the cond. */
12299 cond = TOGGLE_BIT (cond, 0);
12300 constraint (Rn == REG_SP, BAD_SP);
12301 Rm = Rn;
12302 break;
12303
12304 case T_MNEM_csetm:
12305 case T_MNEM_cset:
12306 cond = inst.operands[1].imm;
12307 /* Invert the last bit to invert the cond. */
12308 cond = TOGGLE_BIT (cond, 0);
12309 Rn = REG_PC;
12310 Rm = REG_PC;
12311 break;
12312
12313 default: abort ();
12314 }
12315
12316 set_pred_insn_type (OUTSIDE_PRED_INSN);
12317 inst.instruction = THUMB_OP32 (inst.instruction);
12318 inst.instruction |= Rd << 8;
12319 inst.instruction |= Rn << 16;
12320 inst.instruction |= Rm;
12321 inst.instruction |= cond << 4;
12322}
12323
12324static void
12325do_t_csdb (void)
12326{
12327 set_pred_insn_type (OUTSIDE_PRED_INSN);
12328}
12329
12330static void
12331do_t_cps (void)
12332{
12333 set_pred_insn_type (OUTSIDE_PRED_INSN);
12334 inst.instruction |= inst.operands[0].imm;
12335}
12336
12337static void
12338do_t_cpsi (void)
12339{
12340 set_pred_insn_type (OUTSIDE_PRED_INSN);
12341 if (unified_syntax
12342 && (inst.operands[1].present || inst.size_req == 4)
12343 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
12344 {
12345 unsigned int imod = (inst.instruction & 0x0030) >> 4;
12346 inst.instruction = 0xf3af8000;
12347 inst.instruction |= imod << 9;
12348 inst.instruction |= inst.operands[0].imm << 5;
12349 if (inst.operands[1].present)
12350 inst.instruction |= 0x100 | inst.operands[1].imm;
12351 }
12352 else
12353 {
12354 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
12355 && (inst.operands[0].imm & 4),
12356 _("selected processor does not support 'A' form "
12357 "of this instruction"));
12358 constraint (inst.operands[1].present || inst.size_req == 4,
12359 _("Thumb does not support the 2-argument "
12360 "form of this instruction"));
12361 inst.instruction |= inst.operands[0].imm;
12362 }
12363}
12364
12365/* THUMB CPY instruction (argument parse). */
12366
12367static void
12368do_t_cpy (void)
12369{
12370 if (inst.size_req == 4)
12371 {
12372 inst.instruction = THUMB_OP32 (T_MNEM_mov);
12373 inst.instruction |= inst.operands[0].reg << 8;
12374 inst.instruction |= inst.operands[1].reg;
12375 }
12376 else
12377 {
12378 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
12379 inst.instruction |= (inst.operands[0].reg & 0x7);
12380 inst.instruction |= inst.operands[1].reg << 3;
12381 }
12382}
12383
12384static void
12385do_t_cbz (void)
12386{
12387 set_pred_insn_type (OUTSIDE_PRED_INSN);
12388 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12389 inst.instruction |= inst.operands[0].reg;
12390 inst.relocs[0].pc_rel = 1;
12391 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
12392}
12393
12394static void
12395do_t_dbg (void)
12396{
12397 inst.instruction |= inst.operands[0].imm;
12398}
12399
12400static void
12401do_t_div (void)
12402{
12403 unsigned Rd, Rn, Rm;
12404
12405 Rd = inst.operands[0].reg;
12406 Rn = (inst.operands[1].present
12407 ? inst.operands[1].reg : Rd);
12408 Rm = inst.operands[2].reg;
12409
12410 reject_bad_reg (Rd);
12411 reject_bad_reg (Rn);
12412 reject_bad_reg (Rm);
12413
12414 inst.instruction |= Rd << 8;
12415 inst.instruction |= Rn << 16;
12416 inst.instruction |= Rm;
12417}
12418
12419static void
12420do_t_hint (void)
12421{
12422 if (unified_syntax && inst.size_req == 4)
12423 inst.instruction = THUMB_OP32 (inst.instruction);
12424 else
12425 inst.instruction = THUMB_OP16 (inst.instruction);
12426}
12427
12428static void
12429do_t_it (void)
12430{
12431 unsigned int cond = inst.operands[0].imm;
12432
12433 set_pred_insn_type (IT_INSN);
12434 now_pred.mask = (inst.instruction & 0xf) | 0x10;
12435 now_pred.cc = cond;
12436 now_pred.warn_deprecated = FALSE;
12437 now_pred.type = SCALAR_PRED;
12438
12439 /* If the condition is a negative condition, invert the mask. */
12440 if ((cond & 0x1) == 0x0)
12441 {
12442 unsigned int mask = inst.instruction & 0x000f;
12443
12444 if ((mask & 0x7) == 0)
12445 {
12446 /* No conversion needed. */
12447 now_pred.block_length = 1;
12448 }
12449 else if ((mask & 0x3) == 0)
12450 {
12451 mask ^= 0x8;
12452 now_pred.block_length = 2;
12453 }
12454 else if ((mask & 0x1) == 0)
12455 {
12456 mask ^= 0xC;
12457 now_pred.block_length = 3;
12458 }
12459 else
12460 {
12461 mask ^= 0xE;
12462 now_pred.block_length = 4;
12463 }
12464
12465 inst.instruction &= 0xfff0;
12466 inst.instruction |= mask;
12467 }
12468
12469 inst.instruction |= cond << 4;
12470}
12471
12472/* Helper function used for both push/pop and ldm/stm. */
12473static void
12474encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
12475 bfd_boolean writeback)
12476{
12477 bfd_boolean load, store;
12478
12479 gas_assert (base != -1 || !do_io);
12480 load = do_io && ((inst.instruction & (1 << 20)) != 0);
12481 store = do_io && !load;
12482
12483 if (mask & (1 << 13))
12484 inst.error = _("SP not allowed in register list");
12485
12486 if (do_io && (mask & (1 << base)) != 0
12487 && writeback)
12488 inst.error = _("having the base register in the register list when "
12489 "using write back is UNPREDICTABLE");
12490
12491 if (load)
12492 {
12493 if (mask & (1 << 15))
12494 {
12495 if (mask & (1 << 14))
12496 inst.error = _("LR and PC should not both be in register list");
12497 else
12498 set_pred_insn_type_last ();
12499 }
12500 }
12501 else if (store)
12502 {
12503 if (mask & (1 << 15))
12504 inst.error = _("PC not allowed in register list");
12505 }
12506
12507 if (do_io && ((mask & (mask - 1)) == 0))
12508 {
12509 /* Single register transfers implemented as str/ldr. */
12510 if (writeback)
12511 {
12512 if (inst.instruction & (1 << 23))
12513 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12514 else
12515 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12516 }
12517 else
12518 {
12519 if (inst.instruction & (1 << 23))
12520 inst.instruction = 0x00800000; /* ia -> [base] */
12521 else
12522 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12523 }
12524
12525 inst.instruction |= 0xf8400000;
12526 if (load)
12527 inst.instruction |= 0x00100000;
12528
12529 mask = ffs (mask) - 1;
12530 mask <<= 12;
12531 }
12532 else if (writeback)
12533 inst.instruction |= WRITE_BACK;
12534
12535 inst.instruction |= mask;
12536 if (do_io)
12537 inst.instruction |= base << 16;
12538}
12539
12540static void
12541do_t_ldmstm (void)
12542{
12543 /* This really doesn't seem worth it. */
12544 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
12545 _("expression too complex"));
12546 constraint (inst.operands[1].writeback,
12547 _("Thumb load/store multiple does not support {reglist}^"));
12548
12549 if (unified_syntax)
12550 {
12551 bfd_boolean narrow;
12552 unsigned mask;
12553
12554 narrow = FALSE;
12555 /* See if we can use a 16-bit instruction. */
12556 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
12557 && inst.size_req != 4
12558 && !(inst.operands[1].imm & ~0xff))
12559 {
12560 mask = 1 << inst.operands[0].reg;
12561
12562 if (inst.operands[0].reg <= 7)
12563 {
12564 if (inst.instruction == T_MNEM_stmia
12565 ? inst.operands[0].writeback
12566 : (inst.operands[0].writeback
12567 == !(inst.operands[1].imm & mask)))
12568 {
12569 if (inst.instruction == T_MNEM_stmia
12570 && (inst.operands[1].imm & mask)
12571 && (inst.operands[1].imm & (mask - 1)))
12572 as_warn (_("value stored for r%d is UNKNOWN"),
12573 inst.operands[0].reg);
12574
12575 inst.instruction = THUMB_OP16 (inst.instruction);
12576 inst.instruction |= inst.operands[0].reg << 8;
12577 inst.instruction |= inst.operands[1].imm;
12578 narrow = TRUE;
12579 }
12580 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12581 {
12582 /* This means 1 register in reg list one of 3 situations:
12583 1. Instruction is stmia, but without writeback.
12584 2. lmdia without writeback, but with Rn not in
12585 reglist.
12586 3. ldmia with writeback, but with Rn in reglist.
12587 Case 3 is UNPREDICTABLE behaviour, so we handle
12588 case 1 and 2 which can be converted into a 16-bit
12589 str or ldr. The SP cases are handled below. */
12590 unsigned long opcode;
12591 /* First, record an error for Case 3. */
12592 if (inst.operands[1].imm & mask
12593 && inst.operands[0].writeback)
12594 inst.error =
12595 _("having the base register in the register list when "
12596 "using write back is UNPREDICTABLE");
12597
12598 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
12599 : T_MNEM_ldr);
12600 inst.instruction = THUMB_OP16 (opcode);
12601 inst.instruction |= inst.operands[0].reg << 3;
12602 inst.instruction |= (ffs (inst.operands[1].imm)-1);
12603 narrow = TRUE;
12604 }
12605 }
12606 else if (inst.operands[0] .reg == REG_SP)
12607 {
12608 if (inst.operands[0].writeback)
12609 {
12610 inst.instruction =
12611 THUMB_OP16 (inst.instruction == T_MNEM_stmia
12612 ? T_MNEM_push : T_MNEM_pop);
12613 inst.instruction |= inst.operands[1].imm;
12614 narrow = TRUE;
12615 }
12616 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12617 {
12618 inst.instruction =
12619 THUMB_OP16 (inst.instruction == T_MNEM_stmia
12620 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
12621 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
12622 narrow = TRUE;
12623 }
12624 }
12625 }
12626
12627 if (!narrow)
12628 {
12629 if (inst.instruction < 0xffff)
12630 inst.instruction = THUMB_OP32 (inst.instruction);
12631
12632 encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
12633 inst.operands[1].imm,
12634 inst.operands[0].writeback);
12635 }
12636 }
12637 else
12638 {
12639 constraint (inst.operands[0].reg > 7
12640 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
12641 constraint (inst.instruction != T_MNEM_ldmia
12642 && inst.instruction != T_MNEM_stmia,
12643 _("Thumb-2 instruction only valid in unified syntax"));
12644 if (inst.instruction == T_MNEM_stmia)
12645 {
12646 if (!inst.operands[0].writeback)
12647 as_warn (_("this instruction will write back the base register"));
12648 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12649 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
12650 as_warn (_("value stored for r%d is UNKNOWN"),
12651 inst.operands[0].reg);
12652 }
12653 else
12654 {
12655 if (!inst.operands[0].writeback
12656 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12657 as_warn (_("this instruction will write back the base register"));
12658 else if (inst.operands[0].writeback
12659 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12660 as_warn (_("this instruction will not write back the base register"));
12661 }
12662
12663 inst.instruction = THUMB_OP16 (inst.instruction);
12664 inst.instruction |= inst.operands[0].reg << 8;
12665 inst.instruction |= inst.operands[1].imm;
12666 }
12667}
12668
12669static void
12670do_t_ldrex (void)
12671{
12672 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12673 || inst.operands[1].postind || inst.operands[1].writeback
12674 || inst.operands[1].immisreg || inst.operands[1].shifted
12675 || inst.operands[1].negative,
12676 BAD_ADDR_MODE);
12677
12678 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12679
12680 inst.instruction |= inst.operands[0].reg << 12;
12681 inst.instruction |= inst.operands[1].reg << 16;
12682 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
12683}
12684
12685static void
12686do_t_ldrexd (void)
12687{
12688 if (!inst.operands[1].present)
12689 {
12690 constraint (inst.operands[0].reg == REG_LR,
12691 _("r14 not allowed as first register "
12692 "when second register is omitted"));
12693 inst.operands[1].reg = inst.operands[0].reg + 1;
12694 }
12695 constraint (inst.operands[0].reg == inst.operands[1].reg,
12696 BAD_OVERLAP);
12697
12698 inst.instruction |= inst.operands[0].reg << 12;
12699 inst.instruction |= inst.operands[1].reg << 8;
12700 inst.instruction |= inst.operands[2].reg << 16;
12701}
12702
12703static void
12704do_t_ldst (void)
12705{
12706 unsigned long opcode;
12707 int Rn;
12708
12709 if (inst.operands[0].isreg
12710 && !inst.operands[0].preind
12711 && inst.operands[0].reg == REG_PC)
12712 set_pred_insn_type_last ();
12713
12714 opcode = inst.instruction;
12715 if (unified_syntax)
12716 {
12717 if (!inst.operands[1].isreg)
12718 {
12719 if (opcode <= 0xffff)
12720 inst.instruction = THUMB_OP32 (opcode);
12721 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
12722 return;
12723 }
12724 if (inst.operands[1].isreg
12725 && !inst.operands[1].writeback
12726 && !inst.operands[1].shifted && !inst.operands[1].postind
12727 && !inst.operands[1].negative && inst.operands[0].reg <= 7
12728 && opcode <= 0xffff
12729 && inst.size_req != 4)
12730 {
12731 /* Insn may have a 16-bit form. */
12732 Rn = inst.operands[1].reg;
12733 if (inst.operands[1].immisreg)
12734 {
12735 inst.instruction = THUMB_OP16 (opcode);
12736 /* [Rn, Rik] */
12737 if (Rn <= 7 && inst.operands[1].imm <= 7)
12738 goto op16;
12739 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
12740 reject_bad_reg (inst.operands[1].imm);
12741 }
12742 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
12743 && opcode != T_MNEM_ldrsb)
12744 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
12745 || (Rn == REG_SP && opcode == T_MNEM_str))
12746 {
12747 /* [Rn, #const] */
12748 if (Rn > 7)
12749 {
12750 if (Rn == REG_PC)
12751 {
12752 if (inst.relocs[0].pc_rel)
12753 opcode = T_MNEM_ldr_pc2;
12754 else
12755 opcode = T_MNEM_ldr_pc;
12756 }
12757 else
12758 {
12759 if (opcode == T_MNEM_ldr)
12760 opcode = T_MNEM_ldr_sp;
12761 else
12762 opcode = T_MNEM_str_sp;
12763 }
12764 inst.instruction = inst.operands[0].reg << 8;
12765 }
12766 else
12767 {
12768 inst.instruction = inst.operands[0].reg;
12769 inst.instruction |= inst.operands[1].reg << 3;
12770 }
12771 inst.instruction |= THUMB_OP16 (opcode);
12772 if (inst.size_req == 2)
12773 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12774 else
12775 inst.relax = opcode;
12776 return;
12777 }
12778 }
12779 /* Definitely a 32-bit variant. */
12780
12781 /* Warning for Erratum 752419. */
12782 if (opcode == T_MNEM_ldr
12783 && inst.operands[0].reg == REG_SP
12784 && inst.operands[1].writeback == 1
12785 && !inst.operands[1].immisreg)
12786 {
12787 if (no_cpu_selected ()
12788 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
12789 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
12790 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
12791 as_warn (_("This instruction may be unpredictable "
12792 "if executed on M-profile cores "
12793 "with interrupts enabled."));
12794 }
12795
12796 /* Do some validations regarding addressing modes. */
12797 if (inst.operands[1].immisreg)
12798 reject_bad_reg (inst.operands[1].imm);
12799
12800 constraint (inst.operands[1].writeback == 1
12801 && inst.operands[0].reg == inst.operands[1].reg,
12802 BAD_OVERLAP);
12803
12804 inst.instruction = THUMB_OP32 (opcode);
12805 inst.instruction |= inst.operands[0].reg << 12;
12806 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
12807 check_ldr_r15_aligned ();
12808 return;
12809 }
12810
12811 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12812
12813 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
12814 {
12815 /* Only [Rn,Rm] is acceptable. */
12816 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12817 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12818 || inst.operands[1].postind || inst.operands[1].shifted
12819 || inst.operands[1].negative,
12820 _("Thumb does not support this addressing mode"));
12821 inst.instruction = THUMB_OP16 (inst.instruction);
12822 goto op16;
12823 }
12824
12825 inst.instruction = THUMB_OP16 (inst.instruction);
12826 if (!inst.operands[1].isreg)
12827 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
12828 return;
12829
12830 constraint (!inst.operands[1].preind
12831 || inst.operands[1].shifted
12832 || inst.operands[1].writeback,
12833 _("Thumb does not support this addressing mode"));
12834 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
12835 {
12836 constraint (inst.instruction & 0x0600,
12837 _("byte or halfword not valid for base register"));
12838 constraint (inst.operands[1].reg == REG_PC
12839 && !(inst.instruction & THUMB_LOAD_BIT),
12840 _("r15 based store not allowed"));
12841 constraint (inst.operands[1].immisreg,
12842 _("invalid base register for register offset"));
12843
12844 if (inst.operands[1].reg == REG_PC)
12845 inst.instruction = T_OPCODE_LDR_PC;
12846 else if (inst.instruction & THUMB_LOAD_BIT)
12847 inst.instruction = T_OPCODE_LDR_SP;
12848 else
12849 inst.instruction = T_OPCODE_STR_SP;
12850
12851 inst.instruction |= inst.operands[0].reg << 8;
12852 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12853 return;
12854 }
12855
12856 constraint (inst.operands[1].reg > 7, BAD_HIREG);
12857 if (!inst.operands[1].immisreg)
12858 {
12859 /* Immediate offset. */
12860 inst.instruction |= inst.operands[0].reg;
12861 inst.instruction |= inst.operands[1].reg << 3;
12862 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12863 return;
12864 }
12865
12866 /* Register offset. */
12867 constraint (inst.operands[1].imm > 7, BAD_HIREG);
12868 constraint (inst.operands[1].negative,
12869 _("Thumb does not support this addressing mode"));
12870
12871 op16:
12872 switch (inst.instruction)
12873 {
12874 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12875 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12876 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12877 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12878 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12879 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12880 case 0x5600 /* ldrsb */:
12881 case 0x5e00 /* ldrsh */: break;
12882 default: abort ();
12883 }
12884
12885 inst.instruction |= inst.operands[0].reg;
12886 inst.instruction |= inst.operands[1].reg << 3;
12887 inst.instruction |= inst.operands[1].imm << 6;
12888}
12889
12890static void
12891do_t_ldstd (void)
12892{
12893 if (!inst.operands[1].present)
12894 {
12895 inst.operands[1].reg = inst.operands[0].reg + 1;
12896 constraint (inst.operands[0].reg == REG_LR,
12897 _("r14 not allowed here"));
12898 constraint (inst.operands[0].reg == REG_R12,
12899 _("r12 not allowed here"));
12900 }
12901
12902 if (inst.operands[2].writeback
12903 && (inst.operands[0].reg == inst.operands[2].reg
12904 || inst.operands[1].reg == inst.operands[2].reg))
12905 as_warn (_("base register written back, and overlaps "
12906 "one of transfer registers"));
12907
12908 inst.instruction |= inst.operands[0].reg << 12;
12909 inst.instruction |= inst.operands[1].reg << 8;
12910 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
12911}
12912
12913static void
12914do_t_ldstt (void)
12915{
12916 inst.instruction |= inst.operands[0].reg << 12;
12917 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
12918}
12919
12920static void
12921do_t_mla (void)
12922{
12923 unsigned Rd, Rn, Rm, Ra;
12924
12925 Rd = inst.operands[0].reg;
12926 Rn = inst.operands[1].reg;
12927 Rm = inst.operands[2].reg;
12928 Ra = inst.operands[3].reg;
12929
12930 reject_bad_reg (Rd);
12931 reject_bad_reg (Rn);
12932 reject_bad_reg (Rm);
12933 reject_bad_reg (Ra);
12934
12935 inst.instruction |= Rd << 8;
12936 inst.instruction |= Rn << 16;
12937 inst.instruction |= Rm;
12938 inst.instruction |= Ra << 12;
12939}
12940
12941static void
12942do_t_mlal (void)
12943{
12944 unsigned RdLo, RdHi, Rn, Rm;
12945
12946 RdLo = inst.operands[0].reg;
12947 RdHi = inst.operands[1].reg;
12948 Rn = inst.operands[2].reg;
12949 Rm = inst.operands[3].reg;
12950
12951 reject_bad_reg (RdLo);
12952 reject_bad_reg (RdHi);
12953 reject_bad_reg (Rn);
12954 reject_bad_reg (Rm);
12955
12956 inst.instruction |= RdLo << 12;
12957 inst.instruction |= RdHi << 8;
12958 inst.instruction |= Rn << 16;
12959 inst.instruction |= Rm;
12960}
12961
12962static void
12963do_t_mov_cmp (void)
12964{
12965 unsigned Rn, Rm;
12966
12967 Rn = inst.operands[0].reg;
12968 Rm = inst.operands[1].reg;
12969
12970 if (Rn == REG_PC)
12971 set_pred_insn_type_last ();
12972
12973 if (unified_syntax)
12974 {
12975 int r0off = (inst.instruction == T_MNEM_mov
12976 || inst.instruction == T_MNEM_movs) ? 8 : 16;
12977 unsigned long opcode;
12978 bfd_boolean narrow;
12979 bfd_boolean low_regs;
12980
12981 low_regs = (Rn <= 7 && Rm <= 7);
12982 opcode = inst.instruction;
12983 if (in_pred_block ())
12984 narrow = opcode != T_MNEM_movs;
12985 else
12986 narrow = opcode != T_MNEM_movs || low_regs;
12987 if (inst.size_req == 4
12988 || inst.operands[1].shifted)
12989 narrow = FALSE;
12990
12991 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12992 if (opcode == T_MNEM_movs && inst.operands[1].isreg
12993 && !inst.operands[1].shifted
12994 && Rn == REG_PC
12995 && Rm == REG_LR)
12996 {
12997 inst.instruction = T2_SUBS_PC_LR;
12998 return;
12999 }
13000
13001 if (opcode == T_MNEM_cmp)
13002 {
13003 constraint (Rn == REG_PC, BAD_PC);
13004 if (narrow)
13005 {
13006 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
13007 but valid. */
13008 warn_deprecated_sp (Rm);
13009 /* R15 was documented as a valid choice for Rm in ARMv6,
13010 but as UNPREDICTABLE in ARMv7. ARM's proprietary
13011 tools reject R15, so we do too. */
13012 constraint (Rm == REG_PC, BAD_PC);
13013 }
13014 else
13015 reject_bad_reg (Rm);
13016 }
13017 else if (opcode == T_MNEM_mov
13018 || opcode == T_MNEM_movs)
13019 {
13020 if (inst.operands[1].isreg)
13021 {
13022 if (opcode == T_MNEM_movs)
13023 {
13024 reject_bad_reg (Rn);
13025 reject_bad_reg (Rm);
13026 }
13027 else if (narrow)
13028 {
13029 /* This is mov.n. */
13030 if ((Rn == REG_SP || Rn == REG_PC)
13031 && (Rm == REG_SP || Rm == REG_PC))
13032 {
13033 as_tsktsk (_("Use of r%u as a source register is "
13034 "deprecated when r%u is the destination "
13035 "register."), Rm, Rn);
13036 }
13037 }
13038 else
13039 {
13040 /* This is mov.w. */
13041 constraint (Rn == REG_PC, BAD_PC);
13042 constraint (Rm == REG_PC, BAD_PC);
13043 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13044 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
13045 }
13046 }
13047 else
13048 reject_bad_reg (Rn);
13049 }
13050
13051 if (!inst.operands[1].isreg)
13052 {
13053 /* Immediate operand. */
13054 if (!in_pred_block () && opcode == T_MNEM_mov)
13055 narrow = 0;
13056 if (low_regs && narrow)
13057 {
13058 inst.instruction = THUMB_OP16 (opcode);
13059 inst.instruction |= Rn << 8;
13060 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13061 || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
13062 {
13063 if (inst.size_req == 2)
13064 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
13065 else
13066 inst.relax = opcode;
13067 }
13068 }
13069 else
13070 {
13071 constraint ((inst.relocs[0].type
13072 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
13073 && (inst.relocs[0].type
13074 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
13075 THUMB1_RELOC_ONLY);
13076
13077 inst.instruction = THUMB_OP32 (inst.instruction);
13078 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13079 inst.instruction |= Rn << r0off;
13080 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13081 }
13082 }
13083 else if (inst.operands[1].shifted && inst.operands[1].immisreg
13084 && (inst.instruction == T_MNEM_mov
13085 || inst.instruction == T_MNEM_movs))
13086 {
13087 /* Register shifts are encoded as separate shift instructions. */
13088 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
13089
13090 if (in_pred_block ())
13091 narrow = !flags;
13092 else
13093 narrow = flags;
13094
13095 if (inst.size_req == 4)
13096 narrow = FALSE;
13097
13098 if (!low_regs || inst.operands[1].imm > 7)
13099 narrow = FALSE;
13100
13101 if (Rn != Rm)
13102 narrow = FALSE;
13103
13104 switch (inst.operands[1].shift_kind)
13105 {
13106 case SHIFT_LSL:
13107 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
13108 break;
13109 case SHIFT_ASR:
13110 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
13111 break;
13112 case SHIFT_LSR:
13113 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
13114 break;
13115 case SHIFT_ROR:
13116 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
13117 break;
13118 default:
13119 abort ();
13120 }
13121
13122 inst.instruction = opcode;
13123 if (narrow)
13124 {
13125 inst.instruction |= Rn;
13126 inst.instruction |= inst.operands[1].imm << 3;
13127 }
13128 else
13129 {
13130 if (flags)
13131 inst.instruction |= CONDS_BIT;
13132
13133 inst.instruction |= Rn << 8;
13134 inst.instruction |= Rm << 16;
13135 inst.instruction |= inst.operands[1].imm;
13136 }
13137 }
13138 else if (!narrow)
13139 {
13140 /* Some mov with immediate shift have narrow variants.
13141 Register shifts are handled above. */
13142 if (low_regs && inst.operands[1].shifted
13143 && (inst.instruction == T_MNEM_mov
13144 || inst.instruction == T_MNEM_movs))
13145 {
13146 if (in_pred_block ())
13147 narrow = (inst.instruction == T_MNEM_mov);
13148 else
13149 narrow = (inst.instruction == T_MNEM_movs);
13150 }
13151
13152 if (narrow)
13153 {
13154 switch (inst.operands[1].shift_kind)
13155 {
13156 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13157 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
13158 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13159 default: narrow = FALSE; break;
13160 }
13161 }
13162
13163 if (narrow)
13164 {
13165 inst.instruction |= Rn;
13166 inst.instruction |= Rm << 3;
13167 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13168 }
13169 else
13170 {
13171 inst.instruction = THUMB_OP32 (inst.instruction);
13172 inst.instruction |= Rn << r0off;
13173 encode_thumb32_shifted_operand (1);
13174 }
13175 }
13176 else
13177 switch (inst.instruction)
13178 {
13179 case T_MNEM_mov:
13180 /* In v4t or v5t a move of two lowregs produces unpredictable
13181 results. Don't allow this. */
13182 if (low_regs)
13183 {
13184 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
13185 "MOV Rd, Rs with two low registers is not "
13186 "permitted on this architecture");
13187 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
13188 arm_ext_v6);
13189 }
13190
13191 inst.instruction = T_OPCODE_MOV_HR;
13192 inst.instruction |= (Rn & 0x8) << 4;
13193 inst.instruction |= (Rn & 0x7);
13194 inst.instruction |= Rm << 3;
13195 break;
13196
13197 case T_MNEM_movs:
13198 /* We know we have low registers at this point.
13199 Generate LSLS Rd, Rs, #0. */
13200 inst.instruction = T_OPCODE_LSL_I;
13201 inst.instruction |= Rn;
13202 inst.instruction |= Rm << 3;
13203 break;
13204
13205 case T_MNEM_cmp:
13206 if (low_regs)
13207 {
13208 inst.instruction = T_OPCODE_CMP_LR;
13209 inst.instruction |= Rn;
13210 inst.instruction |= Rm << 3;
13211 }
13212 else
13213 {
13214 inst.instruction = T_OPCODE_CMP_HR;
13215 inst.instruction |= (Rn & 0x8) << 4;
13216 inst.instruction |= (Rn & 0x7);
13217 inst.instruction |= Rm << 3;
13218 }
13219 break;
13220 }
13221 return;
13222 }
13223
13224 inst.instruction = THUMB_OP16 (inst.instruction);
13225
13226 /* PR 10443: Do not silently ignore shifted operands. */
13227 constraint (inst.operands[1].shifted,
13228 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13229
13230 if (inst.operands[1].isreg)
13231 {
13232 if (Rn < 8 && Rm < 8)
13233 {
13234 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13235 since a MOV instruction produces unpredictable results. */
13236 if (inst.instruction == T_OPCODE_MOV_I8)
13237 inst.instruction = T_OPCODE_ADD_I3;
13238 else
13239 inst.instruction = T_OPCODE_CMP_LR;
13240
13241 inst.instruction |= Rn;
13242 inst.instruction |= Rm << 3;
13243 }
13244 else
13245 {
13246 if (inst.instruction == T_OPCODE_MOV_I8)
13247 inst.instruction = T_OPCODE_MOV_HR;
13248 else
13249 inst.instruction = T_OPCODE_CMP_HR;
13250 do_t_cpy ();
13251 }
13252 }
13253 else
13254 {
13255 constraint (Rn > 7,
13256 _("only lo regs allowed with immediate"));
13257 inst.instruction |= Rn << 8;
13258 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
13259 }
13260}
13261
13262static void
13263do_t_mov16 (void)
13264{
13265 unsigned Rd;
13266 bfd_vma imm;
13267 bfd_boolean top;
13268
13269 top = (inst.instruction & 0x00800000) != 0;
13270 if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
13271 {
13272 constraint (top, _(":lower16: not allowed in this instruction"));
13273 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
13274 }
13275 else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
13276 {
13277 constraint (!top, _(":upper16: not allowed in this instruction"));
13278 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
13279 }
13280
13281 Rd = inst.operands[0].reg;
13282 reject_bad_reg (Rd);
13283
13284 inst.instruction |= Rd << 8;
13285 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
13286 {
13287 imm = inst.relocs[0].exp.X_add_number;
13288 inst.instruction |= (imm & 0xf000) << 4;
13289 inst.instruction |= (imm & 0x0800) << 15;
13290 inst.instruction |= (imm & 0x0700) << 4;
13291 inst.instruction |= (imm & 0x00ff);
13292 }
13293}
13294
13295static void
13296do_t_mvn_tst (void)
13297{
13298 unsigned Rn, Rm;
13299
13300 Rn = inst.operands[0].reg;
13301 Rm = inst.operands[1].reg;
13302
13303 if (inst.instruction == T_MNEM_cmp
13304 || inst.instruction == T_MNEM_cmn)
13305 constraint (Rn == REG_PC, BAD_PC);
13306 else
13307 reject_bad_reg (Rn);
13308 reject_bad_reg (Rm);
13309
13310 if (unified_syntax)
13311 {
13312 int r0off = (inst.instruction == T_MNEM_mvn
13313 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
13314 bfd_boolean narrow;
13315
13316 if (inst.size_req == 4
13317 || inst.instruction > 0xffff
13318 || inst.operands[1].shifted
13319 || Rn > 7 || Rm > 7)
13320 narrow = FALSE;
13321 else if (inst.instruction == T_MNEM_cmn
13322 || inst.instruction == T_MNEM_tst)
13323 narrow = TRUE;
13324 else if (THUMB_SETS_FLAGS (inst.instruction))
13325 narrow = !in_pred_block ();
13326 else
13327 narrow = in_pred_block ();
13328
13329 if (!inst.operands[1].isreg)
13330 {
13331 /* For an immediate, we always generate a 32-bit opcode;
13332 section relaxation will shrink it later if possible. */
13333 if (inst.instruction < 0xffff)
13334 inst.instruction = THUMB_OP32 (inst.instruction);
13335 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13336 inst.instruction |= Rn << r0off;
13337 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13338 }
13339 else
13340 {
13341 /* See if we can do this with a 16-bit instruction. */
13342 if (narrow)
13343 {
13344 inst.instruction = THUMB_OP16 (inst.instruction);
13345 inst.instruction |= Rn;
13346 inst.instruction |= Rm << 3;
13347 }
13348 else
13349 {
13350 constraint (inst.operands[1].shifted
13351 && inst.operands[1].immisreg,
13352 _("shift must be constant"));
13353 if (inst.instruction < 0xffff)
13354 inst.instruction = THUMB_OP32 (inst.instruction);
13355 inst.instruction |= Rn << r0off;
13356 encode_thumb32_shifted_operand (1);
13357 }
13358 }
13359 }
13360 else
13361 {
13362 constraint (inst.instruction > 0xffff
13363 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
13364 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
13365 _("unshifted register required"));
13366 constraint (Rn > 7 || Rm > 7,
13367 BAD_HIREG);
13368
13369 inst.instruction = THUMB_OP16 (inst.instruction);
13370 inst.instruction |= Rn;
13371 inst.instruction |= Rm << 3;
13372 }
13373}
13374
13375static void
13376do_t_mrs (void)
13377{
13378 unsigned Rd;
13379
13380 if (do_vfp_nsyn_mrs () == SUCCESS)
13381 return;
13382
13383 Rd = inst.operands[0].reg;
13384 reject_bad_reg (Rd);
13385 inst.instruction |= Rd << 8;
13386
13387 if (inst.operands[1].isreg)
13388 {
13389 unsigned br = inst.operands[1].reg;
13390 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
13391 as_bad (_("bad register for mrs"));
13392
13393 inst.instruction |= br & (0xf << 16);
13394 inst.instruction |= (br & 0x300) >> 4;
13395 inst.instruction |= (br & SPSR_BIT) >> 2;
13396 }
13397 else
13398 {
13399 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13400
13401 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
13402 {
13403 /* PR gas/12698: The constraint is only applied for m_profile.
13404 If the user has specified -march=all, we want to ignore it as
13405 we are building for any CPU type, including non-m variants. */
13406 bfd_boolean m_profile =
13407 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
13408 constraint ((flags != 0) && m_profile, _("selected processor does "
13409 "not support requested special purpose register"));
13410 }
13411 else
13412 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13413 devices). */
13414 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
13415 _("'APSR', 'CPSR' or 'SPSR' expected"));
13416
13417 inst.instruction |= (flags & SPSR_BIT) >> 2;
13418 inst.instruction |= inst.operands[1].imm & 0xff;
13419 inst.instruction |= 0xf0000;
13420 }
13421}
13422
13423static void
13424do_t_msr (void)
13425{
13426 int flags;
13427 unsigned Rn;
13428
13429 if (do_vfp_nsyn_msr () == SUCCESS)
13430 return;
13431
13432 constraint (!inst.operands[1].isreg,
13433 _("Thumb encoding does not support an immediate here"));
13434
13435 if (inst.operands[0].isreg)
13436 flags = (int)(inst.operands[0].reg);
13437 else
13438 flags = inst.operands[0].imm;
13439
13440 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
13441 {
13442 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13443
13444 /* PR gas/12698: The constraint is only applied for m_profile.
13445 If the user has specified -march=all, we want to ignore it as
13446 we are building for any CPU type, including non-m variants. */
13447 bfd_boolean m_profile =
13448 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
13449 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13450 && (bits & ~(PSR_s | PSR_f)) != 0)
13451 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13452 && bits != PSR_f)) && m_profile,
13453 _("selected processor does not support requested special "
13454 "purpose register"));
13455 }
13456 else
13457 constraint ((flags & 0xff) != 0, _("selected processor does not support "
13458 "requested special purpose register"));
13459
13460 Rn = inst.operands[1].reg;
13461 reject_bad_reg (Rn);
13462
13463 inst.instruction |= (flags & SPSR_BIT) >> 2;
13464 inst.instruction |= (flags & 0xf0000) >> 8;
13465 inst.instruction |= (flags & 0x300) >> 4;
13466 inst.instruction |= (flags & 0xff);
13467 inst.instruction |= Rn << 16;
13468}
13469
13470static void
13471do_t_mul (void)
13472{
13473 bfd_boolean narrow;
13474 unsigned Rd, Rn, Rm;
13475
13476 if (!inst.operands[2].present)
13477 inst.operands[2].reg = inst.operands[0].reg;
13478
13479 Rd = inst.operands[0].reg;
13480 Rn = inst.operands[1].reg;
13481 Rm = inst.operands[2].reg;
13482
13483 if (unified_syntax)
13484 {
13485 if (inst.size_req == 4
13486 || (Rd != Rn
13487 && Rd != Rm)
13488 || Rn > 7
13489 || Rm > 7)
13490 narrow = FALSE;
13491 else if (inst.instruction == T_MNEM_muls)
13492 narrow = !in_pred_block ();
13493 else
13494 narrow = in_pred_block ();
13495 }
13496 else
13497 {
13498 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
13499 constraint (Rn > 7 || Rm > 7,
13500 BAD_HIREG);
13501 narrow = TRUE;
13502 }
13503
13504 if (narrow)
13505 {
13506 /* 16-bit MULS/Conditional MUL. */
13507 inst.instruction = THUMB_OP16 (inst.instruction);
13508 inst.instruction |= Rd;
13509
13510 if (Rd == Rn)
13511 inst.instruction |= Rm << 3;
13512 else if (Rd == Rm)
13513 inst.instruction |= Rn << 3;
13514 else
13515 constraint (1, _("dest must overlap one source register"));
13516 }
13517 else
13518 {
13519 constraint (inst.instruction != T_MNEM_mul,
13520 _("Thumb-2 MUL must not set flags"));
13521 /* 32-bit MUL. */
13522 inst.instruction = THUMB_OP32 (inst.instruction);
13523 inst.instruction |= Rd << 8;
13524 inst.instruction |= Rn << 16;
13525 inst.instruction |= Rm << 0;
13526
13527 reject_bad_reg (Rd);
13528 reject_bad_reg (Rn);
13529 reject_bad_reg (Rm);
13530 }
13531}
13532
13533static void
13534do_t_mull (void)
13535{
13536 unsigned RdLo, RdHi, Rn, Rm;
13537
13538 RdLo = inst.operands[0].reg;
13539 RdHi = inst.operands[1].reg;
13540 Rn = inst.operands[2].reg;
13541 Rm = inst.operands[3].reg;
13542
13543 reject_bad_reg (RdLo);
13544 reject_bad_reg (RdHi);
13545 reject_bad_reg (Rn);
13546 reject_bad_reg (Rm);
13547
13548 inst.instruction |= RdLo << 12;
13549 inst.instruction |= RdHi << 8;
13550 inst.instruction |= Rn << 16;
13551 inst.instruction |= Rm;
13552
13553 if (RdLo == RdHi)
13554 as_tsktsk (_("rdhi and rdlo must be different"));
13555}
13556
13557static void
13558do_t_nop (void)
13559{
13560 set_pred_insn_type (NEUTRAL_IT_INSN);
13561
13562 if (unified_syntax)
13563 {
13564 if (inst.size_req == 4 || inst.operands[0].imm > 15)
13565 {
13566 inst.instruction = THUMB_OP32 (inst.instruction);
13567 inst.instruction |= inst.operands[0].imm;
13568 }
13569 else
13570 {
13571 /* PR9722: Check for Thumb2 availability before
13572 generating a thumb2 nop instruction. */
13573 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
13574 {
13575 inst.instruction = THUMB_OP16 (inst.instruction);
13576 inst.instruction |= inst.operands[0].imm << 4;
13577 }
13578 else
13579 inst.instruction = 0x46c0;
13580 }
13581 }
13582 else
13583 {
13584 constraint (inst.operands[0].present,
13585 _("Thumb does not support NOP with hints"));
13586 inst.instruction = 0x46c0;
13587 }
13588}
13589
13590static void
13591do_t_neg (void)
13592{
13593 if (unified_syntax)
13594 {
13595 bfd_boolean narrow;
13596
13597 if (THUMB_SETS_FLAGS (inst.instruction))
13598 narrow = !in_pred_block ();
13599 else
13600 narrow = in_pred_block ();
13601 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13602 narrow = FALSE;
13603 if (inst.size_req == 4)
13604 narrow = FALSE;
13605
13606 if (!narrow)
13607 {
13608 inst.instruction = THUMB_OP32 (inst.instruction);
13609 inst.instruction |= inst.operands[0].reg << 8;
13610 inst.instruction |= inst.operands[1].reg << 16;
13611 }
13612 else
13613 {
13614 inst.instruction = THUMB_OP16 (inst.instruction);
13615 inst.instruction |= inst.operands[0].reg;
13616 inst.instruction |= inst.operands[1].reg << 3;
13617 }
13618 }
13619 else
13620 {
13621 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13622 BAD_HIREG);
13623 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13624
13625 inst.instruction = THUMB_OP16 (inst.instruction);
13626 inst.instruction |= inst.operands[0].reg;
13627 inst.instruction |= inst.operands[1].reg << 3;
13628 }
13629}
13630
13631static void
13632do_t_orn (void)
13633{
13634 unsigned Rd, Rn;
13635
13636 Rd = inst.operands[0].reg;
13637 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13638
13639 reject_bad_reg (Rd);
13640 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13641 reject_bad_reg (Rn);
13642
13643 inst.instruction |= Rd << 8;
13644 inst.instruction |= Rn << 16;
13645
13646 if (!inst.operands[2].isreg)
13647 {
13648 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13649 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13650 }
13651 else
13652 {
13653 unsigned Rm;
13654
13655 Rm = inst.operands[2].reg;
13656 reject_bad_reg (Rm);
13657
13658 constraint (inst.operands[2].shifted
13659 && inst.operands[2].immisreg,
13660 _("shift must be constant"));
13661 encode_thumb32_shifted_operand (2);
13662 }
13663}
13664
13665static void
13666do_t_pkhbt (void)
13667{
13668 unsigned Rd, Rn, Rm;
13669
13670 Rd = inst.operands[0].reg;
13671 Rn = inst.operands[1].reg;
13672 Rm = inst.operands[2].reg;
13673
13674 reject_bad_reg (Rd);
13675 reject_bad_reg (Rn);
13676 reject_bad_reg (Rm);
13677
13678 inst.instruction |= Rd << 8;
13679 inst.instruction |= Rn << 16;
13680 inst.instruction |= Rm;
13681 if (inst.operands[3].present)
13682 {
13683 unsigned int val = inst.relocs[0].exp.X_add_number;
13684 constraint (inst.relocs[0].exp.X_op != O_constant,
13685 _("expression too complex"));
13686 inst.instruction |= (val & 0x1c) << 10;
13687 inst.instruction |= (val & 0x03) << 6;
13688 }
13689}
13690
13691static void
13692do_t_pkhtb (void)
13693{
13694 if (!inst.operands[3].present)
13695 {
13696 unsigned Rtmp;
13697
13698 inst.instruction &= ~0x00000020;
13699
13700 /* PR 10168. Swap the Rm and Rn registers. */
13701 Rtmp = inst.operands[1].reg;
13702 inst.operands[1].reg = inst.operands[2].reg;
13703 inst.operands[2].reg = Rtmp;
13704 }
13705 do_t_pkhbt ();
13706}
13707
13708static void
13709do_t_pld (void)
13710{
13711 if (inst.operands[0].immisreg)
13712 reject_bad_reg (inst.operands[0].imm);
13713
13714 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
13715}
13716
13717static void
13718do_t_push_pop (void)
13719{
13720 unsigned mask;
13721
13722 constraint (inst.operands[0].writeback,
13723 _("push/pop do not support {reglist}^"));
13724 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
13725 _("expression too complex"));
13726
13727 mask = inst.operands[0].imm;
13728 if (inst.size_req != 4 && (mask & ~0xff) == 0)
13729 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
13730 else if (inst.size_req != 4
13731 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
13732 ? REG_LR : REG_PC)))
13733 {
13734 inst.instruction = THUMB_OP16 (inst.instruction);
13735 inst.instruction |= THUMB_PP_PC_LR;
13736 inst.instruction |= mask & 0xff;
13737 }
13738 else if (unified_syntax)
13739 {
13740 inst.instruction = THUMB_OP32 (inst.instruction);
13741 encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
13742 }
13743 else
13744 {
13745 inst.error = _("invalid register list to push/pop instruction");
13746 return;
13747 }
13748}
13749
13750static void
13751do_t_clrm (void)
13752{
13753 if (unified_syntax)
13754 encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
13755 else
13756 {
13757 inst.error = _("invalid register list to push/pop instruction");
13758 return;
13759 }
13760}
13761
13762static void
13763do_t_vscclrm (void)
13764{
13765 if (inst.operands[0].issingle)
13766 {
13767 inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13768 inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13769 inst.instruction |= inst.operands[0].imm;
13770 }
13771 else
13772 {
13773 inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13774 inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13775 inst.instruction |= 1 << 8;
13776 inst.instruction |= inst.operands[0].imm << 1;
13777 }
13778}
13779
13780static void
13781do_t_rbit (void)
13782{
13783 unsigned Rd, Rm;
13784
13785 Rd = inst.operands[0].reg;
13786 Rm = inst.operands[1].reg;
13787
13788 reject_bad_reg (Rd);
13789 reject_bad_reg (Rm);
13790
13791 inst.instruction |= Rd << 8;
13792 inst.instruction |= Rm << 16;
13793 inst.instruction |= Rm;
13794}
13795
13796static void
13797do_t_rev (void)
13798{
13799 unsigned Rd, Rm;
13800
13801 Rd = inst.operands[0].reg;
13802 Rm = inst.operands[1].reg;
13803
13804 reject_bad_reg (Rd);
13805 reject_bad_reg (Rm);
13806
13807 if (Rd <= 7 && Rm <= 7
13808 && inst.size_req != 4)
13809 {
13810 inst.instruction = THUMB_OP16 (inst.instruction);
13811 inst.instruction |= Rd;
13812 inst.instruction |= Rm << 3;
13813 }
13814 else if (unified_syntax)
13815 {
13816 inst.instruction = THUMB_OP32 (inst.instruction);
13817 inst.instruction |= Rd << 8;
13818 inst.instruction |= Rm << 16;
13819 inst.instruction |= Rm;
13820 }
13821 else
13822 inst.error = BAD_HIREG;
13823}
13824
13825static void
13826do_t_rrx (void)
13827{
13828 unsigned Rd, Rm;
13829
13830 Rd = inst.operands[0].reg;
13831 Rm = inst.operands[1].reg;
13832
13833 reject_bad_reg (Rd);
13834 reject_bad_reg (Rm);
13835
13836 inst.instruction |= Rd << 8;
13837 inst.instruction |= Rm;
13838}
13839
13840static void
13841do_t_rsb (void)
13842{
13843 unsigned Rd, Rs;
13844
13845 Rd = inst.operands[0].reg;
13846 Rs = (inst.operands[1].present
13847 ? inst.operands[1].reg /* Rd, Rs, foo */
13848 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
13849
13850 reject_bad_reg (Rd);
13851 reject_bad_reg (Rs);
13852 if (inst.operands[2].isreg)
13853 reject_bad_reg (inst.operands[2].reg);
13854
13855 inst.instruction |= Rd << 8;
13856 inst.instruction |= Rs << 16;
13857 if (!inst.operands[2].isreg)
13858 {
13859 bfd_boolean narrow;
13860
13861 if ((inst.instruction & 0x00100000) != 0)
13862 narrow = !in_pred_block ();
13863 else
13864 narrow = in_pred_block ();
13865
13866 if (Rd > 7 || Rs > 7)
13867 narrow = FALSE;
13868
13869 if (inst.size_req == 4 || !unified_syntax)
13870 narrow = FALSE;
13871
13872 if (inst.relocs[0].exp.X_op != O_constant
13873 || inst.relocs[0].exp.X_add_number != 0)
13874 narrow = FALSE;
13875
13876 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13877 relaxation, but it doesn't seem worth the hassle. */
13878 if (narrow)
13879 {
13880 inst.relocs[0].type = BFD_RELOC_UNUSED;
13881 inst.instruction = THUMB_OP16 (T_MNEM_negs);
13882 inst.instruction |= Rs << 3;
13883 inst.instruction |= Rd;
13884 }
13885 else
13886 {
13887 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13888 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13889 }
13890 }
13891 else
13892 encode_thumb32_shifted_operand (2);
13893}
13894
13895static void
13896do_t_setend (void)
13897{
13898 if (warn_on_deprecated
13899 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13900 as_tsktsk (_("setend use is deprecated for ARMv8"));
13901
13902 set_pred_insn_type (OUTSIDE_PRED_INSN);
13903 if (inst.operands[0].imm)
13904 inst.instruction |= 0x8;
13905}
13906
13907static void
13908do_t_shift (void)
13909{
13910 if (!inst.operands[1].present)
13911 inst.operands[1].reg = inst.operands[0].reg;
13912
13913 if (unified_syntax)
13914 {
13915 bfd_boolean narrow;
13916 int shift_kind;
13917
13918 switch (inst.instruction)
13919 {
13920 case T_MNEM_asr:
13921 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
13922 case T_MNEM_lsl:
13923 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
13924 case T_MNEM_lsr:
13925 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
13926 case T_MNEM_ror:
13927 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
13928 default: abort ();
13929 }
13930
13931 if (THUMB_SETS_FLAGS (inst.instruction))
13932 narrow = !in_pred_block ();
13933 else
13934 narrow = in_pred_block ();
13935 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13936 narrow = FALSE;
13937 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13938 narrow = FALSE;
13939 if (inst.operands[2].isreg
13940 && (inst.operands[1].reg != inst.operands[0].reg
13941 || inst.operands[2].reg > 7))
13942 narrow = FALSE;
13943 if (inst.size_req == 4)
13944 narrow = FALSE;
13945
13946 reject_bad_reg (inst.operands[0].reg);
13947 reject_bad_reg (inst.operands[1].reg);
13948
13949 if (!narrow)
13950 {
13951 if (inst.operands[2].isreg)
13952 {
13953 reject_bad_reg (inst.operands[2].reg);
13954 inst.instruction = THUMB_OP32 (inst.instruction);
13955 inst.instruction |= inst.operands[0].reg << 8;
13956 inst.instruction |= inst.operands[1].reg << 16;
13957 inst.instruction |= inst.operands[2].reg;
13958
13959 /* PR 12854: Error on extraneous shifts. */
13960 constraint (inst.operands[2].shifted,
13961 _("extraneous shift as part of operand to shift insn"));
13962 }
13963 else
13964 {
13965 inst.operands[1].shifted = 1;
13966 inst.operands[1].shift_kind = shift_kind;
13967 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
13968 ? T_MNEM_movs : T_MNEM_mov);
13969 inst.instruction |= inst.operands[0].reg << 8;
13970 encode_thumb32_shifted_operand (1);
13971 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13972 inst.relocs[0].type = BFD_RELOC_UNUSED;
13973 }
13974 }
13975 else
13976 {
13977 if (inst.operands[2].isreg)
13978 {
13979 switch (shift_kind)
13980 {
13981 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
13982 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
13983 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
13984 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
13985 default: abort ();
13986 }
13987
13988 inst.instruction |= inst.operands[0].reg;
13989 inst.instruction |= inst.operands[2].reg << 3;
13990
13991 /* PR 12854: Error on extraneous shifts. */
13992 constraint (inst.operands[2].shifted,
13993 _("extraneous shift as part of operand to shift insn"));
13994 }
13995 else
13996 {
13997 switch (shift_kind)
13998 {
13999 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
14000 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
14001 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
14002 default: abort ();
14003 }
14004 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
14005 inst.instruction |= inst.operands[0].reg;
14006 inst.instruction |= inst.operands[1].reg << 3;
14007 }
14008 }
14009 }
14010 else
14011 {
14012 constraint (inst.operands[0].reg > 7
14013 || inst.operands[1].reg > 7, BAD_HIREG);
14014 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
14015
14016 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
14017 {
14018 constraint (inst.operands[2].reg > 7, BAD_HIREG);
14019 constraint (inst.operands[0].reg != inst.operands[1].reg,
14020 _("source1 and dest must be same register"));
14021
14022 switch (inst.instruction)
14023 {
14024 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
14025 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
14026 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
14027 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
14028 default: abort ();
14029 }
14030
14031 inst.instruction |= inst.operands[0].reg;
14032 inst.instruction |= inst.operands[2].reg << 3;
14033
14034 /* PR 12854: Error on extraneous shifts. */
14035 constraint (inst.operands[2].shifted,
14036 _("extraneous shift as part of operand to shift insn"));
14037 }
14038 else
14039 {
14040 switch (inst.instruction)
14041 {
14042 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
14043 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
14044 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
14045 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
14046 default: abort ();
14047 }
14048 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
14049 inst.instruction |= inst.operands[0].reg;
14050 inst.instruction |= inst.operands[1].reg << 3;
14051 }
14052 }
14053}
14054
14055static void
14056do_t_simd (void)
14057{
14058 unsigned Rd, Rn, Rm;
14059
14060 Rd = inst.operands[0].reg;
14061 Rn = inst.operands[1].reg;
14062 Rm = inst.operands[2].reg;
14063
14064 reject_bad_reg (Rd);
14065 reject_bad_reg (Rn);
14066 reject_bad_reg (Rm);
14067
14068 inst.instruction |= Rd << 8;
14069 inst.instruction |= Rn << 16;
14070 inst.instruction |= Rm;
14071}
14072
14073static void
14074do_t_simd2 (void)
14075{
14076 unsigned Rd, Rn, Rm;
14077
14078 Rd = inst.operands[0].reg;
14079 Rm = inst.operands[1].reg;
14080 Rn = inst.operands[2].reg;
14081
14082 reject_bad_reg (Rd);
14083 reject_bad_reg (Rn);
14084 reject_bad_reg (Rm);
14085
14086 inst.instruction |= Rd << 8;
14087 inst.instruction |= Rn << 16;
14088 inst.instruction |= Rm;
14089}
14090
14091static void
14092do_t_smc (void)
14093{
14094 unsigned int value = inst.relocs[0].exp.X_add_number;
14095 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
14096 _("SMC is not permitted on this architecture"));
14097 constraint (inst.relocs[0].exp.X_op != O_constant,
14098 _("expression too complex"));
14099 constraint (value > 0xf, _("immediate too large (bigger than 0xF)"));
14100
14101 inst.relocs[0].type = BFD_RELOC_UNUSED;
14102 inst.instruction |= (value & 0x000f) << 16;
14103
14104 /* PR gas/15623: SMC instructions must be last in an IT block. */
14105 set_pred_insn_type_last ();
14106}
14107
14108static void
14109do_t_hvc (void)
14110{
14111 unsigned int value = inst.relocs[0].exp.X_add_number;
14112
14113 inst.relocs[0].type = BFD_RELOC_UNUSED;
14114 inst.instruction |= (value & 0x0fff);
14115 inst.instruction |= (value & 0xf000) << 4;
14116}
14117
14118static void
14119do_t_ssat_usat (int bias)
14120{
14121 unsigned Rd, Rn;
14122
14123 Rd = inst.operands[0].reg;
14124 Rn = inst.operands[2].reg;
14125
14126 reject_bad_reg (Rd);
14127 reject_bad_reg (Rn);
14128
14129 inst.instruction |= Rd << 8;
14130 inst.instruction |= inst.operands[1].imm - bias;
14131 inst.instruction |= Rn << 16;
14132
14133 if (inst.operands[3].present)
14134 {
14135 offsetT shift_amount = inst.relocs[0].exp.X_add_number;
14136
14137 inst.relocs[0].type = BFD_RELOC_UNUSED;
14138
14139 constraint (inst.relocs[0].exp.X_op != O_constant,
14140 _("expression too complex"));
14141
14142 if (shift_amount != 0)
14143 {
14144 constraint (shift_amount > 31,
14145 _("shift expression is too large"));
14146
14147 if (inst.operands[3].shift_kind == SHIFT_ASR)
14148 inst.instruction |= 0x00200000; /* sh bit. */
14149
14150 inst.instruction |= (shift_amount & 0x1c) << 10;
14151 inst.instruction |= (shift_amount & 0x03) << 6;
14152 }
14153 }
14154}
14155
14156static void
14157do_t_ssat (void)
14158{
14159 do_t_ssat_usat (1);
14160}
14161
14162static void
14163do_t_ssat16 (void)
14164{
14165 unsigned Rd, Rn;
14166
14167 Rd = inst.operands[0].reg;
14168 Rn = inst.operands[2].reg;
14169
14170 reject_bad_reg (Rd);
14171 reject_bad_reg (Rn);
14172
14173 inst.instruction |= Rd << 8;
14174 inst.instruction |= inst.operands[1].imm - 1;
14175 inst.instruction |= Rn << 16;
14176}
14177
14178static void
14179do_t_strex (void)
14180{
14181 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
14182 || inst.operands[2].postind || inst.operands[2].writeback
14183 || inst.operands[2].immisreg || inst.operands[2].shifted
14184 || inst.operands[2].negative,
14185 BAD_ADDR_MODE);
14186
14187 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
14188
14189 inst.instruction |= inst.operands[0].reg << 8;
14190 inst.instruction |= inst.operands[1].reg << 12;
14191 inst.instruction |= inst.operands[2].reg << 16;
14192 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
14193}
14194
14195static void
14196do_t_strexd (void)
14197{
14198 if (!inst.operands[2].present)
14199 inst.operands[2].reg = inst.operands[1].reg + 1;
14200
14201 constraint (inst.operands[0].reg == inst.operands[1].reg
14202 || inst.operands[0].reg == inst.operands[2].reg
14203 || inst.operands[0].reg == inst.operands[3].reg,
14204 BAD_OVERLAP);
14205
14206 inst.instruction |= inst.operands[0].reg;
14207 inst.instruction |= inst.operands[1].reg << 12;
14208 inst.instruction |= inst.operands[2].reg << 8;
14209 inst.instruction |= inst.operands[3].reg << 16;
14210}
14211
14212static void
14213do_t_sxtah (void)
14214{
14215 unsigned Rd, Rn, Rm;
14216
14217 Rd = inst.operands[0].reg;
14218 Rn = inst.operands[1].reg;
14219 Rm = inst.operands[2].reg;
14220
14221 reject_bad_reg (Rd);
14222 reject_bad_reg (Rn);
14223 reject_bad_reg (Rm);
14224
14225 inst.instruction |= Rd << 8;
14226 inst.instruction |= Rn << 16;
14227 inst.instruction |= Rm;
14228 inst.instruction |= inst.operands[3].imm << 4;
14229}
14230
14231static void
14232do_t_sxth (void)
14233{
14234 unsigned Rd, Rm;
14235
14236 Rd = inst.operands[0].reg;
14237 Rm = inst.operands[1].reg;
14238
14239 reject_bad_reg (Rd);
14240 reject_bad_reg (Rm);
14241
14242 if (inst.instruction <= 0xffff
14243 && inst.size_req != 4
14244 && Rd <= 7 && Rm <= 7
14245 && (!inst.operands[2].present || inst.operands[2].imm == 0))
14246 {
14247 inst.instruction = THUMB_OP16 (inst.instruction);
14248 inst.instruction |= Rd;
14249 inst.instruction |= Rm << 3;
14250 }
14251 else if (unified_syntax)
14252 {
14253 if (inst.instruction <= 0xffff)
14254 inst.instruction = THUMB_OP32 (inst.instruction);
14255 inst.instruction |= Rd << 8;
14256 inst.instruction |= Rm;
14257 inst.instruction |= inst.operands[2].imm << 4;
14258 }
14259 else
14260 {
14261 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
14262 _("Thumb encoding does not support rotation"));
14263 constraint (1, BAD_HIREG);
14264 }
14265}
14266
14267static void
14268do_t_swi (void)
14269{
14270 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
14271}
14272
14273static void
14274do_t_tb (void)
14275{
14276 unsigned Rn, Rm;
14277 int half;
14278
14279 half = (inst.instruction & 0x10) != 0;
14280 set_pred_insn_type_last ();
14281 constraint (inst.operands[0].immisreg,
14282 _("instruction requires register index"));
14283
14284 Rn = inst.operands[0].reg;
14285 Rm = inst.operands[0].imm;
14286
14287 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
14288 constraint (Rn == REG_SP, BAD_SP);
14289 reject_bad_reg (Rm);
14290
14291 constraint (!half && inst.operands[0].shifted,
14292 _("instruction does not allow shifted index"));
14293 inst.instruction |= (Rn << 16) | Rm;
14294}
14295
14296static void
14297do_t_udf (void)
14298{
14299 if (!inst.operands[0].present)
14300 inst.operands[0].imm = 0;
14301
14302 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
14303 {
14304 constraint (inst.size_req == 2,
14305 _("immediate value out of range"));
14306 inst.instruction = THUMB_OP32 (inst.instruction);
14307 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
14308 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
14309 }
14310 else
14311 {
14312 inst.instruction = THUMB_OP16 (inst.instruction);
14313 inst.instruction |= inst.operands[0].imm;
14314 }
14315
14316 set_pred_insn_type (NEUTRAL_IT_INSN);
14317}
14318
14319
14320static void
14321do_t_usat (void)
14322{
14323 do_t_ssat_usat (0);
14324}
14325
14326static void
14327do_t_usat16 (void)
14328{
14329 unsigned Rd, Rn;
14330
14331 Rd = inst.operands[0].reg;
14332 Rn = inst.operands[2].reg;
14333
14334 reject_bad_reg (Rd);
14335 reject_bad_reg (Rn);
14336
14337 inst.instruction |= Rd << 8;
14338 inst.instruction |= inst.operands[1].imm;
14339 inst.instruction |= Rn << 16;
14340}
14341
14342/* Checking the range of the branch offset (VAL) with NBITS bits
14343 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14344static int
14345v8_1_branch_value_check (int val, int nbits, int is_signed)
14346{
14347 gas_assert (nbits > 0 && nbits <= 32);
14348 if (is_signed)
14349 {
14350 int cmp = (1 << (nbits - 1));
14351 if ((val < -cmp) || (val >= cmp) || (val & 0x01))
14352 return FAIL;
14353 }
14354 else
14355 {
14356 if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1))
14357 return FAIL;
14358 }
14359 return SUCCESS;
14360}
14361
14362/* For branches in Armv8.1-M Mainline. */
14363static void
14364do_t_branch_future (void)
14365{
14366 unsigned long insn = inst.instruction;
14367
14368 inst.instruction = THUMB_OP32 (inst.instruction);
14369 if (inst.operands[0].hasreloc == 0)
14370 {
14371 if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
14372 as_bad (BAD_BRANCH_OFF);
14373
14374 inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
14375 }
14376 else
14377 {
14378 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
14379 inst.relocs[0].pc_rel = 1;
14380 }
14381
14382 switch (insn)
14383 {
14384 case T_MNEM_bf:
14385 if (inst.operands[1].hasreloc == 0)
14386 {
14387 int val = inst.operands[1].imm;
14388 if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
14389 as_bad (BAD_BRANCH_OFF);
14390
14391 int immA = (val & 0x0001f000) >> 12;
14392 int immB = (val & 0x00000ffc) >> 2;
14393 int immC = (val & 0x00000002) >> 1;
14394 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14395 }
14396 else
14397 {
14398 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
14399 inst.relocs[1].pc_rel = 1;
14400 }
14401 break;
14402
14403 case T_MNEM_bfl:
14404 if (inst.operands[1].hasreloc == 0)
14405 {
14406 int val = inst.operands[1].imm;
14407 if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
14408 as_bad (BAD_BRANCH_OFF);
14409
14410 int immA = (val & 0x0007f000) >> 12;
14411 int immB = (val & 0x00000ffc) >> 2;
14412 int immC = (val & 0x00000002) >> 1;
14413 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14414 }
14415 else
14416 {
14417 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14418 inst.relocs[1].pc_rel = 1;
14419 }
14420 break;
14421
14422 case T_MNEM_bfcsel:
14423 /* Operand 1. */
14424 if (inst.operands[1].hasreloc == 0)
14425 {
14426 int val = inst.operands[1].imm;
14427 int immA = (val & 0x00001000) >> 12;
14428 int immB = (val & 0x00000ffc) >> 2;
14429 int immC = (val & 0x00000002) >> 1;
14430 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14431 }
14432 else
14433 {
14434 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14435 inst.relocs[1].pc_rel = 1;
14436 }
14437
14438 /* Operand 2. */
14439 if (inst.operands[2].hasreloc == 0)
14440 {
14441 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14442 int val2 = inst.operands[2].imm;
14443 int val0 = inst.operands[0].imm & 0x1f;
14444 int diff = val2 - val0;
14445 if (diff == 4)
14446 inst.instruction |= 1 << 17; /* T bit. */
14447 else if (diff != 2)
14448 as_bad (_("out of range label-relative fixup value"));
14449 }
14450 else
14451 {
14452 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14453 inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14454 inst.relocs[2].pc_rel = 1;
14455 }
14456
14457 /* Operand 3. */
14458 constraint (inst.cond != COND_ALWAYS, BAD_COND);
14459 inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14460 break;
14461
14462 case T_MNEM_bfx:
14463 case T_MNEM_bflx:
14464 inst.instruction |= inst.operands[1].reg << 16;
14465 break;
14466
14467 default: abort ();
14468 }
14469}
14470
14471/* Helper function for do_t_loloop to handle relocations. */
14472static void
14473v8_1_loop_reloc (int is_le)
14474{
14475 if (inst.relocs[0].exp.X_op == O_constant)
14476 {
14477 int value = inst.relocs[0].exp.X_add_number;
14478 value = (is_le) ? -value : value;
14479
14480 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
14481 as_bad (BAD_BRANCH_OFF);
14482
14483 int imml, immh;
14484
14485 immh = (value & 0x00000ffc) >> 2;
14486 imml = (value & 0x00000002) >> 1;
14487
14488 inst.instruction |= (imml << 11) | (immh << 1);
14489 }
14490 else
14491 {
14492 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14493 inst.relocs[0].pc_rel = 1;
14494 }
14495}
14496
14497/* For shifts with four operands in MVE. */
14498static void
14499do_mve_scalar_shift1 (void)
14500{
14501 unsigned int value = inst.operands[2].imm;
14502
14503 inst.instruction |= inst.operands[0].reg << 16;
14504 inst.instruction |= inst.operands[1].reg << 8;
14505
14506 /* Setting the bit for saturation. */
14507 inst.instruction |= ((value == 64) ? 0: 1) << 7;
14508
14509 /* Assuming Rm is already checked not to be 11x1. */
14510 constraint (inst.operands[3].reg == inst.operands[0].reg, BAD_OVERLAP);
14511 constraint (inst.operands[3].reg == inst.operands[1].reg, BAD_OVERLAP);
14512 inst.instruction |= inst.operands[3].reg << 12;
14513}
14514
14515/* For shifts in MVE. */
14516static void
14517do_mve_scalar_shift (void)
14518{
14519 if (!inst.operands[2].present)
14520 {
14521 inst.operands[2] = inst.operands[1];
14522 inst.operands[1].reg = 0xf;
14523 }
14524
14525 inst.instruction |= inst.operands[0].reg << 16;
14526 inst.instruction |= inst.operands[1].reg << 8;
14527
14528 if (inst.operands[2].isreg)
14529 {
14530 /* Assuming Rm is already checked not to be 11x1. */
14531 constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP);
14532 constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP);
14533 inst.instruction |= inst.operands[2].reg << 12;
14534 }
14535 else
14536 {
14537 /* Assuming imm is already checked as [1,32]. */
14538 unsigned int value = inst.operands[2].imm;
14539 inst.instruction |= (value & 0x1c) << 10;
14540 inst.instruction |= (value & 0x03) << 6;
14541 /* Change last 4 bits from 0xd to 0xf. */
14542 inst.instruction |= 0x2;
14543 }
14544}
14545
14546/* MVE instruction encoder helpers. */
14547#define M_MNEM_vabav 0xee800f01
14548#define M_MNEM_vmladav 0xeef00e00
14549#define M_MNEM_vmladava 0xeef00e20
14550#define M_MNEM_vmladavx 0xeef01e00
14551#define M_MNEM_vmladavax 0xeef01e20
14552#define M_MNEM_vmlsdav 0xeef00e01
14553#define M_MNEM_vmlsdava 0xeef00e21
14554#define M_MNEM_vmlsdavx 0xeef01e01
14555#define M_MNEM_vmlsdavax 0xeef01e21
14556#define M_MNEM_vmullt 0xee011e00
14557#define M_MNEM_vmullb 0xee010e00
14558#define M_MNEM_vctp 0xf000e801
14559#define M_MNEM_vst20 0xfc801e00
14560#define M_MNEM_vst21 0xfc801e20
14561#define M_MNEM_vst40 0xfc801e01
14562#define M_MNEM_vst41 0xfc801e21
14563#define M_MNEM_vst42 0xfc801e41
14564#define M_MNEM_vst43 0xfc801e61
14565#define M_MNEM_vld20 0xfc901e00
14566#define M_MNEM_vld21 0xfc901e20
14567#define M_MNEM_vld40 0xfc901e01
14568#define M_MNEM_vld41 0xfc901e21
14569#define M_MNEM_vld42 0xfc901e41
14570#define M_MNEM_vld43 0xfc901e61
14571#define M_MNEM_vstrb 0xec000e00
14572#define M_MNEM_vstrh 0xec000e10
14573#define M_MNEM_vstrw 0xec000e40
14574#define M_MNEM_vstrd 0xec000e50
14575#define M_MNEM_vldrb 0xec100e00
14576#define M_MNEM_vldrh 0xec100e10
14577#define M_MNEM_vldrw 0xec100e40
14578#define M_MNEM_vldrd 0xec100e50
14579#define M_MNEM_vmovlt 0xeea01f40
14580#define M_MNEM_vmovlb 0xeea00f40
14581#define M_MNEM_vmovnt 0xfe311e81
14582#define M_MNEM_vmovnb 0xfe310e81
14583#define M_MNEM_vadc 0xee300f00
14584#define M_MNEM_vadci 0xee301f00
14585#define M_MNEM_vbrsr 0xfe011e60
14586#define M_MNEM_vaddlv 0xee890f00
14587#define M_MNEM_vaddlva 0xee890f20
14588#define M_MNEM_vaddv 0xeef10f00
14589#define M_MNEM_vaddva 0xeef10f20
14590#define M_MNEM_vddup 0xee011f6e
14591#define M_MNEM_vdwdup 0xee011f60
14592#define M_MNEM_vidup 0xee010f6e
14593#define M_MNEM_viwdup 0xee010f60
14594#define M_MNEM_vmaxv 0xeee20f00
14595#define M_MNEM_vmaxav 0xeee00f00
14596#define M_MNEM_vminv 0xeee20f80
14597#define M_MNEM_vminav 0xeee00f80
14598#define M_MNEM_vmlaldav 0xee800e00
14599#define M_MNEM_vmlaldava 0xee800e20
14600#define M_MNEM_vmlaldavx 0xee801e00
14601#define M_MNEM_vmlaldavax 0xee801e20
14602#define M_MNEM_vmlsldav 0xee800e01
14603#define M_MNEM_vmlsldava 0xee800e21
14604#define M_MNEM_vmlsldavx 0xee801e01
14605#define M_MNEM_vmlsldavax 0xee801e21
14606#define M_MNEM_vrmlaldavhx 0xee801f00
14607#define M_MNEM_vrmlaldavhax 0xee801f20
14608#define M_MNEM_vrmlsldavh 0xfe800e01
14609#define M_MNEM_vrmlsldavha 0xfe800e21
14610#define M_MNEM_vrmlsldavhx 0xfe801e01
14611#define M_MNEM_vrmlsldavhax 0xfe801e21
14612#define M_MNEM_vqmovnt 0xee331e01
14613#define M_MNEM_vqmovnb 0xee330e01
14614#define M_MNEM_vqmovunt 0xee311e81
14615#define M_MNEM_vqmovunb 0xee310e81
14616#define M_MNEM_vshrnt 0xee801fc1
14617#define M_MNEM_vshrnb 0xee800fc1
14618#define M_MNEM_vrshrnt 0xfe801fc1
14619#define M_MNEM_vqshrnt 0xee801f40
14620#define M_MNEM_vqshrnb 0xee800f40
14621#define M_MNEM_vqshrunt 0xee801fc0
14622#define M_MNEM_vqshrunb 0xee800fc0
14623#define M_MNEM_vrshrnb 0xfe800fc1
14624#define M_MNEM_vqrshrnt 0xee801f41
14625#define M_MNEM_vqrshrnb 0xee800f41
14626#define M_MNEM_vqrshrunt 0xfe801fc0
14627#define M_MNEM_vqrshrunb 0xfe800fc0
14628
14629/* Bfloat16 instruction encoder helpers. */
14630#define B_MNEM_vfmat 0xfc300850
14631#define B_MNEM_vfmab 0xfc300810
14632
14633/* Neon instruction encoder helpers. */
14634
14635/* Encodings for the different types for various Neon opcodes. */
14636
14637/* An "invalid" code for the following tables. */
14638#define N_INV -1u
14639
14640struct neon_tab_entry
14641{
14642 unsigned integer;
14643 unsigned float_or_poly;
14644 unsigned scalar_or_imm;
14645};
14646
14647/* Map overloaded Neon opcodes to their respective encodings. */
14648#define NEON_ENC_TAB \
14649 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14650 X(vabdl, 0x0800700, N_INV, N_INV), \
14651 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14652 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14653 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14654 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14655 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14656 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14657 X(vaddl, 0x0800000, N_INV, N_INV), \
14658 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14659 X(vsubl, 0x0800200, N_INV, N_INV), \
14660 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14661 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14662 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14663 /* Register variants of the following two instructions are encoded as
14664 vcge / vcgt with the operands reversed. */ \
14665 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14666 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14667 X(vfma, N_INV, 0x0000c10, N_INV), \
14668 X(vfms, N_INV, 0x0200c10, N_INV), \
14669 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14670 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14671 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14672 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14673 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14674 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14675 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14676 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14677 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14678 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14679 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14680 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14681 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14682 X(vshl, 0x0000400, N_INV, 0x0800510), \
14683 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14684 X(vand, 0x0000110, N_INV, 0x0800030), \
14685 X(vbic, 0x0100110, N_INV, 0x0800030), \
14686 X(veor, 0x1000110, N_INV, N_INV), \
14687 X(vorn, 0x0300110, N_INV, 0x0800010), \
14688 X(vorr, 0x0200110, N_INV, 0x0800010), \
14689 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14690 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14691 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14692 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14693 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14694 X(vst1, 0x0000000, 0x0800000, N_INV), \
14695 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14696 X(vst2, 0x0000100, 0x0800100, N_INV), \
14697 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14698 X(vst3, 0x0000200, 0x0800200, N_INV), \
14699 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14700 X(vst4, 0x0000300, 0x0800300, N_INV), \
14701 X(vmovn, 0x1b20200, N_INV, N_INV), \
14702 X(vtrn, 0x1b20080, N_INV, N_INV), \
14703 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14704 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14705 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14706 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14707 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14708 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14709 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14710 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14711 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14712 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14713 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14714 X(vseleq, 0xe000a00, N_INV, N_INV), \
14715 X(vselvs, 0xe100a00, N_INV, N_INV), \
14716 X(vselge, 0xe200a00, N_INV, N_INV), \
14717 X(vselgt, 0xe300a00, N_INV, N_INV), \
14718 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14719 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14720 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14721 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14722 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14723 X(aes, 0x3b00300, N_INV, N_INV), \
14724 X(sha3op, 0x2000c00, N_INV, N_INV), \
14725 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14726 X(sha2op, 0x3ba0380, N_INV, N_INV)
14727
14728enum neon_opc
14729{
14730#define X(OPC,I,F,S) N_MNEM_##OPC
14731NEON_ENC_TAB
14732#undef X
14733};
14734
14735static const struct neon_tab_entry neon_enc_tab[] =
14736{
14737#define X(OPC,I,F,S) { (I), (F), (S) }
14738NEON_ENC_TAB
14739#undef X
14740};
14741
14742/* Do not use these macros; instead, use NEON_ENCODE defined below. */
14743#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14744#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14745#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14746#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14747#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14748#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14749#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14750#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14751#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14752#define NEON_ENC_SINGLE_(X) \
14753 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14754#define NEON_ENC_DOUBLE_(X) \
14755 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14756#define NEON_ENC_FPV8_(X) \
14757 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14758
14759#define NEON_ENCODE(type, inst) \
14760 do \
14761 { \
14762 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14763 inst.is_neon = 1; \
14764 } \
14765 while (0)
14766
14767#define check_neon_suffixes \
14768 do \
14769 { \
14770 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14771 { \
14772 as_bad (_("invalid neon suffix for non neon instruction")); \
14773 return; \
14774 } \
14775 } \
14776 while (0)
14777
14778/* Define shapes for instruction operands. The following mnemonic characters
14779 are used in this table:
14780
14781 F - VFP S<n> register
14782 D - Neon D<n> register
14783 Q - Neon Q<n> register
14784 I - Immediate
14785 S - Scalar
14786 R - ARM register
14787 L - D<n> register list
14788
14789 This table is used to generate various data:
14790 - enumerations of the form NS_DDR to be used as arguments to
14791 neon_select_shape.
14792 - a table classifying shapes into single, double, quad, mixed.
14793 - a table used to drive neon_select_shape. */
14794
14795#define NEON_SHAPE_DEF \
14796 X(4, (R, R, Q, Q), QUAD), \
14797 X(4, (Q, R, R, I), QUAD), \
14798 X(4, (R, R, S, S), QUAD), \
14799 X(4, (S, S, R, R), QUAD), \
14800 X(3, (Q, R, I), QUAD), \
14801 X(3, (I, Q, Q), QUAD), \
14802 X(3, (I, Q, R), QUAD), \
14803 X(3, (R, Q, Q), QUAD), \
14804 X(3, (D, D, D), DOUBLE), \
14805 X(3, (Q, Q, Q), QUAD), \
14806 X(3, (D, D, I), DOUBLE), \
14807 X(3, (Q, Q, I), QUAD), \
14808 X(3, (D, D, S), DOUBLE), \
14809 X(3, (Q, Q, S), QUAD), \
14810 X(3, (Q, Q, R), QUAD), \
14811 X(3, (R, R, Q), QUAD), \
14812 X(2, (R, Q), QUAD), \
14813 X(2, (D, D), DOUBLE), \
14814 X(2, (Q, Q), QUAD), \
14815 X(2, (D, S), DOUBLE), \
14816 X(2, (Q, S), QUAD), \
14817 X(2, (D, R), DOUBLE), \
14818 X(2, (Q, R), QUAD), \
14819 X(2, (D, I), DOUBLE), \
14820 X(2, (Q, I), QUAD), \
14821 X(3, (P, F, I), SINGLE), \
14822 X(3, (P, D, I), DOUBLE), \
14823 X(3, (P, Q, I), QUAD), \
14824 X(4, (P, F, F, I), SINGLE), \
14825 X(4, (P, D, D, I), DOUBLE), \
14826 X(4, (P, Q, Q, I), QUAD), \
14827 X(5, (P, F, F, F, I), SINGLE), \
14828 X(5, (P, D, D, D, I), DOUBLE), \
14829 X(5, (P, Q, Q, Q, I), QUAD), \
14830 X(3, (D, L, D), DOUBLE), \
14831 X(2, (D, Q), MIXED), \
14832 X(2, (Q, D), MIXED), \
14833 X(3, (D, Q, I), MIXED), \
14834 X(3, (Q, D, I), MIXED), \
14835 X(3, (Q, D, D), MIXED), \
14836 X(3, (D, Q, Q), MIXED), \
14837 X(3, (Q, Q, D), MIXED), \
14838 X(3, (Q, D, S), MIXED), \
14839 X(3, (D, Q, S), MIXED), \
14840 X(4, (D, D, D, I), DOUBLE), \
14841 X(4, (Q, Q, Q, I), QUAD), \
14842 X(4, (D, D, S, I), DOUBLE), \
14843 X(4, (Q, Q, S, I), QUAD), \
14844 X(2, (F, F), SINGLE), \
14845 X(3, (F, F, F), SINGLE), \
14846 X(2, (F, I), SINGLE), \
14847 X(2, (F, D), MIXED), \
14848 X(2, (D, F), MIXED), \
14849 X(3, (F, F, I), MIXED), \
14850 X(4, (R, R, F, F), SINGLE), \
14851 X(4, (F, F, R, R), SINGLE), \
14852 X(3, (D, R, R), DOUBLE), \
14853 X(3, (R, R, D), DOUBLE), \
14854 X(2, (S, R), SINGLE), \
14855 X(2, (R, S), SINGLE), \
14856 X(2, (F, R), SINGLE), \
14857 X(2, (R, F), SINGLE), \
14858/* Used for MVE tail predicated loop instructions. */\
14859 X(2, (R, R), QUAD), \
14860/* Half float shape supported so far. */\
14861 X (2, (H, D), MIXED), \
14862 X (2, (D, H), MIXED), \
14863 X (2, (H, F), MIXED), \
14864 X (2, (F, H), MIXED), \
14865 X (2, (H, H), HALF), \
14866 X (2, (H, R), HALF), \
14867 X (2, (R, H), HALF), \
14868 X (2, (H, I), HALF), \
14869 X (3, (H, H, H), HALF), \
14870 X (3, (H, F, I), MIXED), \
14871 X (3, (F, H, I), MIXED), \
14872 X (3, (D, H, H), MIXED), \
14873 X (3, (D, H, S), MIXED)
14874
14875#define S2(A,B) NS_##A##B
14876#define S3(A,B,C) NS_##A##B##C
14877#define S4(A,B,C,D) NS_##A##B##C##D
14878#define S5(A,B,C,D,E) NS_##A##B##C##D##E
14879
14880#define X(N, L, C) S##N L
14881
14882enum neon_shape
14883{
14884 NEON_SHAPE_DEF,
14885 NS_NULL
14886};
14887
14888#undef X
14889#undef S2
14890#undef S3
14891#undef S4
14892#undef S5
14893
14894enum neon_shape_class
14895{
14896 SC_HALF,
14897 SC_SINGLE,
14898 SC_DOUBLE,
14899 SC_QUAD,
14900 SC_MIXED
14901};
14902
14903#define X(N, L, C) SC_##C
14904
14905static enum neon_shape_class neon_shape_class[] =
14906{
14907 NEON_SHAPE_DEF
14908};
14909
14910#undef X
14911
14912enum neon_shape_el
14913{
14914 SE_H,
14915 SE_F,
14916 SE_D,
14917 SE_Q,
14918 SE_I,
14919 SE_S,
14920 SE_R,
14921 SE_L,
14922 SE_P
14923};
14924
14925/* Register widths of above. */
14926static unsigned neon_shape_el_size[] =
14927{
14928 16,
14929 32,
14930 64,
14931 128,
14932 0,
14933 32,
14934 32,
14935 0,
14936 0
14937};
14938
14939struct neon_shape_info
14940{
14941 unsigned els;
14942 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
14943};
14944
14945#define S2(A,B) { SE_##A, SE_##B }
14946#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14947#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14948#define S5(A,B,C,D,E) { SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
14949
14950#define X(N, L, C) { N, S##N L }
14951
14952static struct neon_shape_info neon_shape_tab[] =
14953{
14954 NEON_SHAPE_DEF
14955};
14956
14957#undef X
14958#undef S2
14959#undef S3
14960#undef S4
14961#undef S5
14962
14963/* Bit masks used in type checking given instructions.
14964 'N_EQK' means the type must be the same as (or based on in some way) the key
14965 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14966 set, various other bits can be set as well in order to modify the meaning of
14967 the type constraint. */
14968
14969enum neon_type_mask
14970{
14971 N_S8 = 0x0000001,
14972 N_S16 = 0x0000002,
14973 N_S32 = 0x0000004,
14974 N_S64 = 0x0000008,
14975 N_U8 = 0x0000010,
14976 N_U16 = 0x0000020,
14977 N_U32 = 0x0000040,
14978 N_U64 = 0x0000080,
14979 N_I8 = 0x0000100,
14980 N_I16 = 0x0000200,
14981 N_I32 = 0x0000400,
14982 N_I64 = 0x0000800,
14983 N_8 = 0x0001000,
14984 N_16 = 0x0002000,
14985 N_32 = 0x0004000,
14986 N_64 = 0x0008000,
14987 N_P8 = 0x0010000,
14988 N_P16 = 0x0020000,
14989 N_F16 = 0x0040000,
14990 N_F32 = 0x0080000,
14991 N_F64 = 0x0100000,
14992 N_P64 = 0x0200000,
14993 N_BF16 = 0x0400000,
14994 N_KEY = 0x1000000, /* Key element (main type specifier). */
14995 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
14996 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
14997 N_UNT = 0x8000000, /* Must be explicitly untyped. */
14998 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
14999 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
15000 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
15001 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
15002 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
15003 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
15004 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
15005 N_UTYP = 0,
15006 N_MAX_NONSPECIAL = N_P64
15007};
15008
15009#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
15010
15011#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
15012#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15013#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
15014#define N_S_32 (N_S8 | N_S16 | N_S32)
15015#define N_F_16_32 (N_F16 | N_F32)
15016#define N_SUF_32 (N_SU_32 | N_F_16_32)
15017#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
15018#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
15019#define N_F_ALL (N_F16 | N_F32 | N_F64)
15020#define N_I_MVE (N_I8 | N_I16 | N_I32)
15021#define N_F_MVE (N_F16 | N_F32)
15022#define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15023
15024/* Pass this as the first type argument to neon_check_type to ignore types
15025 altogether. */
15026#define N_IGNORE_TYPE (N_KEY | N_EQK)
15027
15028/* Select a "shape" for the current instruction (describing register types or
15029 sizes) from a list of alternatives. Return NS_NULL if the current instruction
15030 doesn't fit. For non-polymorphic shapes, checking is usually done as a
15031 function of operand parsing, so this function doesn't need to be called.
15032 Shapes should be listed in order of decreasing length. */
15033
15034static enum neon_shape
15035neon_select_shape (enum neon_shape shape, ...)
15036{
15037 va_list ap;
15038 enum neon_shape first_shape = shape;
15039
15040 /* Fix missing optional operands. FIXME: we don't know at this point how
15041 many arguments we should have, so this makes the assumption that we have
15042 > 1. This is true of all current Neon opcodes, I think, but may not be
15043 true in the future. */
15044 if (!inst.operands[1].present)
15045 inst.operands[1] = inst.operands[0];
15046
15047 va_start (ap, shape);
15048
15049 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
15050 {
15051 unsigned j;
15052 int matches = 1;
15053
15054 for (j = 0; j < neon_shape_tab[shape].els; j++)
15055 {
15056 if (!inst.operands[j].present)
15057 {
15058 matches = 0;
15059 break;
15060 }
15061
15062 switch (neon_shape_tab[shape].el[j])
15063 {
15064 /* If a .f16, .16, .u16, .s16 type specifier is given over
15065 a VFP single precision register operand, it's essentially
15066 means only half of the register is used.
15067
15068 If the type specifier is given after the mnemonics, the
15069 information is stored in inst.vectype. If the type specifier
15070 is given after register operand, the information is stored
15071 in inst.operands[].vectype.
15072
15073 When there is only one type specifier, and all the register
15074 operands are the same type of hardware register, the type
15075 specifier applies to all register operands.
15076
15077 If no type specifier is given, the shape is inferred from
15078 operand information.
15079
15080 for example:
15081 vadd.f16 s0, s1, s2: NS_HHH
15082 vabs.f16 s0, s1: NS_HH
15083 vmov.f16 s0, r1: NS_HR
15084 vmov.f16 r0, s1: NS_RH
15085 vcvt.f16 r0, s1: NS_RH
15086 vcvt.f16.s32 s2, s2, #29: NS_HFI
15087 vcvt.f16.s32 s2, s2: NS_HF
15088 */
15089 case SE_H:
15090 if (!(inst.operands[j].isreg
15091 && inst.operands[j].isvec
15092 && inst.operands[j].issingle
15093 && !inst.operands[j].isquad
15094 && ((inst.vectype.elems == 1
15095 && inst.vectype.el[0].size == 16)
15096 || (inst.vectype.elems > 1
15097 && inst.vectype.el[j].size == 16)
15098 || (inst.vectype.elems == 0
15099 && inst.operands[j].vectype.type != NT_invtype
15100 && inst.operands[j].vectype.size == 16))))
15101 matches = 0;
15102 break;
15103
15104 case SE_F:
15105 if (!(inst.operands[j].isreg
15106 && inst.operands[j].isvec
15107 && inst.operands[j].issingle
15108 && !inst.operands[j].isquad
15109 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
15110 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
15111 || (inst.vectype.elems == 0
15112 && (inst.operands[j].vectype.size == 32
15113 || inst.operands[j].vectype.type == NT_invtype)))))
15114 matches = 0;
15115 break;
15116
15117 case SE_D:
15118 if (!(inst.operands[j].isreg
15119 && inst.operands[j].isvec
15120 && !inst.operands[j].isquad
15121 && !inst.operands[j].issingle))
15122 matches = 0;
15123 break;
15124
15125 case SE_R:
15126 if (!(inst.operands[j].isreg
15127 && !inst.operands[j].isvec))
15128 matches = 0;
15129 break;
15130
15131 case SE_Q:
15132 if (!(inst.operands[j].isreg
15133 && inst.operands[j].isvec
15134 && inst.operands[j].isquad
15135 && !inst.operands[j].issingle))
15136 matches = 0;
15137 break;
15138
15139 case SE_I:
15140 if (!(!inst.operands[j].isreg
15141 && !inst.operands[j].isscalar))
15142 matches = 0;
15143 break;
15144
15145 case SE_S:
15146 if (!(!inst.operands[j].isreg
15147 && inst.operands[j].isscalar))
15148 matches = 0;
15149 break;
15150
15151 case SE_P:
15152 case SE_L:
15153 break;
15154 }
15155 if (!matches)
15156 break;
15157 }
15158 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
15159 /* We've matched all the entries in the shape table, and we don't
15160 have any left over operands which have not been matched. */
15161 break;
15162 }
15163
15164 va_end (ap);
15165
15166 if (shape == NS_NULL && first_shape != NS_NULL)
15167 first_error (_("invalid instruction shape"));
15168
15169 return shape;
15170}
15171
15172/* True if SHAPE is predominantly a quadword operation (most of the time, this
15173 means the Q bit should be set). */
15174
15175static int
15176neon_quad (enum neon_shape shape)
15177{
15178 return neon_shape_class[shape] == SC_QUAD;
15179}
15180
15181static void
15182neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
15183 unsigned *g_size)
15184{
15185 /* Allow modification to be made to types which are constrained to be
15186 based on the key element, based on bits set alongside N_EQK. */
15187 if ((typebits & N_EQK) != 0)
15188 {
15189 if ((typebits & N_HLF) != 0)
15190 *g_size /= 2;
15191 else if ((typebits & N_DBL) != 0)
15192 *g_size *= 2;
15193 if ((typebits & N_SGN) != 0)
15194 *g_type = NT_signed;
15195 else if ((typebits & N_UNS) != 0)
15196 *g_type = NT_unsigned;
15197 else if ((typebits & N_INT) != 0)
15198 *g_type = NT_integer;
15199 else if ((typebits & N_FLT) != 0)
15200 *g_type = NT_float;
15201 else if ((typebits & N_SIZ) != 0)
15202 *g_type = NT_untyped;
15203 }
15204}
15205
15206/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15207 operand type, i.e. the single type specified in a Neon instruction when it
15208 is the only one given. */
15209
15210static struct neon_type_el
15211neon_type_promote (struct neon_type_el *key, unsigned thisarg)
15212{
15213 struct neon_type_el dest = *key;
15214
15215 gas_assert ((thisarg & N_EQK) != 0);
15216
15217 neon_modify_type_size (thisarg, &dest.type, &dest.size);
15218
15219 return dest;
15220}
15221
15222/* Convert Neon type and size into compact bitmask representation. */
15223
15224static enum neon_type_mask
15225type_chk_of_el_type (enum neon_el_type type, unsigned size)
15226{
15227 switch (type)
15228 {
15229 case NT_untyped:
15230 switch (size)
15231 {
15232 case 8: return N_8;
15233 case 16: return N_16;
15234 case 32: return N_32;
15235 case 64: return N_64;
15236 default: ;
15237 }
15238 break;
15239
15240 case NT_integer:
15241 switch (size)
15242 {
15243 case 8: return N_I8;
15244 case 16: return N_I16;
15245 case 32: return N_I32;
15246 case 64: return N_I64;
15247 default: ;
15248 }
15249 break;
15250
15251 case NT_float:
15252 switch (size)
15253 {
15254 case 16: return N_F16;
15255 case 32: return N_F32;
15256 case 64: return N_F64;
15257 default: ;
15258 }
15259 break;
15260
15261 case NT_poly:
15262 switch (size)
15263 {
15264 case 8: return N_P8;
15265 case 16: return N_P16;
15266 case 64: return N_P64;
15267 default: ;
15268 }
15269 break;
15270
15271 case NT_signed:
15272 switch (size)
15273 {
15274 case 8: return N_S8;
15275 case 16: return N_S16;
15276 case 32: return N_S32;
15277 case 64: return N_S64;
15278 default: ;
15279 }
15280 break;
15281
15282 case NT_unsigned:
15283 switch (size)
15284 {
15285 case 8: return N_U8;
15286 case 16: return N_U16;
15287 case 32: return N_U32;
15288 case 64: return N_U64;
15289 default: ;
15290 }
15291 break;
15292
15293 case NT_bfloat:
15294 if (size == 16) return N_BF16;
15295 break;
15296
15297 default: ;
15298 }
15299
15300 return N_UTYP;
15301}
15302
15303/* Convert compact Neon bitmask type representation to a type and size. Only
15304 handles the case where a single bit is set in the mask. */
15305
15306static int
15307el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
15308 enum neon_type_mask mask)
15309{
15310 if ((mask & N_EQK) != 0)
15311 return FAIL;
15312
15313 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
15314 *size = 8;
15315 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16 | N_BF16))
15316 != 0)
15317 *size = 16;
15318 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
15319 *size = 32;
15320 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
15321 *size = 64;
15322 else
15323 return FAIL;
15324
15325 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
15326 *type = NT_signed;
15327 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
15328 *type = NT_unsigned;
15329 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
15330 *type = NT_integer;
15331 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
15332 *type = NT_untyped;
15333 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
15334 *type = NT_poly;
15335 else if ((mask & (N_F_ALL)) != 0)
15336 *type = NT_float;
15337 else if ((mask & (N_BF16)) != 0)
15338 *type = NT_bfloat;
15339 else
15340 return FAIL;
15341
15342 return SUCCESS;
15343}
15344
15345/* Modify a bitmask of allowed types. This is only needed for type
15346 relaxation. */
15347
15348static unsigned
15349modify_types_allowed (unsigned allowed, unsigned mods)
15350{
15351 unsigned size;
15352 enum neon_el_type type;
15353 unsigned destmask;
15354 int i;
15355
15356 destmask = 0;
15357
15358 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
15359 {
15360 if (el_type_of_type_chk (&type, &size,
15361 (enum neon_type_mask) (allowed & i)) == SUCCESS)
15362 {
15363 neon_modify_type_size (mods, &type, &size);
15364 destmask |= type_chk_of_el_type (type, size);
15365 }
15366 }
15367
15368 return destmask;
15369}
15370
15371/* Check type and return type classification.
15372 The manual states (paraphrase): If one datatype is given, it indicates the
15373 type given in:
15374 - the second operand, if there is one
15375 - the operand, if there is no second operand
15376 - the result, if there are no operands.
15377 This isn't quite good enough though, so we use a concept of a "key" datatype
15378 which is set on a per-instruction basis, which is the one which matters when
15379 only one data type is written.
15380 Note: this function has side-effects (e.g. filling in missing operands). All
15381 Neon instructions should call it before performing bit encoding. */
15382
15383static struct neon_type_el
15384neon_check_type (unsigned els, enum neon_shape ns, ...)
15385{
15386 va_list ap;
15387 unsigned i, pass, key_el = 0;
15388 unsigned types[NEON_MAX_TYPE_ELS];
15389 enum neon_el_type k_type = NT_invtype;
15390 unsigned k_size = -1u;
15391 struct neon_type_el badtype = {NT_invtype, -1};
15392 unsigned key_allowed = 0;
15393
15394 /* Optional registers in Neon instructions are always (not) in operand 1.
15395 Fill in the missing operand here, if it was omitted. */
15396 if (els > 1 && !inst.operands[1].present)
15397 inst.operands[1] = inst.operands[0];
15398
15399 /* Suck up all the varargs. */
15400 va_start (ap, ns);
15401 for (i = 0; i < els; i++)
15402 {
15403 unsigned thisarg = va_arg (ap, unsigned);
15404 if (thisarg == N_IGNORE_TYPE)
15405 {
15406 va_end (ap);
15407 return badtype;
15408 }
15409 types[i] = thisarg;
15410 if ((thisarg & N_KEY) != 0)
15411 key_el = i;
15412 }
15413 va_end (ap);
15414
15415 if (inst.vectype.elems > 0)
15416 for (i = 0; i < els; i++)
15417 if (inst.operands[i].vectype.type != NT_invtype)
15418 {
15419 first_error (_("types specified in both the mnemonic and operands"));
15420 return badtype;
15421 }
15422
15423 /* Duplicate inst.vectype elements here as necessary.
15424 FIXME: No idea if this is exactly the same as the ARM assembler,
15425 particularly when an insn takes one register and one non-register
15426 operand. */
15427 if (inst.vectype.elems == 1 && els > 1)
15428 {
15429 unsigned j;
15430 inst.vectype.elems = els;
15431 inst.vectype.el[key_el] = inst.vectype.el[0];
15432 for (j = 0; j < els; j++)
15433 if (j != key_el)
15434 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15435 types[j]);
15436 }
15437 else if (inst.vectype.elems == 0 && els > 0)
15438 {
15439 unsigned j;
15440 /* No types were given after the mnemonic, so look for types specified
15441 after each operand. We allow some flexibility here; as long as the
15442 "key" operand has a type, we can infer the others. */
15443 for (j = 0; j < els; j++)
15444 if (inst.operands[j].vectype.type != NT_invtype)
15445 inst.vectype.el[j] = inst.operands[j].vectype;
15446
15447 if (inst.operands[key_el].vectype.type != NT_invtype)
15448 {
15449 for (j = 0; j < els; j++)
15450 if (inst.operands[j].vectype.type == NT_invtype)
15451 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15452 types[j]);
15453 }
15454 else
15455 {
15456 first_error (_("operand types can't be inferred"));
15457 return badtype;
15458 }
15459 }
15460 else if (inst.vectype.elems != els)
15461 {
15462 first_error (_("type specifier has the wrong number of parts"));
15463 return badtype;
15464 }
15465
15466 for (pass = 0; pass < 2; pass++)
15467 {
15468 for (i = 0; i < els; i++)
15469 {
15470 unsigned thisarg = types[i];
15471 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
15472 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
15473 enum neon_el_type g_type = inst.vectype.el[i].type;
15474 unsigned g_size = inst.vectype.el[i].size;
15475
15476 /* Decay more-specific signed & unsigned types to sign-insensitive
15477 integer types if sign-specific variants are unavailable. */
15478 if ((g_type == NT_signed || g_type == NT_unsigned)
15479 && (types_allowed & N_SU_ALL) == 0)
15480 g_type = NT_integer;
15481
15482 /* If only untyped args are allowed, decay any more specific types to
15483 them. Some instructions only care about signs for some element
15484 sizes, so handle that properly. */
15485 if (((types_allowed & N_UNT) == 0)
15486 && ((g_size == 8 && (types_allowed & N_8) != 0)
15487 || (g_size == 16 && (types_allowed & N_16) != 0)
15488 || (g_size == 32 && (types_allowed & N_32) != 0)
15489 || (g_size == 64 && (types_allowed & N_64) != 0)))
15490 g_type = NT_untyped;
15491
15492 if (pass == 0)
15493 {
15494 if ((thisarg & N_KEY) != 0)
15495 {
15496 k_type = g_type;
15497 k_size = g_size;
15498 key_allowed = thisarg & ~N_KEY;
15499
15500 /* Check architecture constraint on FP16 extension. */
15501 if (k_size == 16
15502 && k_type == NT_float
15503 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15504 {
15505 inst.error = _(BAD_FP16);
15506 return badtype;
15507 }
15508 }
15509 }
15510 else
15511 {
15512 if ((thisarg & N_VFP) != 0)
15513 {
15514 enum neon_shape_el regshape;
15515 unsigned regwidth, match;
15516
15517 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15518 if (ns == NS_NULL)
15519 {
15520 first_error (_("invalid instruction shape"));
15521 return badtype;
15522 }
15523 regshape = neon_shape_tab[ns].el[i];
15524 regwidth = neon_shape_el_size[regshape];
15525
15526 /* In VFP mode, operands must match register widths. If we
15527 have a key operand, use its width, else use the width of
15528 the current operand. */
15529 if (k_size != -1u)
15530 match = k_size;
15531 else
15532 match = g_size;
15533
15534 /* FP16 will use a single precision register. */
15535 if (regwidth == 32 && match == 16)
15536 {
15537 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15538 match = regwidth;
15539 else
15540 {
15541 inst.error = _(BAD_FP16);
15542 return badtype;
15543 }
15544 }
15545
15546 if (regwidth != match)
15547 {
15548 first_error (_("operand size must match register width"));
15549 return badtype;
15550 }
15551 }
15552
15553 if ((thisarg & N_EQK) == 0)
15554 {
15555 unsigned given_type = type_chk_of_el_type (g_type, g_size);
15556
15557 if ((given_type & types_allowed) == 0)
15558 {
15559 first_error (BAD_SIMD_TYPE);
15560 return badtype;
15561 }
15562 }
15563 else
15564 {
15565 enum neon_el_type mod_k_type = k_type;
15566 unsigned mod_k_size = k_size;
15567 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
15568 if (g_type != mod_k_type || g_size != mod_k_size)
15569 {
15570 first_error (_("inconsistent types in Neon instruction"));
15571 return badtype;
15572 }
15573 }
15574 }
15575 }
15576 }
15577
15578 return inst.vectype.el[key_el];
15579}
15580
15581/* Neon-style VFP instruction forwarding. */
15582
15583/* Thumb VFP instructions have 0xE in the condition field. */
15584
15585static void
15586do_vfp_cond_or_thumb (void)
15587{
15588 inst.is_neon = 1;
15589
15590 if (thumb_mode)
15591 inst.instruction |= 0xe0000000;
15592 else
15593 inst.instruction |= inst.cond << 28;
15594}
15595
15596/* Look up and encode a simple mnemonic, for use as a helper function for the
15597 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15598 etc. It is assumed that operand parsing has already been done, and that the
15599 operands are in the form expected by the given opcode (this isn't necessarily
15600 the same as the form in which they were parsed, hence some massaging must
15601 take place before this function is called).
15602 Checks current arch version against that in the looked-up opcode. */
15603
15604static void
15605do_vfp_nsyn_opcode (const char *opname)
15606{
15607 const struct asm_opcode *opcode;
15608
15609 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
15610
15611 if (!opcode)
15612 abort ();
15613
15614 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
15615 thumb_mode ? *opcode->tvariant : *opcode->avariant),
15616 _(BAD_FPU));
15617
15618 inst.is_neon = 1;
15619
15620 if (thumb_mode)
15621 {
15622 inst.instruction = opcode->tvalue;
15623 opcode->tencode ();
15624 }
15625 else
15626 {
15627 inst.instruction = (inst.cond << 28) | opcode->avalue;
15628 opcode->aencode ();
15629 }
15630}
15631
15632static void
15633do_vfp_nsyn_add_sub (enum neon_shape rs)
15634{
15635 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15636
15637 if (rs == NS_FFF || rs == NS_HHH)
15638 {
15639 if (is_add)
15640 do_vfp_nsyn_opcode ("fadds");
15641 else
15642 do_vfp_nsyn_opcode ("fsubs");
15643
15644 /* ARMv8.2 fp16 instruction. */
15645 if (rs == NS_HHH)
15646 do_scalar_fp16_v82_encode ();
15647 }
15648 else
15649 {
15650 if (is_add)
15651 do_vfp_nsyn_opcode ("faddd");
15652 else
15653 do_vfp_nsyn_opcode ("fsubd");
15654 }
15655}
15656
15657/* Check operand types to see if this is a VFP instruction, and if so call
15658 PFN (). */
15659
15660static int
15661try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
15662{
15663 enum neon_shape rs;
15664 struct neon_type_el et;
15665
15666 switch (args)
15667 {
15668 case 2:
15669 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15670 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15671 break;
15672
15673 case 3:
15674 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15675 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15676 N_F_ALL | N_KEY | N_VFP);
15677 break;
15678
15679 default:
15680 abort ();
15681 }
15682
15683 if (et.type != NT_invtype)
15684 {
15685 pfn (rs);
15686 return SUCCESS;
15687 }
15688
15689 inst.error = NULL;
15690 return FAIL;
15691}
15692
15693static void
15694do_vfp_nsyn_mla_mls (enum neon_shape rs)
15695{
15696 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
15697
15698 if (rs == NS_FFF || rs == NS_HHH)
15699 {
15700 if (is_mla)
15701 do_vfp_nsyn_opcode ("fmacs");
15702 else
15703 do_vfp_nsyn_opcode ("fnmacs");
15704
15705 /* ARMv8.2 fp16 instruction. */
15706 if (rs == NS_HHH)
15707 do_scalar_fp16_v82_encode ();
15708 }
15709 else
15710 {
15711 if (is_mla)
15712 do_vfp_nsyn_opcode ("fmacd");
15713 else
15714 do_vfp_nsyn_opcode ("fnmacd");
15715 }
15716}
15717
15718static void
15719do_vfp_nsyn_fma_fms (enum neon_shape rs)
15720{
15721 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15722
15723 if (rs == NS_FFF || rs == NS_HHH)
15724 {
15725 if (is_fma)
15726 do_vfp_nsyn_opcode ("ffmas");
15727 else
15728 do_vfp_nsyn_opcode ("ffnmas");
15729
15730 /* ARMv8.2 fp16 instruction. */
15731 if (rs == NS_HHH)
15732 do_scalar_fp16_v82_encode ();
15733 }
15734 else
15735 {
15736 if (is_fma)
15737 do_vfp_nsyn_opcode ("ffmad");
15738 else
15739 do_vfp_nsyn_opcode ("ffnmad");
15740 }
15741}
15742
15743static void
15744do_vfp_nsyn_mul (enum neon_shape rs)
15745{
15746 if (rs == NS_FFF || rs == NS_HHH)
15747 {
15748 do_vfp_nsyn_opcode ("fmuls");
15749
15750 /* ARMv8.2 fp16 instruction. */
15751 if (rs == NS_HHH)
15752 do_scalar_fp16_v82_encode ();
15753 }
15754 else
15755 do_vfp_nsyn_opcode ("fmuld");
15756}
15757
15758static void
15759do_vfp_nsyn_abs_neg (enum neon_shape rs)
15760{
15761 int is_neg = (inst.instruction & 0x80) != 0;
15762 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
15763
15764 if (rs == NS_FF || rs == NS_HH)
15765 {
15766 if (is_neg)
15767 do_vfp_nsyn_opcode ("fnegs");
15768 else
15769 do_vfp_nsyn_opcode ("fabss");
15770
15771 /* ARMv8.2 fp16 instruction. */
15772 if (rs == NS_HH)
15773 do_scalar_fp16_v82_encode ();
15774 }
15775 else
15776 {
15777 if (is_neg)
15778 do_vfp_nsyn_opcode ("fnegd");
15779 else
15780 do_vfp_nsyn_opcode ("fabsd");
15781 }
15782}
15783
15784/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15785 insns belong to Neon, and are handled elsewhere. */
15786
15787static void
15788do_vfp_nsyn_ldm_stm (int is_dbmode)
15789{
15790 int is_ldm = (inst.instruction & (1 << 20)) != 0;
15791 if (is_ldm)
15792 {
15793 if (is_dbmode)
15794 do_vfp_nsyn_opcode ("fldmdbs");
15795 else
15796 do_vfp_nsyn_opcode ("fldmias");
15797 }
15798 else
15799 {
15800 if (is_dbmode)
15801 do_vfp_nsyn_opcode ("fstmdbs");
15802 else
15803 do_vfp_nsyn_opcode ("fstmias");
15804 }
15805}
15806
15807static void
15808do_vfp_nsyn_sqrt (void)
15809{
15810 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15811 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15812
15813 if (rs == NS_FF || rs == NS_HH)
15814 {
15815 do_vfp_nsyn_opcode ("fsqrts");
15816
15817 /* ARMv8.2 fp16 instruction. */
15818 if (rs == NS_HH)
15819 do_scalar_fp16_v82_encode ();
15820 }
15821 else
15822 do_vfp_nsyn_opcode ("fsqrtd");
15823}
15824
15825static void
15826do_vfp_nsyn_div (void)
15827{
15828 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15829 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15830 N_F_ALL | N_KEY | N_VFP);
15831
15832 if (rs == NS_FFF || rs == NS_HHH)
15833 {
15834 do_vfp_nsyn_opcode ("fdivs");
15835
15836 /* ARMv8.2 fp16 instruction. */
15837 if (rs == NS_HHH)
15838 do_scalar_fp16_v82_encode ();
15839 }
15840 else
15841 do_vfp_nsyn_opcode ("fdivd");
15842}
15843
15844static void
15845do_vfp_nsyn_nmul (void)
15846{
15847 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15848 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15849 N_F_ALL | N_KEY | N_VFP);
15850
15851 if (rs == NS_FFF || rs == NS_HHH)
15852 {
15853 NEON_ENCODE (SINGLE, inst);
15854 do_vfp_sp_dyadic ();
15855
15856 /* ARMv8.2 fp16 instruction. */
15857 if (rs == NS_HHH)
15858 do_scalar_fp16_v82_encode ();
15859 }
15860 else
15861 {
15862 NEON_ENCODE (DOUBLE, inst);
15863 do_vfp_dp_rd_rn_rm ();
15864 }
15865 do_vfp_cond_or_thumb ();
15866
15867}
15868
15869/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15870 (0, 1, 2, 3). */
15871
15872static unsigned
15873neon_logbits (unsigned x)
15874{
15875 return ffs (x) - 4;
15876}
15877
15878#define LOW4(R) ((R) & 0xf)
15879#define HI1(R) (((R) >> 4) & 1)
15880#define LOW1(R) ((R) & 0x1)
15881#define HI4(R) (((R) >> 1) & 0xf)
15882
15883static unsigned
15884mve_get_vcmp_vpt_cond (struct neon_type_el et)
15885{
15886 switch (et.type)
15887 {
15888 default:
15889 first_error (BAD_EL_TYPE);
15890 return 0;
15891 case NT_float:
15892 switch (inst.operands[0].imm)
15893 {
15894 default:
15895 first_error (_("invalid condition"));
15896 return 0;
15897 case 0x0:
15898 /* eq. */
15899 return 0;
15900 case 0x1:
15901 /* ne. */
15902 return 1;
15903 case 0xa:
15904 /* ge/ */
15905 return 4;
15906 case 0xb:
15907 /* lt. */
15908 return 5;
15909 case 0xc:
15910 /* gt. */
15911 return 6;
15912 case 0xd:
15913 /* le. */
15914 return 7;
15915 }
15916 case NT_integer:
15917 /* only accept eq and ne. */
15918 if (inst.operands[0].imm > 1)
15919 {
15920 first_error (_("invalid condition"));
15921 return 0;
15922 }
15923 return inst.operands[0].imm;
15924 case NT_unsigned:
15925 if (inst.operands[0].imm == 0x2)
15926 return 2;
15927 else if (inst.operands[0].imm == 0x8)
15928 return 3;
15929 else
15930 {
15931 first_error (_("invalid condition"));
15932 return 0;
15933 }
15934 case NT_signed:
15935 switch (inst.operands[0].imm)
15936 {
15937 default:
15938 first_error (_("invalid condition"));
15939 return 0;
15940 case 0xa:
15941 /* ge. */
15942 return 4;
15943 case 0xb:
15944 /* lt. */
15945 return 5;
15946 case 0xc:
15947 /* gt. */
15948 return 6;
15949 case 0xd:
15950 /* le. */
15951 return 7;
15952 }
15953 }
15954 /* Should be unreachable. */
15955 abort ();
15956}
15957
15958/* For VCTP (create vector tail predicate) in MVE. */
15959static void
15960do_mve_vctp (void)
15961{
15962 int dt = 0;
15963 unsigned size = 0x0;
15964
15965 if (inst.cond > COND_ALWAYS)
15966 inst.pred_insn_type = INSIDE_VPT_INSN;
15967 else
15968 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15969
15970 /* This is a typical MVE instruction which has no type but have size 8, 16,
15971 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15972 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15973 if ((inst.operands[0].present) && (inst.vectype.el[0].type == NT_untyped))
15974 dt = inst.vectype.el[0].size;
15975
15976 /* Setting this does not indicate an actual NEON instruction, but only
15977 indicates that the mnemonic accepts neon-style type suffixes. */
15978 inst.is_neon = 1;
15979
15980 switch (dt)
15981 {
15982 case 8:
15983 break;
15984 case 16:
15985 size = 0x1; break;
15986 case 32:
15987 size = 0x2; break;
15988 case 64:
15989 size = 0x3; break;
15990 default:
15991 first_error (_("Type is not allowed for this instruction"));
15992 }
15993 inst.instruction |= size << 20;
15994 inst.instruction |= inst.operands[0].reg << 16;
15995}
15996
15997static void
15998do_mve_vpt (void)
15999{
16000 /* We are dealing with a vector predicated block. */
16001 if (inst.operands[0].present)
16002 {
16003 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
16004 struct neon_type_el et
16005 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
16006 N_EQK);
16007
16008 unsigned fcond = mve_get_vcmp_vpt_cond (et);
16009
16010 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
16011
16012 if (et.type == NT_invtype)
16013 return;
16014
16015 if (et.type == NT_float)
16016 {
16017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
16018 BAD_FPU);
16019 constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE);
16020 inst.instruction |= (et.size == 16) << 28;
16021 inst.instruction |= 0x3 << 20;
16022 }
16023 else
16024 {
16025 constraint (et.size != 8 && et.size != 16 && et.size != 32,
16026 BAD_EL_TYPE);
16027 inst.instruction |= 1 << 28;
16028 inst.instruction |= neon_logbits (et.size) << 20;
16029 }
16030
16031 if (inst.operands[2].isquad)
16032 {
16033 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16034 inst.instruction |= LOW4 (inst.operands[2].reg);
16035 inst.instruction |= (fcond & 0x2) >> 1;
16036 }
16037 else
16038 {
16039 if (inst.operands[2].reg == REG_SP)
16040 as_tsktsk (MVE_BAD_SP);
16041 inst.instruction |= 1 << 6;
16042 inst.instruction |= (fcond & 0x2) << 4;
16043 inst.instruction |= inst.operands[2].reg;
16044 }
16045 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16046 inst.instruction |= (fcond & 0x4) << 10;
16047 inst.instruction |= (fcond & 0x1) << 7;
16048
16049 }
16050 set_pred_insn_type (VPT_INSN);
16051 now_pred.cc = 0;
16052 now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
16053 | ((inst.instruction & 0xe000) >> 13);
16054 now_pred.warn_deprecated = FALSE;
16055 now_pred.type = VECTOR_PRED;
16056 inst.is_neon = 1;
16057}
16058
16059static void
16060do_mve_vcmp (void)
16061{
16062 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
16063 if (!inst.operands[1].isreg || !inst.operands[1].isquad)
16064 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
16065 if (!inst.operands[2].present)
16066 first_error (_("MVE vector or ARM register expected"));
16067 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
16068
16069 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16070 if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
16071 && inst.operands[1].isquad)
16072 {
16073 inst.instruction = N_MNEM_vcmp;
16074 inst.cond = 0x10;
16075 }
16076
16077 if (inst.cond > COND_ALWAYS)
16078 inst.pred_insn_type = INSIDE_VPT_INSN;
16079 else
16080 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16081
16082 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
16083 struct neon_type_el et
16084 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
16085 N_EQK);
16086
16087 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
16088 && !inst.operands[2].iszr, BAD_PC);
16089
16090 unsigned fcond = mve_get_vcmp_vpt_cond (et);
16091
16092 inst.instruction = 0xee010f00;
16093 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16094 inst.instruction |= (fcond & 0x4) << 10;
16095 inst.instruction |= (fcond & 0x1) << 7;
16096 if (et.type == NT_float)
16097 {
16098 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
16099 BAD_FPU);
16100 inst.instruction |= (et.size == 16) << 28;
16101 inst.instruction |= 0x3 << 20;
16102 }
16103 else
16104 {
16105 inst.instruction |= 1 << 28;
16106 inst.instruction |= neon_logbits (et.size) << 20;
16107 }
16108 if (inst.operands[2].isquad)
16109 {
16110 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16111 inst.instruction |= (fcond & 0x2) >> 1;
16112 inst.instruction |= LOW4 (inst.operands[2].reg);
16113 }
16114 else
16115 {
16116 if (inst.operands[2].reg == REG_SP)
16117 as_tsktsk (MVE_BAD_SP);
16118 inst.instruction |= 1 << 6;
16119 inst.instruction |= (fcond & 0x2) << 4;
16120 inst.instruction |= inst.operands[2].reg;
16121 }
16122
16123 inst.is_neon = 1;
16124 return;
16125}
16126
16127static void
16128do_mve_vmaxa_vmina (void)
16129{
16130 if (inst.cond > COND_ALWAYS)
16131 inst.pred_insn_type = INSIDE_VPT_INSN;
16132 else
16133 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16134
16135 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
16136 struct neon_type_el et
16137 = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
16138
16139 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16140 inst.instruction |= neon_logbits (et.size) << 18;
16141 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16142 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16143 inst.instruction |= LOW4 (inst.operands[1].reg);
16144 inst.is_neon = 1;
16145}
16146
16147static void
16148do_mve_vfmas (void)
16149{
16150 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
16151 struct neon_type_el et
16152 = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK);
16153
16154 if (inst.cond > COND_ALWAYS)
16155 inst.pred_insn_type = INSIDE_VPT_INSN;
16156 else
16157 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16158
16159 if (inst.operands[2].reg == REG_SP)
16160 as_tsktsk (MVE_BAD_SP);
16161 else if (inst.operands[2].reg == REG_PC)
16162 as_tsktsk (MVE_BAD_PC);
16163
16164 inst.instruction |= (et.size == 16) << 28;
16165 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16166 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16167 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16168 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16169 inst.instruction |= inst.operands[2].reg;
16170 inst.is_neon = 1;
16171}
16172
16173static void
16174do_mve_viddup (void)
16175{
16176 if (inst.cond > COND_ALWAYS)
16177 inst.pred_insn_type = INSIDE_VPT_INSN;
16178 else
16179 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16180
16181 unsigned imm = inst.relocs[0].exp.X_add_number;
16182 constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
16183 _("immediate must be either 1, 2, 4 or 8"));
16184
16185 enum neon_shape rs;
16186 struct neon_type_el et;
16187 unsigned Rm;
16188 if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
16189 {
16190 rs = neon_select_shape (NS_QRI, NS_NULL);
16191 et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
16192 Rm = 7;
16193 }
16194 else
16195 {
16196 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
16197 if (inst.operands[2].reg == REG_SP)
16198 as_tsktsk (MVE_BAD_SP);
16199 else if (inst.operands[2].reg == REG_PC)
16200 first_error (BAD_PC);
16201
16202 rs = neon_select_shape (NS_QRRI, NS_NULL);
16203 et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
16204 Rm = inst.operands[2].reg >> 1;
16205 }
16206 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16207 inst.instruction |= neon_logbits (et.size) << 20;
16208 inst.instruction |= inst.operands[1].reg << 16;
16209 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16210 inst.instruction |= (imm > 2) << 7;
16211 inst.instruction |= Rm << 1;
16212 inst.instruction |= (imm == 2 || imm == 8);
16213 inst.is_neon = 1;
16214}
16215
16216static void
16217do_mve_vmlas (void)
16218{
16219 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
16220 struct neon_type_el et
16221 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16222
16223 if (inst.operands[2].reg == REG_PC)
16224 as_tsktsk (MVE_BAD_PC);
16225 else if (inst.operands[2].reg == REG_SP)
16226 as_tsktsk (MVE_BAD_SP);
16227
16228 if (inst.cond > COND_ALWAYS)
16229 inst.pred_insn_type = INSIDE_VPT_INSN;
16230 else
16231 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16232
16233 inst.instruction |= (et.type == NT_unsigned) << 28;
16234 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16235 inst.instruction |= neon_logbits (et.size) << 20;
16236 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16237 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16238 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16239 inst.instruction |= inst.operands[2].reg;
16240 inst.is_neon = 1;
16241}
16242
16243static void
16244do_mve_vshll (void)
16245{
16246 struct neon_type_el et
16247 = neon_check_type (2, NS_QQI, N_EQK, N_S8 | N_U8 | N_S16 | N_U16 | N_KEY);
16248
16249 if (inst.cond > COND_ALWAYS)
16250 inst.pred_insn_type = INSIDE_VPT_INSN;
16251 else
16252 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16253
16254 int imm = inst.operands[2].imm;
16255 constraint (imm < 1 || (unsigned)imm > et.size,
16256 _("immediate value out of range"));
16257
16258 if ((unsigned)imm == et.size)
16259 {
16260 inst.instruction |= neon_logbits (et.size) << 18;
16261 inst.instruction |= 0x110001;
16262 }
16263 else
16264 {
16265 inst.instruction |= (et.size + imm) << 16;
16266 inst.instruction |= 0x800140;
16267 }
16268
16269 inst.instruction |= (et.type == NT_unsigned) << 28;
16270 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16271 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16272 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16273 inst.instruction |= LOW4 (inst.operands[1].reg);
16274 inst.is_neon = 1;
16275}
16276
16277static void
16278do_mve_vshlc (void)
16279{
16280 if (inst.cond > COND_ALWAYS)
16281 inst.pred_insn_type = INSIDE_VPT_INSN;
16282 else
16283 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16284
16285 if (inst.operands[1].reg == REG_PC)
16286 as_tsktsk (MVE_BAD_PC);
16287 else if (inst.operands[1].reg == REG_SP)
16288 as_tsktsk (MVE_BAD_SP);
16289
16290 int imm = inst.operands[2].imm;
16291 constraint (imm < 1 || imm > 32, _("immediate value out of range"));
16292
16293 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16294 inst.instruction |= (imm & 0x1f) << 16;
16295 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16296 inst.instruction |= inst.operands[1].reg;
16297 inst.is_neon = 1;
16298}
16299
16300static void
16301do_mve_vshrn (void)
16302{
16303 unsigned types;
16304 switch (inst.instruction)
16305 {
16306 case M_MNEM_vshrnt:
16307 case M_MNEM_vshrnb:
16308 case M_MNEM_vrshrnt:
16309 case M_MNEM_vrshrnb:
16310 types = N_I16 | N_I32;
16311 break;
16312 case M_MNEM_vqshrnt:
16313 case M_MNEM_vqshrnb:
16314 case M_MNEM_vqrshrnt:
16315 case M_MNEM_vqrshrnb:
16316 types = N_U16 | N_U32 | N_S16 | N_S32;
16317 break;
16318 case M_MNEM_vqshrunt:
16319 case M_MNEM_vqshrunb:
16320 case M_MNEM_vqrshrunt:
16321 case M_MNEM_vqrshrunb:
16322 types = N_S16 | N_S32;
16323 break;
16324 default:
16325 abort ();
16326 }
16327
16328 struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY);
16329
16330 if (inst.cond > COND_ALWAYS)
16331 inst.pred_insn_type = INSIDE_VPT_INSN;
16332 else
16333 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16334
16335 unsigned Qd = inst.operands[0].reg;
16336 unsigned Qm = inst.operands[1].reg;
16337 unsigned imm = inst.operands[2].imm;
16338 constraint (imm < 1 || ((unsigned) imm) > (et.size / 2),
16339 et.size == 16
16340 ? _("immediate operand expected in the range [1,8]")
16341 : _("immediate operand expected in the range [1,16]"));
16342
16343 inst.instruction |= (et.type == NT_unsigned) << 28;
16344 inst.instruction |= HI1 (Qd) << 22;
16345 inst.instruction |= (et.size - imm) << 16;
16346 inst.instruction |= LOW4 (Qd) << 12;
16347 inst.instruction |= HI1 (Qm) << 5;
16348 inst.instruction |= LOW4 (Qm);
16349 inst.is_neon = 1;
16350}
16351
16352static void
16353do_mve_vqmovn (void)
16354{
16355 struct neon_type_el et;
16356 if (inst.instruction == M_MNEM_vqmovnt
16357 || inst.instruction == M_MNEM_vqmovnb)
16358 et = neon_check_type (2, NS_QQ, N_EQK,
16359 N_U16 | N_U32 | N_S16 | N_S32 | N_KEY);
16360 else
16361 et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY);
16362
16363 if (inst.cond > COND_ALWAYS)
16364 inst.pred_insn_type = INSIDE_VPT_INSN;
16365 else
16366 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16367
16368 inst.instruction |= (et.type == NT_unsigned) << 28;
16369 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16370 inst.instruction |= (et.size == 32) << 18;
16371 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16372 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16373 inst.instruction |= LOW4 (inst.operands[1].reg);
16374 inst.is_neon = 1;
16375}
16376
16377static void
16378do_mve_vpsel (void)
16379{
16380 neon_select_shape (NS_QQQ, NS_NULL);
16381
16382 if (inst.cond > COND_ALWAYS)
16383 inst.pred_insn_type = INSIDE_VPT_INSN;
16384 else
16385 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16386
16387 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16388 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16389 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16390 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16391 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16392 inst.instruction |= LOW4 (inst.operands[2].reg);
16393 inst.is_neon = 1;
16394}
16395
16396static void
16397do_mve_vpnot (void)
16398{
16399 if (inst.cond > COND_ALWAYS)
16400 inst.pred_insn_type = INSIDE_VPT_INSN;
16401 else
16402 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16403}
16404
16405static void
16406do_mve_vmaxnma_vminnma (void)
16407{
16408 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
16409 struct neon_type_el et
16410 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
16411
16412 if (inst.cond > COND_ALWAYS)
16413 inst.pred_insn_type = INSIDE_VPT_INSN;
16414 else
16415 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16416
16417 inst.instruction |= (et.size == 16) << 28;
16418 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16419 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16420 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16421 inst.instruction |= LOW4 (inst.operands[1].reg);
16422 inst.is_neon = 1;
16423}
16424
16425static void
16426do_mve_vcmul (void)
16427{
16428 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
16429 struct neon_type_el et
16430 = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
16431
16432 if (inst.cond > COND_ALWAYS)
16433 inst.pred_insn_type = INSIDE_VPT_INSN;
16434 else
16435 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16436
16437 unsigned rot = inst.relocs[0].exp.X_add_number;
16438 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
16439 _("immediate out of range"));
16440
16441 if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
16442 || inst.operands[0].reg == inst.operands[2].reg))
16443 as_tsktsk (BAD_MVE_SRCDEST);
16444
16445 inst.instruction |= (et.size == 32) << 28;
16446 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16447 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16448 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16449 inst.instruction |= (rot > 90) << 12;
16450 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16451 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16452 inst.instruction |= LOW4 (inst.operands[2].reg);
16453 inst.instruction |= (rot == 90 || rot == 270);
16454 inst.is_neon = 1;
16455}
16456
16457/* To handle the Low Overhead Loop instructions
16458 in Armv8.1-M Mainline and MVE. */
16459static void
16460do_t_loloop (void)
16461{
16462 unsigned long insn = inst.instruction;
16463
16464 inst.instruction = THUMB_OP32 (inst.instruction);
16465
16466 if (insn == T_MNEM_lctp)
16467 return;
16468
16469 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN);
16470
16471 if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16472 {
16473 struct neon_type_el et
16474 = neon_check_type (2, NS_RR, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
16475 inst.instruction |= neon_logbits (et.size) << 20;
16476 inst.is_neon = 1;
16477 }
16478
16479 switch (insn)
16480 {
16481 case T_MNEM_letp:
16482 constraint (!inst.operands[0].present,
16483 _("expected LR"));
16484 /* fall through. */
16485 case T_MNEM_le:
16486 /* le <label>. */
16487 if (!inst.operands[0].present)
16488 inst.instruction |= 1 << 21;
16489
16490 v8_1_loop_reloc (TRUE);
16491 break;
16492
16493 case T_MNEM_wls:
16494 case T_MNEM_wlstp:
16495 v8_1_loop_reloc (FALSE);
16496 /* fall through. */
16497 case T_MNEM_dlstp:
16498 case T_MNEM_dls:
16499 constraint (inst.operands[1].isreg != 1, BAD_ARGS);
16500
16501 if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16502 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16503 else if (inst.operands[1].reg == REG_PC)
16504 as_tsktsk (MVE_BAD_PC);
16505 if (inst.operands[1].reg == REG_SP)
16506 as_tsktsk (MVE_BAD_SP);
16507
16508 inst.instruction |= (inst.operands[1].reg << 16);
16509 break;
16510
16511 default:
16512 abort ();
16513 }
16514}
16515
16516
16517static void
16518do_vfp_nsyn_cmp (void)
16519{
16520 enum neon_shape rs;
16521 if (!inst.operands[0].isreg)
16522 {
16523 do_mve_vcmp ();
16524 return;
16525 }
16526 else
16527 {
16528 constraint (inst.operands[2].present, BAD_SYNTAX);
16529 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
16530 BAD_FPU);
16531 }
16532
16533 if (inst.operands[1].isreg)
16534 {
16535 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
16536 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
16537
16538 if (rs == NS_FF || rs == NS_HH)
16539 {
16540 NEON_ENCODE (SINGLE, inst);
16541 do_vfp_sp_monadic ();
16542 }
16543 else
16544 {
16545 NEON_ENCODE (DOUBLE, inst);
16546 do_vfp_dp_rd_rm ();
16547 }
16548 }
16549 else
16550 {
16551 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
16552 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
16553
16554 switch (inst.instruction & 0x0fffffff)
16555 {
16556 case N_MNEM_vcmp:
16557 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
16558 break;
16559 case N_MNEM_vcmpe:
16560 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
16561 break;
16562 default:
16563 abort ();
16564 }
16565
16566 if (rs == NS_FI || rs == NS_HI)
16567 {
16568 NEON_ENCODE (SINGLE, inst);
16569 do_vfp_sp_compare_z ();
16570 }
16571 else
16572 {
16573 NEON_ENCODE (DOUBLE, inst);
16574 do_vfp_dp_rd ();
16575 }
16576 }
16577 do_vfp_cond_or_thumb ();
16578
16579 /* ARMv8.2 fp16 instruction. */
16580 if (rs == NS_HI || rs == NS_HH)
16581 do_scalar_fp16_v82_encode ();
16582}
16583
16584static void
16585nsyn_insert_sp (void)
16586{
16587 inst.operands[1] = inst.operands[0];
16588 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
16589 inst.operands[0].reg = REG_SP;
16590 inst.operands[0].isreg = 1;
16591 inst.operands[0].writeback = 1;
16592 inst.operands[0].present = 1;
16593}
16594
16595/* Fix up Neon data-processing instructions, ORing in the correct bits for
16596 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16597
16598static void
16599neon_dp_fixup (struct arm_it* insn)
16600{
16601 unsigned int i = insn->instruction;
16602 insn->is_neon = 1;
16603
16604 if (thumb_mode)
16605 {
16606 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16607 if (i & (1 << 24))
16608 i |= 1 << 28;
16609
16610 i &= ~(1 << 24);
16611
16612 i |= 0xef000000;
16613 }
16614 else
16615 i |= 0xf2000000;
16616
16617 insn->instruction = i;
16618}
16619
16620static void
16621mve_encode_qqr (int size, int U, int fp)
16622{
16623 if (inst.operands[2].reg == REG_SP)
16624 as_tsktsk (MVE_BAD_SP);
16625 else if (inst.operands[2].reg == REG_PC)
16626 as_tsktsk (MVE_BAD_PC);
16627
16628 if (fp)
16629 {
16630 /* vadd. */
16631 if (((unsigned)inst.instruction) == 0xd00)
16632 inst.instruction = 0xee300f40;
16633 /* vsub. */
16634 else if (((unsigned)inst.instruction) == 0x200d00)
16635 inst.instruction = 0xee301f40;
16636 /* vmul. */
16637 else if (((unsigned)inst.instruction) == 0x1000d10)
16638 inst.instruction = 0xee310e60;
16639
16640 /* Setting size which is 1 for F16 and 0 for F32. */
16641 inst.instruction |= (size == 16) << 28;
16642 }
16643 else
16644 {
16645 /* vadd. */
16646 if (((unsigned)inst.instruction) == 0x800)
16647 inst.instruction = 0xee010f40;
16648 /* vsub. */
16649 else if (((unsigned)inst.instruction) == 0x1000800)
16650 inst.instruction = 0xee011f40;
16651 /* vhadd. */
16652 else if (((unsigned)inst.instruction) == 0)
16653 inst.instruction = 0xee000f40;
16654 /* vhsub. */
16655 else if (((unsigned)inst.instruction) == 0x200)
16656 inst.instruction = 0xee001f40;
16657 /* vmla. */
16658 else if (((unsigned)inst.instruction) == 0x900)
16659 inst.instruction = 0xee010e40;
16660 /* vmul. */
16661 else if (((unsigned)inst.instruction) == 0x910)
16662 inst.instruction = 0xee011e60;
16663 /* vqadd. */
16664 else if (((unsigned)inst.instruction) == 0x10)
16665 inst.instruction = 0xee000f60;
16666 /* vqsub. */
16667 else if (((unsigned)inst.instruction) == 0x210)
16668 inst.instruction = 0xee001f60;
16669 /* vqrdmlah. */
16670 else if (((unsigned)inst.instruction) == 0x3000b10)
16671 inst.instruction = 0xee000e40;
16672 /* vqdmulh. */
16673 else if (((unsigned)inst.instruction) == 0x0000b00)
16674 inst.instruction = 0xee010e60;
16675 /* vqrdmulh. */
16676 else if (((unsigned)inst.instruction) == 0x1000b00)
16677 inst.instruction = 0xfe010e60;
16678
16679 /* Set U-bit. */
16680 inst.instruction |= U << 28;
16681
16682 /* Setting bits for size. */
16683 inst.instruction |= neon_logbits (size) << 20;
16684 }
16685 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16686 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16687 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16688 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16689 inst.instruction |= inst.operands[2].reg;
16690 inst.is_neon = 1;
16691}
16692
16693static void
16694mve_encode_rqq (unsigned bit28, unsigned size)
16695{
16696 inst.instruction |= bit28 << 28;
16697 inst.instruction |= neon_logbits (size) << 20;
16698 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16699 inst.instruction |= inst.operands[0].reg << 12;
16700 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16701 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16702 inst.instruction |= LOW4 (inst.operands[2].reg);
16703 inst.is_neon = 1;
16704}
16705
16706static void
16707mve_encode_qqq (int ubit, int size)
16708{
16709
16710 inst.instruction |= (ubit != 0) << 28;
16711 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16712 inst.instruction |= neon_logbits (size) << 20;
16713 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16714 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16715 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16716 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16717 inst.instruction |= LOW4 (inst.operands[2].reg);
16718
16719 inst.is_neon = 1;
16720}
16721
16722static void
16723mve_encode_rq (unsigned bit28, unsigned size)
16724{
16725 inst.instruction |= bit28 << 28;
16726 inst.instruction |= neon_logbits (size) << 18;
16727 inst.instruction |= inst.operands[0].reg << 12;
16728 inst.instruction |= LOW4 (inst.operands[1].reg);
16729 inst.is_neon = 1;
16730}
16731
16732static void
16733mve_encode_rrqq (unsigned U, unsigned size)
16734{
16735 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
16736
16737 inst.instruction |= U << 28;
16738 inst.instruction |= (inst.operands[1].reg >> 1) << 20;
16739 inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
16740 inst.instruction |= (size == 32) << 16;
16741 inst.instruction |= inst.operands[0].reg << 12;
16742 inst.instruction |= HI1 (inst.operands[2].reg) << 7;
16743 inst.instruction |= inst.operands[3].reg;
16744 inst.is_neon = 1;
16745}
16746
16747/* Helper function for neon_three_same handling the operands. */
16748static void
16749neon_three_args (int isquad)
16750{
16751 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16752 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16753 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16754 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16755 inst.instruction |= LOW4 (inst.operands[2].reg);
16756 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16757 inst.instruction |= (isquad != 0) << 6;
16758 inst.is_neon = 1;
16759}
16760
16761/* Encode insns with bit pattern:
16762
16763 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16764 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16765
16766 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16767 different meaning for some instruction. */
16768
16769static void
16770neon_three_same (int isquad, int ubit, int size)
16771{
16772 neon_three_args (isquad);
16773 inst.instruction |= (ubit != 0) << 24;
16774 if (size != -1)
16775 inst.instruction |= neon_logbits (size) << 20;
16776
16777 neon_dp_fixup (&inst);
16778}
16779
16780/* Encode instructions of the form:
16781
16782 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16783 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16784
16785 Don't write size if SIZE == -1. */
16786
16787static void
16788neon_two_same (int qbit, int ubit, int size)
16789{
16790 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16791 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16792 inst.instruction |= LOW4 (inst.operands[1].reg);
16793 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16794 inst.instruction |= (qbit != 0) << 6;
16795 inst.instruction |= (ubit != 0) << 24;
16796
16797 if (size != -1)
16798 inst.instruction |= neon_logbits (size) << 18;
16799
16800 neon_dp_fixup (&inst);
16801}
16802
16803enum vfp_or_neon_is_neon_bits
16804{
16805NEON_CHECK_CC = 1,
16806NEON_CHECK_ARCH = 2,
16807NEON_CHECK_ARCH8 = 4
16808};
16809
16810/* Call this function if an instruction which may have belonged to the VFP or
16811 Neon instruction sets, but turned out to be a Neon instruction (due to the
16812 operand types involved, etc.). We have to check and/or fix-up a couple of
16813 things:
16814
16815 - Make sure the user hasn't attempted to make a Neon instruction
16816 conditional.
16817 - Alter the value in the condition code field if necessary.
16818 - Make sure that the arch supports Neon instructions.
16819
16820 Which of these operations take place depends on bits from enum
16821 vfp_or_neon_is_neon_bits.
16822
16823 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16824 current instruction's condition is COND_ALWAYS, the condition field is
16825 changed to inst.uncond_value. This is necessary because instructions shared
16826 between VFP and Neon may be conditional for the VFP variants only, and the
16827 unconditional Neon version must have, e.g., 0xF in the condition field. */
16828
16829static int
16830vfp_or_neon_is_neon (unsigned check)
16831{
16832/* Conditions are always legal in Thumb mode (IT blocks). */
16833if (!thumb_mode && (check & NEON_CHECK_CC))
16834 {
16835 if (inst.cond != COND_ALWAYS)
16836 {
16837 first_error (_(BAD_COND));
16838 return FAIL;
16839 }
16840 if (inst.uncond_value != -1)
16841 inst.instruction |= inst.uncond_value << 28;
16842 }
16843
16844
16845 if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
16846 || ((check & NEON_CHECK_ARCH8)
16847 && !mark_feature_used (&fpu_neon_ext_armv8)))
16848 {
16849 first_error (_(BAD_FPU));
16850 return FAIL;
16851 }
16852
16853return SUCCESS;
16854}
16855
16856
16857/* Return TRUE if the SIMD instruction is available for the current
16858 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16859 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16860 vfp_or_neon_is_neon for the NEON specific checks. */
16861
16862static bfd_boolean
16863check_simd_pred_availability (int fp, unsigned check)
16864{
16865if (inst.cond > COND_ALWAYS)
16866 {
16867 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16868 {
16869 inst.error = BAD_FPU;
16870 return FALSE;
16871 }
16872 inst.pred_insn_type = INSIDE_VPT_INSN;
16873 }
16874else if (inst.cond < COND_ALWAYS)
16875 {
16876 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16877 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16878 else if (vfp_or_neon_is_neon (check) == FAIL)
16879 return FALSE;
16880 }
16881else
16882 {
16883 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
16884 && vfp_or_neon_is_neon (check) == FAIL)
16885 return FALSE;
16886
16887 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16888 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16889 }
16890return TRUE;
16891}
16892
16893/* Neon instruction encoders, in approximate order of appearance. */
16894
16895static void
16896do_neon_dyadic_i_su (void)
16897{
16898 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
16899 return;
16900
16901 enum neon_shape rs;
16902 struct neon_type_el et;
16903 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16904 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16905 else
16906 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16907
16908 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY);
16909
16910
16911 if (rs != NS_QQR)
16912 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16913 else
16914 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16915}
16916
16917static void
16918do_neon_dyadic_i64_su (void)
16919{
16920 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
16921 return;
16922 enum neon_shape rs;
16923 struct neon_type_el et;
16924 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16925 {
16926 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16927 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16928 }
16929 else
16930 {
16931 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16932 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16933 }
16934 if (rs == NS_QQR)
16935 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16936 else
16937 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16938}
16939
16940static void
16941neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
16942 unsigned immbits)
16943{
16944 unsigned size = et.size >> 3;
16945 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16946 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16947 inst.instruction |= LOW4 (inst.operands[1].reg);
16948 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16949 inst.instruction |= (isquad != 0) << 6;
16950 inst.instruction |= immbits << 16;
16951 inst.instruction |= (size >> 3) << 7;
16952 inst.instruction |= (size & 0x7) << 19;
16953 if (write_ubit)
16954 inst.instruction |= (uval != 0) << 24;
16955
16956 neon_dp_fixup (&inst);
16957}
16958
16959static void
16960do_neon_shl (void)
16961{
16962 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
16963 return;
16964
16965 if (!inst.operands[2].isreg)
16966 {
16967 enum neon_shape rs;
16968 struct neon_type_el et;
16969 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16970 {
16971 rs = neon_select_shape (NS_QQI, NS_NULL);
16972 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_MVE);
16973 }
16974 else
16975 {
16976 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16977 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
16978 }
16979 int imm = inst.operands[2].imm;
16980
16981 constraint (imm < 0 || (unsigned)imm >= et.size,
16982 _("immediate out of range for shift"));
16983 NEON_ENCODE (IMMED, inst);
16984 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
16985 }
16986 else
16987 {
16988 enum neon_shape rs;
16989 struct neon_type_el et;
16990 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16991 {
16992 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16993 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
16994 }
16995 else
16996 {
16997 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16998 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16999 }
17000
17001
17002 if (rs == NS_QQR)
17003 {
17004 constraint (inst.operands[0].reg != inst.operands[1].reg,
17005 _("invalid instruction shape"));
17006 if (inst.operands[2].reg == REG_SP)
17007 as_tsktsk (MVE_BAD_SP);
17008 else if (inst.operands[2].reg == REG_PC)
17009 as_tsktsk (MVE_BAD_PC);
17010
17011 inst.instruction = 0xee311e60;
17012 inst.instruction |= (et.type == NT_unsigned) << 28;
17013 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17014 inst.instruction |= neon_logbits (et.size) << 18;
17015 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17016 inst.instruction |= inst.operands[2].reg;
17017 inst.is_neon = 1;
17018 }
17019 else
17020 {
17021 unsigned int tmp;
17022
17023 /* VSHL/VQSHL 3-register variants have syntax such as:
17024 vshl.xx Dd, Dm, Dn
17025 whereas other 3-register operations encoded by neon_three_same have
17026 syntax like:
17027 vadd.xx Dd, Dn, Dm
17028 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17029 operands[2].reg here. */
17030 tmp = inst.operands[2].reg;
17031 inst.operands[2].reg = inst.operands[1].reg;
17032 inst.operands[1].reg = tmp;
17033 NEON_ENCODE (INTEGER, inst);
17034 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
17035 }
17036 }
17037}
17038
17039static void
17040do_neon_qshl (void)
17041{
17042 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
17043 return;
17044
17045 if (!inst.operands[2].isreg)
17046 {
17047 enum neon_shape rs;
17048 struct neon_type_el et;
17049 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17050 {
17051 rs = neon_select_shape (NS_QQI, NS_NULL);
17052 et = neon_check_type (2, rs, N_EQK, N_KEY | N_SU_MVE);
17053 }
17054 else
17055 {
17056 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17057 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
17058 }
17059 int imm = inst.operands[2].imm;
17060
17061 constraint (imm < 0 || (unsigned)imm >= et.size,
17062 _("immediate out of range for shift"));
17063 NEON_ENCODE (IMMED, inst);
17064 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
17065 }
17066 else
17067 {
17068 enum neon_shape rs;
17069 struct neon_type_el et;
17070
17071 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17072 {
17073 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17074 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
17075 }
17076 else
17077 {
17078 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17079 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
17080 }
17081
17082 if (rs == NS_QQR)
17083 {
17084 constraint (inst.operands[0].reg != inst.operands[1].reg,
17085 _("invalid instruction shape"));
17086 if (inst.operands[2].reg == REG_SP)
17087 as_tsktsk (MVE_BAD_SP);
17088 else if (inst.operands[2].reg == REG_PC)
17089 as_tsktsk (MVE_BAD_PC);
17090
17091 inst.instruction = 0xee311ee0;
17092 inst.instruction |= (et.type == NT_unsigned) << 28;
17093 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17094 inst.instruction |= neon_logbits (et.size) << 18;
17095 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17096 inst.instruction |= inst.operands[2].reg;
17097 inst.is_neon = 1;
17098 }
17099 else
17100 {
17101 unsigned int tmp;
17102
17103 /* See note in do_neon_shl. */
17104 tmp = inst.operands[2].reg;
17105 inst.operands[2].reg = inst.operands[1].reg;
17106 inst.operands[1].reg = tmp;
17107 NEON_ENCODE (INTEGER, inst);
17108 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
17109 }
17110 }
17111}
17112
17113static void
17114do_neon_rshl (void)
17115{
17116 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
17117 return;
17118
17119 enum neon_shape rs;
17120 struct neon_type_el et;
17121 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17122 {
17123 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17124 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17125 }
17126 else
17127 {
17128 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17129 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
17130 }
17131
17132 unsigned int tmp;
17133
17134 if (rs == NS_QQR)
17135 {
17136 if (inst.operands[2].reg == REG_PC)
17137 as_tsktsk (MVE_BAD_PC);
17138 else if (inst.operands[2].reg == REG_SP)
17139 as_tsktsk (MVE_BAD_SP);
17140
17141 constraint (inst.operands[0].reg != inst.operands[1].reg,
17142 _("invalid instruction shape"));
17143
17144 if (inst.instruction == 0x0000510)
17145 /* We are dealing with vqrshl. */
17146 inst.instruction = 0xee331ee0;
17147 else
17148 /* We are dealing with vrshl. */
17149 inst.instruction = 0xee331e60;
17150
17151 inst.instruction |= (et.type == NT_unsigned) << 28;
17152 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17153 inst.instruction |= neon_logbits (et.size) << 18;
17154 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17155 inst.instruction |= inst.operands[2].reg;
17156 inst.is_neon = 1;
17157 }
17158 else
17159 {
17160 tmp = inst.operands[2].reg;
17161 inst.operands[2].reg = inst.operands[1].reg;
17162 inst.operands[1].reg = tmp;
17163 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
17164 }
17165}
17166
17167static int
17168neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
17169{
17170 /* Handle .I8 pseudo-instructions. */
17171 if (size == 8)
17172 {
17173 /* Unfortunately, this will make everything apart from zero out-of-range.
17174 FIXME is this the intended semantics? There doesn't seem much point in
17175 accepting .I8 if so. */
17176 immediate |= immediate << 8;
17177 size = 16;
17178 }
17179
17180 if (size >= 32)
17181 {
17182 if (immediate == (immediate & 0x000000ff))
17183 {
17184 *immbits = immediate;
17185 return 0x1;
17186 }
17187 else if (immediate == (immediate & 0x0000ff00))
17188 {
17189 *immbits = immediate >> 8;
17190 return 0x3;
17191 }
17192 else if (immediate == (immediate & 0x00ff0000))
17193 {
17194 *immbits = immediate >> 16;
17195 return 0x5;
17196 }
17197 else if (immediate == (immediate & 0xff000000))
17198 {
17199 *immbits = immediate >> 24;
17200 return 0x7;
17201 }
17202 if ((immediate & 0xffff) != (immediate >> 16))
17203 goto bad_immediate;
17204 immediate &= 0xffff;
17205 }
17206
17207 if (immediate == (immediate & 0x000000ff))
17208 {
17209 *immbits = immediate;
17210 return 0x9;
17211 }
17212 else if (immediate == (immediate & 0x0000ff00))
17213 {
17214 *immbits = immediate >> 8;
17215 return 0xb;
17216 }
17217
17218 bad_immediate:
17219 first_error (_("immediate value out of range"));
17220 return FAIL;
17221}
17222
17223static void
17224do_neon_logic (void)
17225{
17226 if (inst.operands[2].present && inst.operands[2].isreg)
17227 {
17228 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17229 if (rs == NS_QQQ
17230 && !check_simd_pred_availability (FALSE,
17231 NEON_CHECK_ARCH | NEON_CHECK_CC))
17232 return;
17233 else if (rs != NS_QQQ
17234 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
17235 first_error (BAD_FPU);
17236
17237 neon_check_type (3, rs, N_IGNORE_TYPE);
17238 /* U bit and size field were set as part of the bitmask. */
17239 NEON_ENCODE (INTEGER, inst);
17240 neon_three_same (neon_quad (rs), 0, -1);
17241 }
17242 else
17243 {
17244 const int three_ops_form = (inst.operands[2].present
17245 && !inst.operands[2].isreg);
17246 const int immoperand = (three_ops_form ? 2 : 1);
17247 enum neon_shape rs = (three_ops_form
17248 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
17249 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
17250 /* Because neon_select_shape makes the second operand a copy of the first
17251 if the second operand is not present. */
17252 if (rs == NS_QQI
17253 && !check_simd_pred_availability (FALSE,
17254 NEON_CHECK_ARCH | NEON_CHECK_CC))
17255 return;
17256 else if (rs != NS_QQI
17257 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
17258 first_error (BAD_FPU);
17259
17260 struct neon_type_el et;
17261 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17262 et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK);
17263 else
17264 et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32
17265 | N_KEY, N_EQK);
17266
17267 if (et.type == NT_invtype)
17268 return;
17269 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
17270 unsigned immbits;
17271 int cmode;
17272
17273
17274 if (three_ops_form)
17275 constraint (inst.operands[0].reg != inst.operands[1].reg,
17276 _("first and second operands shall be the same register"));
17277
17278 NEON_ENCODE (IMMED, inst);
17279
17280 immbits = inst.operands[immoperand].imm;
17281 if (et.size == 64)
17282 {
17283 /* .i64 is a pseudo-op, so the immediate must be a repeating
17284 pattern. */
17285 if (immbits != (inst.operands[immoperand].regisimm ?
17286 inst.operands[immoperand].reg : 0))
17287 {
17288 /* Set immbits to an invalid constant. */
17289 immbits = 0xdeadbeef;
17290 }
17291 }
17292
17293 switch (opcode)
17294 {
17295 case N_MNEM_vbic:
17296 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17297 break;
17298
17299 case N_MNEM_vorr:
17300 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17301 break;
17302
17303 case N_MNEM_vand:
17304 /* Pseudo-instruction for VBIC. */
17305 neon_invert_size (&immbits, 0, et.size);
17306 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17307 break;
17308
17309 case N_MNEM_vorn:
17310 /* Pseudo-instruction for VORR. */
17311 neon_invert_size (&immbits, 0, et.size);
17312 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17313 break;
17314
17315 default:
17316 abort ();
17317 }
17318
17319 if (cmode == FAIL)
17320 return;
17321
17322 inst.instruction |= neon_quad (rs) << 6;
17323 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17324 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17325 inst.instruction |= cmode << 8;
17326 neon_write_immbits (immbits);
17327
17328 neon_dp_fixup (&inst);
17329 }
17330}
17331
17332static void
17333do_neon_bitfield (void)
17334{
17335 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17336 neon_check_type (3, rs, N_IGNORE_TYPE);
17337 neon_three_same (neon_quad (rs), 0, -1);
17338}
17339
17340static void
17341neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
17342 unsigned destbits)
17343{
17344 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17345 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
17346 types | N_KEY);
17347 if (et.type == NT_float)
17348 {
17349 NEON_ENCODE (FLOAT, inst);
17350 if (rs == NS_QQR)
17351 mve_encode_qqr (et.size, 0, 1);
17352 else
17353 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
17354 }
17355 else
17356 {
17357 NEON_ENCODE (INTEGER, inst);
17358 if (rs == NS_QQR)
17359 mve_encode_qqr (et.size, et.type == ubit_meaning, 0);
17360 else
17361 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
17362 }
17363}
17364
17365
17366static void
17367do_neon_dyadic_if_su_d (void)
17368{
17369 /* This version only allow D registers, but that constraint is enforced during
17370 operand parsing so we don't need to do anything extra here. */
17371 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
17372}
17373
17374static void
17375do_neon_dyadic_if_i_d (void)
17376{
17377 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17378 affected if we specify unsigned args. */
17379 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17380}
17381
17382static void
17383do_mve_vstr_vldr_QI (int size, int elsize, int load)
17384{
17385 constraint (size < 32, BAD_ADDR_MODE);
17386 constraint (size != elsize, BAD_EL_TYPE);
17387 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
17388 constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
17389 constraint (load && inst.operands[0].reg == inst.operands[1].reg,
17390 _("destination register and offset register may not be the"
17391 " same"));
17392
17393 int imm = inst.relocs[0].exp.X_add_number;
17394 int add = 1;
17395 if (imm < 0)
17396 {
17397 add = 0;
17398 imm = -imm;
17399 }
17400 constraint ((imm % (size / 8) != 0)
17401 || imm > (0x7f << neon_logbits (size)),
17402 (size == 32) ? _("immediate must be a multiple of 4 in the"
17403 " range of +/-[0,508]")
17404 : _("immediate must be a multiple of 8 in the"
17405 " range of +/-[0,1016]"));
17406 inst.instruction |= 0x11 << 24;
17407 inst.instruction |= add << 23;
17408 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17409 inst.instruction |= inst.operands[1].writeback << 21;
17410 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17411 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17412 inst.instruction |= 1 << 12;
17413 inst.instruction |= (size == 64) << 8;
17414 inst.instruction &= 0xffffff00;
17415 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17416 inst.instruction |= imm >> neon_logbits (size);
17417}
17418
17419static void
17420do_mve_vstr_vldr_RQ (int size, int elsize, int load)
17421{
17422 unsigned os = inst.operands[1].imm >> 5;
17423 unsigned type = inst.vectype.el[0].type;
17424 constraint (os != 0 && size == 8,
17425 _("can not shift offsets when accessing less than half-word"));
17426 constraint (os && os != neon_logbits (size),
17427 _("shift immediate must be 1, 2 or 3 for half-word, word"
17428 " or double-word accesses respectively"));
17429 if (inst.operands[1].reg == REG_PC)
17430 as_tsktsk (MVE_BAD_PC);
17431
17432 switch (size)
17433 {
17434 case 8:
17435 constraint (elsize >= 64, BAD_EL_TYPE);
17436 break;
17437 case 16:
17438 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17439 break;
17440 case 32:
17441 case 64:
17442 constraint (elsize != size, BAD_EL_TYPE);
17443 break;
17444 default:
17445 break;
17446 }
17447 constraint (inst.operands[1].writeback || !inst.operands[1].preind,
17448 BAD_ADDR_MODE);
17449 if (load)
17450 {
17451 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
17452 _("destination register and offset register may not be"
17453 " the same"));
17454 constraint (size == elsize && type == NT_signed, BAD_EL_TYPE);
17455 constraint (size != elsize && type != NT_unsigned && type != NT_signed,
17456 BAD_EL_TYPE);
17457 inst.instruction |= ((size == elsize) || (type == NT_unsigned)) << 28;
17458 }
17459 else
17460 {
17461 constraint (type != NT_untyped, BAD_EL_TYPE);
17462 }
17463
17464 inst.instruction |= 1 << 23;
17465 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17466 inst.instruction |= inst.operands[1].reg << 16;
17467 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17468 inst.instruction |= neon_logbits (elsize) << 7;
17469 inst.instruction |= HI1 (inst.operands[1].imm) << 5;
17470 inst.instruction |= LOW4 (inst.operands[1].imm);
17471 inst.instruction |= !!os;
17472}
17473
17474static void
17475do_mve_vstr_vldr_RI (int size, int elsize, int load)
17476{
17477 enum neon_el_type type = inst.vectype.el[0].type;
17478
17479 constraint (size >= 64, BAD_ADDR_MODE);
17480 switch (size)
17481 {
17482 case 16:
17483 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17484 break;
17485 case 32:
17486 constraint (elsize != size, BAD_EL_TYPE);
17487 break;
17488 default:
17489 break;
17490 }
17491 if (load)
17492 {
17493 constraint (elsize != size && type != NT_unsigned
17494 && type != NT_signed, BAD_EL_TYPE);
17495 }
17496 else
17497 {
17498 constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE);
17499 }
17500
17501 int imm = inst.relocs[0].exp.X_add_number;
17502 int add = 1;
17503 if (imm < 0)
17504 {
17505 add = 0;
17506 imm = -imm;
17507 }
17508
17509 if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size)))
17510 {
17511 switch (size)
17512 {
17513 case 8:
17514 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17515 break;
17516 case 16:
17517 constraint (1, _("immediate must be a multiple of 2 in the"
17518 " range of +/-[0,254]"));
17519 break;
17520 case 32:
17521 constraint (1, _("immediate must be a multiple of 4 in the"
17522 " range of +/-[0,508]"));
17523 break;
17524 }
17525 }
17526
17527 if (size != elsize)
17528 {
17529 constraint (inst.operands[1].reg > 7, BAD_HIREG);
17530 constraint (inst.operands[0].reg > 14,
17531 _("MVE vector register in the range [Q0..Q7] expected"));
17532 inst.instruction |= (load && type == NT_unsigned) << 28;
17533 inst.instruction |= (size == 16) << 19;
17534 inst.instruction |= neon_logbits (elsize) << 7;
17535 }
17536 else
17537 {
17538 if (inst.operands[1].reg == REG_PC)
17539 as_tsktsk (MVE_BAD_PC);
17540 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17541 as_tsktsk (MVE_BAD_SP);
17542 inst.instruction |= 1 << 12;
17543 inst.instruction |= neon_logbits (size) << 7;
17544 }
17545 inst.instruction |= inst.operands[1].preind << 24;
17546 inst.instruction |= add << 23;
17547 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17548 inst.instruction |= inst.operands[1].writeback << 21;
17549 inst.instruction |= inst.operands[1].reg << 16;
17550 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17551 inst.instruction &= 0xffffff80;
17552 inst.instruction |= imm >> neon_logbits (size);
17553
17554}
17555
17556static void
17557do_mve_vstr_vldr (void)
17558{
17559 unsigned size;
17560 int load = 0;
17561
17562 if (inst.cond > COND_ALWAYS)
17563 inst.pred_insn_type = INSIDE_VPT_INSN;
17564 else
17565 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17566
17567 switch (inst.instruction)
17568 {
17569 default:
17570 gas_assert (0);
17571 break;
17572 case M_MNEM_vldrb:
17573 load = 1;
17574 /* fall through. */
17575 case M_MNEM_vstrb:
17576 size = 8;
17577 break;
17578 case M_MNEM_vldrh:
17579 load = 1;
17580 /* fall through. */
17581 case M_MNEM_vstrh:
17582 size = 16;
17583 break;
17584 case M_MNEM_vldrw:
17585 load = 1;
17586 /* fall through. */
17587 case M_MNEM_vstrw:
17588 size = 32;
17589 break;
17590 case M_MNEM_vldrd:
17591 load = 1;
17592 /* fall through. */
17593 case M_MNEM_vstrd:
17594 size = 64;
17595 break;
17596 }
17597 unsigned elsize = inst.vectype.el[0].size;
17598
17599 if (inst.operands[1].isquad)
17600 {
17601 /* We are dealing with [Q, imm]{!} cases. */
17602 do_mve_vstr_vldr_QI (size, elsize, load);
17603 }
17604 else
17605 {
17606 if (inst.operands[1].immisreg == 2)
17607 {
17608 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17609 do_mve_vstr_vldr_RQ (size, elsize, load);
17610 }
17611 else if (!inst.operands[1].immisreg)
17612 {
17613 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17614 do_mve_vstr_vldr_RI (size, elsize, load);
17615 }
17616 else
17617 constraint (1, BAD_ADDR_MODE);
17618 }
17619
17620 inst.is_neon = 1;
17621}
17622
17623static void
17624do_mve_vst_vld (void)
17625{
17626 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17627 return;
17628
17629 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
17630 || inst.relocs[0].exp.X_add_number != 0
17631 || inst.operands[1].immisreg != 0,
17632 BAD_ADDR_MODE);
17633 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
17634 if (inst.operands[1].reg == REG_PC)
17635 as_tsktsk (MVE_BAD_PC);
17636 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17637 as_tsktsk (MVE_BAD_SP);
17638
17639
17640 /* These instructions are one of the "exceptions" mentioned in
17641 handle_pred_state. They are MVE instructions that are not VPT compatible
17642 and do not accept a VPT code, thus appending such a code is a syntax
17643 error. */
17644 if (inst.cond > COND_ALWAYS)
17645 first_error (BAD_SYNTAX);
17646 /* If we append a scalar condition code we can set this to
17647 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17648 else if (inst.cond < COND_ALWAYS)
17649 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17650 else
17651 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
17652
17653 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17654 inst.instruction |= inst.operands[1].writeback << 21;
17655 inst.instruction |= inst.operands[1].reg << 16;
17656 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17657 inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
17658 inst.is_neon = 1;
17659}
17660
17661static void
17662do_mve_vaddlv (void)
17663{
17664 enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
17665 struct neon_type_el et
17666 = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
17667
17668 if (et.type == NT_invtype)
17669 first_error (BAD_EL_TYPE);
17670
17671 if (inst.cond > COND_ALWAYS)
17672 inst.pred_insn_type = INSIDE_VPT_INSN;
17673 else
17674 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17675
17676 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17677
17678 inst.instruction |= (et.type == NT_unsigned) << 28;
17679 inst.instruction |= inst.operands[1].reg << 19;
17680 inst.instruction |= inst.operands[0].reg << 12;
17681 inst.instruction |= inst.operands[2].reg;
17682 inst.is_neon = 1;
17683}
17684
17685static void
17686do_neon_dyadic_if_su (void)
17687{
17688 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17689 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17690 N_SUF_32 | N_KEY);
17691
17692 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
17693 || inst.instruction == ((unsigned) N_MNEM_vmin))
17694 && et.type == NT_float
17695 && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
17696
17697 if (!check_simd_pred_availability (et.type == NT_float,
17698 NEON_CHECK_ARCH | NEON_CHECK_CC))
17699 return;
17700
17701 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
17702}
17703
17704static void
17705do_neon_addsub_if_i (void)
17706{
17707 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
17708 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
17709 return;
17710
17711 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17712 struct neon_type_el et = neon_check_type (3, rs, N_EQK,
17713 N_EQK, N_IF_32 | N_I64 | N_KEY);
17714
17715 constraint (rs == NS_QQR && et.size == 64, BAD_FPU);
17716 /* If we are parsing Q registers and the element types match MVE, which NEON
17717 also supports, then we must check whether this is an instruction that can
17718 be used by both MVE/NEON. This distinction can be made based on whether
17719 they are predicated or not. */
17720 if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64)
17721 {
17722 if (!check_simd_pred_availability (et.type == NT_float,
17723 NEON_CHECK_ARCH | NEON_CHECK_CC))
17724 return;
17725 }
17726 else
17727 {
17728 /* If they are either in a D register or are using an unsupported. */
17729 if (rs != NS_QQR
17730 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
17731 return;
17732 }
17733
17734 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17735 affected if we specify unsigned args. */
17736 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
17737}
17738
17739/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17740 result to be:
17741 V<op> A,B (A is operand 0, B is operand 2)
17742 to mean:
17743 V<op> A,B,A
17744 not:
17745 V<op> A,B,B
17746 so handle that case specially. */
17747
17748static void
17749neon_exchange_operands (void)
17750{
17751 if (inst.operands[1].present)
17752 {
17753 void *scratch = xmalloc (sizeof (inst.operands[0]));
17754
17755 /* Swap operands[1] and operands[2]. */
17756 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
17757 inst.operands[1] = inst.operands[2];
17758 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
17759 free (scratch);
17760 }
17761 else
17762 {
17763 inst.operands[1] = inst.operands[2];
17764 inst.operands[2] = inst.operands[0];
17765 }
17766}
17767
17768static void
17769neon_compare (unsigned regtypes, unsigned immtypes, int invert)
17770{
17771 if (inst.operands[2].isreg)
17772 {
17773 if (invert)
17774 neon_exchange_operands ();
17775 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
17776 }
17777 else
17778 {
17779 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17780 struct neon_type_el et = neon_check_type (2, rs,
17781 N_EQK | N_SIZ, immtypes | N_KEY);
17782
17783 NEON_ENCODE (IMMED, inst);
17784 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17785 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17786 inst.instruction |= LOW4 (inst.operands[1].reg);
17787 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17788 inst.instruction |= neon_quad (rs) << 6;
17789 inst.instruction |= (et.type == NT_float) << 10;
17790 inst.instruction |= neon_logbits (et.size) << 18;
17791
17792 neon_dp_fixup (&inst);
17793 }
17794}
17795
17796static void
17797do_neon_cmp (void)
17798{
17799 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
17800}
17801
17802static void
17803do_neon_cmp_inv (void)
17804{
17805 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
17806}
17807
17808static void
17809do_neon_ceq (void)
17810{
17811 neon_compare (N_IF_32, N_IF_32, FALSE);
17812}
17813
17814/* For multiply instructions, we have the possibility of 16-bit or 32-bit
17815 scalars, which are encoded in 5 bits, M : Rm.
17816 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17817 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17818 index in M.
17819
17820 Dot Product instructions are similar to multiply instructions except elsize
17821 should always be 32.
17822
17823 This function translates SCALAR, which is GAS's internal encoding of indexed
17824 scalar register, to raw encoding. There is also register and index range
17825 check based on ELSIZE. */
17826
17827static unsigned
17828neon_scalar_for_mul (unsigned scalar, unsigned elsize)
17829{
17830 unsigned regno = NEON_SCALAR_REG (scalar);
17831 unsigned elno = NEON_SCALAR_INDEX (scalar);
17832
17833 switch (elsize)
17834 {
17835 case 16:
17836 if (regno > 7 || elno > 3)
17837 goto bad_scalar;
17838 return regno | (elno << 3);
17839
17840 case 32:
17841 if (regno > 15 || elno > 1)
17842 goto bad_scalar;
17843 return regno | (elno << 4);
17844
17845 default:
17846 bad_scalar:
17847 first_error (_("scalar out of range for multiply instruction"));
17848 }
17849
17850 return 0;
17851}
17852
17853/* Encode multiply / multiply-accumulate scalar instructions. */
17854
17855static void
17856neon_mul_mac (struct neon_type_el et, int ubit)
17857{
17858 unsigned scalar;
17859
17860 /* Give a more helpful error message if we have an invalid type. */
17861 if (et.type == NT_invtype)
17862 return;
17863
17864 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
17865 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17866 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17867 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17868 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17869 inst.instruction |= LOW4 (scalar);
17870 inst.instruction |= HI1 (scalar) << 5;
17871 inst.instruction |= (et.type == NT_float) << 8;
17872 inst.instruction |= neon_logbits (et.size) << 20;
17873 inst.instruction |= (ubit != 0) << 24;
17874
17875 neon_dp_fixup (&inst);
17876}
17877
17878static void
17879do_neon_mac_maybe_scalar (void)
17880{
17881 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
17882 return;
17883
17884 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
17885 return;
17886
17887 if (inst.operands[2].isscalar)
17888 {
17889 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17890 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17891 struct neon_type_el et = neon_check_type (3, rs,
17892 N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
17893 NEON_ENCODE (SCALAR, inst);
17894 neon_mul_mac (et, neon_quad (rs));
17895 }
17896 else if (!inst.operands[2].isvec)
17897 {
17898 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17899
17900 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17901 neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17902
17903 neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0);
17904 }
17905 else
17906 {
17907 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17908 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17909 affected if we specify unsigned args. */
17910 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17911 }
17912}
17913
17914static void
17915do_bfloat_vfma (void)
17916{
17917 constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU));
17918 constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16));
17919 enum neon_shape rs;
17920 int t_bit = 0;
17921
17922 if (inst.instruction != B_MNEM_vfmab)
17923 {
17924 t_bit = 1;
17925 inst.instruction = B_MNEM_vfmat;
17926 }
17927
17928 if (inst.operands[2].isscalar)
17929 {
17930 rs = neon_select_shape (NS_QQS, NS_NULL);
17931 neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
17932
17933 inst.instruction |= (1 << 25);
17934 int index = inst.operands[2].reg & 0xf;
17935 constraint (!(index < 4), _("index must be in the range 0 to 3"));
17936 inst.operands[2].reg >>= 4;
17937 constraint (!(inst.operands[2].reg < 8),
17938 _("indexed register must be less than 8"));
17939 neon_three_args (t_bit);
17940 inst.instruction |= ((index & 1) << 3);
17941 inst.instruction |= ((index & 2) << 4);
17942 }
17943 else
17944 {
17945 rs = neon_select_shape (NS_QQQ, NS_NULL);
17946 neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
17947 neon_three_args (t_bit);
17948 }
17949
17950}
17951
17952static void
17953do_neon_fmac (void)
17954{
17955 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma)
17956 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
17957 return;
17958
17959 if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH))
17960 return;
17961
17962 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
17963 {
17964 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17965 struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK,
17966 N_EQK);
17967
17968 if (rs == NS_QQR)
17969 {
17970
17971 if (inst.operands[2].reg == REG_SP)
17972 as_tsktsk (MVE_BAD_SP);
17973 else if (inst.operands[2].reg == REG_PC)
17974 as_tsktsk (MVE_BAD_PC);
17975
17976 inst.instruction = 0xee310e40;
17977 inst.instruction |= (et.size == 16) << 28;
17978 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17979 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17980 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17981 inst.instruction |= HI1 (inst.operands[1].reg) << 6;
17982 inst.instruction |= inst.operands[2].reg;
17983 inst.is_neon = 1;
17984 return;
17985 }
17986 }
17987 else
17988 {
17989 constraint (!inst.operands[2].isvec, BAD_FPU);
17990 }
17991
17992 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17993}
17994
17995static void
17996do_mve_vfma (void)
17997{
17998 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_bf16) &&
17999 inst.cond == COND_ALWAYS)
18000 {
18001 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
18002 inst.instruction = N_MNEM_vfma;
18003 inst.pred_insn_type = INSIDE_VPT_INSN;
18004 inst.cond = 0xf;
18005 return do_neon_fmac();
18006 }
18007 else
18008 {
18009 do_bfloat_vfma();
18010 }
18011}
18012
18013static void
18014do_neon_tst (void)
18015{
18016 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18017 struct neon_type_el et = neon_check_type (3, rs,
18018 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18019 neon_three_same (neon_quad (rs), 0, et.size);
18020}
18021
18022/* VMUL with 3 registers allows the P8 type. The scalar version supports the
18023 same types as the MAC equivalents. The polynomial type for this instruction
18024 is encoded the same as the integer type. */
18025
18026static void
18027do_neon_mul (void)
18028{
18029 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
18030 return;
18031
18032 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
18033 return;
18034
18035 if (inst.operands[2].isscalar)
18036 {
18037 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
18038 do_neon_mac_maybe_scalar ();
18039 }
18040 else
18041 {
18042 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18043 {
18044 enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
18045 struct neon_type_el et
18046 = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY);
18047 if (et.type == NT_float)
18048 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
18049 BAD_FPU);
18050
18051 neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0);
18052 }
18053 else
18054 {
18055 constraint (!inst.operands[2].isvec, BAD_FPU);
18056 neon_dyadic_misc (NT_poly,
18057 N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
18058 }
18059 }
18060}
18061
18062static void
18063do_neon_qdmulh (void)
18064{
18065 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
18066 return;
18067
18068 if (inst.operands[2].isscalar)
18069 {
18070 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
18071 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
18072 struct neon_type_el et = neon_check_type (3, rs,
18073 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18074 NEON_ENCODE (SCALAR, inst);
18075 neon_mul_mac (et, neon_quad (rs));
18076 }
18077 else
18078 {
18079 enum neon_shape rs;
18080 struct neon_type_el et;
18081 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18082 {
18083 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
18084 et = neon_check_type (3, rs,
18085 N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18086 }
18087 else
18088 {
18089 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18090 et = neon_check_type (3, rs,
18091 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18092 }
18093
18094 NEON_ENCODE (INTEGER, inst);
18095 if (rs == NS_QQR)
18096 mve_encode_qqr (et.size, 0, 0);
18097 else
18098 /* The U bit (rounding) comes from bit mask. */
18099 neon_three_same (neon_quad (rs), 0, et.size);
18100 }
18101}
18102
18103static void
18104do_mve_vaddv (void)
18105{
18106 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18107 struct neon_type_el et
18108 = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
18109
18110 if (et.type == NT_invtype)
18111 first_error (BAD_EL_TYPE);
18112
18113 if (inst.cond > COND_ALWAYS)
18114 inst.pred_insn_type = INSIDE_VPT_INSN;
18115 else
18116 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18117
18118 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
18119
18120 mve_encode_rq (et.type == NT_unsigned, et.size);
18121}
18122
18123static void
18124do_mve_vhcadd (void)
18125{
18126 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
18127 struct neon_type_el et
18128 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18129
18130 if (inst.cond > COND_ALWAYS)
18131 inst.pred_insn_type = INSIDE_VPT_INSN;
18132 else
18133 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18134
18135 unsigned rot = inst.relocs[0].exp.X_add_number;
18136 constraint (rot != 90 && rot != 270, _("immediate out of range"));
18137
18138 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
18139 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18140 "operand makes instruction UNPREDICTABLE"));
18141
18142 mve_encode_qqq (0, et.size);
18143 inst.instruction |= (rot == 270) << 12;
18144 inst.is_neon = 1;
18145}
18146
18147static void
18148do_mve_vqdmull (void)
18149{
18150 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
18151 struct neon_type_el et
18152 = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18153
18154 if (et.size == 32
18155 && (inst.operands[0].reg == inst.operands[1].reg
18156 || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
18157 as_tsktsk (BAD_MVE_SRCDEST);
18158
18159 if (inst.cond > COND_ALWAYS)
18160 inst.pred_insn_type = INSIDE_VPT_INSN;
18161 else
18162 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18163
18164 if (rs == NS_QQQ)
18165 {
18166 mve_encode_qqq (et.size == 32, 64);
18167 inst.instruction |= 1;
18168 }
18169 else
18170 {
18171 mve_encode_qqr (64, et.size == 32, 0);
18172 inst.instruction |= 0x3 << 5;
18173 }
18174}
18175
18176static void
18177do_mve_vadc (void)
18178{
18179 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18180 struct neon_type_el et
18181 = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK);
18182
18183 if (et.type == NT_invtype)
18184 first_error (BAD_EL_TYPE);
18185
18186 if (inst.cond > COND_ALWAYS)
18187 inst.pred_insn_type = INSIDE_VPT_INSN;
18188 else
18189 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18190
18191 mve_encode_qqq (0, 64);
18192}
18193
18194static void
18195do_mve_vbrsr (void)
18196{
18197 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18198 struct neon_type_el et
18199 = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18200
18201 if (inst.cond > COND_ALWAYS)
18202 inst.pred_insn_type = INSIDE_VPT_INSN;
18203 else
18204 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18205
18206 mve_encode_qqr (et.size, 0, 0);
18207}
18208
18209static void
18210do_mve_vsbc (void)
18211{
18212 neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY);
18213
18214 if (inst.cond > COND_ALWAYS)
18215 inst.pred_insn_type = INSIDE_VPT_INSN;
18216 else
18217 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18218
18219 mve_encode_qqq (1, 64);
18220}
18221
18222static void
18223do_mve_vmulh (void)
18224{
18225 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18226 struct neon_type_el et
18227 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
18228
18229 if (inst.cond > COND_ALWAYS)
18230 inst.pred_insn_type = INSIDE_VPT_INSN;
18231 else
18232 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18233
18234 mve_encode_qqq (et.type == NT_unsigned, et.size);
18235}
18236
18237static void
18238do_mve_vqdmlah (void)
18239{
18240 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18241 struct neon_type_el et
18242 = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
18243
18244 if (inst.cond > COND_ALWAYS)
18245 inst.pred_insn_type = INSIDE_VPT_INSN;
18246 else
18247 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18248
18249 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
18250}
18251
18252static void
18253do_mve_vqdmladh (void)
18254{
18255 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18256 struct neon_type_el et
18257 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18258
18259 if (inst.cond > COND_ALWAYS)
18260 inst.pred_insn_type = INSIDE_VPT_INSN;
18261 else
18262 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18263
18264 mve_encode_qqq (0, et.size);
18265}
18266
18267
18268static void
18269do_mve_vmull (void)
18270{
18271
18272 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
18273 NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
18274 if (inst.cond == COND_ALWAYS
18275 && ((unsigned)inst.instruction) == M_MNEM_vmullt)
18276 {
18277
18278 if (rs == NS_QQQ)
18279 {
18280 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18281 goto neon_vmul;
18282 }
18283 else
18284 goto neon_vmul;
18285 }
18286
18287 constraint (rs != NS_QQQ, BAD_FPU);
18288 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
18289 N_SU_32 | N_P8 | N_P16 | N_KEY);
18290
18291 /* We are dealing with MVE's vmullt. */
18292 if (et.size == 32
18293 && (inst.operands[0].reg == inst.operands[1].reg
18294 || inst.operands[0].reg == inst.operands[2].reg))
18295 as_tsktsk (BAD_MVE_SRCDEST);
18296
18297 if (inst.cond > COND_ALWAYS)
18298 inst.pred_insn_type = INSIDE_VPT_INSN;
18299 else
18300 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18301
18302 if (et.type == NT_poly)
18303 mve_encode_qqq (neon_logbits (et.size), 64);
18304 else
18305 mve_encode_qqq (et.type == NT_unsigned, et.size);
18306
18307 return;
18308
18309 neon_vmul:
18310 inst.instruction = N_MNEM_vmul;
18311 inst.cond = 0xb;
18312 if (thumb_mode)
18313 inst.pred_insn_type = INSIDE_IT_INSN;
18314 do_neon_mul ();
18315}
18316
18317static void
18318do_mve_vabav (void)
18319{
18320 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
18321
18322 if (rs == NS_NULL)
18323 return;
18324
18325 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18326 return;
18327
18328 struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8
18329 | N_S16 | N_S32 | N_U8 | N_U16
18330 | N_U32);
18331
18332 if (inst.cond > COND_ALWAYS)
18333 inst.pred_insn_type = INSIDE_VPT_INSN;
18334 else
18335 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18336
18337 mve_encode_rqq (et.type == NT_unsigned, et.size);
18338}
18339
18340static void
18341do_mve_vmladav (void)
18342{
18343 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
18344 struct neon_type_el et = neon_check_type (3, rs,
18345 N_EQK, N_EQK, N_SU_MVE | N_KEY);
18346
18347 if (et.type == NT_unsigned
18348 && (inst.instruction == M_MNEM_vmladavx
18349 || inst.instruction == M_MNEM_vmladavax
18350 || inst.instruction == M_MNEM_vmlsdav
18351 || inst.instruction == M_MNEM_vmlsdava
18352 || inst.instruction == M_MNEM_vmlsdavx
18353 || inst.instruction == M_MNEM_vmlsdavax))
18354 first_error (BAD_SIMD_TYPE);
18355
18356 constraint (inst.operands[2].reg > 14,
18357 _("MVE vector register in the range [Q0..Q7] expected"));
18358
18359 if (inst.cond > COND_ALWAYS)
18360 inst.pred_insn_type = INSIDE_VPT_INSN;
18361 else
18362 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18363
18364 if (inst.instruction == M_MNEM_vmlsdav
18365 || inst.instruction == M_MNEM_vmlsdava
18366 || inst.instruction == M_MNEM_vmlsdavx
18367 || inst.instruction == M_MNEM_vmlsdavax)
18368 inst.instruction |= (et.size == 8) << 28;
18369 else
18370 inst.instruction |= (et.size == 8) << 8;
18371
18372 mve_encode_rqq (et.type == NT_unsigned, 64);
18373 inst.instruction |= (et.size == 32) << 16;
18374}
18375
18376static void
18377do_mve_vmlaldav (void)
18378{
18379 enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL);
18380 struct neon_type_el et
18381 = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK,
18382 N_S16 | N_S32 | N_U16 | N_U32 | N_KEY);
18383
18384 if (et.type == NT_unsigned
18385 && (inst.instruction == M_MNEM_vmlsldav
18386 || inst.instruction == M_MNEM_vmlsldava
18387 || inst.instruction == M_MNEM_vmlsldavx
18388 || inst.instruction == M_MNEM_vmlsldavax))
18389 first_error (BAD_SIMD_TYPE);
18390
18391 if (inst.cond > COND_ALWAYS)
18392 inst.pred_insn_type = INSIDE_VPT_INSN;
18393 else
18394 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18395
18396 mve_encode_rrqq (et.type == NT_unsigned, et.size);
18397}
18398
18399static void
18400do_mve_vrmlaldavh (void)
18401{
18402 struct neon_type_el et;
18403 if (inst.instruction == M_MNEM_vrmlsldavh
18404 || inst.instruction == M_MNEM_vrmlsldavha
18405 || inst.instruction == M_MNEM_vrmlsldavhx
18406 || inst.instruction == M_MNEM_vrmlsldavhax)
18407 {
18408 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18409 if (inst.operands[1].reg == REG_SP)
18410 as_tsktsk (MVE_BAD_SP);
18411 }
18412 else
18413 {
18414 if (inst.instruction == M_MNEM_vrmlaldavhx
18415 || inst.instruction == M_MNEM_vrmlaldavhax)
18416 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18417 else
18418 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK,
18419 N_U32 | N_S32 | N_KEY);
18420 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18421 with vmax/min instructions, making the use of SP in assembly really
18422 nonsensical, so instead of issuing a warning like we do for other uses
18423 of SP for the odd register operand we error out. */
18424 constraint (inst.operands[1].reg == REG_SP, BAD_SP);
18425 }
18426
18427 /* Make sure we still check the second operand is an odd one and that PC is
18428 disallowed. This because we are parsing for any GPR operand, to be able
18429 to distinguish between giving a warning or an error for SP as described
18430 above. */
18431 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
18432 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
18433
18434 if (inst.cond > COND_ALWAYS)
18435 inst.pred_insn_type = INSIDE_VPT_INSN;
18436 else
18437 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18438
18439 mve_encode_rrqq (et.type == NT_unsigned, 0);
18440}
18441
18442
18443static void
18444do_mve_vmaxnmv (void)
18445{
18446 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18447 struct neon_type_el et
18448 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
18449
18450 if (inst.cond > COND_ALWAYS)
18451 inst.pred_insn_type = INSIDE_VPT_INSN;
18452 else
18453 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18454
18455 if (inst.operands[0].reg == REG_SP)
18456 as_tsktsk (MVE_BAD_SP);
18457 else if (inst.operands[0].reg == REG_PC)
18458 as_tsktsk (MVE_BAD_PC);
18459
18460 mve_encode_rq (et.size == 16, 64);
18461}
18462
18463static void
18464do_mve_vmaxv (void)
18465{
18466 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18467 struct neon_type_el et;
18468
18469 if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
18470 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
18471 else
18472 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18473
18474 if (inst.cond > COND_ALWAYS)
18475 inst.pred_insn_type = INSIDE_VPT_INSN;
18476 else
18477 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18478
18479 if (inst.operands[0].reg == REG_SP)
18480 as_tsktsk (MVE_BAD_SP);
18481 else if (inst.operands[0].reg == REG_PC)
18482 as_tsktsk (MVE_BAD_PC);
18483
18484 mve_encode_rq (et.type == NT_unsigned, et.size);
18485}
18486
18487
18488static void
18489do_neon_qrdmlah (void)
18490{
18491 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
18492 return;
18493 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18494 {
18495 /* Check we're on the correct architecture. */
18496 if (!mark_feature_used (&fpu_neon_ext_armv8))
18497 inst.error
18498 = _("instruction form not available on this architecture.");
18499 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
18500 {
18501 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18502 record_feature_use (&fpu_neon_ext_v8_1);
18503 }
18504 if (inst.operands[2].isscalar)
18505 {
18506 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
18507 struct neon_type_el et = neon_check_type (3, rs,
18508 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18509 NEON_ENCODE (SCALAR, inst);
18510 neon_mul_mac (et, neon_quad (rs));
18511 }
18512 else
18513 {
18514 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18515 struct neon_type_el et = neon_check_type (3, rs,
18516 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18517 NEON_ENCODE (INTEGER, inst);
18518 /* The U bit (rounding) comes from bit mask. */
18519 neon_three_same (neon_quad (rs), 0, et.size);
18520 }
18521 }
18522 else
18523 {
18524 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18525 struct neon_type_el et
18526 = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
18527
18528 NEON_ENCODE (INTEGER, inst);
18529 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
18530 }
18531}
18532
18533static void
18534do_neon_fcmp_absolute (void)
18535{
18536 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18537 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18538 N_F_16_32 | N_KEY);
18539 /* Size field comes from bit mask. */
18540 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
18541}
18542
18543static void
18544do_neon_fcmp_absolute_inv (void)
18545{
18546 neon_exchange_operands ();
18547 do_neon_fcmp_absolute ();
18548}
18549
18550static void
18551do_neon_step (void)
18552{
18553 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18554 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18555 N_F_16_32 | N_KEY);
18556 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
18557}
18558
18559static void
18560do_neon_abs_neg (void)
18561{
18562 enum neon_shape rs;
18563 struct neon_type_el et;
18564
18565 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
18566 return;
18567
18568 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
18569 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
18570
18571 if (!check_simd_pred_availability (et.type == NT_float,
18572 NEON_CHECK_ARCH | NEON_CHECK_CC))
18573 return;
18574
18575 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18576 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18577 inst.instruction |= LOW4 (inst.operands[1].reg);
18578 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18579 inst.instruction |= neon_quad (rs) << 6;
18580 inst.instruction |= (et.type == NT_float) << 10;
18581 inst.instruction |= neon_logbits (et.size) << 18;
18582
18583 neon_dp_fixup (&inst);
18584}
18585
18586static void
18587do_neon_sli (void)
18588{
18589 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
18590 return;
18591
18592 enum neon_shape rs;
18593 struct neon_type_el et;
18594 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18595 {
18596 rs = neon_select_shape (NS_QQI, NS_NULL);
18597 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18598 }
18599 else
18600 {
18601 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18602 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18603 }
18604
18605
18606 int imm = inst.operands[2].imm;
18607 constraint (imm < 0 || (unsigned)imm >= et.size,
18608 _("immediate out of range for insert"));
18609 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
18610}
18611
18612static void
18613do_neon_sri (void)
18614{
18615 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
18616 return;
18617
18618 enum neon_shape rs;
18619 struct neon_type_el et;
18620 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18621 {
18622 rs = neon_select_shape (NS_QQI, NS_NULL);
18623 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18624 }
18625 else
18626 {
18627 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18628 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18629 }
18630
18631 int imm = inst.operands[2].imm;
18632 constraint (imm < 1 || (unsigned)imm > et.size,
18633 _("immediate out of range for insert"));
18634 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
18635}
18636
18637static void
18638do_neon_qshlu_imm (void)
18639{
18640 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
18641 return;
18642
18643 enum neon_shape rs;
18644 struct neon_type_el et;
18645 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18646 {
18647 rs = neon_select_shape (NS_QQI, NS_NULL);
18648 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18649 }
18650 else
18651 {
18652 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18653 et = neon_check_type (2, rs, N_EQK | N_UNS,
18654 N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
18655 }
18656
18657 int imm = inst.operands[2].imm;
18658 constraint (imm < 0 || (unsigned)imm >= et.size,
18659 _("immediate out of range for shift"));
18660 /* Only encodes the 'U present' variant of the instruction.
18661 In this case, signed types have OP (bit 8) set to 0.
18662 Unsigned types have OP set to 1. */
18663 inst.instruction |= (et.type == NT_unsigned) << 8;
18664 /* The rest of the bits are the same as other immediate shifts. */
18665 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
18666}
18667
18668static void
18669do_neon_qmovn (void)
18670{
18671 struct neon_type_el et = neon_check_type (2, NS_DQ,
18672 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18673 /* Saturating move where operands can be signed or unsigned, and the
18674 destination has the same signedness. */
18675 NEON_ENCODE (INTEGER, inst);
18676 if (et.type == NT_unsigned)
18677 inst.instruction |= 0xc0;
18678 else
18679 inst.instruction |= 0x80;
18680 neon_two_same (0, 1, et.size / 2);
18681}
18682
18683static void
18684do_neon_qmovun (void)
18685{
18686 struct neon_type_el et = neon_check_type (2, NS_DQ,
18687 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18688 /* Saturating move with unsigned results. Operands must be signed. */
18689 NEON_ENCODE (INTEGER, inst);
18690 neon_two_same (0, 1, et.size / 2);
18691}
18692
18693static void
18694do_neon_rshift_sat_narrow (void)
18695{
18696 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18697 or unsigned. If operands are unsigned, results must also be unsigned. */
18698 struct neon_type_el et = neon_check_type (2, NS_DQI,
18699 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18700 int imm = inst.operands[2].imm;
18701 /* This gets the bounds check, size encoding and immediate bits calculation
18702 right. */
18703 et.size /= 2;
18704
18705 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18706 VQMOVN.I<size> <Dd>, <Qm>. */
18707 if (imm == 0)
18708 {
18709 inst.operands[2].present = 0;
18710 inst.instruction = N_MNEM_vqmovn;
18711 do_neon_qmovn ();
18712 return;
18713 }
18714
18715 constraint (imm < 1 || (unsigned)imm > et.size,
18716 _("immediate out of range"));
18717 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
18718}
18719
18720static void
18721do_neon_rshift_sat_narrow_u (void)
18722{
18723 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18724 or unsigned. If operands are unsigned, results must also be unsigned. */
18725 struct neon_type_el et = neon_check_type (2, NS_DQI,
18726 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18727 int imm = inst.operands[2].imm;
18728 /* This gets the bounds check, size encoding and immediate bits calculation
18729 right. */
18730 et.size /= 2;
18731
18732 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18733 VQMOVUN.I<size> <Dd>, <Qm>. */
18734 if (imm == 0)
18735 {
18736 inst.operands[2].present = 0;
18737 inst.instruction = N_MNEM_vqmovun;
18738 do_neon_qmovun ();
18739 return;
18740 }
18741
18742 constraint (imm < 1 || (unsigned)imm > et.size,
18743 _("immediate out of range"));
18744 /* FIXME: The manual is kind of unclear about what value U should have in
18745 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18746 must be 1. */
18747 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
18748}
18749
18750static void
18751do_neon_movn (void)
18752{
18753 struct neon_type_el et = neon_check_type (2, NS_DQ,
18754 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
18755 NEON_ENCODE (INTEGER, inst);
18756 neon_two_same (0, 1, et.size / 2);
18757}
18758
18759static void
18760do_neon_rshift_narrow (void)
18761{
18762 struct neon_type_el et = neon_check_type (2, NS_DQI,
18763 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
18764 int imm = inst.operands[2].imm;
18765 /* This gets the bounds check, size encoding and immediate bits calculation
18766 right. */
18767 et.size /= 2;
18768
18769 /* If immediate is zero then we are a pseudo-instruction for
18770 VMOVN.I<size> <Dd>, <Qm> */
18771 if (imm == 0)
18772 {
18773 inst.operands[2].present = 0;
18774 inst.instruction = N_MNEM_vmovn;
18775 do_neon_movn ();
18776 return;
18777 }
18778
18779 constraint (imm < 1 || (unsigned)imm > et.size,
18780 _("immediate out of range for narrowing operation"));
18781 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
18782}
18783
18784static void
18785do_neon_shll (void)
18786{
18787 /* FIXME: Type checking when lengthening. */
18788 struct neon_type_el et = neon_check_type (2, NS_QDI,
18789 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
18790 unsigned imm = inst.operands[2].imm;
18791
18792 if (imm == et.size)
18793 {
18794 /* Maximum shift variant. */
18795 NEON_ENCODE (INTEGER, inst);
18796 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18797 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18798 inst.instruction |= LOW4 (inst.operands[1].reg);
18799 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18800 inst.instruction |= neon_logbits (et.size) << 18;
18801
18802 neon_dp_fixup (&inst);
18803 }
18804 else
18805 {
18806 /* A more-specific type check for non-max versions. */
18807 et = neon_check_type (2, NS_QDI,
18808 N_EQK | N_DBL, N_SU_32 | N_KEY);
18809 NEON_ENCODE (IMMED, inst);
18810 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
18811 }
18812}
18813
18814/* Check the various types for the VCVT instruction, and return which version
18815 the current instruction is. */
18816
18817#define CVT_FLAVOUR_VAR \
18818 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18819 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18820 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18821 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18822 /* Half-precision conversions. */ \
18823 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18824 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18825 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18826 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18827 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18828 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18829 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18830 Compared with single/double precision variants, only the co-processor \
18831 field is different, so the encoding flow is reused here. */ \
18832 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18833 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18834 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18835 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18836 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18837 /* VFP instructions. */ \
18838 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18839 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18840 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18841 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18842 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18843 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18844 /* VFP instructions with bitshift. */ \
18845 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18846 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18847 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18848 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18849 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18850 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18851 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18852 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18853
18854#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18855 neon_cvt_flavour_##C,
18856
18857/* The different types of conversions we can do. */
18858enum neon_cvt_flavour
18859{
18860 CVT_FLAVOUR_VAR
18861 neon_cvt_flavour_invalid,
18862 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
18863};
18864
18865#undef CVT_VAR
18866
18867static enum neon_cvt_flavour
18868get_neon_cvt_flavour (enum neon_shape rs)
18869{
18870#define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18871 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18872 if (et.type != NT_invtype) \
18873 { \
18874 inst.error = NULL; \
18875 return (neon_cvt_flavour_##C); \
18876 }
18877
18878 struct neon_type_el et;
18879 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
18880 || rs == NS_FF) ? N_VFP : 0;
18881 /* The instruction versions which take an immediate take one register
18882 argument, which is extended to the width of the full register. Thus the
18883 "source" and "destination" registers must have the same width. Hack that
18884 here by making the size equal to the key (wider, in this case) operand. */
18885 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
18886
18887 CVT_FLAVOUR_VAR;
18888
18889 return neon_cvt_flavour_invalid;
18890#undef CVT_VAR
18891}
18892
18893enum neon_cvt_mode
18894{
18895 neon_cvt_mode_a,
18896 neon_cvt_mode_n,
18897 neon_cvt_mode_p,
18898 neon_cvt_mode_m,
18899 neon_cvt_mode_z,
18900 neon_cvt_mode_x,
18901 neon_cvt_mode_r
18902};
18903
18904/* Neon-syntax VFP conversions. */
18905
18906static void
18907do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
18908{
18909 const char *opname = 0;
18910
18911 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
18912 || rs == NS_FHI || rs == NS_HFI)
18913 {
18914 /* Conversions with immediate bitshift. */
18915 const char *enc[] =
18916 {
18917#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18918 CVT_FLAVOUR_VAR
18919 NULL
18920#undef CVT_VAR
18921 };
18922
18923 if (flavour < (int) ARRAY_SIZE (enc))
18924 {
18925 opname = enc[flavour];
18926 constraint (inst.operands[0].reg != inst.operands[1].reg,
18927 _("operands 0 and 1 must be the same register"));
18928 inst.operands[1] = inst.operands[2];
18929 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
18930 }
18931 }
18932 else
18933 {
18934 /* Conversions without bitshift. */
18935 const char *enc[] =
18936 {
18937#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18938 CVT_FLAVOUR_VAR
18939 NULL
18940#undef CVT_VAR
18941 };
18942
18943 if (flavour < (int) ARRAY_SIZE (enc))
18944 opname = enc[flavour];
18945 }
18946
18947 if (opname)
18948 do_vfp_nsyn_opcode (opname);
18949
18950 /* ARMv8.2 fp16 VCVT instruction. */
18951 if (flavour == neon_cvt_flavour_s32_f16
18952 || flavour == neon_cvt_flavour_u32_f16
18953 || flavour == neon_cvt_flavour_f16_u32
18954 || flavour == neon_cvt_flavour_f16_s32)
18955 do_scalar_fp16_v82_encode ();
18956}
18957
18958static void
18959do_vfp_nsyn_cvtz (void)
18960{
18961 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
18962 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
18963 const char *enc[] =
18964 {
18965#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18966 CVT_FLAVOUR_VAR
18967 NULL
18968#undef CVT_VAR
18969 };
18970
18971 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
18972 do_vfp_nsyn_opcode (enc[flavour]);
18973}
18974
18975static void
18976do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
18977 enum neon_cvt_mode mode)
18978{
18979 int sz, op;
18980 int rm;
18981
18982 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18983 D register operands. */
18984 if (flavour == neon_cvt_flavour_s32_f64
18985 || flavour == neon_cvt_flavour_u32_f64)
18986 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18987 _(BAD_FPU));
18988
18989 if (flavour == neon_cvt_flavour_s32_f16
18990 || flavour == neon_cvt_flavour_u32_f16)
18991 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
18992 _(BAD_FP16));
18993
18994 set_pred_insn_type (OUTSIDE_PRED_INSN);
18995
18996 switch (flavour)
18997 {
18998 case neon_cvt_flavour_s32_f64:
18999 sz = 1;
19000 op = 1;
19001 break;
19002 case neon_cvt_flavour_s32_f32:
19003 sz = 0;
19004 op = 1;
19005 break;
19006 case neon_cvt_flavour_s32_f16:
19007 sz = 0;
19008 op = 1;
19009 break;
19010 case neon_cvt_flavour_u32_f64:
19011 sz = 1;
19012 op = 0;
19013 break;
19014 case neon_cvt_flavour_u32_f32:
19015 sz = 0;
19016 op = 0;
19017 break;
19018 case neon_cvt_flavour_u32_f16:
19019 sz = 0;
19020 op = 0;
19021 break;
19022 default:
19023 first_error (_("invalid instruction shape"));
19024 return;
19025 }
19026
19027 switch (mode)
19028 {
19029 case neon_cvt_mode_a: rm = 0; break;
19030 case neon_cvt_mode_n: rm = 1; break;
19031 case neon_cvt_mode_p: rm = 2; break;
19032 case neon_cvt_mode_m: rm = 3; break;
19033 default: first_error (_("invalid rounding mode")); return;
19034 }
19035
19036 NEON_ENCODE (FPV8, inst);
19037 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
19038 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
19039 inst.instruction |= sz << 8;
19040
19041 /* ARMv8.2 fp16 VCVT instruction. */
19042 if (flavour == neon_cvt_flavour_s32_f16
19043 ||flavour == neon_cvt_flavour_u32_f16)
19044 do_scalar_fp16_v82_encode ();
19045 inst.instruction |= op << 7;
19046 inst.instruction |= rm << 16;
19047 inst.instruction |= 0xf0000000;
19048 inst.is_neon = TRUE;
19049}
19050
19051static void
19052do_neon_cvt_1 (enum neon_cvt_mode mode)
19053{
19054 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
19055 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
19056 NS_FH, NS_HF, NS_FHI, NS_HFI,
19057 NS_NULL);
19058 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
19059
19060 if (flavour == neon_cvt_flavour_invalid)
19061 return;
19062
19063 /* PR11109: Handle round-to-zero for VCVT conversions. */
19064 if (mode == neon_cvt_mode_z
19065 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
19066 && (flavour == neon_cvt_flavour_s16_f16
19067 || flavour == neon_cvt_flavour_u16_f16
19068 || flavour == neon_cvt_flavour_s32_f32
19069 || flavour == neon_cvt_flavour_u32_f32
19070 || flavour == neon_cvt_flavour_s32_f64
19071 || flavour == neon_cvt_flavour_u32_f64)
19072 && (rs == NS_FD || rs == NS_FF))
19073 {
19074 do_vfp_nsyn_cvtz ();
19075 return;
19076 }
19077
19078 /* ARMv8.2 fp16 VCVT conversions. */
19079 if (mode == neon_cvt_mode_z
19080 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
19081 && (flavour == neon_cvt_flavour_s32_f16
19082 || flavour == neon_cvt_flavour_u32_f16)
19083 && (rs == NS_FH))
19084 {
19085 do_vfp_nsyn_cvtz ();
19086 do_scalar_fp16_v82_encode ();
19087 return;
19088 }
19089
19090 if ((rs == NS_FD || rs == NS_QQI) && mode == neon_cvt_mode_n
19091 && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19092 {
19093 /* We are dealing with vcvt with the 'ne' condition. */
19094 inst.cond = 0x1;
19095 inst.instruction = N_MNEM_vcvt;
19096 do_neon_cvt_1 (neon_cvt_mode_z);
19097 return;
19098 }
19099
19100 /* VFP rather than Neon conversions. */
19101 if (flavour >= neon_cvt_flavour_first_fp)
19102 {
19103 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
19104 do_vfp_nsyn_cvt (rs, flavour);
19105 else
19106 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
19107
19108 return;
19109 }
19110
19111 switch (rs)
19112 {
19113 case NS_QQI:
19114 if (mode == neon_cvt_mode_z
19115 && (flavour == neon_cvt_flavour_f16_s16
19116 || flavour == neon_cvt_flavour_f16_u16
19117 || flavour == neon_cvt_flavour_s16_f16
19118 || flavour == neon_cvt_flavour_u16_f16
19119 || flavour == neon_cvt_flavour_f32_u32
19120 || flavour == neon_cvt_flavour_f32_s32
19121 || flavour == neon_cvt_flavour_s32_f32
19122 || flavour == neon_cvt_flavour_u32_f32))
19123 {
19124 if (!check_simd_pred_availability (TRUE,
19125 NEON_CHECK_CC | NEON_CHECK_ARCH))
19126 return;
19127 }
19128 /* fall through. */
19129 case NS_DDI:
19130 {
19131 unsigned immbits;
19132 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19133 0x0000100, 0x1000100, 0x0, 0x1000000};
19134
19135 if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19136 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19137 return;
19138
19139 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19140 {
19141 constraint (inst.operands[2].present && inst.operands[2].imm == 0,
19142 _("immediate value out of range"));
19143 switch (flavour)
19144 {
19145 case neon_cvt_flavour_f16_s16:
19146 case neon_cvt_flavour_f16_u16:
19147 case neon_cvt_flavour_s16_f16:
19148 case neon_cvt_flavour_u16_f16:
19149 constraint (inst.operands[2].imm > 16,
19150 _("immediate value out of range"));
19151 break;
19152 case neon_cvt_flavour_f32_u32:
19153 case neon_cvt_flavour_f32_s32:
19154 case neon_cvt_flavour_s32_f32:
19155 case neon_cvt_flavour_u32_f32:
19156 constraint (inst.operands[2].imm > 32,
19157 _("immediate value out of range"));
19158 break;
19159 default:
19160 inst.error = BAD_FPU;
19161 return;
19162 }
19163 }
19164
19165 /* Fixed-point conversion with #0 immediate is encoded as an
19166 integer conversion. */
19167 if (inst.operands[2].present && inst.operands[2].imm == 0)
19168 goto int_encode;
19169 NEON_ENCODE (IMMED, inst);
19170 if (flavour != neon_cvt_flavour_invalid)
19171 inst.instruction |= enctab[flavour];
19172 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19173 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19174 inst.instruction |= LOW4 (inst.operands[1].reg);
19175 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19176 inst.instruction |= neon_quad (rs) << 6;
19177 inst.instruction |= 1 << 21;
19178 if (flavour < neon_cvt_flavour_s16_f16)
19179 {
19180 inst.instruction |= 1 << 21;
19181 immbits = 32 - inst.operands[2].imm;
19182 inst.instruction |= immbits << 16;
19183 }
19184 else
19185 {
19186 inst.instruction |= 3 << 20;
19187 immbits = 16 - inst.operands[2].imm;
19188 inst.instruction |= immbits << 16;
19189 inst.instruction &= ~(1 << 9);
19190 }
19191
19192 neon_dp_fixup (&inst);
19193 }
19194 break;
19195
19196 case NS_QQ:
19197 if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
19198 || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
19199 && (flavour == neon_cvt_flavour_s16_f16
19200 || flavour == neon_cvt_flavour_u16_f16
19201 || flavour == neon_cvt_flavour_s32_f32
19202 || flavour == neon_cvt_flavour_u32_f32))
19203 {
19204 if (!check_simd_pred_availability (TRUE,
19205 NEON_CHECK_CC | NEON_CHECK_ARCH8))
19206 return;
19207 }
19208 else if (mode == neon_cvt_mode_z
19209 && (flavour == neon_cvt_flavour_f16_s16
19210 || flavour == neon_cvt_flavour_f16_u16
19211 || flavour == neon_cvt_flavour_s16_f16
19212 || flavour == neon_cvt_flavour_u16_f16
19213 || flavour == neon_cvt_flavour_f32_u32
19214 || flavour == neon_cvt_flavour_f32_s32
19215 || flavour == neon_cvt_flavour_s32_f32
19216 || flavour == neon_cvt_flavour_u32_f32))
19217 {
19218 if (!check_simd_pred_availability (TRUE,
19219 NEON_CHECK_CC | NEON_CHECK_ARCH))
19220 return;
19221 }
19222 /* fall through. */
19223 case NS_DD:
19224 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
19225 {
19226
19227 NEON_ENCODE (FLOAT, inst);
19228 if (!check_simd_pred_availability (TRUE,
19229 NEON_CHECK_CC | NEON_CHECK_ARCH8))
19230 return;
19231
19232 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19233 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19234 inst.instruction |= LOW4 (inst.operands[1].reg);
19235 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19236 inst.instruction |= neon_quad (rs) << 6;
19237 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
19238 || flavour == neon_cvt_flavour_u32_f32) << 7;
19239 inst.instruction |= mode << 8;
19240 if (flavour == neon_cvt_flavour_u16_f16
19241 || flavour == neon_cvt_flavour_s16_f16)
19242 /* Mask off the original size bits and reencode them. */
19243 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
19244
19245 if (thumb_mode)
19246 inst.instruction |= 0xfc000000;
19247 else
19248 inst.instruction |= 0xf0000000;
19249 }
19250 else
19251 {
19252 int_encode:
19253 {
19254 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
19255 0x100, 0x180, 0x0, 0x080};
19256
19257 NEON_ENCODE (INTEGER, inst);
19258
19259 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19260 {
19261 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19262 return;
19263 }
19264
19265 if (flavour != neon_cvt_flavour_invalid)
19266 inst.instruction |= enctab[flavour];
19267
19268 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19269 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19270 inst.instruction |= LOW4 (inst.operands[1].reg);
19271 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19272 inst.instruction |= neon_quad (rs) << 6;
19273 if (flavour >= neon_cvt_flavour_s16_f16
19274 && flavour <= neon_cvt_flavour_f16_u16)
19275 /* Half precision. */
19276 inst.instruction |= 1 << 18;
19277 else
19278 inst.instruction |= 2 << 18;
19279
19280 neon_dp_fixup (&inst);
19281 }
19282 }
19283 break;
19284
19285 /* Half-precision conversions for Advanced SIMD -- neon. */
19286 case NS_QD:
19287 case NS_DQ:
19288 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19289 return;
19290
19291 if ((rs == NS_DQ)
19292 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
19293 {
19294 as_bad (_("operand size must match register width"));
19295 break;
19296 }
19297
19298 if ((rs == NS_QD)
19299 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
19300 {
19301 as_bad (_("operand size must match register width"));
19302 break;
19303 }
19304
19305 if (rs == NS_DQ)
19306 {
19307 if (flavour == neon_cvt_flavour_bf16_f32)
19308 {
19309 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8) == FAIL)
19310 return;
19311 constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16));
19312 /* VCVT.bf16.f32. */
19313 inst.instruction = 0x11b60640;
19314 }
19315 else
19316 /* VCVT.f16.f32. */
19317 inst.instruction = 0x3b60600;
19318 }
19319 else
19320 /* VCVT.f32.f16. */
19321 inst.instruction = 0x3b60700;
19322
19323 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19324 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19325 inst.instruction |= LOW4 (inst.operands[1].reg);
19326 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19327 neon_dp_fixup (&inst);
19328 break;
19329
19330 default:
19331 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19332 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
19333 do_vfp_nsyn_cvt (rs, flavour);
19334 else
19335 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
19336 }
19337}
19338
19339static void
19340do_neon_cvtr (void)
19341{
19342 do_neon_cvt_1 (neon_cvt_mode_x);
19343}
19344
19345static void
19346do_neon_cvt (void)
19347{
19348 do_neon_cvt_1 (neon_cvt_mode_z);
19349}
19350
19351static void
19352do_neon_cvta (void)
19353{
19354 do_neon_cvt_1 (neon_cvt_mode_a);
19355}
19356
19357static void
19358do_neon_cvtn (void)
19359{
19360 do_neon_cvt_1 (neon_cvt_mode_n);
19361}
19362
19363static void
19364do_neon_cvtp (void)
19365{
19366 do_neon_cvt_1 (neon_cvt_mode_p);
19367}
19368
19369static void
19370do_neon_cvtm (void)
19371{
19372 do_neon_cvt_1 (neon_cvt_mode_m);
19373}
19374
19375static void
19376do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
19377{
19378 if (is_double)
19379 mark_feature_used (&fpu_vfp_ext_armv8);
19380
19381 encode_arm_vfp_reg (inst.operands[0].reg,
19382 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
19383 encode_arm_vfp_reg (inst.operands[1].reg,
19384 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
19385 inst.instruction |= to ? 0x10000 : 0;
19386 inst.instruction |= t ? 0x80 : 0;
19387 inst.instruction |= is_double ? 0x100 : 0;
19388 do_vfp_cond_or_thumb ();
19389}
19390
19391static void
19392do_neon_cvttb_1 (bfd_boolean t)
19393{
19394 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
19395 NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
19396
19397 if (rs == NS_NULL)
19398 return;
19399 else if (rs == NS_QQ || rs == NS_QQI)
19400 {
19401 int single_to_half = 0;
19402 if (!check_simd_pred_availability (TRUE, NEON_CHECK_ARCH))
19403 return;
19404
19405 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
19406
19407 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19408 && (flavour == neon_cvt_flavour_u16_f16
19409 || flavour == neon_cvt_flavour_s16_f16
19410 || flavour == neon_cvt_flavour_f16_s16
19411 || flavour == neon_cvt_flavour_f16_u16
19412 || flavour == neon_cvt_flavour_u32_f32
19413 || flavour == neon_cvt_flavour_s32_f32
19414 || flavour == neon_cvt_flavour_f32_s32
19415 || flavour == neon_cvt_flavour_f32_u32))
19416 {
19417 inst.cond = 0xf;
19418 inst.instruction = N_MNEM_vcvt;
19419 set_pred_insn_type (INSIDE_VPT_INSN);
19420 do_neon_cvt_1 (neon_cvt_mode_z);
19421 return;
19422 }
19423 else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
19424 single_to_half = 1;
19425 else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
19426 {
19427 first_error (BAD_FPU);
19428 return;
19429 }
19430
19431 inst.instruction = 0xee3f0e01;
19432 inst.instruction |= single_to_half << 28;
19433 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19434 inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
19435 inst.instruction |= t << 12;
19436 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19437 inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
19438 inst.is_neon = 1;
19439 }
19440 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
19441 {
19442 inst.error = NULL;
19443 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
19444 }
19445 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
19446 {
19447 inst.error = NULL;
19448 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
19449 }
19450 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
19451 {
19452 /* The VCVTB and VCVTT instructions with D-register operands
19453 don't work for SP only targets. */
19454 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19455 _(BAD_FPU));
19456
19457 inst.error = NULL;
19458 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
19459 }
19460 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
19461 {
19462 /* The VCVTB and VCVTT instructions with D-register operands
19463 don't work for SP only targets. */
19464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19465 _(BAD_FPU));
19466
19467 inst.error = NULL;
19468 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
19469 }
19470 else if (neon_check_type (2, rs, N_BF16 | N_VFP, N_F32).type != NT_invtype)
19471 {
19472 constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16));
19473 inst.error = NULL;
19474 inst.instruction |= (1 << 8);
19475 inst.instruction &= ~(1 << 9);
19476 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
19477 }
19478 else
19479 return;
19480}
19481
19482static void
19483do_neon_cvtb (void)
19484{
19485 do_neon_cvttb_1 (FALSE);
19486}
19487
19488
19489static void
19490do_neon_cvtt (void)
19491{
19492 do_neon_cvttb_1 (TRUE);
19493}
19494
19495static void
19496neon_move_immediate (void)
19497{
19498 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
19499 struct neon_type_el et = neon_check_type (2, rs,
19500 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
19501 unsigned immlo, immhi = 0, immbits;
19502 int op, cmode, float_p;
19503
19504 constraint (et.type == NT_invtype,
19505 _("operand size must be specified for immediate VMOV"));
19506
19507 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19508 op = (inst.instruction & (1 << 5)) != 0;
19509
19510 immlo = inst.operands[1].imm;
19511 if (inst.operands[1].regisimm)
19512 immhi = inst.operands[1].reg;
19513
19514 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
19515 _("immediate has bits set outside the operand size"));
19516
19517 float_p = inst.operands[1].immisfloat;
19518
19519 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
19520 et.size, et.type)) == FAIL)
19521 {
19522 /* Invert relevant bits only. */
19523 neon_invert_size (&immlo, &immhi, et.size);
19524 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19525 with one or the other; those cases are caught by
19526 neon_cmode_for_move_imm. */
19527 op = !op;
19528 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
19529 &op, et.size, et.type)) == FAIL)
19530 {
19531 first_error (_("immediate out of range"));
19532 return;
19533 }
19534 }
19535
19536 inst.instruction &= ~(1 << 5);
19537 inst.instruction |= op << 5;
19538
19539 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19540 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19541 inst.instruction |= neon_quad (rs) << 6;
19542 inst.instruction |= cmode << 8;
19543
19544 neon_write_immbits (immbits);
19545}
19546
19547static void
19548do_neon_mvn (void)
19549{
19550 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
19551 return;
19552
19553 if (inst.operands[1].isreg)
19554 {
19555 enum neon_shape rs;
19556 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19557 rs = neon_select_shape (NS_QQ, NS_NULL);
19558 else
19559 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19560
19561 NEON_ENCODE (INTEGER, inst);
19562 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19563 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19564 inst.instruction |= LOW4 (inst.operands[1].reg);
19565 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19566 inst.instruction |= neon_quad (rs) << 6;
19567 }
19568 else
19569 {
19570 NEON_ENCODE (IMMED, inst);
19571 neon_move_immediate ();
19572 }
19573
19574 neon_dp_fixup (&inst);
19575
19576 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19577 {
19578 constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU);
19579 }
19580}
19581
19582/* Encode instructions of form:
19583
19584 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19585 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19586
19587static void
19588neon_mixed_length (struct neon_type_el et, unsigned size)
19589{
19590 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19591 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19592 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19593 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19594 inst.instruction |= LOW4 (inst.operands[2].reg);
19595 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19596 inst.instruction |= (et.type == NT_unsigned) << 24;
19597 inst.instruction |= neon_logbits (size) << 20;
19598
19599 neon_dp_fixup (&inst);
19600}
19601
19602static void
19603do_neon_dyadic_long (void)
19604{
19605 enum neon_shape rs = neon_select_shape (NS_QDD, NS_HHH, NS_FFF, NS_DDD, NS_NULL);
19606 if (rs == NS_QDD)
19607 {
19608 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
19609 return;
19610
19611 NEON_ENCODE (INTEGER, inst);
19612 /* FIXME: Type checking for lengthening op. */
19613 struct neon_type_el et = neon_check_type (3, NS_QDD,
19614 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
19615 neon_mixed_length (et, et.size);
19616 }
19617 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19618 && (inst.cond == 0xf || inst.cond == 0x10))
19619 {
19620 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19621 in an IT block with le/lt conditions. */
19622
19623 if (inst.cond == 0xf)
19624 inst.cond = 0xb;
19625 else if (inst.cond == 0x10)
19626 inst.cond = 0xd;
19627
19628 inst.pred_insn_type = INSIDE_IT_INSN;
19629
19630 if (inst.instruction == N_MNEM_vaddl)
19631 {
19632 inst.instruction = N_MNEM_vadd;
19633 do_neon_addsub_if_i ();
19634 }
19635 else if (inst.instruction == N_MNEM_vsubl)
19636 {
19637 inst.instruction = N_MNEM_vsub;
19638 do_neon_addsub_if_i ();
19639 }
19640 else if (inst.instruction == N_MNEM_vabdl)
19641 {
19642 inst.instruction = N_MNEM_vabd;
19643 do_neon_dyadic_if_su ();
19644 }
19645 }
19646 else
19647 first_error (BAD_FPU);
19648}
19649
19650static void
19651do_neon_abal (void)
19652{
19653 struct neon_type_el et = neon_check_type (3, NS_QDD,
19654 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
19655 neon_mixed_length (et, et.size);
19656}
19657
19658static void
19659neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
19660{
19661 if (inst.operands[2].isscalar)
19662 {
19663 struct neon_type_el et = neon_check_type (3, NS_QDS,
19664 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
19665 NEON_ENCODE (SCALAR, inst);
19666 neon_mul_mac (et, et.type == NT_unsigned);
19667 }
19668 else
19669 {
19670 struct neon_type_el et = neon_check_type (3, NS_QDD,
19671 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
19672 NEON_ENCODE (INTEGER, inst);
19673 neon_mixed_length (et, et.size);
19674 }
19675}
19676
19677static void
19678do_neon_mac_maybe_scalar_long (void)
19679{
19680 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
19681}
19682
19683/* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19684 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19685
19686static unsigned
19687neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
19688{
19689 unsigned regno = NEON_SCALAR_REG (scalar);
19690 unsigned elno = NEON_SCALAR_INDEX (scalar);
19691
19692 if (quad_p)
19693 {
19694 if (regno > 7 || elno > 3)
19695 goto bad_scalar;
19696
19697 return ((regno & 0x7)
19698 | ((elno & 0x1) << 3)
19699 | (((elno >> 1) & 0x1) << 5));
19700 }
19701 else
19702 {
19703 if (regno > 15 || elno > 1)
19704 goto bad_scalar;
19705
19706 return (((regno & 0x1) << 5)
19707 | ((regno >> 1) & 0x7)
19708 | ((elno & 0x1) << 3));
19709 }
19710
19711 bad_scalar:
19712 first_error (_("scalar out of range for multiply instruction"));
19713 return 0;
19714}
19715
19716static void
19717do_neon_fmac_maybe_scalar_long (int subtype)
19718{
19719 enum neon_shape rs;
19720 int high8;
19721 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19722 field (bits[21:20]) has different meaning. For scalar index variant, it's
19723 used to differentiate add and subtract, otherwise it's with fixed value
19724 0x2. */
19725 int size = -1;
19726
19727 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19728 be a scalar index register. */
19729 if (inst.operands[2].isscalar)
19730 {
19731 high8 = 0xfe000000;
19732 if (subtype)
19733 size = 16;
19734 rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
19735 }
19736 else
19737 {
19738 high8 = 0xfc000000;
19739 size = 32;
19740 if (subtype)
19741 inst.instruction |= (0x1 << 23);
19742 rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
19743 }
19744
19745
19746 if (inst.cond != COND_ALWAYS)
19747 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19748 "behaviour is UNPREDICTABLE"));
19749
19750 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
19751 _(BAD_FP16));
19752
19753 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
19754 _(BAD_FPU));
19755
19756 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19757 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19758 so we simply pass -1 as size. */
19759 unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
19760 neon_three_same (quad_p, 0, size);
19761
19762 /* Undo neon_dp_fixup. Redo the high eight bits. */
19763 inst.instruction &= 0x00ffffff;
19764 inst.instruction |= high8;
19765
19766 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19767 whether the instruction is in Q form and whether Vm is a scalar indexed
19768 operand. */
19769 if (inst.operands[2].isscalar)
19770 {
19771 unsigned rm
19772 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
19773 inst.instruction &= 0xffffffd0;
19774 inst.instruction |= rm;
19775
19776 if (!quad_p)
19777 {
19778 /* Redo Rn as well. */
19779 inst.instruction &= 0xfff0ff7f;
19780 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19781 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19782 }
19783 }
19784 else if (!quad_p)
19785 {
19786 /* Redo Rn and Rm. */
19787 inst.instruction &= 0xfff0ff50;
19788 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19789 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19790 inst.instruction |= HI4 (inst.operands[2].reg);
19791 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
19792 }
19793}
19794
19795static void
19796do_neon_vfmal (void)
19797{
19798 return do_neon_fmac_maybe_scalar_long (0);
19799}
19800
19801static void
19802do_neon_vfmsl (void)
19803{
19804 return do_neon_fmac_maybe_scalar_long (1);
19805}
19806
19807static void
19808do_neon_dyadic_wide (void)
19809{
19810 struct neon_type_el et = neon_check_type (3, NS_QQD,
19811 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
19812 neon_mixed_length (et, et.size);
19813}
19814
19815static void
19816do_neon_dyadic_narrow (void)
19817{
19818 struct neon_type_el et = neon_check_type (3, NS_QDD,
19819 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
19820 /* Operand sign is unimportant, and the U bit is part of the opcode,
19821 so force the operand type to integer. */
19822 et.type = NT_integer;
19823 neon_mixed_length (et, et.size / 2);
19824}
19825
19826static void
19827do_neon_mul_sat_scalar_long (void)
19828{
19829 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
19830}
19831
19832static void
19833do_neon_vmull (void)
19834{
19835 if (inst.operands[2].isscalar)
19836 do_neon_mac_maybe_scalar_long ();
19837 else
19838 {
19839 struct neon_type_el et = neon_check_type (3, NS_QDD,
19840 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
19841
19842 if (et.type == NT_poly)
19843 NEON_ENCODE (POLY, inst);
19844 else
19845 NEON_ENCODE (INTEGER, inst);
19846
19847 /* For polynomial encoding the U bit must be zero, and the size must
19848 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19849 obviously, as 0b10). */
19850 if (et.size == 64)
19851 {
19852 /* Check we're on the correct architecture. */
19853 if (!mark_feature_used (&fpu_crypto_ext_armv8))
19854 inst.error =
19855 _("Instruction form not available on this architecture.");
19856
19857 et.size = 32;
19858 }
19859
19860 neon_mixed_length (et, et.size);
19861 }
19862}
19863
19864static void
19865do_neon_ext (void)
19866{
19867 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
19868 struct neon_type_el et = neon_check_type (3, rs,
19869 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
19870 unsigned imm = (inst.operands[3].imm * et.size) / 8;
19871
19872 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
19873 _("shift out of range"));
19874 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19875 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19876 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19877 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19878 inst.instruction |= LOW4 (inst.operands[2].reg);
19879 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19880 inst.instruction |= neon_quad (rs) << 6;
19881 inst.instruction |= imm << 8;
19882
19883 neon_dp_fixup (&inst);
19884}
19885
19886static void
19887do_neon_rev (void)
19888{
19889 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
19890 return;
19891
19892 enum neon_shape rs;
19893 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19894 rs = neon_select_shape (NS_QQ, NS_NULL);
19895 else
19896 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19897
19898 struct neon_type_el et = neon_check_type (2, rs,
19899 N_EQK, N_8 | N_16 | N_32 | N_KEY);
19900
19901 unsigned op = (inst.instruction >> 7) & 3;
19902 /* N (width of reversed regions) is encoded as part of the bitmask. We
19903 extract it here to check the elements to be reversed are smaller.
19904 Otherwise we'd get a reserved instruction. */
19905 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
19906
19907 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64
19908 && inst.operands[0].reg == inst.operands[1].reg)
19909 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19910 " operands makes instruction UNPREDICTABLE"));
19911
19912 gas_assert (elsize != 0);
19913 constraint (et.size >= elsize,
19914 _("elements must be smaller than reversal region"));
19915 neon_two_same (neon_quad (rs), 1, et.size);
19916}
19917
19918static void
19919do_neon_dup (void)
19920{
19921 if (inst.operands[1].isscalar)
19922 {
19923 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19924 BAD_FPU);
19925 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
19926 struct neon_type_el et = neon_check_type (2, rs,
19927 N_EQK, N_8 | N_16 | N_32 | N_KEY);
19928 unsigned sizebits = et.size >> 3;
19929 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
19930 int logsize = neon_logbits (et.size);
19931 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
19932
19933 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
19934 return;
19935
19936 NEON_ENCODE (SCALAR, inst);
19937 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19938 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19939 inst.instruction |= LOW4 (dm);
19940 inst.instruction |= HI1 (dm) << 5;
19941 inst.instruction |= neon_quad (rs) << 6;
19942 inst.instruction |= x << 17;
19943 inst.instruction |= sizebits << 16;
19944
19945 neon_dp_fixup (&inst);
19946 }
19947 else
19948 {
19949 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
19950 struct neon_type_el et = neon_check_type (2, rs,
19951 N_8 | N_16 | N_32 | N_KEY, N_EQK);
19952 if (rs == NS_QR)
19953 {
19954 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH))
19955 return;
19956 }
19957 else
19958 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19959 BAD_FPU);
19960
19961 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19962 {
19963 if (inst.operands[1].reg == REG_SP)
19964 as_tsktsk (MVE_BAD_SP);
19965 else if (inst.operands[1].reg == REG_PC)
19966 as_tsktsk (MVE_BAD_PC);
19967 }
19968
19969 /* Duplicate ARM register to lanes of vector. */
19970 NEON_ENCODE (ARMREG, inst);
19971 switch (et.size)
19972 {
19973 case 8: inst.instruction |= 0x400000; break;
19974 case 16: inst.instruction |= 0x000020; break;
19975 case 32: inst.instruction |= 0x000000; break;
19976 default: break;
19977 }
19978 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
19979 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
19980 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
19981 inst.instruction |= neon_quad (rs) << 21;
19982 /* The encoding for this instruction is identical for the ARM and Thumb
19983 variants, except for the condition field. */
19984 do_vfp_cond_or_thumb ();
19985 }
19986}
19987
19988static void
19989do_mve_mov (int toQ)
19990{
19991 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19992 return;
19993 if (inst.cond > COND_ALWAYS)
19994 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
19995
19996 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
19997 if (toQ)
19998 {
19999 Q0 = 0;
20000 Q1 = 1;
20001 Rt = 2;
20002 Rt2 = 3;
20003 }
20004
20005 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
20006 _("Index one must be [2,3] and index two must be two less than"
20007 " index one."));
20008 constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg,
20009 _("General purpose registers may not be the same"));
20010 constraint (inst.operands[Rt].reg == REG_SP
20011 || inst.operands[Rt2].reg == REG_SP,
20012 BAD_SP);
20013 constraint (inst.operands[Rt].reg == REG_PC
20014 || inst.operands[Rt2].reg == REG_PC,
20015 BAD_PC);
20016
20017 inst.instruction = 0xec000f00;
20018 inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
20019 inst.instruction |= !!toQ << 20;
20020 inst.instruction |= inst.operands[Rt2].reg << 16;
20021 inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
20022 inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
20023 inst.instruction |= inst.operands[Rt].reg;
20024}
20025
20026static void
20027do_mve_movn (void)
20028{
20029 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20030 return;
20031
20032 if (inst.cond > COND_ALWAYS)
20033 inst.pred_insn_type = INSIDE_VPT_INSN;
20034 else
20035 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
20036
20037 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32
20038 | N_KEY);
20039
20040 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20041 inst.instruction |= (neon_logbits (et.size) - 1) << 18;
20042 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20043 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20044 inst.instruction |= LOW4 (inst.operands[1].reg);
20045 inst.is_neon = 1;
20046
20047}
20048
20049/* VMOV has particularly many variations. It can be one of:
20050 0. VMOV<c><q> <Qd>, <Qm>
20051 1. VMOV<c><q> <Dd>, <Dm>
20052 (Register operations, which are VORR with Rm = Rn.)
20053 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20054 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20055 (Immediate loads.)
20056 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20057 (ARM register to scalar.)
20058 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20059 (Two ARM registers to vector.)
20060 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20061 (Scalar to ARM register.)
20062 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20063 (Vector to two ARM registers.)
20064 8. VMOV.F32 <Sd>, <Sm>
20065 9. VMOV.F64 <Dd>, <Dm>
20066 (VFP register moves.)
20067 10. VMOV.F32 <Sd>, #imm
20068 11. VMOV.F64 <Dd>, #imm
20069 (VFP float immediate load.)
20070 12. VMOV <Rd>, <Sm>
20071 (VFP single to ARM reg.)
20072 13. VMOV <Sd>, <Rm>
20073 (ARM reg to VFP single.)
20074 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20075 (Two ARM regs to two VFP singles.)
20076 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20077 (Two VFP singles to two ARM regs.)
20078 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20079 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20080 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20081 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20082
20083 These cases can be disambiguated using neon_select_shape, except cases 1/9
20084 and 3/11 which depend on the operand type too.
20085
20086 All the encoded bits are hardcoded by this function.
20087
20088 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20089 Cases 5, 7 may be used with VFPv2 and above.
20090
20091 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20092 can specify a type where it doesn't make sense to, and is ignored). */
20093
20094static void
20095do_neon_mov (void)
20096{
20097 enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR,
20098 NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI,
20099 NS_DI, NS_SR, NS_RS, NS_FF, NS_FI,
20100 NS_RF, NS_FR, NS_HR, NS_RH, NS_HI,
20101 NS_NULL);
20102 struct neon_type_el et;
20103 const char *ldconst = 0;
20104
20105 switch (rs)
20106 {
20107 case NS_DD: /* case 1/9. */
20108 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
20109 /* It is not an error here if no type is given. */
20110 inst.error = NULL;
20111
20112 /* In MVE we interpret the following instructions as same, so ignoring
20113 the following type (float) and size (64) checks.
20114 a: VMOV<c><q> <Dd>, <Dm>
20115 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20116 if ((et.type == NT_float && et.size == 64)
20117 || (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
20118 {
20119 do_vfp_nsyn_opcode ("fcpyd");
20120 break;
20121 }
20122 /* fall through. */
20123
20124 case NS_QQ: /* case 0/1. */
20125 {
20126 if (!check_simd_pred_availability (FALSE,
20127 NEON_CHECK_CC | NEON_CHECK_ARCH))
20128 return;
20129 /* The architecture manual I have doesn't explicitly state which
20130 value the U bit should have for register->register moves, but
20131 the equivalent VORR instruction has U = 0, so do that. */
20132 inst.instruction = 0x0200110;
20133 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20134 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20135 inst.instruction |= LOW4 (inst.operands[1].reg);
20136 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20137 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20138 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20139 inst.instruction |= neon_quad (rs) << 6;
20140
20141 neon_dp_fixup (&inst);
20142 }
20143 break;
20144
20145 case NS_DI: /* case 3/11. */
20146 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
20147 inst.error = NULL;
20148 if (et.type == NT_float && et.size == 64)
20149 {
20150 /* case 11 (fconstd). */
20151 ldconst = "fconstd";
20152 goto encode_fconstd;
20153 }
20154 /* fall through. */
20155
20156 case NS_QI: /* case 2/3. */
20157 if (!check_simd_pred_availability (FALSE,
20158 NEON_CHECK_CC | NEON_CHECK_ARCH))
20159 return;
20160 inst.instruction = 0x0800010;
20161 neon_move_immediate ();
20162 neon_dp_fixup (&inst);
20163 break;
20164
20165 case NS_SR: /* case 4. */
20166 {
20167 unsigned bcdebits = 0;
20168 int logsize;
20169 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
20170 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
20171
20172 /* .<size> is optional here, defaulting to .32. */
20173 if (inst.vectype.elems == 0
20174 && inst.operands[0].vectype.type == NT_invtype
20175 && inst.operands[1].vectype.type == NT_invtype)
20176 {
20177 inst.vectype.el[0].type = NT_untyped;
20178 inst.vectype.el[0].size = 32;
20179 inst.vectype.elems = 1;
20180 }
20181
20182 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
20183 logsize = neon_logbits (et.size);
20184
20185 if (et.size != 32)
20186 {
20187 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20188 && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL)
20189 return;
20190 }
20191 else
20192 {
20193 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
20194 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20195 _(BAD_FPU));
20196 }
20197
20198 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20199 {
20200 if (inst.operands[1].reg == REG_SP)
20201 as_tsktsk (MVE_BAD_SP);
20202 else if (inst.operands[1].reg == REG_PC)
20203 as_tsktsk (MVE_BAD_PC);
20204 }
20205 unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
20206
20207 constraint (et.type == NT_invtype, _("bad type for scalar"));
20208 constraint (x >= size / et.size, _("scalar index out of range"));
20209
20210
20211 switch (et.size)
20212 {
20213 case 8: bcdebits = 0x8; break;
20214 case 16: bcdebits = 0x1; break;
20215 case 32: bcdebits = 0x0; break;
20216 default: ;
20217 }
20218
20219 bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
20220
20221 inst.instruction = 0xe000b10;
20222 do_vfp_cond_or_thumb ();
20223 inst.instruction |= LOW4 (dn) << 16;
20224 inst.instruction |= HI1 (dn) << 7;
20225 inst.instruction |= inst.operands[1].reg << 12;
20226 inst.instruction |= (bcdebits & 3) << 5;
20227 inst.instruction |= ((bcdebits >> 2) & 3) << 21;
20228 inst.instruction |= (x >> (3-logsize)) << 16;
20229 }
20230 break;
20231
20232 case NS_DRR: /* case 5 (fmdrr). */
20233 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20234 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20235 _(BAD_FPU));
20236
20237 inst.instruction = 0xc400b10;
20238 do_vfp_cond_or_thumb ();
20239 inst.instruction |= LOW4 (inst.operands[0].reg);
20240 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
20241 inst.instruction |= inst.operands[1].reg << 12;
20242 inst.instruction |= inst.operands[2].reg << 16;
20243 break;
20244
20245 case NS_RS: /* case 6. */
20246 {
20247 unsigned logsize;
20248 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
20249 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
20250 unsigned abcdebits = 0;
20251
20252 /* .<dt> is optional here, defaulting to .32. */
20253 if (inst.vectype.elems == 0
20254 && inst.operands[0].vectype.type == NT_invtype
20255 && inst.operands[1].vectype.type == NT_invtype)
20256 {
20257 inst.vectype.el[0].type = NT_untyped;
20258 inst.vectype.el[0].size = 32;
20259 inst.vectype.elems = 1;
20260 }
20261
20262 et = neon_check_type (2, NS_NULL,
20263 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
20264 logsize = neon_logbits (et.size);
20265
20266 if (et.size != 32)
20267 {
20268 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20269 && vfp_or_neon_is_neon (NEON_CHECK_CC
20270 | NEON_CHECK_ARCH) == FAIL)
20271 return;
20272 }
20273 else
20274 {
20275 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
20276 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20277 _(BAD_FPU));
20278 }
20279
20280 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20281 {
20282 if (inst.operands[0].reg == REG_SP)
20283 as_tsktsk (MVE_BAD_SP);
20284 else if (inst.operands[0].reg == REG_PC)
20285 as_tsktsk (MVE_BAD_PC);
20286 }
20287
20288 unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
20289
20290 constraint (et.type == NT_invtype, _("bad type for scalar"));
20291 constraint (x >= size / et.size, _("scalar index out of range"));
20292
20293 switch (et.size)
20294 {
20295 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
20296 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
20297 case 32: abcdebits = 0x00; break;
20298 default: ;
20299 }
20300
20301 abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
20302 inst.instruction = 0xe100b10;
20303 do_vfp_cond_or_thumb ();
20304 inst.instruction |= LOW4 (dn) << 16;
20305 inst.instruction |= HI1 (dn) << 7;
20306 inst.instruction |= inst.operands[0].reg << 12;
20307 inst.instruction |= (abcdebits & 3) << 5;
20308 inst.instruction |= (abcdebits >> 2) << 21;
20309 inst.instruction |= (x >> (3-logsize)) << 16;
20310 }
20311 break;
20312
20313 case NS_RRD: /* case 7 (fmrrd). */
20314 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20315 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20316 _(BAD_FPU));
20317
20318 inst.instruction = 0xc500b10;
20319 do_vfp_cond_or_thumb ();
20320 inst.instruction |= inst.operands[0].reg << 12;
20321 inst.instruction |= inst.operands[1].reg << 16;
20322 inst.instruction |= LOW4 (inst.operands[2].reg);
20323 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20324 break;
20325
20326 case NS_FF: /* case 8 (fcpys). */
20327 do_vfp_nsyn_opcode ("fcpys");
20328 break;
20329
20330 case NS_HI:
20331 case NS_FI: /* case 10 (fconsts). */
20332 ldconst = "fconsts";
20333 encode_fconstd:
20334 if (!inst.operands[1].immisfloat)
20335 {
20336 unsigned new_imm;
20337 /* Immediate has to fit in 8 bits so float is enough. */
20338 float imm = (float) inst.operands[1].imm;
20339 memcpy (&new_imm, &imm, sizeof (float));
20340 /* But the assembly may have been written to provide an integer
20341 bit pattern that equates to a float, so check that the
20342 conversion has worked. */
20343 if (is_quarter_float (new_imm))
20344 {
20345 if (is_quarter_float (inst.operands[1].imm))
20346 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20347
20348 inst.operands[1].imm = new_imm;
20349 inst.operands[1].immisfloat = 1;
20350 }
20351 }
20352
20353 if (is_quarter_float (inst.operands[1].imm))
20354 {
20355 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
20356 do_vfp_nsyn_opcode (ldconst);
20357
20358 /* ARMv8.2 fp16 vmov.f16 instruction. */
20359 if (rs == NS_HI)
20360 do_scalar_fp16_v82_encode ();
20361 }
20362 else
20363 first_error (_("immediate out of range"));
20364 break;
20365
20366 case NS_RH:
20367 case NS_RF: /* case 12 (fmrs). */
20368 do_vfp_nsyn_opcode ("fmrs");
20369 /* ARMv8.2 fp16 vmov.f16 instruction. */
20370 if (rs == NS_RH)
20371 do_scalar_fp16_v82_encode ();
20372 break;
20373
20374 case NS_HR:
20375 case NS_FR: /* case 13 (fmsr). */
20376 do_vfp_nsyn_opcode ("fmsr");
20377 /* ARMv8.2 fp16 vmov.f16 instruction. */
20378 if (rs == NS_HR)
20379 do_scalar_fp16_v82_encode ();
20380 break;
20381
20382 case NS_RRSS:
20383 do_mve_mov (0);
20384 break;
20385 case NS_SSRR:
20386 do_mve_mov (1);
20387 break;
20388
20389 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20390 (one of which is a list), but we have parsed four. Do some fiddling to
20391 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20392 expect. */
20393 case NS_RRFF: /* case 14 (fmrrs). */
20394 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20395 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20396 _(BAD_FPU));
20397 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
20398 _("VFP registers must be adjacent"));
20399 inst.operands[2].imm = 2;
20400 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20401 do_vfp_nsyn_opcode ("fmrrs");
20402 break;
20403
20404 case NS_FFRR: /* case 15 (fmsrr). */
20405 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20406 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20407 _(BAD_FPU));
20408 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
20409 _("VFP registers must be adjacent"));
20410 inst.operands[1] = inst.operands[2];
20411 inst.operands[2] = inst.operands[3];
20412 inst.operands[0].imm = 2;
20413 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20414 do_vfp_nsyn_opcode ("fmsrr");
20415 break;
20416
20417 case NS_NULL:
20418 /* neon_select_shape has determined that the instruction
20419 shape is wrong and has already set the error message. */
20420 break;
20421
20422 default:
20423 abort ();
20424 }
20425}
20426
20427static void
20428do_mve_movl (void)
20429{
20430 if (!(inst.operands[0].present && inst.operands[0].isquad
20431 && inst.operands[1].present && inst.operands[1].isquad
20432 && !inst.operands[2].present))
20433 {
20434 inst.instruction = 0;
20435 inst.cond = 0xb;
20436 if (thumb_mode)
20437 set_pred_insn_type (INSIDE_IT_INSN);
20438 do_neon_mov ();
20439 return;
20440 }
20441
20442 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20443 return;
20444
20445 if (inst.cond != COND_ALWAYS)
20446 inst.pred_insn_type = INSIDE_VPT_INSN;
20447
20448 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8
20449 | N_S16 | N_U16 | N_KEY);
20450
20451 inst.instruction |= (et.type == NT_unsigned) << 28;
20452 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20453 inst.instruction |= (neon_logbits (et.size) + 1) << 19;
20454 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20455 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20456 inst.instruction |= LOW4 (inst.operands[1].reg);
20457 inst.is_neon = 1;
20458}
20459
20460static void
20461do_neon_rshift_round_imm (void)
20462{
20463 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
20464 return;
20465
20466 enum neon_shape rs;
20467 struct neon_type_el et;
20468
20469 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20470 {
20471 rs = neon_select_shape (NS_QQI, NS_NULL);
20472 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
20473 }
20474 else
20475 {
20476 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
20477 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
20478 }
20479 int imm = inst.operands[2].imm;
20480
20481 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20482 if (imm == 0)
20483 {
20484 inst.operands[2].present = 0;
20485 do_neon_mov ();
20486 return;
20487 }
20488
20489 constraint (imm < 1 || (unsigned)imm > et.size,
20490 _("immediate out of range for shift"));
20491 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
20492 et.size - imm);
20493}
20494
20495static void
20496do_neon_movhf (void)
20497{
20498 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
20499 constraint (rs != NS_HH, _("invalid suffix"));
20500
20501 if (inst.cond != COND_ALWAYS)
20502 {
20503 if (thumb_mode)
20504 {
20505 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20506 " the behaviour is UNPREDICTABLE"));
20507 }
20508 else
20509 {
20510 inst.error = BAD_COND;
20511 return;
20512 }
20513 }
20514
20515 do_vfp_sp_monadic ();
20516
20517 inst.is_neon = 1;
20518 inst.instruction |= 0xf0000000;
20519}
20520
20521static void
20522do_neon_movl (void)
20523{
20524 struct neon_type_el et = neon_check_type (2, NS_QD,
20525 N_EQK | N_DBL, N_SU_32 | N_KEY);
20526 unsigned sizebits = et.size >> 3;
20527 inst.instruction |= sizebits << 19;
20528 neon_two_same (0, et.type == NT_unsigned, -1);
20529}
20530
20531static void
20532do_neon_trn (void)
20533{
20534 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20535 struct neon_type_el et = neon_check_type (2, rs,
20536 N_EQK, N_8 | N_16 | N_32 | N_KEY);
20537 NEON_ENCODE (INTEGER, inst);
20538 neon_two_same (neon_quad (rs), 1, et.size);
20539}
20540
20541static void
20542do_neon_zip_uzp (void)
20543{
20544 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20545 struct neon_type_el et = neon_check_type (2, rs,
20546 N_EQK, N_8 | N_16 | N_32 | N_KEY);
20547 if (rs == NS_DD && et.size == 32)
20548 {
20549 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20550 inst.instruction = N_MNEM_vtrn;
20551 do_neon_trn ();
20552 return;
20553 }
20554 neon_two_same (neon_quad (rs), 1, et.size);
20555}
20556
20557static void
20558do_neon_sat_abs_neg (void)
20559{
20560 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
20561 return;
20562
20563 enum neon_shape rs;
20564 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20565 rs = neon_select_shape (NS_QQ, NS_NULL);
20566 else
20567 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20568 struct neon_type_el et = neon_check_type (2, rs,
20569 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
20570 neon_two_same (neon_quad (rs), 1, et.size);
20571}
20572
20573static void
20574do_neon_pair_long (void)
20575{
20576 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20577 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
20578 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20579 inst.instruction |= (et.type == NT_unsigned) << 7;
20580 neon_two_same (neon_quad (rs), 1, et.size);
20581}
20582
20583static void
20584do_neon_recip_est (void)
20585{
20586 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20587 struct neon_type_el et = neon_check_type (2, rs,
20588 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
20589 inst.instruction |= (et.type == NT_float) << 8;
20590 neon_two_same (neon_quad (rs), 1, et.size);
20591}
20592
20593static void
20594do_neon_cls (void)
20595{
20596 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
20597 return;
20598
20599 enum neon_shape rs;
20600 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20601 rs = neon_select_shape (NS_QQ, NS_NULL);
20602 else
20603 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20604
20605 struct neon_type_el et = neon_check_type (2, rs,
20606 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
20607 neon_two_same (neon_quad (rs), 1, et.size);
20608}
20609
20610static void
20611do_neon_clz (void)
20612{
20613 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
20614 return;
20615
20616 enum neon_shape rs;
20617 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20618 rs = neon_select_shape (NS_QQ, NS_NULL);
20619 else
20620 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20621
20622 struct neon_type_el et = neon_check_type (2, rs,
20623 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
20624 neon_two_same (neon_quad (rs), 1, et.size);
20625}
20626
20627static void
20628do_neon_cnt (void)
20629{
20630 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20631 struct neon_type_el et = neon_check_type (2, rs,
20632 N_EQK | N_INT, N_8 | N_KEY);
20633 neon_two_same (neon_quad (rs), 1, et.size);
20634}
20635
20636static void
20637do_neon_swp (void)
20638{
20639 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20640 neon_two_same (neon_quad (rs), 1, -1);
20641}
20642
20643static void
20644do_neon_tbl_tbx (void)
20645{
20646 unsigned listlenbits;
20647 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
20648
20649 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
20650 {
20651 first_error (_("bad list length for table lookup"));
20652 return;
20653 }
20654
20655 listlenbits = inst.operands[1].imm - 1;
20656 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20657 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20658 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20659 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20660 inst.instruction |= LOW4 (inst.operands[2].reg);
20661 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20662 inst.instruction |= listlenbits << 8;
20663
20664 neon_dp_fixup (&inst);
20665}
20666
20667static void
20668do_neon_ldm_stm (void)
20669{
20670 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
20671 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20672 _(BAD_FPU));
20673 /* P, U and L bits are part of bitmask. */
20674 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
20675 unsigned offsetbits = inst.operands[1].imm * 2;
20676
20677 if (inst.operands[1].issingle)
20678 {
20679 do_vfp_nsyn_ldm_stm (is_dbmode);
20680 return;
20681 }
20682
20683 constraint (is_dbmode && !inst.operands[0].writeback,
20684 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20685
20686 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20687 _("register list must contain at least 1 and at most 16 "
20688 "registers"));
20689
20690 inst.instruction |= inst.operands[0].reg << 16;
20691 inst.instruction |= inst.operands[0].writeback << 21;
20692 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
20693 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
20694
20695 inst.instruction |= offsetbits;
20696
20697 do_vfp_cond_or_thumb ();
20698}
20699
20700static void
20701do_vfp_nsyn_pop (void)
20702{
20703 nsyn_insert_sp ();
20704 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) {
20705 return do_vfp_nsyn_opcode ("vldm");
20706 }
20707
20708 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
20709 _(BAD_FPU));
20710
20711 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20712 _("register list must contain at least 1 and at most 16 "
20713 "registers"));
20714
20715 if (inst.operands[1].issingle)
20716 do_vfp_nsyn_opcode ("fldmias");
20717 else
20718 do_vfp_nsyn_opcode ("fldmiad");
20719}
20720
20721static void
20722do_vfp_nsyn_push (void)
20723{
20724 nsyn_insert_sp ();
20725 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) {
20726 return do_vfp_nsyn_opcode ("vstmdb");
20727 }
20728
20729 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
20730 _(BAD_FPU));
20731
20732 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20733 _("register list must contain at least 1 and at most 16 "
20734 "registers"));
20735
20736 if (inst.operands[1].issingle)
20737 do_vfp_nsyn_opcode ("fstmdbs");
20738 else
20739 do_vfp_nsyn_opcode ("fstmdbd");
20740}
20741
20742
20743static void
20744do_neon_ldr_str (void)
20745{
20746 int is_ldr = (inst.instruction & (1 << 20)) != 0;
20747
20748 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20749 And is UNPREDICTABLE in thumb mode. */
20750 if (!is_ldr
20751 && inst.operands[1].reg == REG_PC
20752 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
20753 {
20754 if (thumb_mode)
20755 inst.error = _("Use of PC here is UNPREDICTABLE");
20756 else if (warn_on_deprecated)
20757 as_tsktsk (_("Use of PC here is deprecated"));
20758 }
20759
20760 if (inst.operands[0].issingle)
20761 {
20762 if (is_ldr)
20763 do_vfp_nsyn_opcode ("flds");
20764 else
20765 do_vfp_nsyn_opcode ("fsts");
20766
20767 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20768 if (inst.vectype.el[0].size == 16)
20769 do_scalar_fp16_v82_encode ();
20770 }
20771 else
20772 {
20773 if (is_ldr)
20774 do_vfp_nsyn_opcode ("fldd");
20775 else
20776 do_vfp_nsyn_opcode ("fstd");
20777 }
20778}
20779
20780static void
20781do_t_vldr_vstr_sysreg (void)
20782{
20783 int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
20784 bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
20785
20786 /* Use of PC is UNPREDICTABLE. */
20787 if (inst.operands[1].reg == REG_PC)
20788 inst.error = _("Use of PC here is UNPREDICTABLE");
20789
20790 if (inst.operands[1].immisreg)
20791 inst.error = _("instruction does not accept register index");
20792
20793 if (!inst.operands[1].isreg)
20794 inst.error = _("instruction does not accept PC-relative addressing");
20795
20796 if (abs (inst.operands[1].imm) >= (1 << 7))
20797 inst.error = _("immediate value out of range");
20798
20799 inst.instruction = 0xec000f80;
20800 if (is_vldr)
20801 inst.instruction |= 1 << sysreg_vldr_bitno;
20802 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
20803 inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
20804 inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
20805}
20806
20807static void
20808do_vldr_vstr (void)
20809{
20810 bfd_boolean sysreg_op = !inst.operands[0].isreg;
20811
20812 /* VLDR/VSTR (System Register). */
20813 if (sysreg_op)
20814 {
20815 if (!mark_feature_used (&arm_ext_v8_1m_main))
20816 as_bad (_("Instruction not permitted on this architecture"));
20817
20818 do_t_vldr_vstr_sysreg ();
20819 }
20820 /* VLDR/VSTR. */
20821 else
20822 {
20823 if (!mark_feature_used (&fpu_vfp_ext_v1xd)
20824 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20825 as_bad (_("Instruction not permitted on this architecture"));
20826 do_neon_ldr_str ();
20827 }
20828}
20829
20830/* "interleave" version also handles non-interleaving register VLD1/VST1
20831 instructions. */
20832
20833static void
20834do_neon_ld_st_interleave (void)
20835{
20836 struct neon_type_el et = neon_check_type (1, NS_NULL,
20837 N_8 | N_16 | N_32 | N_64);
20838 unsigned alignbits = 0;
20839 unsigned idx;
20840 /* The bits in this table go:
20841 0: register stride of one (0) or two (1)
20842 1,2: register list length, minus one (1, 2, 3, 4).
20843 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20844 We use -1 for invalid entries. */
20845 const int typetable[] =
20846 {
20847 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20848 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20849 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20850 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20851 };
20852 int typebits;
20853
20854 if (et.type == NT_invtype)
20855 return;
20856
20857 if (inst.operands[1].immisalign)
20858 switch (inst.operands[1].imm >> 8)
20859 {
20860 case 64: alignbits = 1; break;
20861 case 128:
20862 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
20863 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20864 goto bad_alignment;
20865 alignbits = 2;
20866 break;
20867 case 256:
20868 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20869 goto bad_alignment;
20870 alignbits = 3;
20871 break;
20872 default:
20873 bad_alignment:
20874 first_error (_("bad alignment"));
20875 return;
20876 }
20877
20878 inst.instruction |= alignbits << 4;
20879 inst.instruction |= neon_logbits (et.size) << 6;
20880
20881 /* Bits [4:6] of the immediate in a list specifier encode register stride
20882 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20883 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20884 up the right value for "type" in a table based on this value and the given
20885 list style, then stick it back. */
20886 idx = ((inst.operands[0].imm >> 4) & 7)
20887 | (((inst.instruction >> 8) & 3) << 3);
20888
20889 typebits = typetable[idx];
20890
20891 constraint (typebits == -1, _("bad list type for instruction"));
20892 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
20893 BAD_EL_TYPE);
20894
20895 inst.instruction &= ~0xf00;
20896 inst.instruction |= typebits << 8;
20897}
20898
20899/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20900 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20901 otherwise. The variable arguments are a list of pairs of legal (size, align)
20902 values, terminated with -1. */
20903
20904static int
20905neon_alignment_bit (int size, int align, int *do_alignment, ...)
20906{
20907 va_list ap;
20908 int result = FAIL, thissize, thisalign;
20909
20910 if (!inst.operands[1].immisalign)
20911 {
20912 *do_alignment = 0;
20913 return SUCCESS;
20914 }
20915
20916 va_start (ap, do_alignment);
20917
20918 do
20919 {
20920 thissize = va_arg (ap, int);
20921 if (thissize == -1)
20922 break;
20923 thisalign = va_arg (ap, int);
20924
20925 if (size == thissize && align == thisalign)
20926 result = SUCCESS;
20927 }
20928 while (result != SUCCESS);
20929
20930 va_end (ap);
20931
20932 if (result == SUCCESS)
20933 *do_alignment = 1;
20934 else
20935 first_error (_("unsupported alignment for instruction"));
20936
20937 return result;
20938}
20939
20940static void
20941do_neon_ld_st_lane (void)
20942{
20943 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
20944 int align_good, do_alignment = 0;
20945 int logsize = neon_logbits (et.size);
20946 int align = inst.operands[1].imm >> 8;
20947 int n = (inst.instruction >> 8) & 3;
20948 int max_el = 64 / et.size;
20949
20950 if (et.type == NT_invtype)
20951 return;
20952
20953 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
20954 _("bad list length"));
20955 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
20956 _("scalar index out of range"));
20957 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
20958 && et.size == 8,
20959 _("stride of 2 unavailable when element size is 8"));
20960
20961 switch (n)
20962 {
20963 case 0: /* VLD1 / VST1. */
20964 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
20965 32, 32, -1);
20966 if (align_good == FAIL)
20967 return;
20968 if (do_alignment)
20969 {
20970 unsigned alignbits = 0;
20971 switch (et.size)
20972 {
20973 case 16: alignbits = 0x1; break;
20974 case 32: alignbits = 0x3; break;
20975 default: ;
20976 }
20977 inst.instruction |= alignbits << 4;
20978 }
20979 break;
20980
20981 case 1: /* VLD2 / VST2. */
20982 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
20983 16, 32, 32, 64, -1);
20984 if (align_good == FAIL)
20985 return;
20986 if (do_alignment)
20987 inst.instruction |= 1 << 4;
20988 break;
20989
20990 case 2: /* VLD3 / VST3. */
20991 constraint (inst.operands[1].immisalign,
20992 _("can't use alignment with this instruction"));
20993 break;
20994
20995 case 3: /* VLD4 / VST4. */
20996 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
20997 16, 64, 32, 64, 32, 128, -1);
20998 if (align_good == FAIL)
20999 return;
21000 if (do_alignment)
21001 {
21002 unsigned alignbits = 0;
21003 switch (et.size)
21004 {
21005 case 8: alignbits = 0x1; break;
21006 case 16: alignbits = 0x1; break;
21007 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
21008 default: ;
21009 }
21010 inst.instruction |= alignbits << 4;
21011 }
21012 break;
21013
21014 default: ;
21015 }
21016
21017 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
21018 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
21019 inst.instruction |= 1 << (4 + logsize);
21020
21021 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
21022 inst.instruction |= logsize << 10;
21023}
21024
21025/* Encode single n-element structure to all lanes VLD<n> instructions. */
21026
21027static void
21028do_neon_ld_dup (void)
21029{
21030 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
21031 int align_good, do_alignment = 0;
21032
21033 if (et.type == NT_invtype)
21034 return;
21035
21036 switch ((inst.instruction >> 8) & 3)
21037 {
21038 case 0: /* VLD1. */
21039 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
21040 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
21041 &do_alignment, 16, 16, 32, 32, -1);
21042 if (align_good == FAIL)
21043 return;
21044 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
21045 {
21046 case 1: break;
21047 case 2: inst.instruction |= 1 << 5; break;
21048 default: first_error (_("bad list length")); return;
21049 }
21050 inst.instruction |= neon_logbits (et.size) << 6;
21051 break;
21052
21053 case 1: /* VLD2. */
21054 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
21055 &do_alignment, 8, 16, 16, 32, 32, 64,
21056 -1);
21057 if (align_good == FAIL)
21058 return;
21059 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
21060 _("bad list length"));
21061 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
21062 inst.instruction |= 1 << 5;
21063 inst.instruction |= neon_logbits (et.size) << 6;
21064 break;
21065
21066 case 2: /* VLD3. */
21067 constraint (inst.operands[1].immisalign,
21068 _("can't use alignment with this instruction"));
21069 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
21070 _("bad list length"));
21071 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
21072 inst.instruction |= 1 << 5;
21073 inst.instruction |= neon_logbits (et.size) << 6;
21074 break;
21075
21076 case 3: /* VLD4. */
21077 {
21078 int align = inst.operands[1].imm >> 8;
21079 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
21080 16, 64, 32, 64, 32, 128, -1);
21081 if (align_good == FAIL)
21082 return;
21083 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
21084 _("bad list length"));
21085 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
21086 inst.instruction |= 1 << 5;
21087 if (et.size == 32 && align == 128)
21088 inst.instruction |= 0x3 << 6;
21089 else
21090 inst.instruction |= neon_logbits (et.size) << 6;
21091 }
21092 break;
21093
21094 default: ;
21095 }
21096
21097 inst.instruction |= do_alignment << 4;
21098}
21099
21100/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21101 apart from bits [11:4]. */
21102
21103static void
21104do_neon_ldx_stx (void)
21105{
21106 if (inst.operands[1].isreg)
21107 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
21108
21109 switch (NEON_LANE (inst.operands[0].imm))
21110 {
21111 case NEON_INTERLEAVE_LANES:
21112 NEON_ENCODE (INTERLV, inst);
21113 do_neon_ld_st_interleave ();
21114 break;
21115
21116 case NEON_ALL_LANES:
21117 NEON_ENCODE (DUP, inst);
21118 if (inst.instruction == N_INV)
21119 {
21120 first_error ("only loads support such operands");
21121 break;
21122 }
21123 do_neon_ld_dup ();
21124 break;
21125
21126 default:
21127 NEON_ENCODE (LANE, inst);
21128 do_neon_ld_st_lane ();
21129 }
21130
21131 /* L bit comes from bit mask. */
21132 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21133 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21134 inst.instruction |= inst.operands[1].reg << 16;
21135
21136 if (inst.operands[1].postind)
21137 {
21138 int postreg = inst.operands[1].imm & 0xf;
21139 constraint (!inst.operands[1].immisreg,
21140 _("post-index must be a register"));
21141 constraint (postreg == 0xd || postreg == 0xf,
21142 _("bad register for post-index"));
21143 inst.instruction |= postreg;
21144 }
21145 else
21146 {
21147 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
21148 constraint (inst.relocs[0].exp.X_op != O_constant
21149 || inst.relocs[0].exp.X_add_number != 0,
21150 BAD_ADDR_MODE);
21151
21152 if (inst.operands[1].writeback)
21153 {
21154 inst.instruction |= 0xd;
21155 }
21156 else
21157 inst.instruction |= 0xf;
21158 }
21159
21160 if (thumb_mode)
21161 inst.instruction |= 0xf9000000;
21162 else
21163 inst.instruction |= 0xf4000000;
21164}
21165
21166/* FP v8. */
21167static void
21168do_vfp_nsyn_fpv8 (enum neon_shape rs)
21169{
21170 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21171 D register operands. */
21172 if (neon_shape_class[rs] == SC_DOUBLE)
21173 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
21174 _(BAD_FPU));
21175
21176 NEON_ENCODE (FPV8, inst);
21177
21178 if (rs == NS_FFF || rs == NS_HHH)
21179 {
21180 do_vfp_sp_dyadic ();
21181
21182 /* ARMv8.2 fp16 instruction. */
21183 if (rs == NS_HHH)
21184 do_scalar_fp16_v82_encode ();
21185 }
21186 else
21187 do_vfp_dp_rd_rn_rm ();
21188
21189 if (rs == NS_DDD)
21190 inst.instruction |= 0x100;
21191
21192 inst.instruction |= 0xf0000000;
21193}
21194
21195static void
21196do_vsel (void)
21197{
21198 set_pred_insn_type (OUTSIDE_PRED_INSN);
21199
21200 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
21201 first_error (_("invalid instruction shape"));
21202}
21203
21204static void
21205do_vmaxnm (void)
21206{
21207 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21208 set_pred_insn_type (OUTSIDE_PRED_INSN);
21209
21210 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
21211 return;
21212
21213 if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH8))
21214 return;
21215
21216 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
21217}
21218
21219static void
21220do_vrint_1 (enum neon_cvt_mode mode)
21221{
21222 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
21223 struct neon_type_el et;
21224
21225 if (rs == NS_NULL)
21226 return;
21227
21228 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21229 D register operands. */
21230 if (neon_shape_class[rs] == SC_DOUBLE)
21231 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
21232 _(BAD_FPU));
21233
21234 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
21235 | N_VFP);
21236 if (et.type != NT_invtype)
21237 {
21238 /* VFP encodings. */
21239 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
21240 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
21241 set_pred_insn_type (OUTSIDE_PRED_INSN);
21242
21243 NEON_ENCODE (FPV8, inst);
21244 if (rs == NS_FF || rs == NS_HH)
21245 do_vfp_sp_monadic ();
21246 else
21247 do_vfp_dp_rd_rm ();
21248
21249 switch (mode)
21250 {
21251 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
21252 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
21253 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
21254 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
21255 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
21256 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
21257 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
21258 default: abort ();
21259 }
21260
21261 inst.instruction |= (rs == NS_DD) << 8;
21262 do_vfp_cond_or_thumb ();
21263
21264 /* ARMv8.2 fp16 vrint instruction. */
21265 if (rs == NS_HH)
21266 do_scalar_fp16_v82_encode ();
21267 }
21268 else
21269 {
21270 /* Neon encodings (or something broken...). */
21271 inst.error = NULL;
21272 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
21273
21274 if (et.type == NT_invtype)
21275 return;
21276
21277 if (!check_simd_pred_availability (TRUE,
21278 NEON_CHECK_CC | NEON_CHECK_ARCH8))
21279 return;
21280
21281 NEON_ENCODE (FLOAT, inst);
21282
21283 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21284 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21285 inst.instruction |= LOW4 (inst.operands[1].reg);
21286 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21287 inst.instruction |= neon_quad (rs) << 6;
21288 /* Mask off the original size bits and reencode them. */
21289 inst.instruction = ((inst.instruction & 0xfff3ffff)
21290 | neon_logbits (et.size) << 18);
21291
21292 switch (mode)
21293 {
21294 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
21295 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
21296 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
21297 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
21298 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
21299 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
21300 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
21301 default: abort ();
21302 }
21303
21304 if (thumb_mode)
21305 inst.instruction |= 0xfc000000;
21306 else
21307 inst.instruction |= 0xf0000000;
21308 }
21309}
21310
21311static void
21312do_vrintx (void)
21313{
21314 do_vrint_1 (neon_cvt_mode_x);
21315}
21316
21317static void
21318do_vrintz (void)
21319{
21320 do_vrint_1 (neon_cvt_mode_z);
21321}
21322
21323static void
21324do_vrintr (void)
21325{
21326 do_vrint_1 (neon_cvt_mode_r);
21327}
21328
21329static void
21330do_vrinta (void)
21331{
21332 do_vrint_1 (neon_cvt_mode_a);
21333}
21334
21335static void
21336do_vrintn (void)
21337{
21338 do_vrint_1 (neon_cvt_mode_n);
21339}
21340
21341static void
21342do_vrintp (void)
21343{
21344 do_vrint_1 (neon_cvt_mode_p);
21345}
21346
21347static void
21348do_vrintm (void)
21349{
21350 do_vrint_1 (neon_cvt_mode_m);
21351}
21352
21353static unsigned
21354neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
21355{
21356 unsigned regno = NEON_SCALAR_REG (opnd);
21357 unsigned elno = NEON_SCALAR_INDEX (opnd);
21358
21359 if (elsize == 16 && elno < 2 && regno < 16)
21360 return regno | (elno << 4);
21361 else if (elsize == 32 && elno == 0)
21362 return regno;
21363
21364 first_error (_("scalar out of range"));
21365 return 0;
21366}
21367
21368static void
21369do_vcmla (void)
21370{
21371 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
21372 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
21373 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
21374 constraint (inst.relocs[0].exp.X_op != O_constant,
21375 _("expression too complex"));
21376 unsigned rot = inst.relocs[0].exp.X_add_number;
21377 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
21378 _("immediate out of range"));
21379 rot /= 90;
21380
21381 if (!check_simd_pred_availability (TRUE,
21382 NEON_CHECK_ARCH8 | NEON_CHECK_CC))
21383 return;
21384
21385 if (inst.operands[2].isscalar)
21386 {
21387 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
21388 first_error (_("invalid instruction shape"));
21389 enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
21390 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
21391 N_KEY | N_F16 | N_F32).size;
21392 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
21393 inst.is_neon = 1;
21394 inst.instruction = 0xfe000800;
21395 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21396 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21397 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21398 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21399 inst.instruction |= LOW4 (m);
21400 inst.instruction |= HI1 (m) << 5;
21401 inst.instruction |= neon_quad (rs) << 6;
21402 inst.instruction |= rot << 20;
21403 inst.instruction |= (size == 32) << 23;
21404 }
21405 else
21406 {
21407 enum neon_shape rs;
21408 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
21409 rs = neon_select_shape (NS_QQQI, NS_NULL);
21410 else
21411 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
21412
21413 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
21414 N_KEY | N_F16 | N_F32).size;
21415 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
21416 && (inst.operands[0].reg == inst.operands[1].reg
21417 || inst.operands[0].reg == inst.operands[2].reg))
21418 as_tsktsk (BAD_MVE_SRCDEST);
21419
21420 neon_three_same (neon_quad (rs), 0, -1);
21421 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21422 inst.instruction |= 0xfc200800;
21423 inst.instruction |= rot << 23;
21424 inst.instruction |= (size == 32) << 20;
21425 }
21426}
21427
21428static void
21429do_vcadd (void)
21430{
21431 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
21432 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
21433 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
21434 constraint (inst.relocs[0].exp.X_op != O_constant,
21435 _("expression too complex"));
21436
21437 unsigned rot = inst.relocs[0].exp.X_add_number;
21438 constraint (rot != 90 && rot != 270, _("immediate out of range"));
21439 enum neon_shape rs;
21440 struct neon_type_el et;
21441 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21442 {
21443 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
21444 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
21445 }
21446 else
21447 {
21448 rs = neon_select_shape (NS_QQQI, NS_NULL);
21449 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
21450 | N_I16 | N_I32);
21451 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
21452 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21453 "operand makes instruction UNPREDICTABLE"));
21454 }
21455
21456 if (et.type == NT_invtype)
21457 return;
21458
21459 if (!check_simd_pred_availability (et.type == NT_float,
21460 NEON_CHECK_ARCH8 | NEON_CHECK_CC))
21461 return;
21462
21463 if (et.type == NT_float)
21464 {
21465 neon_three_same (neon_quad (rs), 0, -1);
21466 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21467 inst.instruction |= 0xfc800800;
21468 inst.instruction |= (rot == 270) << 24;
21469 inst.instruction |= (et.size == 32) << 20;
21470 }
21471 else
21472 {
21473 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
21474 inst.instruction = 0xfe000f00;
21475 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21476 inst.instruction |= neon_logbits (et.size) << 20;
21477 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21478 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21479 inst.instruction |= (rot == 270) << 12;
21480 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21481 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
21482 inst.instruction |= LOW4 (inst.operands[2].reg);
21483 inst.is_neon = 1;
21484 }
21485}
21486
21487/* Dot Product instructions encoding support. */
21488
21489static void
21490do_neon_dotproduct (int unsigned_p)
21491{
21492 enum neon_shape rs;
21493 unsigned scalar_oprd2 = 0;
21494 int high8;
21495
21496 if (inst.cond != COND_ALWAYS)
21497 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21498 "is UNPREDICTABLE"));
21499
21500 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
21501 _(BAD_FPU));
21502
21503 /* Dot Product instructions are in three-same D/Q register format or the third
21504 operand can be a scalar index register. */
21505 if (inst.operands[2].isscalar)
21506 {
21507 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
21508 high8 = 0xfe000000;
21509 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21510 }
21511 else
21512 {
21513 high8 = 0xfc000000;
21514 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
21515 }
21516
21517 if (unsigned_p)
21518 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
21519 else
21520 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
21521
21522 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21523 Product instruction, so we pass 0 as the "ubit" parameter. And the
21524 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21525 neon_three_same (neon_quad (rs), 0, 32);
21526
21527 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21528 different NEON three-same encoding. */
21529 inst.instruction &= 0x00ffffff;
21530 inst.instruction |= high8;
21531 /* Encode 'U' bit which indicates signedness. */
21532 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
21533 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21534 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21535 the instruction encoding. */
21536 if (inst.operands[2].isscalar)
21537 {
21538 inst.instruction &= 0xffffffd0;
21539 inst.instruction |= LOW4 (scalar_oprd2);
21540 inst.instruction |= HI1 (scalar_oprd2) << 5;
21541 }
21542}
21543
21544/* Dot Product instructions for signed integer. */
21545
21546static void
21547do_neon_dotproduct_s (void)
21548{
21549 return do_neon_dotproduct (0);
21550}
21551
21552/* Dot Product instructions for unsigned integer. */
21553
21554static void
21555do_neon_dotproduct_u (void)
21556{
21557 return do_neon_dotproduct (1);
21558}
21559
21560static void
21561do_vusdot (void)
21562{
21563 enum neon_shape rs;
21564 set_pred_insn_type (OUTSIDE_PRED_INSN);
21565 if (inst.operands[2].isscalar)
21566 {
21567 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21568 neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_KEY);
21569
21570 inst.instruction |= (1 << 25);
21571 int index = inst.operands[2].reg & 0xf;
21572 constraint ((index != 1 && index != 0), _("index must be 0 or 1"));
21573 inst.operands[2].reg >>= 4;
21574 constraint (!(inst.operands[2].reg < 16),
21575 _("indexed register must be less than 16"));
21576 neon_three_args (rs == NS_QQS);
21577 inst.instruction |= (index << 5);
21578 }
21579 else
21580 {
21581 inst.instruction |= (1 << 21);
21582 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
21583 neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_KEY);
21584 neon_three_args (rs == NS_QQQ);
21585 }
21586}
21587
21588static void
21589do_vsudot (void)
21590{
21591 enum neon_shape rs;
21592 set_pred_insn_type (OUTSIDE_PRED_INSN);
21593 if (inst.operands[2].isscalar)
21594 {
21595 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21596 neon_check_type (3, rs, N_EQK, N_EQK, N_U8 | N_KEY);
21597
21598 inst.instruction |= (1 << 25);
21599 int index = inst.operands[2].reg & 0xf;
21600 constraint ((index != 1 && index != 0), _("index must be 0 or 1"));
21601 inst.operands[2].reg >>= 4;
21602 constraint (!(inst.operands[2].reg < 16),
21603 _("indexed register must be less than 16"));
21604 neon_three_args (rs == NS_QQS);
21605 inst.instruction |= (index << 5);
21606 }
21607}
21608
21609static void
21610do_vsmmla (void)
21611{
21612 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
21613 neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_KEY);
21614
21615 set_pred_insn_type (OUTSIDE_PRED_INSN);
21616
21617 neon_three_args (1);
21618
21619}
21620
21621static void
21622do_vummla (void)
21623{
21624 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
21625 neon_check_type (3, rs, N_EQK, N_EQK, N_U8 | N_KEY);
21626
21627 set_pred_insn_type (OUTSIDE_PRED_INSN);
21628
21629 neon_three_args (1);
21630
21631}
21632
21633static void
21634check_cde_operand (size_t index, int is_dual)
21635{
21636 unsigned Rx = inst.operands[index].reg;
21637 bfd_boolean isvec = inst.operands[index].isvec;
21638 if (is_dual == 0 && thumb_mode)
21639 constraint (
21640 !((Rx <= 14 && Rx != 13) || (Rx == REG_PC && isvec)),
21641 _("Register must be r0-r14 except r13, or APSR_nzcv."));
21642 else
21643 constraint ( !((Rx <= 10 && Rx % 2 == 0 )),
21644 _("Register must be an even register between r0-r10."));
21645}
21646
21647static bfd_boolean
21648cde_coproc_enabled (unsigned coproc)
21649{
21650 switch (coproc)
21651 {
21652 case 0: return mark_feature_used (&arm_ext_cde0);
21653 case 1: return mark_feature_used (&arm_ext_cde1);
21654 case 2: return mark_feature_used (&arm_ext_cde2);
21655 case 3: return mark_feature_used (&arm_ext_cde3);
21656 case 4: return mark_feature_used (&arm_ext_cde4);
21657 case 5: return mark_feature_used (&arm_ext_cde5);
21658 case 6: return mark_feature_used (&arm_ext_cde6);
21659 case 7: return mark_feature_used (&arm_ext_cde7);
21660 default: return FALSE;
21661 }
21662}
21663
21664#define cde_coproc_pos 8
21665static void
21666cde_handle_coproc (void)
21667{
21668 unsigned coproc = inst.operands[0].reg;
21669 constraint (coproc > 7, _("CDE Coprocessor must be in range 0-7"));
21670 constraint (!(cde_coproc_enabled (coproc)), BAD_CDE_COPROC);
21671 inst.instruction |= coproc << cde_coproc_pos;
21672}
21673#undef cde_coproc_pos
21674
21675static void
21676cxn_handle_predication (bfd_boolean is_accum)
21677{
21678 if (is_accum && conditional_insn ())
21679 set_pred_insn_type (INSIDE_IT_INSN);
21680 else if (conditional_insn ())
21681 /* conditional_insn essentially checks for a suffix, not whether the
21682 instruction is inside an IT block or not.
21683 The non-accumulator versions should not have suffixes. */
21684 inst.error = BAD_SYNTAX;
21685 else
21686 set_pred_insn_type (OUTSIDE_PRED_INSN);
21687}
21688
21689static void
21690do_custom_instruction_1 (int is_dual, bfd_boolean is_accum)
21691{
21692
21693 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
21694
21695 unsigned imm, Rd;
21696
21697 Rd = inst.operands[1].reg;
21698 check_cde_operand (1, is_dual);
21699
21700 if (is_dual == 1)
21701 {
21702 constraint (inst.operands[2].reg != Rd + 1,
21703 _("cx1d requires consecutive destination registers."));
21704 imm = inst.operands[3].imm;
21705 }
21706 else if (is_dual == 0)
21707 imm = inst.operands[2].imm;
21708 else
21709 abort ();
21710
21711 inst.instruction |= Rd << 12;
21712 inst.instruction |= (imm & 0x1F80) << 9;
21713 inst.instruction |= (imm & 0x0040) << 1;
21714 inst.instruction |= (imm & 0x003f);
21715
21716 cde_handle_coproc ();
21717 cxn_handle_predication (is_accum);
21718}
21719
21720static void
21721do_custom_instruction_2 (int is_dual, bfd_boolean is_accum)
21722{
21723
21724 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
21725
21726 unsigned imm, Rd, Rn;
21727
21728 Rd = inst.operands[1].reg;
21729
21730 if (is_dual == 1)
21731 {
21732 constraint (inst.operands[2].reg != Rd + 1,
21733 _("cx2d requires consecutive destination registers."));
21734 imm = inst.operands[4].imm;
21735 Rn = inst.operands[3].reg;
21736 }
21737 else if (is_dual == 0)
21738 {
21739 imm = inst.operands[3].imm;
21740 Rn = inst.operands[2].reg;
21741 }
21742 else
21743 abort ();
21744
21745 check_cde_operand (2 + is_dual, /* is_dual = */0);
21746 check_cde_operand (1, is_dual);
21747
21748 inst.instruction |= Rd << 12;
21749 inst.instruction |= Rn << 16;
21750
21751 inst.instruction |= (imm & 0x0380) << 13;
21752 inst.instruction |= (imm & 0x0040) << 1;
21753 inst.instruction |= (imm & 0x003f);
21754
21755 cde_handle_coproc ();
21756 cxn_handle_predication (is_accum);
21757}
21758
21759static void
21760do_custom_instruction_3 (int is_dual, bfd_boolean is_accum)
21761{
21762
21763 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
21764
21765 unsigned imm, Rd, Rn, Rm;
21766
21767 Rd = inst.operands[1].reg;
21768
21769 if (is_dual == 1)
21770 {
21771 constraint (inst.operands[2].reg != Rd + 1,
21772 _("cx3d requires consecutive destination registers."));
21773 imm = inst.operands[5].imm;
21774 Rn = inst.operands[3].reg;
21775 Rm = inst.operands[4].reg;
21776 }
21777 else if (is_dual == 0)
21778 {
21779 imm = inst.operands[4].imm;
21780 Rn = inst.operands[2].reg;
21781 Rm = inst.operands[3].reg;
21782 }
21783 else
21784 abort ();
21785
21786 check_cde_operand (1, is_dual);
21787 check_cde_operand (2 + is_dual, /* is_dual = */0);
21788 check_cde_operand (3 + is_dual, /* is_dual = */0);
21789
21790 inst.instruction |= Rd;
21791 inst.instruction |= Rn << 16;
21792 inst.instruction |= Rm << 12;
21793
21794 inst.instruction |= (imm & 0x0038) << 17;
21795 inst.instruction |= (imm & 0x0004) << 5;
21796 inst.instruction |= (imm & 0x0003) << 4;
21797
21798 cde_handle_coproc ();
21799 cxn_handle_predication (is_accum);
21800}
21801
21802static void
21803do_cx1 (void)
21804{
21805 return do_custom_instruction_1 (0, 0);
21806}
21807
21808static void
21809do_cx1a (void)
21810{
21811 return do_custom_instruction_1 (0, 1);
21812}
21813
21814static void
21815do_cx1d (void)
21816{
21817 return do_custom_instruction_1 (1, 0);
21818}
21819
21820static void
21821do_cx1da (void)
21822{
21823 return do_custom_instruction_1 (1, 1);
21824}
21825
21826static void
21827do_cx2 (void)
21828{
21829 return do_custom_instruction_2 (0, 0);
21830}
21831
21832static void
21833do_cx2a (void)
21834{
21835 return do_custom_instruction_2 (0, 1);
21836}
21837
21838static void
21839do_cx2d (void)
21840{
21841 return do_custom_instruction_2 (1, 0);
21842}
21843
21844static void
21845do_cx2da (void)
21846{
21847 return do_custom_instruction_2 (1, 1);
21848}
21849
21850static void
21851do_cx3 (void)
21852{
21853 return do_custom_instruction_3 (0, 0);
21854}
21855
21856static void
21857do_cx3a (void)
21858{
21859 return do_custom_instruction_3 (0, 1);
21860}
21861
21862static void
21863do_cx3d (void)
21864{
21865 return do_custom_instruction_3 (1, 0);
21866}
21867
21868static void
21869do_cx3da (void)
21870{
21871 return do_custom_instruction_3 (1, 1);
21872}
21873
21874static void
21875vcx_assign_vec_d (unsigned regnum)
21876{
21877 inst.instruction |= HI4 (regnum) << 12;
21878 inst.instruction |= LOW1 (regnum) << 22;
21879}
21880
21881static void
21882vcx_assign_vec_m (unsigned regnum)
21883{
21884 inst.instruction |= HI4 (regnum);
21885 inst.instruction |= LOW1 (regnum) << 5;
21886}
21887
21888static void
21889vcx_assign_vec_n (unsigned regnum)
21890{
21891 inst.instruction |= HI4 (regnum) << 16;
21892 inst.instruction |= LOW1 (regnum) << 7;
21893}
21894
21895enum vcx_reg_type {
21896 q_reg,
21897 d_reg,
21898 s_reg
21899};
21900
21901static enum vcx_reg_type
21902vcx_get_reg_type (enum neon_shape ns)
21903{
21904 gas_assert (ns == NS_PQI
21905 || ns == NS_PDI
21906 || ns == NS_PFI
21907 || ns == NS_PQQI
21908 || ns == NS_PDDI
21909 || ns == NS_PFFI
21910 || ns == NS_PQQQI
21911 || ns == NS_PDDDI
21912 || ns == NS_PFFFI);
21913 if (ns == NS_PQI || ns == NS_PQQI || ns == NS_PQQQI)
21914 return q_reg;
21915 if (ns == NS_PDI || ns == NS_PDDI || ns == NS_PDDDI)
21916 return d_reg;
21917 return s_reg;
21918}
21919
21920#define vcx_size_pos 24
21921#define vcx_vec_pos 6
21922static unsigned
21923vcx_handle_shape (enum vcx_reg_type reg_type)
21924{
21925 unsigned mult = 2;
21926 if (reg_type == q_reg)
21927 inst.instruction |= 1 << vcx_vec_pos;
21928 else if (reg_type == d_reg)
21929 inst.instruction |= 1 << vcx_size_pos;
21930 else
21931 mult = 1;
21932 /* NOTE:
21933 The documentation says that the Q registers are encoded as 2*N in the D:Vd
21934 bits (or equivalent for N and M registers).
21935 Similarly the D registers are encoded as N in D:Vd bits.
21936 While the S registers are encoded as N in the Vd:D bits.
21937
21938 Taking into account the maximum values of these registers we can see a
21939 nicer pattern for calculation:
21940 Q -> 7, D -> 15, S -> 31
21941
21942 If we say that everything is encoded in the Vd:D bits, then we can say
21943 that Q is encoded as 4*N, and D is encoded as 2*N.
21944 This way the bits will end up the same, and calculation is simpler.
21945 (calculation is now:
21946 1. Multiply by a number determined by the register letter.
21947 2. Encode resulting number in Vd:D bits.)
21948
21949 This is made a little more complicated by automatic handling of 'Q'
21950 registers elsewhere, which means the register number is already 2*N where
21951 N is the number the user wrote after the register letter.
21952 */
21953 return mult;
21954}
21955#undef vcx_vec_pos
21956#undef vcx_size_pos
21957
21958static void
21959vcx_ensure_register_in_range (unsigned R, enum vcx_reg_type reg_type)
21960{
21961 if (reg_type == q_reg)
21962 {
21963 gas_assert (R % 2 == 0);
21964 constraint (R >= 16, _("'q' register must be in range 0-7"));
21965 }
21966 else if (reg_type == d_reg)
21967 constraint (R >= 16, _("'d' register must be in range 0-15"));
21968 else
21969 constraint (R >= 32, _("'s' register must be in range 0-31"));
21970}
21971
21972static void (*vcx_assign_vec[3]) (unsigned) = {
21973 vcx_assign_vec_d,
21974 vcx_assign_vec_m,
21975 vcx_assign_vec_n
21976};
21977
21978static void
21979vcx_handle_register_arguments (unsigned num_registers,
21980 enum vcx_reg_type reg_type)
21981{
21982 unsigned R, i;
21983 unsigned reg_mult = vcx_handle_shape (reg_type);
21984 for (i = 0; i < num_registers; i++)
21985 {
21986 R = inst.operands[i+1].reg;
21987 vcx_ensure_register_in_range (R, reg_type);
21988 if (num_registers == 3 && i > 0)
21989 {
21990 if (i == 2)
21991 vcx_assign_vec[1] (R * reg_mult);
21992 else
21993 vcx_assign_vec[2] (R * reg_mult);
21994 continue;
21995 }
21996 vcx_assign_vec[i](R * reg_mult);
21997 }
21998}
21999
22000static void
22001vcx_handle_insn_block (enum vcx_reg_type reg_type)
22002{
22003 if (reg_type == q_reg)
22004 if (inst.cond > COND_ALWAYS)
22005 inst.pred_insn_type = INSIDE_VPT_INSN;
22006 else
22007 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
22008 else if (inst.cond == COND_ALWAYS)
22009 inst.pred_insn_type = OUTSIDE_PRED_INSN;
22010 else
22011 inst.error = BAD_NOT_IT;
22012}
22013
22014static void
22015vcx_handle_common_checks (unsigned num_args, enum neon_shape rs)
22016{
22017 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
22018 cde_handle_coproc ();
22019 enum vcx_reg_type reg_type = vcx_get_reg_type (rs);
22020 vcx_handle_register_arguments (num_args, reg_type);
22021 vcx_handle_insn_block (reg_type);
22022 if (reg_type == q_reg)
22023 constraint (!mark_feature_used (&mve_ext),
22024 _("vcx instructions with Q registers require MVE"));
22025 else
22026 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp, cpu_variant)
22027 && mark_feature_used (&armv8m_fp))
22028 && !mark_feature_used (&mve_ext),
22029 _("vcx instructions with S or D registers require either MVE"
22030 " or Armv8-M floating point extension."));
22031}
22032
22033static void
22034do_vcx1 (void)
22035{
22036 enum neon_shape rs = neon_select_shape (NS_PQI, NS_PDI, NS_PFI, NS_NULL);
22037 vcx_handle_common_checks (1, rs);
22038
22039 unsigned imm = inst.operands[2].imm;
22040 inst.instruction |= (imm & 0x03f);
22041 inst.instruction |= (imm & 0x040) << 1;
22042 inst.instruction |= (imm & 0x780) << 9;
22043 if (rs != NS_PQI)
22044 constraint (imm >= 2048,
22045 _("vcx1 with S or D registers takes immediate within 0-2047"));
22046 inst.instruction |= (imm & 0x800) << 13;
22047}
22048
22049static void
22050do_vcx2 (void)
22051{
22052 enum neon_shape rs = neon_select_shape (NS_PQQI, NS_PDDI, NS_PFFI, NS_NULL);
22053 vcx_handle_common_checks (2, rs);
22054
22055 unsigned imm = inst.operands[3].imm;
22056 inst.instruction |= (imm & 0x01) << 4;
22057 inst.instruction |= (imm & 0x02) << 6;
22058 inst.instruction |= (imm & 0x3c) << 14;
22059 if (rs != NS_PQQI)
22060 constraint (imm >= 64,
22061 _("vcx2 with S or D registers takes immediate within 0-63"));
22062 inst.instruction |= (imm & 0x40) << 18;
22063}
22064
22065static void
22066do_vcx3 (void)
22067{
22068 enum neon_shape rs = neon_select_shape (NS_PQQQI, NS_PDDDI, NS_PFFFI, NS_NULL);
22069 vcx_handle_common_checks (3, rs);
22070
22071 unsigned imm = inst.operands[4].imm;
22072 inst.instruction |= (imm & 0x1) << 4;
22073 inst.instruction |= (imm & 0x6) << 19;
22074 if (rs != NS_PQQQI)
22075 constraint (imm >= 8,
22076 _("vcx2 with S or D registers takes immediate within 0-7"));
22077 inst.instruction |= (imm & 0x8) << 21;
22078}
22079
22080/* Crypto v1 instructions. */
22081static void
22082do_crypto_2op_1 (unsigned elttype, int op)
22083{
22084 set_pred_insn_type (OUTSIDE_PRED_INSN);
22085
22086 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
22087 == NT_invtype)
22088 return;
22089
22090 inst.error = NULL;
22091
22092 NEON_ENCODE (INTEGER, inst);
22093 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
22094 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
22095 inst.instruction |= LOW4 (inst.operands[1].reg);
22096 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
22097 if (op != -1)
22098 inst.instruction |= op << 6;
22099
22100 if (thumb_mode)
22101 inst.instruction |= 0xfc000000;
22102 else
22103 inst.instruction |= 0xf0000000;
22104}
22105
22106static void
22107do_crypto_3op_1 (int u, int op)
22108{
22109 set_pred_insn_type (OUTSIDE_PRED_INSN);
22110
22111 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
22112 N_32 | N_UNT | N_KEY).type == NT_invtype)
22113 return;
22114
22115 inst.error = NULL;
22116
22117 NEON_ENCODE (INTEGER, inst);
22118 neon_three_same (1, u, 8 << op);
22119}
22120
22121static void
22122do_aese (void)
22123{
22124 do_crypto_2op_1 (N_8, 0);
22125}
22126
22127static void
22128do_aesd (void)
22129{
22130 do_crypto_2op_1 (N_8, 1);
22131}
22132
22133static void
22134do_aesmc (void)
22135{
22136 do_crypto_2op_1 (N_8, 2);
22137}
22138
22139static void
22140do_aesimc (void)
22141{
22142 do_crypto_2op_1 (N_8, 3);
22143}
22144
22145static void
22146do_sha1c (void)
22147{
22148 do_crypto_3op_1 (0, 0);
22149}
22150
22151static void
22152do_sha1p (void)
22153{
22154 do_crypto_3op_1 (0, 1);
22155}
22156
22157static void
22158do_sha1m (void)
22159{
22160 do_crypto_3op_1 (0, 2);
22161}
22162
22163static void
22164do_sha1su0 (void)
22165{
22166 do_crypto_3op_1 (0, 3);
22167}
22168
22169static void
22170do_sha256h (void)
22171{
22172 do_crypto_3op_1 (1, 0);
22173}
22174
22175static void
22176do_sha256h2 (void)
22177{
22178 do_crypto_3op_1 (1, 1);
22179}
22180
22181static void
22182do_sha256su1 (void)
22183{
22184 do_crypto_3op_1 (1, 2);
22185}
22186
22187static void
22188do_sha1h (void)
22189{
22190 do_crypto_2op_1 (N_32, -1);
22191}
22192
22193static void
22194do_sha1su1 (void)
22195{
22196 do_crypto_2op_1 (N_32, 0);
22197}
22198
22199static void
22200do_sha256su0 (void)
22201{
22202 do_crypto_2op_1 (N_32, 1);
22203}
22204
22205static void
22206do_crc32_1 (unsigned int poly, unsigned int sz)
22207{
22208 unsigned int Rd = inst.operands[0].reg;
22209 unsigned int Rn = inst.operands[1].reg;
22210 unsigned int Rm = inst.operands[2].reg;
22211
22212 set_pred_insn_type (OUTSIDE_PRED_INSN);
22213 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
22214 inst.instruction |= LOW4 (Rn) << 16;
22215 inst.instruction |= LOW4 (Rm);
22216 inst.instruction |= sz << (thumb_mode ? 4 : 21);
22217 inst.instruction |= poly << (thumb_mode ? 20 : 9);
22218
22219 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
22220 as_warn (UNPRED_REG ("r15"));
22221}
22222
22223static void
22224do_crc32b (void)
22225{
22226 do_crc32_1 (0, 0);
22227}
22228
22229static void
22230do_crc32h (void)
22231{
22232 do_crc32_1 (0, 1);
22233}
22234
22235static void
22236do_crc32w (void)
22237{
22238 do_crc32_1 (0, 2);
22239}
22240
22241static void
22242do_crc32cb (void)
22243{
22244 do_crc32_1 (1, 0);
22245}
22246
22247static void
22248do_crc32ch (void)
22249{
22250 do_crc32_1 (1, 1);
22251}
22252
22253static void
22254do_crc32cw (void)
22255{
22256 do_crc32_1 (1, 2);
22257}
22258
22259static void
22260do_vjcvt (void)
22261{
22262 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
22263 _(BAD_FPU));
22264 neon_check_type (2, NS_FD, N_S32, N_F64);
22265 do_vfp_sp_dp_cvt ();
22266 do_vfp_cond_or_thumb ();
22267}
22268
22269static void
22270do_vdot (void)
22271{
22272 enum neon_shape rs;
22273 constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU));
22274 set_pred_insn_type (OUTSIDE_PRED_INSN);
22275 if (inst.operands[2].isscalar)
22276 {
22277 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
22278 neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
22279
22280 inst.instruction |= (1 << 25);
22281 int index = inst.operands[2].reg & 0xf;
22282 constraint ((index != 1 && index != 0), _("index must be 0 or 1"));
22283 inst.operands[2].reg >>= 4;
22284 constraint (!(inst.operands[2].reg < 16),
22285 _("indexed register must be less than 16"));
22286 neon_three_args (rs == NS_QQS);
22287 inst.instruction |= (index << 5);
22288 }
22289 else
22290 {
22291 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
22292 neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
22293 neon_three_args (rs == NS_QQQ);
22294 }
22295}
22296
22297static void
22298do_vmmla (void)
22299{
22300 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
22301 neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
22302
22303 constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU));
22304 set_pred_insn_type (OUTSIDE_PRED_INSN);
22305
22306 neon_three_args (1);
22307}
22308
22309\f
22310/* Overall per-instruction processing. */
22311
22312/* We need to be able to fix up arbitrary expressions in some statements.
22313 This is so that we can handle symbols that are an arbitrary distance from
22314 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22315 which returns part of an address in a form which will be valid for
22316 a data instruction. We do this by pushing the expression into a symbol
22317 in the expr_section, and creating a fix for that. */
22318
22319static void
22320fix_new_arm (fragS * frag,
22321 int where,
22322 short int size,
22323 expressionS * exp,
22324 int pc_rel,
22325 int reloc)
22326{
22327 fixS * new_fix;
22328
22329 switch (exp->X_op)
22330 {
22331 case O_constant:
22332 if (pc_rel)
22333 {
22334 /* Create an absolute valued symbol, so we have something to
22335 refer to in the object file. Unfortunately for us, gas's
22336 generic expression parsing will already have folded out
22337 any use of .set foo/.type foo %function that may have
22338 been used to set type information of the target location,
22339 that's being specified symbolically. We have to presume
22340 the user knows what they are doing. */
22341 char name[16 + 8];
22342 symbolS *symbol;
22343
22344 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
22345
22346 symbol = symbol_find_or_make (name);
22347 S_SET_SEGMENT (symbol, absolute_section);
22348 symbol_set_frag (symbol, &zero_address_frag);
22349 S_SET_VALUE (symbol, exp->X_add_number);
22350 exp->X_op = O_symbol;
22351 exp->X_add_symbol = symbol;
22352 exp->X_add_number = 0;
22353 }
22354 /* FALLTHROUGH */
22355 case O_symbol:
22356 case O_add:
22357 case O_subtract:
22358 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
22359 (enum bfd_reloc_code_real) reloc);
22360 break;
22361
22362 default:
22363 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
22364 pc_rel, (enum bfd_reloc_code_real) reloc);
22365 break;
22366 }
22367
22368 /* Mark whether the fix is to a THUMB instruction, or an ARM
22369 instruction. */
22370 new_fix->tc_fix_data = thumb_mode;
22371}
22372
22373/* Create a frg for an instruction requiring relaxation. */
22374static void
22375output_relax_insn (void)
22376{
22377 char * to;
22378 symbolS *sym;
22379 int offset;
22380
22381 /* The size of the instruction is unknown, so tie the debug info to the
22382 start of the instruction. */
22383 dwarf2_emit_insn (0);
22384
22385 switch (inst.relocs[0].exp.X_op)
22386 {
22387 case O_symbol:
22388 sym = inst.relocs[0].exp.X_add_symbol;
22389 offset = inst.relocs[0].exp.X_add_number;
22390 break;
22391 case O_constant:
22392 sym = NULL;
22393 offset = inst.relocs[0].exp.X_add_number;
22394 break;
22395 default:
22396 sym = make_expr_symbol (&inst.relocs[0].exp);
22397 offset = 0;
22398 break;
22399 }
22400 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
22401 inst.relax, sym, offset, NULL/*offset, opcode*/);
22402 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
22403}
22404
22405/* Write a 32-bit thumb instruction to buf. */
22406static void
22407put_thumb32_insn (char * buf, unsigned long insn)
22408{
22409 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
22410 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
22411}
22412
22413static void
22414output_inst (const char * str)
22415{
22416 char * to = NULL;
22417
22418 if (inst.error)
22419 {
22420 as_bad ("%s -- `%s'", inst.error, str);
22421 return;
22422 }
22423 if (inst.relax)
22424 {
22425 output_relax_insn ();
22426 return;
22427 }
22428 if (inst.size == 0)
22429 return;
22430
22431 to = frag_more (inst.size);
22432 /* PR 9814: Record the thumb mode into the current frag so that we know
22433 what type of NOP padding to use, if necessary. We override any previous
22434 setting so that if the mode has changed then the NOPS that we use will
22435 match the encoding of the last instruction in the frag. */
22436 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
22437
22438 if (thumb_mode && (inst.size > THUMB_SIZE))
22439 {
22440 gas_assert (inst.size == (2 * THUMB_SIZE));
22441 put_thumb32_insn (to, inst.instruction);
22442 }
22443 else if (inst.size > INSN_SIZE)
22444 {
22445 gas_assert (inst.size == (2 * INSN_SIZE));
22446 md_number_to_chars (to, inst.instruction, INSN_SIZE);
22447 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
22448 }
22449 else
22450 md_number_to_chars (to, inst.instruction, inst.size);
22451
22452 int r;
22453 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
22454 {
22455 if (inst.relocs[r].type != BFD_RELOC_UNUSED)
22456 fix_new_arm (frag_now, to - frag_now->fr_literal,
22457 inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
22458 inst.relocs[r].type);
22459 }
22460
22461 dwarf2_emit_insn (inst.size);
22462}
22463
22464static char *
22465output_it_inst (int cond, int mask, char * to)
22466{
22467 unsigned long instruction = 0xbf00;
22468
22469 mask &= 0xf;
22470 instruction |= mask;
22471 instruction |= cond << 4;
22472
22473 if (to == NULL)
22474 {
22475 to = frag_more (2);
22476#ifdef OBJ_ELF
22477 dwarf2_emit_insn (2);
22478#endif
22479 }
22480
22481 md_number_to_chars (to, instruction, 2);
22482
22483 return to;
22484}
22485
22486/* Tag values used in struct asm_opcode's tag field. */
22487enum opcode_tag
22488{
22489 OT_unconditional, /* Instruction cannot be conditionalized.
22490 The ARM condition field is still 0xE. */
22491 OT_unconditionalF, /* Instruction cannot be conditionalized
22492 and carries 0xF in its ARM condition field. */
22493 OT_csuffix, /* Instruction takes a conditional suffix. */
22494 OT_csuffixF, /* Some forms of the instruction take a scalar
22495 conditional suffix, others place 0xF where the
22496 condition field would be, others take a vector
22497 conditional suffix. */
22498 OT_cinfix3, /* Instruction takes a conditional infix,
22499 beginning at character index 3. (In
22500 unified mode, it becomes a suffix.) */
22501 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
22502 tsts, cmps, cmns, and teqs. */
22503 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
22504 character index 3, even in unified mode. Used for
22505 legacy instructions where suffix and infix forms
22506 may be ambiguous. */
22507 OT_csuf_or_in3, /* Instruction takes either a conditional
22508 suffix or an infix at character index 3. */
22509 OT_odd_infix_unc, /* This is the unconditional variant of an
22510 instruction that takes a conditional infix
22511 at an unusual position. In unified mode,
22512 this variant will accept a suffix. */
22513 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
22514 are the conditional variants of instructions that
22515 take conditional infixes in unusual positions.
22516 The infix appears at character index
22517 (tag - OT_odd_infix_0). These are not accepted
22518 in unified mode. */
22519};
22520
22521/* Subroutine of md_assemble, responsible for looking up the primary
22522 opcode from the mnemonic the user wrote. STR points to the
22523 beginning of the mnemonic.
22524
22525 This is not simply a hash table lookup, because of conditional
22526 variants. Most instructions have conditional variants, which are
22527 expressed with a _conditional affix_ to the mnemonic. If we were
22528 to encode each conditional variant as a literal string in the opcode
22529 table, it would have approximately 20,000 entries.
22530
22531 Most mnemonics take this affix as a suffix, and in unified syntax,
22532 'most' is upgraded to 'all'. However, in the divided syntax, some
22533 instructions take the affix as an infix, notably the s-variants of
22534 the arithmetic instructions. Of those instructions, all but six
22535 have the infix appear after the third character of the mnemonic.
22536
22537 Accordingly, the algorithm for looking up primary opcodes given
22538 an identifier is:
22539
22540 1. Look up the identifier in the opcode table.
22541 If we find a match, go to step U.
22542
22543 2. Look up the last two characters of the identifier in the
22544 conditions table. If we find a match, look up the first N-2
22545 characters of the identifier in the opcode table. If we
22546 find a match, go to step CE.
22547
22548 3. Look up the fourth and fifth characters of the identifier in
22549 the conditions table. If we find a match, extract those
22550 characters from the identifier, and look up the remaining
22551 characters in the opcode table. If we find a match, go
22552 to step CM.
22553
22554 4. Fail.
22555
22556 U. Examine the tag field of the opcode structure, in case this is
22557 one of the six instructions with its conditional infix in an
22558 unusual place. If it is, the tag tells us where to find the
22559 infix; look it up in the conditions table and set inst.cond
22560 accordingly. Otherwise, this is an unconditional instruction.
22561 Again set inst.cond accordingly. Return the opcode structure.
22562
22563 CE. Examine the tag field to make sure this is an instruction that
22564 should receive a conditional suffix. If it is not, fail.
22565 Otherwise, set inst.cond from the suffix we already looked up,
22566 and return the opcode structure.
22567
22568 CM. Examine the tag field to make sure this is an instruction that
22569 should receive a conditional infix after the third character.
22570 If it is not, fail. Otherwise, undo the edits to the current
22571 line of input and proceed as for case CE. */
22572
22573static const struct asm_opcode *
22574opcode_lookup (char **str)
22575{
22576 char *end, *base;
22577 char *affix;
22578 const struct asm_opcode *opcode;
22579 const struct asm_cond *cond;
22580 char save[2];
22581
22582 /* Scan up to the end of the mnemonic, which must end in white space,
22583 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22584 for (base = end = *str; *end != '\0'; end++)
22585 if (*end == ' ' || *end == '.')
22586 break;
22587
22588 if (end == base)
22589 return NULL;
22590
22591 /* Handle a possible width suffix and/or Neon type suffix. */
22592 if (end[0] == '.')
22593 {
22594 int offset = 2;
22595
22596 /* The .w and .n suffixes are only valid if the unified syntax is in
22597 use. */
22598 if (unified_syntax && end[1] == 'w')
22599 inst.size_req = 4;
22600 else if (unified_syntax && end[1] == 'n')
22601 inst.size_req = 2;
22602 else
22603 offset = 0;
22604
22605 inst.vectype.elems = 0;
22606
22607 *str = end + offset;
22608
22609 if (end[offset] == '.')
22610 {
22611 /* See if we have a Neon type suffix (possible in either unified or
22612 non-unified ARM syntax mode). */
22613 if (parse_neon_type (&inst.vectype, str) == FAIL)
22614 return NULL;
22615 }
22616 else if (end[offset] != '\0' && end[offset] != ' ')
22617 return NULL;
22618 }
22619 else
22620 *str = end;
22621
22622 /* Look for unaffixed or special-case affixed mnemonic. */
22623 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
22624 end - base);
22625 if (opcode)
22626 {
22627 /* step U */
22628 if (opcode->tag < OT_odd_infix_0)
22629 {
22630 inst.cond = COND_ALWAYS;
22631 return opcode;
22632 }
22633
22634 if (warn_on_deprecated && unified_syntax)
22635 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22636 affix = base + (opcode->tag - OT_odd_infix_0);
22637 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
22638 gas_assert (cond);
22639
22640 inst.cond = cond->value;
22641 return opcode;
22642 }
22643 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
22644 {
22645 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22646 */
22647 if (end - base < 2)
22648 return NULL;
22649 affix = end - 1;
22650 cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1);
22651 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
22652 affix - base);
22653 /* If this opcode can not be vector predicated then don't accept it with a
22654 vector predication code. */
22655 if (opcode && !opcode->mayBeVecPred)
22656 opcode = NULL;
22657 }
22658 if (!opcode || !cond)
22659 {
22660 /* Cannot have a conditional suffix on a mnemonic of less than two
22661 characters. */
22662 if (end - base < 3)
22663 return NULL;
22664
22665 /* Look for suffixed mnemonic. */
22666 affix = end - 2;
22667 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
22668 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
22669 affix - base);
22670 }
22671
22672 if (opcode && cond)
22673 {
22674 /* step CE */
22675 switch (opcode->tag)
22676 {
22677 case OT_cinfix3_legacy:
22678 /* Ignore conditional suffixes matched on infix only mnemonics. */
22679 break;
22680
22681 case OT_cinfix3:
22682 case OT_cinfix3_deprecated:
22683 case OT_odd_infix_unc:
22684 if (!unified_syntax)
22685 return NULL;
22686 /* Fall through. */
22687
22688 case OT_csuffix:
22689 case OT_csuffixF:
22690 case OT_csuf_or_in3:
22691 inst.cond = cond->value;
22692 return opcode;
22693
22694 case OT_unconditional:
22695 case OT_unconditionalF:
22696 if (thumb_mode)
22697 inst.cond = cond->value;
22698 else
22699 {
22700 /* Delayed diagnostic. */
22701 inst.error = BAD_COND;
22702 inst.cond = COND_ALWAYS;
22703 }
22704 return opcode;
22705
22706 default:
22707 return NULL;
22708 }
22709 }
22710
22711 /* Cannot have a usual-position infix on a mnemonic of less than
22712 six characters (five would be a suffix). */
22713 if (end - base < 6)
22714 return NULL;
22715
22716 /* Look for infixed mnemonic in the usual position. */
22717 affix = base + 3;
22718 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
22719 if (!cond)
22720 return NULL;
22721
22722 memcpy (save, affix, 2);
22723 memmove (affix, affix + 2, (end - affix) - 2);
22724 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
22725 (end - base) - 2);
22726 memmove (affix + 2, affix, (end - affix) - 2);
22727 memcpy (affix, save, 2);
22728
22729 if (opcode
22730 && (opcode->tag == OT_cinfix3
22731 || opcode->tag == OT_cinfix3_deprecated
22732 || opcode->tag == OT_csuf_or_in3
22733 || opcode->tag == OT_cinfix3_legacy))
22734 {
22735 /* Step CM. */
22736 if (warn_on_deprecated && unified_syntax
22737 && (opcode->tag == OT_cinfix3
22738 || opcode->tag == OT_cinfix3_deprecated))
22739 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22740
22741 inst.cond = cond->value;
22742 return opcode;
22743 }
22744
22745 return NULL;
22746}
22747
22748/* This function generates an initial IT instruction, leaving its block
22749 virtually open for the new instructions. Eventually,
22750 the mask will be updated by now_pred_add_mask () each time
22751 a new instruction needs to be included in the IT block.
22752 Finally, the block is closed with close_automatic_it_block ().
22753 The block closure can be requested either from md_assemble (),
22754 a tencode (), or due to a label hook. */
22755
22756static void
22757new_automatic_it_block (int cond)
22758{
22759 now_pred.state = AUTOMATIC_PRED_BLOCK;
22760 now_pred.mask = 0x18;
22761 now_pred.cc = cond;
22762 now_pred.block_length = 1;
22763 mapping_state (MAP_THUMB);
22764 now_pred.insn = output_it_inst (cond, now_pred.mask, NULL);
22765 now_pred.warn_deprecated = FALSE;
22766 now_pred.insn_cond = TRUE;
22767}
22768
22769/* Close an automatic IT block.
22770 See comments in new_automatic_it_block (). */
22771
22772static void
22773close_automatic_it_block (void)
22774{
22775 now_pred.mask = 0x10;
22776 now_pred.block_length = 0;
22777}
22778
22779/* Update the mask of the current automatically-generated IT
22780 instruction. See comments in new_automatic_it_block (). */
22781
22782static void
22783now_pred_add_mask (int cond)
22784{
22785#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22786#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22787 | ((bitvalue) << (nbit)))
22788 const int resulting_bit = (cond & 1);
22789
22790 now_pred.mask &= 0xf;
22791 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
22792 resulting_bit,
22793 (5 - now_pred.block_length));
22794 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
22795 1,
22796 ((5 - now_pred.block_length) - 1));
22797 output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn);
22798
22799#undef CLEAR_BIT
22800#undef SET_BIT_VALUE
22801}
22802
22803/* The IT blocks handling machinery is accessed through the these functions:
22804 it_fsm_pre_encode () from md_assemble ()
22805 set_pred_insn_type () optional, from the tencode functions
22806 set_pred_insn_type_last () ditto
22807 in_pred_block () ditto
22808 it_fsm_post_encode () from md_assemble ()
22809 force_automatic_it_block_close () from label handling functions
22810
22811 Rationale:
22812 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22813 initializing the IT insn type with a generic initial value depending
22814 on the inst.condition.
22815 2) During the tencode function, two things may happen:
22816 a) The tencode function overrides the IT insn type by
22817 calling either set_pred_insn_type (type) or
22818 set_pred_insn_type_last ().
22819 b) The tencode function queries the IT block state by
22820 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22821
22822 Both set_pred_insn_type and in_pred_block run the internal FSM state
22823 handling function (handle_pred_state), because: a) setting the IT insn
22824 type may incur in an invalid state (exiting the function),
22825 and b) querying the state requires the FSM to be updated.
22826 Specifically we want to avoid creating an IT block for conditional
22827 branches, so it_fsm_pre_encode is actually a guess and we can't
22828 determine whether an IT block is required until the tencode () routine
22829 has decided what type of instruction this actually it.
22830 Because of this, if set_pred_insn_type and in_pred_block have to be
22831 used, set_pred_insn_type has to be called first.
22832
22833 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22834 that determines the insn IT type depending on the inst.cond code.
22835 When a tencode () routine encodes an instruction that can be
22836 either outside an IT block, or, in the case of being inside, has to be
22837 the last one, set_pred_insn_type_last () will determine the proper
22838 IT instruction type based on the inst.cond code. Otherwise,
22839 set_pred_insn_type can be called for overriding that logic or
22840 for covering other cases.
22841
22842 Calling handle_pred_state () may not transition the IT block state to
22843 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22844 still queried. Instead, if the FSM determines that the state should
22845 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22846 after the tencode () function: that's what it_fsm_post_encode () does.
22847
22848 Since in_pred_block () calls the state handling function to get an
22849 updated state, an error may occur (due to invalid insns combination).
22850 In that case, inst.error is set.
22851 Therefore, inst.error has to be checked after the execution of
22852 the tencode () routine.
22853
22854 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22855 any pending state change (if any) that didn't take place in
22856 handle_pred_state () as explained above. */
22857
22858static void
22859it_fsm_pre_encode (void)
22860{
22861 if (inst.cond != COND_ALWAYS)
22862 inst.pred_insn_type = INSIDE_IT_INSN;
22863 else
22864 inst.pred_insn_type = OUTSIDE_PRED_INSN;
22865
22866 now_pred.state_handled = 0;
22867}
22868
22869/* IT state FSM handling function. */
22870/* MVE instructions and non-MVE instructions are handled differently because of
22871 the introduction of VPT blocks.
22872 Specifications say that any non-MVE instruction inside a VPT block is
22873 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22874 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22875 few exceptions we have MVE_UNPREDICABLE_INSN.
22876 The error messages provided depending on the different combinations possible
22877 are described in the cases below:
22878 For 'most' MVE instructions:
22879 1) In an IT block, with an IT code: syntax error
22880 2) In an IT block, with a VPT code: error: must be in a VPT block
22881 3) In an IT block, with no code: warning: UNPREDICTABLE
22882 4) In a VPT block, with an IT code: syntax error
22883 5) In a VPT block, with a VPT code: OK!
22884 6) In a VPT block, with no code: error: missing code
22885 7) Outside a pred block, with an IT code: error: syntax error
22886 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22887 9) Outside a pred block, with no code: OK!
22888 For non-MVE instructions:
22889 10) In an IT block, with an IT code: OK!
22890 11) In an IT block, with a VPT code: syntax error
22891 12) In an IT block, with no code: error: missing code
22892 13) In a VPT block, with an IT code: error: should be in an IT block
22893 14) In a VPT block, with a VPT code: syntax error
22894 15) In a VPT block, with no code: UNPREDICTABLE
22895 16) Outside a pred block, with an IT code: error: should be in an IT block
22896 17) Outside a pred block, with a VPT code: syntax error
22897 18) Outside a pred block, with no code: OK!
22898 */
22899
22900
22901static int
22902handle_pred_state (void)
22903{
22904 now_pred.state_handled = 1;
22905 now_pred.insn_cond = FALSE;
22906
22907 switch (now_pred.state)
22908 {
22909 case OUTSIDE_PRED_BLOCK:
22910 switch (inst.pred_insn_type)
22911 {
22912 case MVE_UNPREDICABLE_INSN:
22913 case MVE_OUTSIDE_PRED_INSN:
22914 if (inst.cond < COND_ALWAYS)
22915 {
22916 /* Case 7: Outside a pred block, with an IT code: error: syntax
22917 error. */
22918 inst.error = BAD_SYNTAX;
22919 return FAIL;
22920 }
22921 /* Case 9: Outside a pred block, with no code: OK! */
22922 break;
22923 case OUTSIDE_PRED_INSN:
22924 if (inst.cond > COND_ALWAYS)
22925 {
22926 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22927 */
22928 inst.error = BAD_SYNTAX;
22929 return FAIL;
22930 }
22931 /* Case 18: Outside a pred block, with no code: OK! */
22932 break;
22933
22934 case INSIDE_VPT_INSN:
22935 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22936 a VPT block. */
22937 inst.error = BAD_OUT_VPT;
22938 return FAIL;
22939
22940 case INSIDE_IT_INSN:
22941 case INSIDE_IT_LAST_INSN:
22942 if (inst.cond < COND_ALWAYS)
22943 {
22944 /* Case 16: Outside a pred block, with an IT code: error: should
22945 be in an IT block. */
22946 if (thumb_mode == 0)
22947 {
22948 if (unified_syntax
22949 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
22950 as_tsktsk (_("Warning: conditional outside an IT block"\
22951 " for Thumb."));
22952 }
22953 else
22954 {
22955 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
22956 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
22957 {
22958 /* Automatically generate the IT instruction. */
22959 new_automatic_it_block (inst.cond);
22960 if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
22961 close_automatic_it_block ();
22962 }
22963 else
22964 {
22965 inst.error = BAD_OUT_IT;
22966 return FAIL;
22967 }
22968 }
22969 break;
22970 }
22971 else if (inst.cond > COND_ALWAYS)
22972 {
22973 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22974 */
22975 inst.error = BAD_SYNTAX;
22976 return FAIL;
22977 }
22978 else
22979 gas_assert (0);
22980 case IF_INSIDE_IT_LAST_INSN:
22981 case NEUTRAL_IT_INSN:
22982 break;
22983
22984 case VPT_INSN:
22985 if (inst.cond != COND_ALWAYS)
22986 first_error (BAD_SYNTAX);
22987 now_pred.state = MANUAL_PRED_BLOCK;
22988 now_pred.block_length = 0;
22989 now_pred.type = VECTOR_PRED;
22990 now_pred.cc = 0;
22991 break;
22992 case IT_INSN:
22993 now_pred.state = MANUAL_PRED_BLOCK;
22994 now_pred.block_length = 0;
22995 now_pred.type = SCALAR_PRED;
22996 break;
22997 }
22998 break;
22999
23000 case AUTOMATIC_PRED_BLOCK:
23001 /* Three things may happen now:
23002 a) We should increment current it block size;
23003 b) We should close current it block (closing insn or 4 insns);
23004 c) We should close current it block and start a new one (due
23005 to incompatible conditions or
23006 4 insns-length block reached). */
23007
23008 switch (inst.pred_insn_type)
23009 {
23010 case INSIDE_VPT_INSN:
23011 case VPT_INSN:
23012 case MVE_UNPREDICABLE_INSN:
23013 case MVE_OUTSIDE_PRED_INSN:
23014 gas_assert (0);
23015 case OUTSIDE_PRED_INSN:
23016 /* The closure of the block shall happen immediately,
23017 so any in_pred_block () call reports the block as closed. */
23018 force_automatic_it_block_close ();
23019 break;
23020
23021 case INSIDE_IT_INSN:
23022 case INSIDE_IT_LAST_INSN:
23023 case IF_INSIDE_IT_LAST_INSN:
23024 now_pred.block_length++;
23025
23026 if (now_pred.block_length > 4
23027 || !now_pred_compatible (inst.cond))
23028 {
23029 force_automatic_it_block_close ();
23030 if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
23031 new_automatic_it_block (inst.cond);
23032 }
23033 else
23034 {
23035 now_pred.insn_cond = TRUE;
23036 now_pred_add_mask (inst.cond);
23037 }
23038
23039 if (now_pred.state == AUTOMATIC_PRED_BLOCK
23040 && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
23041 || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
23042 close_automatic_it_block ();
23043 break;
23044
23045 /* Fallthrough. */
23046 case NEUTRAL_IT_INSN:
23047 now_pred.block_length++;
23048 now_pred.insn_cond = TRUE;
23049
23050 if (now_pred.block_length > 4)
23051 force_automatic_it_block_close ();
23052 else
23053 now_pred_add_mask (now_pred.cc & 1);
23054 break;
23055
23056 case IT_INSN:
23057 close_automatic_it_block ();
23058 now_pred.state = MANUAL_PRED_BLOCK;
23059 break;
23060 }
23061 break;
23062
23063 case MANUAL_PRED_BLOCK:
23064 {
23065 int cond, is_last;
23066 if (now_pred.type == SCALAR_PRED)
23067 {
23068 /* Check conditional suffixes. */
23069 cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1;
23070 now_pred.mask <<= 1;
23071 now_pred.mask &= 0x1f;
23072 is_last = (now_pred.mask == 0x10);
23073 }
23074 else
23075 {
23076 now_pred.cc ^= (now_pred.mask >> 4);
23077 cond = now_pred.cc + 0xf;
23078 now_pred.mask <<= 1;
23079 now_pred.mask &= 0x1f;
23080 is_last = now_pred.mask == 0x10;
23081 }
23082 now_pred.insn_cond = TRUE;
23083
23084 switch (inst.pred_insn_type)
23085 {
23086 case OUTSIDE_PRED_INSN:
23087 if (now_pred.type == SCALAR_PRED)
23088 {
23089 if (inst.cond == COND_ALWAYS)
23090 {
23091 /* Case 12: In an IT block, with no code: error: missing
23092 code. */
23093 inst.error = BAD_NOT_IT;
23094 return FAIL;
23095 }
23096 else if (inst.cond > COND_ALWAYS)
23097 {
23098 /* Case 11: In an IT block, with a VPT code: syntax error.
23099 */
23100 inst.error = BAD_SYNTAX;
23101 return FAIL;
23102 }
23103 else if (thumb_mode)
23104 {
23105 /* This is for some special cases where a non-MVE
23106 instruction is not allowed in an IT block, such as cbz,
23107 but are put into one with a condition code.
23108 You could argue this should be a syntax error, but we
23109 gave the 'not allowed in IT block' diagnostic in the
23110 past so we will keep doing so. */
23111 inst.error = BAD_NOT_IT;
23112 return FAIL;
23113 }
23114 break;
23115 }
23116 else
23117 {
23118 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
23119 as_tsktsk (MVE_NOT_VPT);
23120 return SUCCESS;
23121 }
23122 case MVE_OUTSIDE_PRED_INSN:
23123 if (now_pred.type == SCALAR_PRED)
23124 {
23125 if (inst.cond == COND_ALWAYS)
23126 {
23127 /* Case 3: In an IT block, with no code: warning:
23128 UNPREDICTABLE. */
23129 as_tsktsk (MVE_NOT_IT);
23130 return SUCCESS;
23131 }
23132 else if (inst.cond < COND_ALWAYS)
23133 {
23134 /* Case 1: In an IT block, with an IT code: syntax error.
23135 */
23136 inst.error = BAD_SYNTAX;
23137 return FAIL;
23138 }
23139 else
23140 gas_assert (0);
23141 }
23142 else
23143 {
23144 if (inst.cond < COND_ALWAYS)
23145 {
23146 /* Case 4: In a VPT block, with an IT code: syntax error.
23147 */
23148 inst.error = BAD_SYNTAX;
23149 return FAIL;
23150 }
23151 else if (inst.cond == COND_ALWAYS)
23152 {
23153 /* Case 6: In a VPT block, with no code: error: missing
23154 code. */
23155 inst.error = BAD_NOT_VPT;
23156 return FAIL;
23157 }
23158 else
23159 {
23160 gas_assert (0);
23161 }
23162 }
23163 case MVE_UNPREDICABLE_INSN:
23164 as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT);
23165 return SUCCESS;
23166 case INSIDE_IT_INSN:
23167 if (inst.cond > COND_ALWAYS)
23168 {
23169 /* Case 11: In an IT block, with a VPT code: syntax error. */
23170 /* Case 14: In a VPT block, with a VPT code: syntax error. */
23171 inst.error = BAD_SYNTAX;
23172 return FAIL;
23173 }
23174 else if (now_pred.type == SCALAR_PRED)
23175 {
23176 /* Case 10: In an IT block, with an IT code: OK! */
23177 if (cond != inst.cond)
23178 {
23179 inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
23180 BAD_VPT_COND;
23181 return FAIL;
23182 }
23183 }
23184 else
23185 {
23186 /* Case 13: In a VPT block, with an IT code: error: should be
23187 in an IT block. */
23188 inst.error = BAD_OUT_IT;
23189 return FAIL;
23190 }
23191 break;
23192
23193 case INSIDE_VPT_INSN:
23194 if (now_pred.type == SCALAR_PRED)
23195 {
23196 /* Case 2: In an IT block, with a VPT code: error: must be in a
23197 VPT block. */
23198 inst.error = BAD_OUT_VPT;
23199 return FAIL;
23200 }
23201 /* Case 5: In a VPT block, with a VPT code: OK! */
23202 else if (cond != inst.cond)
23203 {
23204 inst.error = BAD_VPT_COND;
23205 return FAIL;
23206 }
23207 break;
23208 case INSIDE_IT_LAST_INSN:
23209 case IF_INSIDE_IT_LAST_INSN:
23210 if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
23211 {
23212 /* Case 4: In a VPT block, with an IT code: syntax error. */
23213 /* Case 11: In an IT block, with a VPT code: syntax error. */
23214 inst.error = BAD_SYNTAX;
23215 return FAIL;
23216 }
23217 else if (cond != inst.cond)
23218 {
23219 inst.error = BAD_IT_COND;
23220 return FAIL;
23221 }
23222 if (!is_last)
23223 {
23224 inst.error = BAD_BRANCH;
23225 return FAIL;
23226 }
23227 break;
23228
23229 case NEUTRAL_IT_INSN:
23230 /* The BKPT instruction is unconditional even in a IT or VPT
23231 block. */
23232 break;
23233
23234 case IT_INSN:
23235 if (now_pred.type == SCALAR_PRED)
23236 {
23237 inst.error = BAD_IT_IT;
23238 return FAIL;
23239 }
23240 /* fall through. */
23241 case VPT_INSN:
23242 if (inst.cond == COND_ALWAYS)
23243 {
23244 /* Executing a VPT/VPST instruction inside an IT block or a
23245 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23246 */
23247 if (now_pred.type == SCALAR_PRED)
23248 as_tsktsk (MVE_NOT_IT);
23249 else
23250 as_tsktsk (MVE_NOT_VPT);
23251 return SUCCESS;
23252 }
23253 else
23254 {
23255 /* VPT/VPST do not accept condition codes. */
23256 inst.error = BAD_SYNTAX;
23257 return FAIL;
23258 }
23259 }
23260 }
23261 break;
23262 }
23263
23264 return SUCCESS;
23265}
23266
23267struct depr_insn_mask
23268{
23269 unsigned long pattern;
23270 unsigned long mask;
23271 const char* description;
23272};
23273
23274/* List of 16-bit instruction patterns deprecated in an IT block in
23275 ARMv8. */
23276static const struct depr_insn_mask depr_it_insns[] = {
23277 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23278 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23279 { 0xa000, 0xb800, N_("ADR") },
23280 { 0x4800, 0xf800, N_("Literal loads") },
23281 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23282 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
23283 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23284 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
23285 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
23286 { 0, 0, NULL }
23287};
23288
23289static void
23290it_fsm_post_encode (void)
23291{
23292 int is_last;
23293
23294 if (!now_pred.state_handled)
23295 handle_pred_state ();
23296
23297 if (now_pred.insn_cond
23298 && warn_on_restrict_it
23299 && !now_pred.warn_deprecated
23300 && warn_on_deprecated
23301 && (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
23302 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8r))
23303 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
23304 {
23305 if (inst.instruction >= 0x10000)
23306 {
23307 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
23308 "performance deprecated in ARMv8-A and ARMv8-R"));
23309 now_pred.warn_deprecated = TRUE;
23310 }
23311 else
23312 {
23313 const struct depr_insn_mask *p = depr_it_insns;
23314
23315 while (p->mask != 0)
23316 {
23317 if ((inst.instruction & p->mask) == p->pattern)
23318 {
23319 as_tsktsk (_("IT blocks containing 16-bit Thumb "
23320 "instructions of the following class are "
23321 "performance deprecated in ARMv8-A and "
23322 "ARMv8-R: %s"), p->description);
23323 now_pred.warn_deprecated = TRUE;
23324 break;
23325 }
23326
23327 ++p;
23328 }
23329 }
23330
23331 if (now_pred.block_length > 1)
23332 {
23333 as_tsktsk (_("IT blocks containing more than one conditional "
23334 "instruction are performance deprecated in ARMv8-A and "
23335 "ARMv8-R"));
23336 now_pred.warn_deprecated = TRUE;
23337 }
23338 }
23339
23340 is_last = (now_pred.mask == 0x10);
23341 if (is_last)
23342 {
23343 now_pred.state = OUTSIDE_PRED_BLOCK;
23344 now_pred.mask = 0;
23345 }
23346}
23347
23348static void
23349force_automatic_it_block_close (void)
23350{
23351 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
23352 {
23353 close_automatic_it_block ();
23354 now_pred.state = OUTSIDE_PRED_BLOCK;
23355 now_pred.mask = 0;
23356 }
23357}
23358
23359static int
23360in_pred_block (void)
23361{
23362 if (!now_pred.state_handled)
23363 handle_pred_state ();
23364
23365 return now_pred.state != OUTSIDE_PRED_BLOCK;
23366}
23367
23368/* Whether OPCODE only has T32 encoding. Since this function is only used by
23369 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23370 here, hence the "known" in the function name. */
23371
23372static bfd_boolean
23373known_t32_only_insn (const struct asm_opcode *opcode)
23374{
23375 /* Original Thumb-1 wide instruction. */
23376 if (opcode->tencode == do_t_blx
23377 || opcode->tencode == do_t_branch23
23378 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
23379 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
23380 return TRUE;
23381
23382 /* Wide-only instruction added to ARMv8-M Baseline. */
23383 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
23384 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
23385 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
23386 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
23387 return TRUE;
23388
23389 return FALSE;
23390}
23391
23392/* Whether wide instruction variant can be used if available for a valid OPCODE
23393 in ARCH. */
23394
23395static bfd_boolean
23396t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
23397{
23398 if (known_t32_only_insn (opcode))
23399 return TRUE;
23400
23401 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
23402 of variant T3 of B.W is checked in do_t_branch. */
23403 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
23404 && opcode->tencode == do_t_branch)
23405 return TRUE;
23406
23407 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
23408 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
23409 && opcode->tencode == do_t_mov_cmp
23410 /* Make sure CMP instruction is not affected. */
23411 && opcode->aencode == do_mov)
23412 return TRUE;
23413
23414 /* Wide instruction variants of all instructions with narrow *and* wide
23415 variants become available with ARMv6t2. Other opcodes are either
23416 narrow-only or wide-only and are thus available if OPCODE is valid. */
23417 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
23418 return TRUE;
23419
23420 /* OPCODE with narrow only instruction variant or wide variant not
23421 available. */
23422 return FALSE;
23423}
23424
23425void
23426md_assemble (char *str)
23427{
23428 char *p = str;
23429 const struct asm_opcode * opcode;
23430
23431 /* Align the previous label if needed. */
23432 if (last_label_seen != NULL)
23433 {
23434 symbol_set_frag (last_label_seen, frag_now);
23435 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
23436 S_SET_SEGMENT (last_label_seen, now_seg);
23437 }
23438
23439 memset (&inst, '\0', sizeof (inst));
23440 int r;
23441 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
23442 inst.relocs[r].type = BFD_RELOC_UNUSED;
23443
23444 opcode = opcode_lookup (&p);
23445 if (!opcode)
23446 {
23447 /* It wasn't an instruction, but it might be a register alias of
23448 the form alias .req reg, or a Neon .dn/.qn directive. */
23449 if (! create_register_alias (str, p)
23450 && ! create_neon_reg_alias (str, p))
23451 as_bad (_("bad instruction `%s'"), str);
23452
23453 return;
23454 }
23455
23456 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
23457 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
23458
23459 /* The value which unconditional instructions should have in place of the
23460 condition field. */
23461 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
23462
23463 if (thumb_mode)
23464 {
23465 arm_feature_set variant;
23466
23467 variant = cpu_variant;
23468 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
23469 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
23470 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
23471 /* Check that this instruction is supported for this CPU. */
23472 if (!opcode->tvariant
23473 || (thumb_mode == 1
23474 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
23475 {
23476 if (opcode->tencode == do_t_swi)
23477 as_bad (_("SVC is not permitted on this architecture"));
23478 else
23479 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
23480 return;
23481 }
23482 if (inst.cond != COND_ALWAYS && !unified_syntax
23483 && opcode->tencode != do_t_branch)
23484 {
23485 as_bad (_("Thumb does not support conditional execution"));
23486 return;
23487 }
23488
23489 /* Two things are addressed here:
23490 1) Implicit require narrow instructions on Thumb-1.
23491 This avoids relaxation accidentally introducing Thumb-2
23492 instructions.
23493 2) Reject wide instructions in non Thumb-2 cores.
23494
23495 Only instructions with narrow and wide variants need to be handled
23496 but selecting all non wide-only instructions is easier. */
23497 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
23498 && !t32_insn_ok (variant, opcode))
23499 {
23500 if (inst.size_req == 0)
23501 inst.size_req = 2;
23502 else if (inst.size_req == 4)
23503 {
23504 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
23505 as_bad (_("selected processor does not support 32bit wide "
23506 "variant of instruction `%s'"), str);
23507 else
23508 as_bad (_("selected processor does not support `%s' in "
23509 "Thumb-2 mode"), str);
23510 return;
23511 }
23512 }
23513
23514 inst.instruction = opcode->tvalue;
23515
23516 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
23517 {
23518 /* Prepare the pred_insn_type for those encodings that don't set
23519 it. */
23520 it_fsm_pre_encode ();
23521
23522 opcode->tencode ();
23523
23524 it_fsm_post_encode ();
23525 }
23526
23527 if (!(inst.error || inst.relax))
23528 {
23529 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
23530 inst.size = (inst.instruction > 0xffff ? 4 : 2);
23531 if (inst.size_req && inst.size_req != inst.size)
23532 {
23533 as_bad (_("cannot honor width suffix -- `%s'"), str);
23534 return;
23535 }
23536 }
23537
23538 /* Something has gone badly wrong if we try to relax a fixed size
23539 instruction. */
23540 gas_assert (inst.size_req == 0 || !inst.relax);
23541
23542 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
23543 *opcode->tvariant);
23544 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23545 set those bits when Thumb-2 32-bit instructions are seen. The impact
23546 of relaxable instructions will be considered later after we finish all
23547 relaxation. */
23548 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
23549 variant = arm_arch_none;
23550 else
23551 variant = cpu_variant;
23552 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
23553 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
23554 arm_ext_v6t2);
23555
23556 check_neon_suffixes;
23557
23558 if (!inst.error)
23559 {
23560 mapping_state (MAP_THUMB);
23561 }
23562 }
23563 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23564 {
23565 bfd_boolean is_bx;
23566
23567 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23568 is_bx = (opcode->aencode == do_bx);
23569
23570 /* Check that this instruction is supported for this CPU. */
23571 if (!(is_bx && fix_v4bx)
23572 && !(opcode->avariant &&
23573 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
23574 {
23575 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
23576 return;
23577 }
23578 if (inst.size_req)
23579 {
23580 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
23581 return;
23582 }
23583
23584 inst.instruction = opcode->avalue;
23585 if (opcode->tag == OT_unconditionalF)
23586 inst.instruction |= 0xFU << 28;
23587 else
23588 inst.instruction |= inst.cond << 28;
23589 inst.size = INSN_SIZE;
23590 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
23591 {
23592 it_fsm_pre_encode ();
23593 opcode->aencode ();
23594 it_fsm_post_encode ();
23595 }
23596 /* Arm mode bx is marked as both v4T and v5 because it's still required
23597 on a hypothetical non-thumb v5 core. */
23598 if (is_bx)
23599 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
23600 else
23601 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
23602 *opcode->avariant);
23603
23604 check_neon_suffixes;
23605
23606 if (!inst.error)
23607 {
23608 mapping_state (MAP_ARM);
23609 }
23610 }
23611 else
23612 {
23613 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23614 "-- `%s'"), str);
23615 return;
23616 }
23617 output_inst (str);
23618}
23619
23620static void
23621check_pred_blocks_finished (void)
23622{
23623#ifdef OBJ_ELF
23624 asection *sect;
23625
23626 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
23627 if (seg_info (sect)->tc_segment_info_data.current_pred.state
23628 == MANUAL_PRED_BLOCK)
23629 {
23630 if (now_pred.type == SCALAR_PRED)
23631 as_warn (_("section '%s' finished with an open IT block."),
23632 sect->name);
23633 else
23634 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23635 sect->name);
23636 }
23637#else
23638 if (now_pred.state == MANUAL_PRED_BLOCK)
23639 {
23640 if (now_pred.type == SCALAR_PRED)
23641 as_warn (_("file finished with an open IT block."));
23642 else
23643 as_warn (_("file finished with an open VPT/VPST block."));
23644 }
23645#endif
23646}
23647
23648/* Various frobbings of labels and their addresses. */
23649
23650void
23651arm_start_line_hook (void)
23652{
23653 last_label_seen = NULL;
23654}
23655
23656void
23657arm_frob_label (symbolS * sym)
23658{
23659 last_label_seen = sym;
23660
23661 ARM_SET_THUMB (sym, thumb_mode);
23662
23663#if defined OBJ_COFF || defined OBJ_ELF
23664 ARM_SET_INTERWORK (sym, support_interwork);
23665#endif
23666
23667 force_automatic_it_block_close ();
23668
23669 /* Note - do not allow local symbols (.Lxxx) to be labelled
23670 as Thumb functions. This is because these labels, whilst
23671 they exist inside Thumb code, are not the entry points for
23672 possible ARM->Thumb calls. Also, these labels can be used
23673 as part of a computed goto or switch statement. eg gcc
23674 can generate code that looks like this:
23675
23676 ldr r2, [pc, .Laaa]
23677 lsl r3, r3, #2
23678 ldr r2, [r3, r2]
23679 mov pc, r2
23680
23681 .Lbbb: .word .Lxxx
23682 .Lccc: .word .Lyyy
23683 ..etc...
23684 .Laaa: .word Lbbb
23685
23686 The first instruction loads the address of the jump table.
23687 The second instruction converts a table index into a byte offset.
23688 The third instruction gets the jump address out of the table.
23689 The fourth instruction performs the jump.
23690
23691 If the address stored at .Laaa is that of a symbol which has the
23692 Thumb_Func bit set, then the linker will arrange for this address
23693 to have the bottom bit set, which in turn would mean that the
23694 address computation performed by the third instruction would end
23695 up with the bottom bit set. Since the ARM is capable of unaligned
23696 word loads, the instruction would then load the incorrect address
23697 out of the jump table, and chaos would ensue. */
23698 if (label_is_thumb_function_name
23699 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
23700 && (bfd_section_flags (now_seg) & SEC_CODE) != 0)
23701 {
23702 /* When the address of a Thumb function is taken the bottom
23703 bit of that address should be set. This will allow
23704 interworking between Arm and Thumb functions to work
23705 correctly. */
23706
23707 THUMB_SET_FUNC (sym, 1);
23708
23709 label_is_thumb_function_name = FALSE;
23710 }
23711
23712 dwarf2_emit_label (sym);
23713}
23714
23715bfd_boolean
23716arm_data_in_code (void)
23717{
23718 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
23719 {
23720 *input_line_pointer = '/';
23721 input_line_pointer += 5;
23722 *input_line_pointer = 0;
23723 return TRUE;
23724 }
23725
23726 return FALSE;
23727}
23728
23729char *
23730arm_canonicalize_symbol_name (char * name)
23731{
23732 int len;
23733
23734 if (thumb_mode && (len = strlen (name)) > 5
23735 && streq (name + len - 5, "/data"))
23736 *(name + len - 5) = 0;
23737
23738 return name;
23739}
23740\f
23741/* Table of all register names defined by default. The user can
23742 define additional names with .req. Note that all register names
23743 should appear in both upper and lowercase variants. Some registers
23744 also have mixed-case names. */
23745
23746#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23747#define REGNUM(p,n,t) REGDEF(p##n, n, t)
23748#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23749#define REGSET(p,t) \
23750 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23751 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23752 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23753 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23754#define REGSETH(p,t) \
23755 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23756 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23757 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23758 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23759#define REGSET2(p,t) \
23760 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23761 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23762 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23763 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23764#define SPLRBANK(base,bank,t) \
23765 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23766 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23767 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23768 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23769 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23770 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23771
23772static const struct reg_entry reg_names[] =
23773{
23774 /* ARM integer registers. */
23775 REGSET(r, RN), REGSET(R, RN),
23776
23777 /* ATPCS synonyms. */
23778 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
23779 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
23780 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
23781
23782 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
23783 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
23784 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
23785
23786 /* Well-known aliases. */
23787 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
23788 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
23789
23790 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
23791 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
23792
23793 /* Defining the new Zero register from ARMv8.1-M. */
23794 REGDEF(zr,15,ZR),
23795 REGDEF(ZR,15,ZR),
23796
23797 /* Coprocessor numbers. */
23798 REGSET(p, CP), REGSET(P, CP),
23799
23800 /* Coprocessor register numbers. The "cr" variants are for backward
23801 compatibility. */
23802 REGSET(c, CN), REGSET(C, CN),
23803 REGSET(cr, CN), REGSET(CR, CN),
23804
23805 /* ARM banked registers. */
23806 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
23807 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
23808 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
23809 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
23810 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
23811 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
23812 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
23813
23814 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
23815 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
23816 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
23817 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
23818 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
23819 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
23820 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
23821 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
23822
23823 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
23824 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
23825 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
23826 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
23827 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
23828 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
23829 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
23830 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
23831 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
23832
23833 /* FPA registers. */
23834 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
23835 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
23836
23837 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
23838 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
23839
23840 /* VFP SP registers. */
23841 REGSET(s,VFS), REGSET(S,VFS),
23842 REGSETH(s,VFS), REGSETH(S,VFS),
23843
23844 /* VFP DP Registers. */
23845 REGSET(d,VFD), REGSET(D,VFD),
23846 /* Extra Neon DP registers. */
23847 REGSETH(d,VFD), REGSETH(D,VFD),
23848
23849 /* Neon QP registers. */
23850 REGSET2(q,NQ), REGSET2(Q,NQ),
23851
23852 /* VFP control registers. */
23853 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
23854 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
23855 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
23856 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
23857 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
23858 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
23859 REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
23860 REGDEF(fpscr_nzcvqc,2,VFC), REGDEF(FPSCR_nzcvqc,2,VFC),
23861 REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC),
23862 REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC),
23863 REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC),
23864
23865 /* Maverick DSP coprocessor registers. */
23866 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
23867 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
23868
23869 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
23870 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
23871 REGDEF(dspsc,0,DSPSC),
23872
23873 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
23874 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
23875 REGDEF(DSPSC,0,DSPSC),
23876
23877 /* iWMMXt data registers - p0, c0-15. */
23878 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
23879
23880 /* iWMMXt control registers - p1, c0-3. */
23881 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
23882 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
23883 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
23884 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
23885
23886 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23887 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
23888 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
23889 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
23890 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
23891
23892 /* XScale accumulator registers. */
23893 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
23894};
23895#undef REGDEF
23896#undef REGNUM
23897#undef REGSET
23898
23899/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23900 within psr_required_here. */
23901static const struct asm_psr psrs[] =
23902{
23903 /* Backward compatibility notation. Note that "all" is no longer
23904 truly all possible PSR bits. */
23905 {"all", PSR_c | PSR_f},
23906 {"flg", PSR_f},
23907 {"ctl", PSR_c},
23908
23909 /* Individual flags. */
23910 {"f", PSR_f},
23911 {"c", PSR_c},
23912 {"x", PSR_x},
23913 {"s", PSR_s},
23914
23915 /* Combinations of flags. */
23916 {"fs", PSR_f | PSR_s},
23917 {"fx", PSR_f | PSR_x},
23918 {"fc", PSR_f | PSR_c},
23919 {"sf", PSR_s | PSR_f},
23920 {"sx", PSR_s | PSR_x},
23921 {"sc", PSR_s | PSR_c},
23922 {"xf", PSR_x | PSR_f},
23923 {"xs", PSR_x | PSR_s},
23924 {"xc", PSR_x | PSR_c},
23925 {"cf", PSR_c | PSR_f},
23926 {"cs", PSR_c | PSR_s},
23927 {"cx", PSR_c | PSR_x},
23928 {"fsx", PSR_f | PSR_s | PSR_x},
23929 {"fsc", PSR_f | PSR_s | PSR_c},
23930 {"fxs", PSR_f | PSR_x | PSR_s},
23931 {"fxc", PSR_f | PSR_x | PSR_c},
23932 {"fcs", PSR_f | PSR_c | PSR_s},
23933 {"fcx", PSR_f | PSR_c | PSR_x},
23934 {"sfx", PSR_s | PSR_f | PSR_x},
23935 {"sfc", PSR_s | PSR_f | PSR_c},
23936 {"sxf", PSR_s | PSR_x | PSR_f},
23937 {"sxc", PSR_s | PSR_x | PSR_c},
23938 {"scf", PSR_s | PSR_c | PSR_f},
23939 {"scx", PSR_s | PSR_c | PSR_x},
23940 {"xfs", PSR_x | PSR_f | PSR_s},
23941 {"xfc", PSR_x | PSR_f | PSR_c},
23942 {"xsf", PSR_x | PSR_s | PSR_f},
23943 {"xsc", PSR_x | PSR_s | PSR_c},
23944 {"xcf", PSR_x | PSR_c | PSR_f},
23945 {"xcs", PSR_x | PSR_c | PSR_s},
23946 {"cfs", PSR_c | PSR_f | PSR_s},
23947 {"cfx", PSR_c | PSR_f | PSR_x},
23948 {"csf", PSR_c | PSR_s | PSR_f},
23949 {"csx", PSR_c | PSR_s | PSR_x},
23950 {"cxf", PSR_c | PSR_x | PSR_f},
23951 {"cxs", PSR_c | PSR_x | PSR_s},
23952 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
23953 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
23954 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
23955 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
23956 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
23957 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
23958 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
23959 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
23960 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
23961 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
23962 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
23963 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
23964 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
23965 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
23966 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
23967 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
23968 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
23969 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
23970 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
23971 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
23972 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
23973 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
23974 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
23975 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
23976};
23977
23978/* Table of V7M psr names. */
23979static const struct asm_psr v7m_psrs[] =
23980{
23981 {"apsr", 0x0 }, {"APSR", 0x0 },
23982 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23983 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23984 {"psr", 0x3 }, {"PSR", 0x3 },
23985 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23986 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23987 {"epsr", 0x6 }, {"EPSR", 0x6 },
23988 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23989 {"msp", 0x8 }, {"MSP", 0x8 },
23990 {"psp", 0x9 }, {"PSP", 0x9 },
23991 {"msplim", 0xa }, {"MSPLIM", 0xa },
23992 {"psplim", 0xb }, {"PSPLIM", 0xb },
23993 {"primask", 0x10}, {"PRIMASK", 0x10},
23994 {"basepri", 0x11}, {"BASEPRI", 0x11},
23995 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23996 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23997 {"control", 0x14}, {"CONTROL", 0x14},
23998 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23999 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
24000 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
24001 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
24002 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
24003 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
24004 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24005 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
24006 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
24007};
24008
24009/* Table of all shift-in-operand names. */
24010static const struct asm_shift_name shift_names [] =
24011{
24012 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
24013 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
24014 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
24015 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
24016 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
24017 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX },
24018 { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW}
24019};
24020
24021/* Table of all explicit relocation names. */
24022#ifdef OBJ_ELF
24023static struct reloc_entry reloc_names[] =
24024{
24025 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
24026 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
24027 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
24028 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
24029 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
24030 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
24031 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
24032 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
24033 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
24034 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
24035 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
24036 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
24037 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
24038 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
24039 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
24040 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
24041 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
24042 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ},
24043 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC },
24044 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC },
24045 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC },
24046 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC },
24047 { "funcdesc", BFD_RELOC_ARM_FUNCDESC },
24048 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC },
24049 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC },
24050 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC },
24051 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC },
24052};
24053#endif
24054
24055/* Table of all conditional affixes. */
24056static const struct asm_cond conds[] =
24057{
24058 {"eq", 0x0},
24059 {"ne", 0x1},
24060 {"cs", 0x2}, {"hs", 0x2},
24061 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24062 {"mi", 0x4},
24063 {"pl", 0x5},
24064 {"vs", 0x6},
24065 {"vc", 0x7},
24066 {"hi", 0x8},
24067 {"ls", 0x9},
24068 {"ge", 0xa},
24069 {"lt", 0xb},
24070 {"gt", 0xc},
24071 {"le", 0xd},
24072 {"al", 0xe}
24073};
24074static const struct asm_cond vconds[] =
24075{
24076 {"t", 0xf},
24077 {"e", 0x10}
24078};
24079
24080#define UL_BARRIER(L,U,CODE,FEAT) \
24081 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24082 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
24083
24084static struct asm_barrier_opt barrier_opt_names[] =
24085{
24086 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
24087 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
24088 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
24089 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
24090 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
24091 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
24092 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
24093 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
24094 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
24095 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
24096 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
24097 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
24098 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
24099 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
24100 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
24101 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
24102};
24103
24104#undef UL_BARRIER
24105
24106/* Table of ARM-format instructions. */
24107
24108/* Macros for gluing together operand strings. N.B. In all cases
24109 other than OPS0, the trailing OP_stop comes from default
24110 zero-initialization of the unspecified elements of the array. */
24111#define OPS0() { OP_stop, }
24112#define OPS1(a) { OP_##a, }
24113#define OPS2(a,b) { OP_##a,OP_##b, }
24114#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
24115#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
24116#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24117#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24118
24119/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24120 This is useful when mixing operands for ARM and THUMB, i.e. using the
24121 MIX_ARM_THUMB_OPERANDS macro.
24122 In order to use these macros, prefix the number of operands with _
24123 e.g. _3. */
24124#define OPS_1(a) { a, }
24125#define OPS_2(a,b) { a,b, }
24126#define OPS_3(a,b,c) { a,b,c, }
24127#define OPS_4(a,b,c,d) { a,b,c,d, }
24128#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
24129#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24130
24131/* These macros abstract out the exact format of the mnemonic table and
24132 save some repeated characters. */
24133
24134/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
24135#define TxCE(mnem, op, top, nops, ops, ae, te) \
24136 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
24137 THUMB_VARIANT, do_##ae, do_##te, 0 }
24138
24139/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24140 a T_MNEM_xyz enumerator. */
24141#define TCE(mnem, aop, top, nops, ops, ae, te) \
24142 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
24143#define tCE(mnem, aop, top, nops, ops, ae, te) \
24144 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24145
24146/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24147 infix after the third character. */
24148#define TxC3(mnem, op, top, nops, ops, ae, te) \
24149 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
24150 THUMB_VARIANT, do_##ae, do_##te, 0 }
24151#define TxC3w(mnem, op, top, nops, ops, ae, te) \
24152 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
24153 THUMB_VARIANT, do_##ae, do_##te, 0 }
24154#define TC3(mnem, aop, top, nops, ops, ae, te) \
24155 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
24156#define TC3w(mnem, aop, top, nops, ops, ae, te) \
24157 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
24158#define tC3(mnem, aop, top, nops, ops, ae, te) \
24159 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24160#define tC3w(mnem, aop, top, nops, ops, ae, te) \
24161 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24162
24163/* Mnemonic that cannot be conditionalized. The ARM condition-code
24164 field is still 0xE. Many of the Thumb variants can be executed
24165 conditionally, so this is checked separately. */
24166#define TUE(mnem, op, top, nops, ops, ae, te) \
24167 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24168 THUMB_VARIANT, do_##ae, do_##te, 0 }
24169
24170/* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24171 Used by mnemonics that have very minimal differences in the encoding for
24172 ARM and Thumb variants and can be handled in a common function. */
24173#define TUEc(mnem, op, top, nops, ops, en) \
24174 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24175 THUMB_VARIANT, do_##en, do_##en, 0 }
24176
24177/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24178 condition code field. */
24179#define TUF(mnem, op, top, nops, ops, ae, te) \
24180 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
24181 THUMB_VARIANT, do_##ae, do_##te, 0 }
24182
24183/* ARM-only variants of all the above. */
24184#define CE(mnem, op, nops, ops, ae) \
24185 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24186
24187#define C3(mnem, op, nops, ops, ae) \
24188 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24189
24190/* Thumb-only variants of TCE and TUE. */
24191#define ToC(mnem, top, nops, ops, te) \
24192 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24193 do_##te, 0 }
24194
24195#define ToU(mnem, top, nops, ops, te) \
24196 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
24197 NULL, do_##te, 0 }
24198
24199/* T_MNEM_xyz enumerator variants of ToC. */
24200#define toC(mnem, top, nops, ops, te) \
24201 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
24202 do_##te, 0 }
24203
24204/* T_MNEM_xyz enumerator variants of ToU. */
24205#define toU(mnem, top, nops, ops, te) \
24206 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
24207 NULL, do_##te, 0 }
24208
24209/* Legacy mnemonics that always have conditional infix after the third
24210 character. */
24211#define CL(mnem, op, nops, ops, ae) \
24212 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24213 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24214
24215/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
24216#define cCE(mnem, op, nops, ops, ae) \
24217 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24218
24219/* mov instructions that are shared between coprocessor and MVE. */
24220#define mcCE(mnem, op, nops, ops, ae) \
24221 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24222
24223/* Legacy coprocessor instructions where conditional infix and conditional
24224 suffix are ambiguous. For consistency this includes all FPA instructions,
24225 not just the potentially ambiguous ones. */
24226#define cCL(mnem, op, nops, ops, ae) \
24227 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24228 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24229
24230/* Coprocessor, takes either a suffix or a position-3 infix
24231 (for an FPA corner case). */
24232#define C3E(mnem, op, nops, ops, ae) \
24233 { mnem, OPS##nops ops, OT_csuf_or_in3, \
24234 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24235
24236#define xCM_(m1, m2, m3, op, nops, ops, ae) \
24237 { m1 #m2 m3, OPS##nops ops, \
24238 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
24239 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24240
24241#define CM(m1, m2, op, nops, ops, ae) \
24242 xCM_ (m1, , m2, op, nops, ops, ae), \
24243 xCM_ (m1, eq, m2, op, nops, ops, ae), \
24244 xCM_ (m1, ne, m2, op, nops, ops, ae), \
24245 xCM_ (m1, cs, m2, op, nops, ops, ae), \
24246 xCM_ (m1, hs, m2, op, nops, ops, ae), \
24247 xCM_ (m1, cc, m2, op, nops, ops, ae), \
24248 xCM_ (m1, ul, m2, op, nops, ops, ae), \
24249 xCM_ (m1, lo, m2, op, nops, ops, ae), \
24250 xCM_ (m1, mi, m2, op, nops, ops, ae), \
24251 xCM_ (m1, pl, m2, op, nops, ops, ae), \
24252 xCM_ (m1, vs, m2, op, nops, ops, ae), \
24253 xCM_ (m1, vc, m2, op, nops, ops, ae), \
24254 xCM_ (m1, hi, m2, op, nops, ops, ae), \
24255 xCM_ (m1, ls, m2, op, nops, ops, ae), \
24256 xCM_ (m1, ge, m2, op, nops, ops, ae), \
24257 xCM_ (m1, lt, m2, op, nops, ops, ae), \
24258 xCM_ (m1, gt, m2, op, nops, ops, ae), \
24259 xCM_ (m1, le, m2, op, nops, ops, ae), \
24260 xCM_ (m1, al, m2, op, nops, ops, ae)
24261
24262#define UE(mnem, op, nops, ops, ae) \
24263 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24264
24265#define UF(mnem, op, nops, ops, ae) \
24266 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24267
24268/* Neon data-processing. ARM versions are unconditional with cond=0xf.
24269 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24270 use the same encoding function for each. */
24271#define NUF(mnem, op, nops, ops, enc) \
24272 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24273 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24274
24275/* Neon data processing, version which indirects through neon_enc_tab for
24276 the various overloaded versions of opcodes. */
24277#define nUF(mnem, op, nops, ops, enc) \
24278 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24279 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24280
24281/* Neon insn with conditional suffix for the ARM version, non-overloaded
24282 version. */
24283#define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24284 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
24285 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24286
24287#define NCE(mnem, op, nops, ops, enc) \
24288 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24289
24290#define NCEF(mnem, op, nops, ops, enc) \
24291 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24292
24293/* Neon insn with conditional suffix for the ARM version, overloaded types. */
24294#define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24295 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
24296 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24297
24298#define nCE(mnem, op, nops, ops, enc) \
24299 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24300
24301#define nCEF(mnem, op, nops, ops, enc) \
24302 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24303
24304/* */
24305#define mCEF(mnem, op, nops, ops, enc) \
24306 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
24307 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24308
24309
24310/* nCEF but for MVE predicated instructions. */
24311#define mnCEF(mnem, op, nops, ops, enc) \
24312 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24313
24314/* nCE but for MVE predicated instructions. */
24315#define mnCE(mnem, op, nops, ops, enc) \
24316 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24317
24318/* NUF but for potentially MVE predicated instructions. */
24319#define MNUF(mnem, op, nops, ops, enc) \
24320 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24321 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24322
24323/* nUF but for potentially MVE predicated instructions. */
24324#define mnUF(mnem, op, nops, ops, enc) \
24325 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24326 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24327
24328/* ToC but for potentially MVE predicated instructions. */
24329#define mToC(mnem, top, nops, ops, te) \
24330 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24331 do_##te, 1 }
24332
24333/* NCE but for MVE predicated instructions. */
24334#define MNCE(mnem, op, nops, ops, enc) \
24335 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24336
24337/* NCEF but for MVE predicated instructions. */
24338#define MNCEF(mnem, op, nops, ops, enc) \
24339 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24340#define do_0 0
24341
24342static const struct asm_opcode insns[] =
24343{
24344#define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
24345#define THUMB_VARIANT & arm_ext_v4t
24346 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
24347 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
24348 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
24349 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
24350 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
24351 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
24352 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
24353 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
24354 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
24355 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
24356 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
24357 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
24358 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
24359 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
24360 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
24361 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
24362
24363 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24364 for setting PSR flag bits. They are obsolete in V6 and do not
24365 have Thumb equivalents. */
24366 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
24367 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
24368 CL("tstp", 110f000, 2, (RR, SH), cmp),
24369 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
24370 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
24371 CL("cmpp", 150f000, 2, (RR, SH), cmp),
24372 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
24373 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
24374 CL("cmnp", 170f000, 2, (RR, SH), cmp),
24375
24376 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
24377 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
24378 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
24379 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
24380
24381 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
24382 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
24383 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
24384 OP_RRnpc),
24385 OP_ADDRGLDR),ldst, t_ldst),
24386 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
24387
24388 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24389 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24390 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24391 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24392 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24393 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24394
24395 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
24396 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
24397
24398 /* Pseudo ops. */
24399 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
24400 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
24401 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
24402 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
24403
24404 /* Thumb-compatibility pseudo ops. */
24405 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
24406 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
24407 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
24408 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
24409 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
24410 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
24411 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
24412 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
24413 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
24414 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
24415 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
24416 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
24417
24418 /* These may simplify to neg. */
24419 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
24420 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
24421
24422#undef THUMB_VARIANT
24423#define THUMB_VARIANT & arm_ext_os
24424
24425 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
24426 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
24427
24428#undef THUMB_VARIANT
24429#define THUMB_VARIANT & arm_ext_v6
24430
24431 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
24432
24433 /* V1 instructions with no Thumb analogue prior to V6T2. */
24434#undef THUMB_VARIANT
24435#define THUMB_VARIANT & arm_ext_v6t2
24436
24437 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
24438 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
24439 CL("teqp", 130f000, 2, (RR, SH), cmp),
24440
24441 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
24442 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
24443 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
24444 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
24445
24446 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24447 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24448
24449 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24450 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24451
24452 /* V1 instructions with no Thumb analogue at all. */
24453 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
24454 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
24455
24456 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
24457 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
24458 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
24459 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
24460 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
24461 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
24462 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
24463 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
24464
24465#undef ARM_VARIANT
24466#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
24467#undef THUMB_VARIANT
24468#define THUMB_VARIANT & arm_ext_v4t
24469
24470 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
24471 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
24472
24473#undef THUMB_VARIANT
24474#define THUMB_VARIANT & arm_ext_v6t2
24475
24476 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
24477 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
24478
24479 /* Generic coprocessor instructions. */
24480 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
24481 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24482 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24483 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24484 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24485 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
24486 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
24487
24488#undef ARM_VARIANT
24489#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
24490
24491 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
24492 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
24493
24494#undef ARM_VARIANT
24495#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
24496#undef THUMB_VARIANT
24497#define THUMB_VARIANT & arm_ext_msr
24498
24499 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
24500 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
24501
24502#undef ARM_VARIANT
24503#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
24504#undef THUMB_VARIANT
24505#define THUMB_VARIANT & arm_ext_v6t2
24506
24507 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24508 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24509 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24510 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24511 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24512 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24513 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24514 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24515
24516#undef ARM_VARIANT
24517#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
24518#undef THUMB_VARIANT
24519#define THUMB_VARIANT & arm_ext_v4t
24520
24521 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24522 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24523 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24524 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24525 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24526 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24527
24528#undef ARM_VARIANT
24529#define ARM_VARIANT & arm_ext_v4t_5
24530
24531 /* ARM Architecture 4T. */
24532 /* Note: bx (and blx) are required on V5, even if the processor does
24533 not support Thumb. */
24534 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
24535
24536#undef ARM_VARIANT
24537#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24538#undef THUMB_VARIANT
24539#define THUMB_VARIANT & arm_ext_v5t
24540
24541 /* Note: blx has 2 variants; the .value coded here is for
24542 BLX(2). Only this variant has conditional execution. */
24543 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
24544 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
24545
24546#undef THUMB_VARIANT
24547#define THUMB_VARIANT & arm_ext_v6t2
24548
24549 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
24550 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24551 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24552 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24553 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24554 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
24555 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
24556 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
24557
24558#undef ARM_VARIANT
24559#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24560#undef THUMB_VARIANT
24561#define THUMB_VARIANT & arm_ext_v5exp
24562
24563 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
24564 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
24565 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
24566 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
24567
24568 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
24569 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
24570
24571 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
24572 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
24573 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
24574 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
24575
24576 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24577 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24578 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24579 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24580
24581 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24582 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24583
24584 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
24585 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
24586 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
24587 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
24588
24589#undef ARM_VARIANT
24590#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24591#undef THUMB_VARIANT
24592#define THUMB_VARIANT & arm_ext_v6t2
24593
24594 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
24595 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
24596 ldrd, t_ldstd),
24597 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
24598 ADDRGLDRS), ldrd, t_ldstd),
24599
24600 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
24601 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
24602
24603#undef ARM_VARIANT
24604#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24605
24606 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
24607
24608#undef ARM_VARIANT
24609#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24610#undef THUMB_VARIANT
24611#define THUMB_VARIANT & arm_ext_v6
24612
24613 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
24614 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
24615 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
24616 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
24617 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
24618 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24619 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24620 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24621 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24622 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
24623
24624#undef THUMB_VARIANT
24625#define THUMB_VARIANT & arm_ext_v6t2_v8m
24626
24627 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
24628 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
24629 strex, t_strex),
24630#undef THUMB_VARIANT
24631#define THUMB_VARIANT & arm_ext_v6t2
24632
24633 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
24634 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
24635
24636 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
24637 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
24638
24639/* ARM V6 not included in V7M. */
24640#undef THUMB_VARIANT
24641#define THUMB_VARIANT & arm_ext_v6_notm
24642 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
24643 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
24644 UF(rfeib, 9900a00, 1, (RRw), rfe),
24645 UF(rfeda, 8100a00, 1, (RRw), rfe),
24646 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
24647 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
24648 UF(rfefa, 8100a00, 1, (RRw), rfe),
24649 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
24650 UF(rfeed, 9900a00, 1, (RRw), rfe),
24651 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
24652 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
24653 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
24654 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
24655 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
24656 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
24657 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
24658 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
24659 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
24660 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
24661
24662/* ARM V6 not included in V7M (eg. integer SIMD). */
24663#undef THUMB_VARIANT
24664#define THUMB_VARIANT & arm_ext_v6_dsp
24665 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
24666 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
24667 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24668 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24669 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24670 /* Old name for QASX. */
24671 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24672 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24673 /* Old name for QSAX. */
24674 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24675 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24676 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24677 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24678 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24679 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24680 /* Old name for SASX. */
24681 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24682 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24683 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24684 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24685 /* Old name for SHASX. */
24686 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24687 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24688 /* Old name for SHSAX. */
24689 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24690 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24691 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24692 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24693 /* Old name for SSAX. */
24694 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24695 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24696 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24697 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24698 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24699 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24700 /* Old name for UASX. */
24701 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24702 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24703 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24704 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24705 /* Old name for UHASX. */
24706 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24707 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24708 /* Old name for UHSAX. */
24709 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24710 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24711 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24712 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24713 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24714 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24715 /* Old name for UQASX. */
24716 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24717 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24718 /* Old name for UQSAX. */
24719 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24720 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24721 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24722 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24723 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24724 /* Old name for USAX. */
24725 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24726 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24727 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24728 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24729 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24730 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24731 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24732 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24733 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24734 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24735 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24736 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24737 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24738 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24739 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24740 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24741 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24742 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24743 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24744 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24745 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24746 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24747 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24748 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24749 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24750 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24751 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24752 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24753 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24754 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
24755 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
24756 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24757 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24758 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
24759
24760#undef ARM_VARIANT
24761#define ARM_VARIANT & arm_ext_v6k_v6t2
24762#undef THUMB_VARIANT
24763#define THUMB_VARIANT & arm_ext_v6k_v6t2
24764
24765 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
24766 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
24767 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
24768 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
24769
24770#undef THUMB_VARIANT
24771#define THUMB_VARIANT & arm_ext_v6_notm
24772 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
24773 ldrexd, t_ldrexd),
24774 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
24775 RRnpcb), strexd, t_strexd),
24776
24777#undef THUMB_VARIANT
24778#define THUMB_VARIANT & arm_ext_v6t2_v8m
24779 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
24780 rd_rn, rd_rn),
24781 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
24782 rd_rn, rd_rn),
24783 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
24784 strex, t_strexbh),
24785 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
24786 strex, t_strexbh),
24787 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
24788
24789#undef ARM_VARIANT
24790#define ARM_VARIANT & arm_ext_sec
24791#undef THUMB_VARIANT
24792#define THUMB_VARIANT & arm_ext_sec
24793
24794 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
24795
24796#undef ARM_VARIANT
24797#define ARM_VARIANT & arm_ext_virt
24798#undef THUMB_VARIANT
24799#define THUMB_VARIANT & arm_ext_virt
24800
24801 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
24802 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
24803
24804#undef ARM_VARIANT
24805#define ARM_VARIANT & arm_ext_pan
24806#undef THUMB_VARIANT
24807#define THUMB_VARIANT & arm_ext_pan
24808
24809 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
24810
24811#undef ARM_VARIANT
24812#define ARM_VARIANT & arm_ext_v6t2
24813#undef THUMB_VARIANT
24814#define THUMB_VARIANT & arm_ext_v6t2
24815
24816 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
24817 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
24818 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
24819 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
24820
24821 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
24822 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
24823
24824 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24825 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24826 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24827 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24828
24829#undef ARM_VARIANT
24830#define ARM_VARIANT & arm_ext_v3
24831#undef THUMB_VARIANT
24832#define THUMB_VARIANT & arm_ext_v6t2
24833
24834 TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
24835 TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb),
24836 TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb),
24837
24838#undef ARM_VARIANT
24839#define ARM_VARIANT & arm_ext_v6t2
24840#undef THUMB_VARIANT
24841#define THUMB_VARIANT & arm_ext_v6t2_v8m
24842 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
24843 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
24844
24845 /* Thumb-only instructions. */
24846#undef ARM_VARIANT
24847#define ARM_VARIANT NULL
24848 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
24849 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
24850
24851 /* ARM does not really have an IT instruction, so always allow it.
24852 The opcode is copied from Thumb in order to allow warnings in
24853 -mimplicit-it=[never | arm] modes. */
24854#undef ARM_VARIANT
24855#define ARM_VARIANT & arm_ext_v1
24856#undef THUMB_VARIANT
24857#define THUMB_VARIANT & arm_ext_v6t2
24858
24859 TUE("it", bf08, bf08, 1, (COND), it, t_it),
24860 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
24861 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
24862 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
24863 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
24864 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
24865 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
24866 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
24867 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
24868 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
24869 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
24870 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
24871 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
24872 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
24873 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
24874 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24875 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
24876 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
24877
24878 /* Thumb2 only instructions. */
24879#undef ARM_VARIANT
24880#define ARM_VARIANT NULL
24881
24882 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
24883 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
24884 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
24885 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
24886 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
24887 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
24888
24889 /* Hardware division instructions. */
24890#undef ARM_VARIANT
24891#define ARM_VARIANT & arm_ext_adiv
24892#undef THUMB_VARIANT
24893#define THUMB_VARIANT & arm_ext_div
24894
24895 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
24896 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
24897
24898 /* ARM V6M/V7 instructions. */
24899#undef ARM_VARIANT
24900#define ARM_VARIANT & arm_ext_barrier
24901#undef THUMB_VARIANT
24902#define THUMB_VARIANT & arm_ext_barrier
24903
24904 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
24905 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
24906 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
24907
24908 /* ARM V7 instructions. */
24909#undef ARM_VARIANT
24910#define ARM_VARIANT & arm_ext_v7
24911#undef THUMB_VARIANT
24912#define THUMB_VARIANT & arm_ext_v7
24913
24914 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
24915 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
24916
24917#undef ARM_VARIANT
24918#define ARM_VARIANT & arm_ext_mp
24919#undef THUMB_VARIANT
24920#define THUMB_VARIANT & arm_ext_mp
24921
24922 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
24923
24924 /* AArchv8 instructions. */
24925#undef ARM_VARIANT
24926#define ARM_VARIANT & arm_ext_v8
24927
24928/* Instructions shared between armv8-a and armv8-m. */
24929#undef THUMB_VARIANT
24930#define THUMB_VARIANT & arm_ext_atomics
24931
24932 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24933 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24934 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24935 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
24936 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
24937 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
24938 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24939 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
24940 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24941 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
24942 stlex, t_stlex),
24943 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
24944 stlex, t_stlex),
24945 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
24946 stlex, t_stlex),
24947#undef THUMB_VARIANT
24948#define THUMB_VARIANT & arm_ext_v8
24949
24950 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
24951 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
24952 ldrexd, t_ldrexd),
24953 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
24954 strexd, t_strexd),
24955#undef THUMB_VARIANT
24956#define THUMB_VARIANT & arm_ext_v8r
24957#undef ARM_VARIANT
24958#define ARM_VARIANT & arm_ext_v8r
24959
24960/* ARMv8-R instructions. */
24961 TUF("dfb", 57ff04c, f3bf8f4c, 0, (), noargs, noargs),
24962
24963/* Defined in V8 but is in undefined encoding space for earlier
24964 architectures. However earlier architectures are required to treat
24965 this instuction as a semihosting trap as well. Hence while not explicitly
24966 defined as such, it is in fact correct to define the instruction for all
24967 architectures. */
24968#undef THUMB_VARIANT
24969#define THUMB_VARIANT & arm_ext_v1
24970#undef ARM_VARIANT
24971#define ARM_VARIANT & arm_ext_v1
24972 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
24973
24974 /* ARMv8 T32 only. */
24975#undef ARM_VARIANT
24976#define ARM_VARIANT NULL
24977 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
24978 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
24979 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
24980
24981 /* FP for ARMv8. */
24982#undef ARM_VARIANT
24983#define ARM_VARIANT & fpu_vfp_ext_armv8xd
24984#undef THUMB_VARIANT
24985#define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24986
24987 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
24988 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
24989 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
24990 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
24991 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
24992 mnCE(vrintz, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintz),
24993 mnCE(vrintx, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintx),
24994 mnUF(vrinta, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrinta),
24995 mnUF(vrintn, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintn),
24996 mnUF(vrintp, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintp),
24997 mnUF(vrintm, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintm),
24998
24999 /* Crypto v1 extensions. */
25000#undef ARM_VARIANT
25001#define ARM_VARIANT & fpu_crypto_ext_armv8
25002#undef THUMB_VARIANT
25003#define THUMB_VARIANT & fpu_crypto_ext_armv8
25004
25005 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
25006 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
25007 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
25008 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
25009 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
25010 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
25011 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
25012 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
25013 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
25014 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
25015 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
25016 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
25017 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
25018 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
25019
25020#undef ARM_VARIANT
25021#define ARM_VARIANT & arm_ext_crc
25022#undef THUMB_VARIANT
25023#define THUMB_VARIANT & arm_ext_crc
25024 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
25025 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
25026 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
25027 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
25028 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
25029 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
25030
25031 /* ARMv8.2 RAS extension. */
25032#undef ARM_VARIANT
25033#define ARM_VARIANT & arm_ext_ras
25034#undef THUMB_VARIANT
25035#define THUMB_VARIANT & arm_ext_ras
25036 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
25037
25038#undef ARM_VARIANT
25039#define ARM_VARIANT & arm_ext_v8_3
25040#undef THUMB_VARIANT
25041#define THUMB_VARIANT & arm_ext_v8_3
25042 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
25043
25044#undef ARM_VARIANT
25045#define ARM_VARIANT & fpu_neon_ext_dotprod
25046#undef THUMB_VARIANT
25047#define THUMB_VARIANT & fpu_neon_ext_dotprod
25048 NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
25049 NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
25050
25051#undef ARM_VARIANT
25052#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
25053#undef THUMB_VARIANT
25054#define THUMB_VARIANT NULL
25055
25056 cCE("wfs", e200110, 1, (RR), rd),
25057 cCE("rfs", e300110, 1, (RR), rd),
25058 cCE("wfc", e400110, 1, (RR), rd),
25059 cCE("rfc", e500110, 1, (RR), rd),
25060
25061 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
25062 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
25063 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
25064 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
25065
25066 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
25067 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
25068 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
25069 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
25070
25071 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
25072 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
25073 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
25074 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
25075 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
25076 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
25077 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
25078 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
25079 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
25080 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
25081 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
25082 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
25083
25084 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
25085 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
25086 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
25087 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
25088 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
25089 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
25090 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
25091 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
25092 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
25093 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
25094 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
25095 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
25096
25097 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
25098 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
25099 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
25100 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
25101 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
25102 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
25103 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
25104 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
25105 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
25106 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
25107 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
25108 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
25109
25110 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
25111 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
25112 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
25113 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
25114 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
25115 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
25116 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
25117 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
25118 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
25119 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
25120 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
25121 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
25122
25123 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
25124 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
25125 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
25126 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
25127 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
25128 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
25129 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
25130 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
25131 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
25132 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
25133 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
25134 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
25135
25136 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
25137 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
25138 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
25139 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
25140 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
25141 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
25142 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
25143 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
25144 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
25145 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
25146 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
25147 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
25148
25149 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
25150 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
25151 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
25152 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
25153 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
25154 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
25155 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
25156 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
25157 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
25158 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
25159 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
25160 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
25161
25162 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
25163 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
25164 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
25165 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
25166 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
25167 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
25168 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
25169 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
25170 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
25171 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
25172 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
25173 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
25174
25175 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
25176 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
25177 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
25178 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
25179 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
25180 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
25181 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
25182 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
25183 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
25184 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
25185 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
25186 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
25187
25188 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
25189 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
25190 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
25191 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
25192 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
25193 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
25194 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
25195 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
25196 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
25197 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
25198 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
25199 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
25200
25201 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
25202 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
25203 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
25204 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
25205 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
25206 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
25207 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
25208 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
25209 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
25210 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
25211 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
25212 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
25213
25214 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
25215 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
25216 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
25217 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
25218 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
25219 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
25220 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
25221 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
25222 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
25223 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
25224 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
25225 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
25226
25227 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
25228 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
25229 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
25230 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
25231 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
25232 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
25233 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
25234 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
25235 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
25236 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
25237 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
25238 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
25239
25240 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
25241 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
25242 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
25243 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
25244 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
25245 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
25246 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
25247 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
25248 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
25249 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
25250 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
25251 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
25252
25253 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
25254 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
25255 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
25256 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
25257 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
25258 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
25259 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
25260 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
25261 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
25262 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
25263 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
25264 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
25265
25266 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
25267 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
25268 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
25269 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
25270 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
25271 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
25272 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
25273 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
25274 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
25275 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
25276 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
25277 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
25278
25279 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
25280 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
25281 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
25282 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
25283 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
25284 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25285 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25286 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25287 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
25288 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
25289 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
25290 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
25291
25292 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
25293 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
25294 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
25295 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
25296 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
25297 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25298 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25299 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25300 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
25301 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
25302 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
25303 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
25304
25305 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
25306 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
25307 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
25308 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
25309 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
25310 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25311 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25312 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25313 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
25314 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
25315 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
25316 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
25317
25318 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
25319 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
25320 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
25321 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
25322 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
25323 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25324 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25325 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25326 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
25327 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
25328 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
25329 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
25330
25331 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
25332 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
25333 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
25334 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
25335 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
25336 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25337 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25338 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25339 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
25340 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
25341 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
25342 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
25343
25344 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
25345 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
25346 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
25347 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
25348 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
25349 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25350 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25351 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25352 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
25353 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
25354 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
25355 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
25356
25357 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
25358 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
25359 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
25360 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
25361 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
25362 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25363 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25364 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25365 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
25366 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
25367 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
25368 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
25369
25370 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
25371 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
25372 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
25373 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
25374 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
25375 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25376 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25377 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25378 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
25379 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
25380 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
25381 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
25382
25383 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
25384 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
25385 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
25386 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
25387 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
25388 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25389 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25390 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25391 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
25392 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
25393 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
25394 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
25395
25396 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
25397 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
25398 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
25399 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
25400 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
25401 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25402 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25403 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25404 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
25405 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
25406 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
25407 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
25408
25409 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
25410 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
25411 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
25412 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
25413 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
25414 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25415 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25416 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25417 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
25418 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
25419 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
25420 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
25421
25422 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
25423 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
25424 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
25425 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
25426 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
25427 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25428 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25429 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25430 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
25431 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
25432 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
25433 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
25434
25435 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
25436 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
25437 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
25438 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
25439 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
25440 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25441 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25442 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25443 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
25444 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
25445 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
25446 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
25447
25448 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
25449 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
25450 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
25451 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
25452
25453 cCL("flts", e000110, 2, (RF, RR), rn_rd),
25454 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
25455 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
25456 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
25457 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
25458 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
25459 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
25460 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
25461 cCL("flte", e080110, 2, (RF, RR), rn_rd),
25462 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
25463 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
25464 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
25465
25466 /* The implementation of the FIX instruction is broken on some
25467 assemblers, in that it accepts a precision specifier as well as a
25468 rounding specifier, despite the fact that this is meaningless.
25469 To be more compatible, we accept it as well, though of course it
25470 does not set any bits. */
25471 cCE("fix", e100110, 2, (RR, RF), rd_rm),
25472 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
25473 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
25474 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
25475 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
25476 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
25477 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
25478 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
25479 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
25480 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
25481 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
25482 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
25483 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
25484
25485 /* Instructions that were new with the real FPA, call them V2. */
25486#undef ARM_VARIANT
25487#define ARM_VARIANT & fpu_fpa_ext_v2
25488
25489 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25490 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25491 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25492 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25493 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25494 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25495
25496#undef ARM_VARIANT
25497#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
25498#undef THUMB_VARIANT
25499#define THUMB_VARIANT & arm_ext_v6t2
25500 mcCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vmrs),
25501 mcCE(vmsr, ee00a10, 2, (RVC, RR), vmsr),
25502 mcCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
25503 mcCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
25504 mcCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
25505 mcCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
25506
25507 /* Memory operations. */
25508 mcCE(fldmias, c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
25509 mcCE(fldmdbs, d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
25510 mcCE(fstmias, c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
25511 mcCE(fstmdbs, d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
25512#undef THUMB_VARIANT
25513
25514 /* Moves and type conversions. */
25515 cCE("fmstat", ef1fa10, 0, (), noargs),
25516 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
25517 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
25518 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
25519 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
25520 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
25521 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
25522 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
25523 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
25524
25525 /* Memory operations. */
25526 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
25527 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
25528 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
25529 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
25530 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
25531 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
25532 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
25533 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
25534 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
25535 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
25536 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
25537 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
25538
25539 /* Monadic operations. */
25540 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
25541 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
25542 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
25543
25544 /* Dyadic operations. */
25545 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25546 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25547 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25548 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25549 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25550 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25551 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25552 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25553 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25554
25555 /* Comparisons. */
25556 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
25557 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
25558 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
25559 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
25560
25561 /* Double precision load/store are still present on single precision
25562 implementations. */
25563 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
25564 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
25565 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
25566 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
25567 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
25568 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
25569 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
25570 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
25571
25572#undef ARM_VARIANT
25573#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25574
25575 /* Moves and type conversions. */
25576 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
25577 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
25578 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
25579 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
25580 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
25581 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
25582 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
25583 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
25584 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
25585 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
25586 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
25587 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
25588
25589 /* Monadic operations. */
25590 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
25591 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
25592 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
25593
25594 /* Dyadic operations. */
25595 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25596 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25597 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25598 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25599 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25600 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25601 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25602 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25603 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25604
25605 /* Comparisons. */
25606 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
25607 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
25608 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
25609 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
25610
25611/* Instructions which may belong to either the Neon or VFP instruction sets.
25612 Individual encoder functions perform additional architecture checks. */
25613#undef ARM_VARIANT
25614#define ARM_VARIANT & fpu_vfp_ext_v1xd
25615#undef THUMB_VARIANT
25616#define THUMB_VARIANT & arm_ext_v6t2
25617
25618 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25619 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25620 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25621 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25622 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25623 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25624
25625 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
25626 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
25627
25628#undef THUMB_VARIANT
25629#define THUMB_VARIANT & fpu_vfp_ext_v1xd
25630
25631 /* These mnemonics are unique to VFP. */
25632 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
25633 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
25634 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25635 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25636 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25637 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
25638
25639 /* Mnemonics shared by Neon and VFP. */
25640 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
25641
25642 mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
25643 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
25644 MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
25645 MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
25646
25647
25648 /* NOTE: All VMOV encoding is special-cased! */
25649 NCE(vmovq, 0, 1, (VMOV), neon_mov),
25650
25651#undef THUMB_VARIANT
25652/* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25653 by different feature bits. Since we are setting the Thumb guard, we can
25654 require Thumb-1 which makes it a nop guard and set the right feature bit in
25655 do_vldr_vstr (). */
25656#define THUMB_VARIANT & arm_ext_v4t
25657 NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
25658 NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
25659
25660#undef ARM_VARIANT
25661#define ARM_VARIANT & arm_ext_fp16
25662#undef THUMB_VARIANT
25663#define THUMB_VARIANT & arm_ext_fp16
25664 /* New instructions added from v8.2, allowing the extraction and insertion of
25665 the upper 16 bits of a 32-bit vector register. */
25666 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
25667 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
25668
25669 /* New backported fma/fms instructions optional in v8.2. */
25670 NUF (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
25671 NUF (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
25672
25673#undef THUMB_VARIANT
25674#define THUMB_VARIANT & fpu_neon_ext_v1
25675#undef ARM_VARIANT
25676#define ARM_VARIANT & fpu_neon_ext_v1
25677
25678 /* Data processing with three registers of the same length. */
25679 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25680 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
25681 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
25682 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
25683 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
25684 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
25685 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25686 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
25687 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
25688 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
25689 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
25690 /* If not immediate, fall back to neon_dyadic_i64_su.
25691 shl should accept I8 I16 I32 I64,
25692 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25693 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl),
25694 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl),
25695 /* Logic ops, types optional & ignored. */
25696 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
25697 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
25698 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
25699 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
25700 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
25701 /* Bitfield ops, untyped. */
25702 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
25703 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
25704 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
25705 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
25706 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
25707 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
25708 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25709 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
25710 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
25711 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
25712 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25713 back to neon_dyadic_if_su. */
25714 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
25715 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
25716 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
25717 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
25718 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
25719 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
25720 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
25721 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
25722 /* Comparison. Type I8 I16 I32 F32. */
25723 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
25724 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
25725 /* As above, D registers only. */
25726 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
25727 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
25728 /* Int and float variants, signedness unimportant. */
25729 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
25730 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
25731 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
25732 /* Add/sub take types I8 I16 I32 I64 F32. */
25733 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
25734 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
25735 /* vtst takes sizes 8, 16, 32. */
25736 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
25737 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
25738 /* VMUL takes I8 I16 I32 F32 P8. */
25739 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
25740 /* VQD{R}MULH takes S16 S32. */
25741 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
25742 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
25743 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
25744 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
25745 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
25746 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
25747 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
25748 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
25749 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
25750 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
25751 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
25752 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
25753 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
25754 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
25755 /* ARM v8.1 extension. */
25756 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
25757 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
25758 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
25759
25760 /* Two address, int/float. Types S8 S16 S32 F32. */
25761 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
25762 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
25763
25764 /* Data processing with two registers and a shift amount. */
25765 /* Right shifts, and variants with rounding.
25766 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25767 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
25768 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
25769 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
25770 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
25771 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
25772 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
25773 /* Shift and insert. Sizes accepted 8 16 32 64. */
25774 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
25775 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
25776 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25777 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
25778 /* Right shift immediate, saturating & narrowing, with rounding variants.
25779 Types accepted S16 S32 S64 U16 U32 U64. */
25780 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
25781 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
25782 /* As above, unsigned. Types accepted S16 S32 S64. */
25783 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
25784 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
25785 /* Right shift narrowing. Types accepted I16 I32 I64. */
25786 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
25787 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
25788 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25789 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
25790 /* CVT with optional immediate for fixed-point variant. */
25791 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
25792
25793 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
25794
25795 /* Data processing, three registers of different lengths. */
25796 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25797 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
25798 /* If not scalar, fall back to neon_dyadic_long.
25799 Vector types as above, scalar types S16 S32 U16 U32. */
25800 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
25801 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
25802 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25803 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
25804 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
25805 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25806 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
25807 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
25808 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
25809 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
25810 /* Saturating doubling multiplies. Types S16 S32. */
25811 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
25812 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
25813 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
25814 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25815 S16 S32 U16 U32. */
25816 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
25817
25818 /* Extract. Size 8. */
25819 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
25820 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
25821
25822 /* Two registers, miscellaneous. */
25823 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25824 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
25825 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
25826 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
25827 /* Vector replicate. Sizes 8 16 32. */
25828 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
25829 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25830 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
25831 /* VMOVN. Types I16 I32 I64. */
25832 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
25833 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25834 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
25835 /* VQMOVUN. Types S16 S32 S64. */
25836 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
25837 /* VZIP / VUZP. Sizes 8 16 32. */
25838 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
25839 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
25840 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
25841 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
25842 /* VQABS / VQNEG. Types S8 S16 S32. */
25843 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
25844 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
25845 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25846 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
25847 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
25848 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
25849 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
25850 /* Reciprocal estimates. Types U32 F16 F32. */
25851 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
25852 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
25853 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
25854 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
25855 /* VCLS. Types S8 S16 S32. */
25856 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
25857 /* VCLZ. Types I8 I16 I32. */
25858 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
25859 /* VCNT. Size 8. */
25860 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
25861 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
25862 /* Two address, untyped. */
25863 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
25864 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
25865 /* VTRN. Sizes 8 16 32. */
25866 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
25867 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
25868
25869 /* Table lookup. Size 8. */
25870 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
25871 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
25872
25873#undef THUMB_VARIANT
25874#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25875#undef ARM_VARIANT
25876#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25877
25878 /* Neon element/structure load/store. */
25879 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
25880 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
25881 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
25882 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
25883 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
25884 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
25885 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
25886 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
25887
25888#undef THUMB_VARIANT
25889#define THUMB_VARIANT & fpu_vfp_ext_v3xd
25890#undef ARM_VARIANT
25891#define ARM_VARIANT & fpu_vfp_ext_v3xd
25892 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
25893 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25894 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25895 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25896 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25897 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25898 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25899 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25900 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25901
25902#undef THUMB_VARIANT
25903#define THUMB_VARIANT & fpu_vfp_ext_v3
25904#undef ARM_VARIANT
25905#define ARM_VARIANT & fpu_vfp_ext_v3
25906
25907 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
25908 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
25909 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
25910 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
25911 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
25912 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
25913 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
25914 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
25915 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
25916
25917#undef ARM_VARIANT
25918#define ARM_VARIANT & fpu_vfp_ext_fma
25919#undef THUMB_VARIANT
25920#define THUMB_VARIANT & fpu_vfp_ext_fma
25921 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25922 VFP FMA variant; NEON and VFP FMA always includes the NEON
25923 FMA instructions. */
25924 mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac),
25925 TUF ("vfmat", c300850, fc300850, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), mve_vfma, mve_vfma),
25926 mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac),
25927
25928 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25929 the v form should always be used. */
25930 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25931 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25932 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25933 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25934 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25935 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25936
25937#undef THUMB_VARIANT
25938#undef ARM_VARIANT
25939#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25940
25941 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25942 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25943 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25944 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25945 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25946 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25947 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
25948 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
25949
25950#undef ARM_VARIANT
25951#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25952
25953 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
25954 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
25955 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
25956 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
25957 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
25958 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
25959 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
25960 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
25961 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
25962 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25963 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25964 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25965 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
25966 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
25967 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
25968 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25969 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25970 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25971 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
25972 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
25973 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25974 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25975 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25976 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25977 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25978 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25979 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
25980 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
25981 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
25982 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
25983 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
25984 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
25985 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
25986 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
25987 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
25988 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
25989 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
25990 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25991 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25992 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25993 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25994 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25995 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25996 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25997 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25998 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25999 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
26000 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26001 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26002 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26003 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26004 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26005 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26006 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26007 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26008 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26009 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26010 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26011 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26012 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26013 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26014 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26015 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26016 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26017 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26018 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26019 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
26020 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
26021 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
26022 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
26023 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26024 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26025 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26026 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26027 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26028 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26029 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26030 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26031 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26032 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26033 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26034 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26035 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26036 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26037 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26038 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26039 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26040 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26041 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
26042 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26043 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26044 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26045 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26046 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26047 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26048 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26049 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26050 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26051 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26052 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26053 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26054 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26055 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26056 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26057 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26058 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26059 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26060 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26061 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26062 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26063 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
26064 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26065 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26066 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26067 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26068 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26069 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26070 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26071 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26072 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26073 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26074 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26075 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26076 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26077 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26078 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26079 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26080 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26081 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26082 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
26083 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
26084 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
26085 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
26086 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26087 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26088 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26089 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26090 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26091 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26092 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26093 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26094 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26095 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
26096 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
26097 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
26098 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
26099 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
26100 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
26101 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26102 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26103 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26104 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
26105 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
26106 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
26107 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
26108 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
26109 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
26110 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26111 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26112 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26113 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26114 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
26115
26116#undef ARM_VARIANT
26117#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
26118
26119 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
26120 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
26121 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
26122 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
26123 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
26124 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
26125 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26126 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26127 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26128 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26129 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26130 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26131 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26132 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26133 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26134 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26135 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26136 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26137 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26138 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26139 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
26140 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26141 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26142 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26143 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26144 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26145 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26146 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26147 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26148 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26149 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26150 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26151 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26152 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26153 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26154 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26155 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26156 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26157 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26158 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26159 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26160 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26161 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26162 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26163 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26164 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26165 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26166 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26167 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26168 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26169 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26170 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26171 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26172 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26173 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26174 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26175 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26176
26177#undef ARM_VARIANT
26178#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
26179
26180 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
26181 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
26182 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
26183 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
26184 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
26185 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
26186 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
26187 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
26188 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
26189 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
26190 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
26191 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
26192 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
26193 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
26194 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
26195 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
26196 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
26197 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
26198 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
26199 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
26200 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
26201 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
26202 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
26203 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
26204 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
26205 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
26206 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
26207 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
26208 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
26209 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
26210 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
26211 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
26212 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
26213 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
26214 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
26215 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
26216 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
26217 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
26218 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
26219 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
26220 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
26221 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
26222 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
26223 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
26224 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
26225 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
26226 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
26227 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
26228 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
26229 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
26230 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
26231 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
26232 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
26233 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
26234 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
26235 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
26236 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
26237 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
26238 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
26239 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
26240 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
26241 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
26242 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
26243 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
26244 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
26245 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
26246 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
26247 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
26248 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
26249 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
26250 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
26251 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
26252 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
26253 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
26254 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
26255 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
26256
26257 /* ARMv8.5-A instructions. */
26258#undef ARM_VARIANT
26259#define ARM_VARIANT & arm_ext_sb
26260#undef THUMB_VARIANT
26261#define THUMB_VARIANT & arm_ext_sb
26262 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
26263
26264#undef ARM_VARIANT
26265#define ARM_VARIANT & arm_ext_predres
26266#undef THUMB_VARIANT
26267#define THUMB_VARIANT & arm_ext_predres
26268 CE("cfprctx", e070f93, 1, (RRnpc), rd),
26269 CE("dvprctx", e070fb3, 1, (RRnpc), rd),
26270 CE("cpprctx", e070ff3, 1, (RRnpc), rd),
26271
26272 /* ARMv8-M instructions. */
26273#undef ARM_VARIANT
26274#define ARM_VARIANT NULL
26275#undef THUMB_VARIANT
26276#define THUMB_VARIANT & arm_ext_v8m
26277 ToU("sg", e97fe97f, 0, (), noargs),
26278 ToC("blxns", 4784, 1, (RRnpc), t_blx),
26279 ToC("bxns", 4704, 1, (RRnpc), t_bx),
26280 ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt),
26281 ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt),
26282 ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt),
26283 ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt),
26284
26285 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
26286 instructions behave as nop if no VFP is present. */
26287#undef THUMB_VARIANT
26288#define THUMB_VARIANT & arm_ext_v8m_main
26289 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
26290 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
26291
26292 /* Armv8.1-M Mainline instructions. */
26293#undef THUMB_VARIANT
26294#define THUMB_VARIANT & arm_ext_v8_1m_main
26295 toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
26296 toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond),
26297 toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond),
26298 toU("csel", _csel, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
26299 toU("csetm", _csetm, 2, (RRnpcsp, COND), t_cond),
26300 toU("cset", _cset, 2, (RRnpcsp, COND), t_cond),
26301 toU("csinc", _csinc, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
26302 toU("csinv", _csinv, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
26303 toU("csneg", _csneg, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
26304
26305 toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
26306 toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
26307 toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
26308 toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
26309 toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
26310
26311 toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
26312 toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
26313 toU("le", _le, 2, (oLR, EXP), t_loloop),
26314
26315 ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm),
26316 ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm),
26317
26318#undef THUMB_VARIANT
26319#define THUMB_VARIANT & mve_ext
26320 ToC("lsll", ea50010d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
26321 ToC("lsrl", ea50011f, 3, (RRe, RRo, I32), mve_scalar_shift),
26322 ToC("asrl", ea50012d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
26323 ToC("uqrshll", ea51010d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1),
26324 ToC("sqrshrl", ea51012d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1),
26325 ToC("uqshll", ea51010f, 3, (RRe, RRo, I32), mve_scalar_shift),
26326 ToC("urshrl", ea51011f, 3, (RRe, RRo, I32), mve_scalar_shift),
26327 ToC("srshrl", ea51012f, 3, (RRe, RRo, I32), mve_scalar_shift),
26328 ToC("sqshll", ea51013f, 3, (RRe, RRo, I32), mve_scalar_shift),
26329 ToC("uqrshl", ea500f0d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
26330 ToC("sqrshr", ea500f2d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
26331 ToC("uqshl", ea500f0f, 2, (RRnpcsp, I32), mve_scalar_shift),
26332 ToC("urshr", ea500f1f, 2, (RRnpcsp, I32), mve_scalar_shift),
26333 ToC("srshr", ea500f2f, 2, (RRnpcsp, I32), mve_scalar_shift),
26334 ToC("sqshl", ea500f3f, 2, (RRnpcsp, I32), mve_scalar_shift),
26335
26336 ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26337 ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26338 ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26339 ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26340 ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26341 ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26342 ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26343 ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26344 ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26345 ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26346 ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26347 ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26348 ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26349 ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26350 ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26351
26352 ToC("vpst", fe710f4d, 0, (), mve_vpt),
26353 ToC("vpstt", fe318f4d, 0, (), mve_vpt),
26354 ToC("vpste", fe718f4d, 0, (), mve_vpt),
26355 ToC("vpsttt", fe314f4d, 0, (), mve_vpt),
26356 ToC("vpstte", fe31cf4d, 0, (), mve_vpt),
26357 ToC("vpstet", fe71cf4d, 0, (), mve_vpt),
26358 ToC("vpstee", fe714f4d, 0, (), mve_vpt),
26359 ToC("vpstttt", fe312f4d, 0, (), mve_vpt),
26360 ToC("vpsttte", fe316f4d, 0, (), mve_vpt),
26361 ToC("vpsttet", fe31ef4d, 0, (), mve_vpt),
26362 ToC("vpsttee", fe31af4d, 0, (), mve_vpt),
26363 ToC("vpstett", fe71af4d, 0, (), mve_vpt),
26364 ToC("vpstete", fe71ef4d, 0, (), mve_vpt),
26365 ToC("vpsteet", fe716f4d, 0, (), mve_vpt),
26366 ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
26367
26368 /* MVE and MVE FP only. */
26369 mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd),
26370 mCEF(vctp, _vctp, 1, (RRnpc), mve_vctp),
26371 mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc),
26372 mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc),
26373 mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
26374 mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
26375 mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull),
26376 mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
26377 mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
26378 mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
26379 mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
26380 mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
26381 mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
26382 mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
26383 mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav),
26384 mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav),
26385 mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
26386 mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
26387
26388 mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
26389 mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
26390 mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26391 mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26392 mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26393 mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26394 mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
26395 mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
26396 mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26397 mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26398 mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26399 mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26400 mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26401 mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26402 mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26403 mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26404 mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26405 mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26406 mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26407 mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26408
26409 mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
26410 mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
26411 mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
26412 mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv),
26413 mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
26414 mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
26415 mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
26416 mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup),
26417 mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
26418 mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
26419 mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
26420 mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
26421 mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
26422 mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv),
26423 mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv),
26424 mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv),
26425 mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv),
26426
26427 mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26428 mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26429 mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26430 mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26431 mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26432 mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26433 mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26434 mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26435 mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26436 mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26437 mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26438 mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26439 mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26440 mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26441 mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26442 mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26443 mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26444 mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26445 mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26446 mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26447
26448 mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas),
26449 mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
26450 mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
26451 mToC("vpnot", fe310f4d, 0, (), mve_vpnot),
26452 mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel),
26453
26454 mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26455 mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26456 mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26457 mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26458 mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26459 mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26460 mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26461 mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26462 mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
26463 mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
26464 mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah),
26465 mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
26466 mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
26467 mCEF(vqmovnt, _vqmovnt, 2, (RMQ, RMQ), mve_vqmovn),
26468 mCEF(vqmovnb, _vqmovnb, 2, (RMQ, RMQ), mve_vqmovn),
26469 mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn),
26470 mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn),
26471
26472 mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26473 mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26474 mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26475 mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26476 mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26477 mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26478 mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26479 mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26480 mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26481 mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26482 mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26483 mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26484
26485 mToC("vshlc", eea00fc0, 3, (RMQ, RR, I32z), mve_vshlc),
26486 mToC("vshllt", ee201e00, 3, (RMQ, RMQ, I32), mve_vshll),
26487 mToC("vshllb", ee200e00, 3, (RMQ, RMQ, I32), mve_vshll),
26488
26489 toU("dlstp", _dlstp, 2, (LR, RR), t_loloop),
26490 toU("wlstp", _wlstp, 3, (LR, RR, EXP), t_loloop),
26491 toU("letp", _letp, 2, (LR, EXP), t_loloop),
26492 toU("lctp", _lctp, 0, (), t_loloop),
26493
26494#undef THUMB_VARIANT
26495#define THUMB_VARIANT & mve_fp_ext
26496 mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
26497 mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
26498 mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
26499 mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
26500 mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv),
26501 mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv),
26502 mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv),
26503 mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv),
26504
26505#undef ARM_VARIANT
26506#define ARM_VARIANT & fpu_vfp_ext_v1
26507#undef THUMB_VARIANT
26508#define THUMB_VARIANT & arm_ext_v6t2
26509 mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
26510 mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
26511
26512 mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
26513
26514#undef ARM_VARIANT
26515#define ARM_VARIANT & fpu_vfp_ext_v1xd
26516
26517 MNCE(vmov, 0, 1, (VMOV), neon_mov),
26518 mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
26519 mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
26520 mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
26521
26522 mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull),
26523 mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
26524 mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
26525
26526 MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
26527 MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
26528
26529 mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl),
26530 mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl),
26531
26532 mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
26533 mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
26534
26535#undef ARM_VARIANT
26536#define ARM_VARIANT & fpu_vfp_ext_v2
26537
26538 mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
26539 mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
26540 mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
26541 mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
26542
26543#undef ARM_VARIANT
26544#define ARM_VARIANT & fpu_vfp_ext_armv8xd
26545 mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta),
26546 mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
26547 mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
26548 mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
26549 mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
26550 mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
26551
26552#undef ARM_VARIANT
26553#define ARM_VARIANT & fpu_neon_ext_v1
26554 mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
26555 mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
26556 mnUF(vaddl, _vaddl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
26557 mnUF(vsubl, _vsubl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
26558 mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26559 mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26560 mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26561 mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26562 mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
26563 MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
26564 MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
26565 mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
26566 MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
26567 MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
26568 MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
26569 mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
26570 mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
26571 MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
26572 MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
26573 mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn),
26574 MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
26575 MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
26576 mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah),
26577 mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
26578 mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
26579 MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
26580 MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
26581 MNUF(vshr, 0800010, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
26582 MNUF(vrshr, 0800210, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
26583 MNUF(vsli, 1800510, 3, (RNDQMQ, oRNDQMQ, I63), neon_sli),
26584 MNUF(vsri, 1800410, 3, (RNDQMQ, oRNDQMQ, I64z), neon_sri),
26585 MNUF(vrev64, 1b00000, 2, (RNDQMQ, RNDQMQ), neon_rev),
26586 MNUF(vrev32, 1b00080, 2, (RNDQMQ, RNDQMQ), neon_rev),
26587 MNUF(vrev16, 1b00100, 2, (RNDQMQ, RNDQMQ), neon_rev),
26588 mnUF(vshl, _vshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_shl),
26589 mnUF(vqshl, _vqshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_qshl),
26590 MNUF(vqshlu, 1800610, 3, (RNDQMQ, oRNDQMQ, I63), neon_qshlu_imm),
26591
26592#undef ARM_VARIANT
26593#define ARM_VARIANT & arm_ext_v8_3
26594#undef THUMB_VARIANT
26595#define THUMB_VARIANT & arm_ext_v6t2_v8m
26596 MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
26597 MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
26598
26599#undef ARM_VARIANT
26600#define ARM_VARIANT &arm_ext_bf16
26601#undef THUMB_VARIANT
26602#define THUMB_VARIANT &arm_ext_bf16
26603 TUF ("vdot", c000d00, fc000d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), vdot, vdot),
26604 TUF ("vmmla", c000c40, fc000c40, 3, (RNQ, RNQ, RNQ), vmmla, vmmla),
26605 TUF ("vfmab", c300810, fc300810, 3, (RNDQ, RNDQ, RNDQ_RNSC), bfloat_vfma, bfloat_vfma),
26606
26607#undef ARM_VARIANT
26608#define ARM_VARIANT &arm_ext_i8mm
26609#undef THUMB_VARIANT
26610#define THUMB_VARIANT &arm_ext_i8mm
26611 TUF ("vsmmla", c200c40, fc200c40, 3, (RNQ, RNQ, RNQ), vsmmla, vsmmla),
26612 TUF ("vummla", c200c50, fc200c50, 3, (RNQ, RNQ, RNQ), vummla, vummla),
26613 TUF ("vusmmla", ca00c40, fca00c40, 3, (RNQ, RNQ, RNQ), vsmmla, vsmmla),
26614 TUF ("vusdot", c800d00, fc800d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), vusdot, vusdot),
26615 TUF ("vsudot", c800d10, fc800d10, 3, (RNDQ, RNDQ, RNSC), vsudot, vsudot),
26616
26617#undef ARM_VARIANT
26618#undef THUMB_VARIANT
26619#define THUMB_VARIANT &arm_ext_cde
26620 ToC ("cx1", ee000000, 3, (RCP, APSR_RR, I8191), cx1),
26621 ToC ("cx1a", fe000000, 3, (RCP, APSR_RR, I8191), cx1a),
26622 ToC ("cx1d", ee000040, 4, (RCP, RR, APSR_RR, I8191), cx1d),
26623 ToC ("cx1da", fe000040, 4, (RCP, RR, APSR_RR, I8191), cx1da),
26624
26625 ToC ("cx2", ee400000, 4, (RCP, APSR_RR, APSR_RR, I511), cx2),
26626 ToC ("cx2a", fe400000, 4, (RCP, APSR_RR, APSR_RR, I511), cx2a),
26627 ToC ("cx2d", ee400040, 5, (RCP, RR, APSR_RR, APSR_RR, I511), cx2d),
26628 ToC ("cx2da", fe400040, 5, (RCP, RR, APSR_RR, APSR_RR, I511), cx2da),
26629
26630 ToC ("cx3", ee800000, 5, (RCP, APSR_RR, APSR_RR, APSR_RR, I63), cx3),
26631 ToC ("cx3a", fe800000, 5, (RCP, APSR_RR, APSR_RR, APSR_RR, I63), cx3a),
26632 ToC ("cx3d", ee800040, 6, (RCP, RR, APSR_RR, APSR_RR, APSR_RR, I63), cx3d),
26633 ToC ("cx3da", fe800040, 6, (RCP, RR, APSR_RR, APSR_RR, APSR_RR, I63), cx3da),
26634
26635 mToC ("vcx1", ec200000, 3, (RCP, RNSDMQ, I4095), vcx1),
26636 mToC ("vcx1a", fc200000, 3, (RCP, RNSDMQ, I4095), vcx1),
26637
26638 mToC ("vcx2", ec300000, 4, (RCP, RNSDMQ, RNSDMQ, I127), vcx2),
26639 mToC ("vcx2a", fc300000, 4, (RCP, RNSDMQ, RNSDMQ, I127), vcx2),
26640
26641 mToC ("vcx3", ec800000, 5, (RCP, RNSDMQ, RNSDMQ, RNSDMQ, I15), vcx3),
26642 mToC ("vcx3a", fc800000, 5, (RCP, RNSDMQ, RNSDMQ, RNSDMQ, I15), vcx3),
26643};
26644
26645#undef ARM_VARIANT
26646#undef THUMB_VARIANT
26647#undef TCE
26648#undef TUE
26649#undef TUF
26650#undef TCC
26651#undef cCE
26652#undef cCL
26653#undef C3E
26654#undef C3
26655#undef CE
26656#undef CM
26657#undef CL
26658#undef UE
26659#undef UF
26660#undef UT
26661#undef NUF
26662#undef nUF
26663#undef NCE
26664#undef nCE
26665#undef OPS0
26666#undef OPS1
26667#undef OPS2
26668#undef OPS3
26669#undef OPS4
26670#undef OPS5
26671#undef OPS6
26672#undef do_0
26673#undef ToC
26674#undef toC
26675#undef ToU
26676#undef toU
26677\f
26678/* MD interface: bits in the object file. */
26679
26680/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26681 for use in the a.out file, and stores them in the array pointed to by buf.
26682 This knows about the endian-ness of the target machine and does
26683 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26684 2 (short) and 4 (long) Floating numbers are put out as a series of
26685 LITTLENUMS (shorts, here at least). */
26686
26687void
26688md_number_to_chars (char * buf, valueT val, int n)
26689{
26690 if (target_big_endian)
26691 number_to_chars_bigendian (buf, val, n);
26692 else
26693 number_to_chars_littleendian (buf, val, n);
26694}
26695
26696static valueT
26697md_chars_to_number (char * buf, int n)
26698{
26699 valueT result = 0;
26700 unsigned char * where = (unsigned char *) buf;
26701
26702 if (target_big_endian)
26703 {
26704 while (n--)
26705 {
26706 result <<= 8;
26707 result |= (*where++ & 255);
26708 }
26709 }
26710 else
26711 {
26712 while (n--)
26713 {
26714 result <<= 8;
26715 result |= (where[n] & 255);
26716 }
26717 }
26718
26719 return result;
26720}
26721
26722/* MD interface: Sections. */
26723
26724/* Calculate the maximum variable size (i.e., excluding fr_fix)
26725 that an rs_machine_dependent frag may reach. */
26726
26727unsigned int
26728arm_frag_max_var (fragS *fragp)
26729{
26730 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26731 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26732
26733 Note that we generate relaxable instructions even for cases that don't
26734 really need it, like an immediate that's a trivial constant. So we're
26735 overestimating the instruction size for some of those cases. Rather
26736 than putting more intelligence here, it would probably be better to
26737 avoid generating a relaxation frag in the first place when it can be
26738 determined up front that a short instruction will suffice. */
26739
26740 gas_assert (fragp->fr_type == rs_machine_dependent);
26741 return INSN_SIZE;
26742}
26743
26744/* Estimate the size of a frag before relaxing. Assume everything fits in
26745 2 bytes. */
26746
26747int
26748md_estimate_size_before_relax (fragS * fragp,
26749 segT segtype ATTRIBUTE_UNUSED)
26750{
26751 fragp->fr_var = 2;
26752 return 2;
26753}
26754
26755/* Convert a machine dependent frag. */
26756
26757void
26758md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
26759{
26760 unsigned long insn;
26761 unsigned long old_op;
26762 char *buf;
26763 expressionS exp;
26764 fixS *fixp;
26765 int reloc_type;
26766 int pc_rel;
26767 int opcode;
26768
26769 buf = fragp->fr_literal + fragp->fr_fix;
26770
26771 old_op = bfd_get_16(abfd, buf);
26772 if (fragp->fr_symbol)
26773 {
26774 exp.X_op = O_symbol;
26775 exp.X_add_symbol = fragp->fr_symbol;
26776 }
26777 else
26778 {
26779 exp.X_op = O_constant;
26780 }
26781 exp.X_add_number = fragp->fr_offset;
26782 opcode = fragp->fr_subtype;
26783 switch (opcode)
26784 {
26785 case T_MNEM_ldr_pc:
26786 case T_MNEM_ldr_pc2:
26787 case T_MNEM_ldr_sp:
26788 case T_MNEM_str_sp:
26789 case T_MNEM_ldr:
26790 case T_MNEM_ldrb:
26791 case T_MNEM_ldrh:
26792 case T_MNEM_str:
26793 case T_MNEM_strb:
26794 case T_MNEM_strh:
26795 if (fragp->fr_var == 4)
26796 {
26797 insn = THUMB_OP32 (opcode);
26798 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
26799 {
26800 insn |= (old_op & 0x700) << 4;
26801 }
26802 else
26803 {
26804 insn |= (old_op & 7) << 12;
26805 insn |= (old_op & 0x38) << 13;
26806 }
26807 insn |= 0x00000c00;
26808 put_thumb32_insn (buf, insn);
26809 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
26810 }
26811 else
26812 {
26813 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
26814 }
26815 pc_rel = (opcode == T_MNEM_ldr_pc2);
26816 break;
26817 case T_MNEM_adr:
26818 if (fragp->fr_var == 4)
26819 {
26820 insn = THUMB_OP32 (opcode);
26821 insn |= (old_op & 0xf0) << 4;
26822 put_thumb32_insn (buf, insn);
26823 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
26824 }
26825 else
26826 {
26827 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
26828 exp.X_add_number -= 4;
26829 }
26830 pc_rel = 1;
26831 break;
26832 case T_MNEM_mov:
26833 case T_MNEM_movs:
26834 case T_MNEM_cmp:
26835 case T_MNEM_cmn:
26836 if (fragp->fr_var == 4)
26837 {
26838 int r0off = (opcode == T_MNEM_mov
26839 || opcode == T_MNEM_movs) ? 0 : 8;
26840 insn = THUMB_OP32 (opcode);
26841 insn = (insn & 0xe1ffffff) | 0x10000000;
26842 insn |= (old_op & 0x700) << r0off;
26843 put_thumb32_insn (buf, insn);
26844 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
26845 }
26846 else
26847 {
26848 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
26849 }
26850 pc_rel = 0;
26851 break;
26852 case T_MNEM_b:
26853 if (fragp->fr_var == 4)
26854 {
26855 insn = THUMB_OP32(opcode);
26856 put_thumb32_insn (buf, insn);
26857 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
26858 }
26859 else
26860 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
26861 pc_rel = 1;
26862 break;
26863 case T_MNEM_bcond:
26864 if (fragp->fr_var == 4)
26865 {
26866 insn = THUMB_OP32(opcode);
26867 insn |= (old_op & 0xf00) << 14;
26868 put_thumb32_insn (buf, insn);
26869 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
26870 }
26871 else
26872 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
26873 pc_rel = 1;
26874 break;
26875 case T_MNEM_add_sp:
26876 case T_MNEM_add_pc:
26877 case T_MNEM_inc_sp:
26878 case T_MNEM_dec_sp:
26879 if (fragp->fr_var == 4)
26880 {
26881 /* ??? Choose between add and addw. */
26882 insn = THUMB_OP32 (opcode);
26883 insn |= (old_op & 0xf0) << 4;
26884 put_thumb32_insn (buf, insn);
26885 if (opcode == T_MNEM_add_pc)
26886 reloc_type = BFD_RELOC_ARM_T32_IMM12;
26887 else
26888 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
26889 }
26890 else
26891 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
26892 pc_rel = 0;
26893 break;
26894
26895 case T_MNEM_addi:
26896 case T_MNEM_addis:
26897 case T_MNEM_subi:
26898 case T_MNEM_subis:
26899 if (fragp->fr_var == 4)
26900 {
26901 insn = THUMB_OP32 (opcode);
26902 insn |= (old_op & 0xf0) << 4;
26903 insn |= (old_op & 0xf) << 16;
26904 put_thumb32_insn (buf, insn);
26905 if (insn & (1 << 20))
26906 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
26907 else
26908 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
26909 }
26910 else
26911 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
26912 pc_rel = 0;
26913 break;
26914 default:
26915 abort ();
26916 }
26917 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
26918 (enum bfd_reloc_code_real) reloc_type);
26919 fixp->fx_file = fragp->fr_file;
26920 fixp->fx_line = fragp->fr_line;
26921 fragp->fr_fix += fragp->fr_var;
26922
26923 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26924 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
26925 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
26926 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
26927}
26928
26929/* Return the size of a relaxable immediate operand instruction.
26930 SHIFT and SIZE specify the form of the allowable immediate. */
26931static int
26932relax_immediate (fragS *fragp, int size, int shift)
26933{
26934 offsetT offset;
26935 offsetT mask;
26936 offsetT low;
26937
26938 /* ??? Should be able to do better than this. */
26939 if (fragp->fr_symbol)
26940 return 4;
26941
26942 low = (1 << shift) - 1;
26943 mask = (1 << (shift + size)) - (1 << shift);
26944 offset = fragp->fr_offset;
26945 /* Force misaligned offsets to 32-bit variant. */
26946 if (offset & low)
26947 return 4;
26948 if (offset & ~mask)
26949 return 4;
26950 return 2;
26951}
26952
26953/* Get the address of a symbol during relaxation. */
26954static addressT
26955relaxed_symbol_addr (fragS *fragp, long stretch)
26956{
26957 fragS *sym_frag;
26958 addressT addr;
26959 symbolS *sym;
26960
26961 sym = fragp->fr_symbol;
26962 sym_frag = symbol_get_frag (sym);
26963 know (S_GET_SEGMENT (sym) != absolute_section
26964 || sym_frag == &zero_address_frag);
26965 addr = S_GET_VALUE (sym) + fragp->fr_offset;
26966
26967 /* If frag has yet to be reached on this pass, assume it will
26968 move by STRETCH just as we did. If this is not so, it will
26969 be because some frag between grows, and that will force
26970 another pass. */
26971
26972 if (stretch != 0
26973 && sym_frag->relax_marker != fragp->relax_marker)
26974 {
26975 fragS *f;
26976
26977 /* Adjust stretch for any alignment frag. Note that if have
26978 been expanding the earlier code, the symbol may be
26979 defined in what appears to be an earlier frag. FIXME:
26980 This doesn't handle the fr_subtype field, which specifies
26981 a maximum number of bytes to skip when doing an
26982 alignment. */
26983 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
26984 {
26985 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
26986 {
26987 if (stretch < 0)
26988 stretch = - ((- stretch)
26989 & ~ ((1 << (int) f->fr_offset) - 1));
26990 else
26991 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
26992 if (stretch == 0)
26993 break;
26994 }
26995 }
26996 if (f != NULL)
26997 addr += stretch;
26998 }
26999
27000 return addr;
27001}
27002
27003/* Return the size of a relaxable adr pseudo-instruction or PC-relative
27004 load. */
27005static int
27006relax_adr (fragS *fragp, asection *sec, long stretch)
27007{
27008 addressT addr;
27009 offsetT val;
27010
27011 /* Assume worst case for symbols not known to be in the same section. */
27012 if (fragp->fr_symbol == NULL
27013 || !S_IS_DEFINED (fragp->fr_symbol)
27014 || sec != S_GET_SEGMENT (fragp->fr_symbol)
27015 || S_IS_WEAK (fragp->fr_symbol))
27016 return 4;
27017
27018 val = relaxed_symbol_addr (fragp, stretch);
27019 addr = fragp->fr_address + fragp->fr_fix;
27020 addr = (addr + 4) & ~3;
27021 /* Force misaligned targets to 32-bit variant. */
27022 if (val & 3)
27023 return 4;
27024 val -= addr;
27025 if (val < 0 || val > 1020)
27026 return 4;
27027 return 2;
27028}
27029
27030/* Return the size of a relaxable add/sub immediate instruction. */
27031static int
27032relax_addsub (fragS *fragp, asection *sec)
27033{
27034 char *buf;
27035 int op;
27036
27037 buf = fragp->fr_literal + fragp->fr_fix;
27038 op = bfd_get_16(sec->owner, buf);
27039 if ((op & 0xf) == ((op >> 4) & 0xf))
27040 return relax_immediate (fragp, 8, 0);
27041 else
27042 return relax_immediate (fragp, 3, 0);
27043}
27044
27045/* Return TRUE iff the definition of symbol S could be pre-empted
27046 (overridden) at link or load time. */
27047static bfd_boolean
27048symbol_preemptible (symbolS *s)
27049{
27050 /* Weak symbols can always be pre-empted. */
27051 if (S_IS_WEAK (s))
27052 return TRUE;
27053
27054 /* Non-global symbols cannot be pre-empted. */
27055 if (! S_IS_EXTERNAL (s))
27056 return FALSE;
27057
27058#ifdef OBJ_ELF
27059 /* In ELF, a global symbol can be marked protected, or private. In that
27060 case it can't be pre-empted (other definitions in the same link unit
27061 would violate the ODR). */
27062 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
27063 return FALSE;
27064#endif
27065
27066 /* Other global symbols might be pre-empted. */
27067 return TRUE;
27068}
27069
27070/* Return the size of a relaxable branch instruction. BITS is the
27071 size of the offset field in the narrow instruction. */
27072
27073static int
27074relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
27075{
27076 addressT addr;
27077 offsetT val;
27078 offsetT limit;
27079
27080 /* Assume worst case for symbols not known to be in the same section. */
27081 if (!S_IS_DEFINED (fragp->fr_symbol)
27082 || sec != S_GET_SEGMENT (fragp->fr_symbol)
27083 || S_IS_WEAK (fragp->fr_symbol))
27084 return 4;
27085
27086#ifdef OBJ_ELF
27087 /* A branch to a function in ARM state will require interworking. */
27088 if (S_IS_DEFINED (fragp->fr_symbol)
27089 && ARM_IS_FUNC (fragp->fr_symbol))
27090 return 4;
27091#endif
27092
27093 if (symbol_preemptible (fragp->fr_symbol))
27094 return 4;
27095
27096 val = relaxed_symbol_addr (fragp, stretch);
27097 addr = fragp->fr_address + fragp->fr_fix + 4;
27098 val -= addr;
27099
27100 /* Offset is a signed value *2 */
27101 limit = 1 << bits;
27102 if (val >= limit || val < -limit)
27103 return 4;
27104 return 2;
27105}
27106
27107
27108/* Relax a machine dependent frag. This returns the amount by which
27109 the current size of the frag should change. */
27110
27111int
27112arm_relax_frag (asection *sec, fragS *fragp, long stretch)
27113{
27114 int oldsize;
27115 int newsize;
27116
27117 oldsize = fragp->fr_var;
27118 switch (fragp->fr_subtype)
27119 {
27120 case T_MNEM_ldr_pc2:
27121 newsize = relax_adr (fragp, sec, stretch);
27122 break;
27123 case T_MNEM_ldr_pc:
27124 case T_MNEM_ldr_sp:
27125 case T_MNEM_str_sp:
27126 newsize = relax_immediate (fragp, 8, 2);
27127 break;
27128 case T_MNEM_ldr:
27129 case T_MNEM_str:
27130 newsize = relax_immediate (fragp, 5, 2);
27131 break;
27132 case T_MNEM_ldrh:
27133 case T_MNEM_strh:
27134 newsize = relax_immediate (fragp, 5, 1);
27135 break;
27136 case T_MNEM_ldrb:
27137 case T_MNEM_strb:
27138 newsize = relax_immediate (fragp, 5, 0);
27139 break;
27140 case T_MNEM_adr:
27141 newsize = relax_adr (fragp, sec, stretch);
27142 break;
27143 case T_MNEM_mov:
27144 case T_MNEM_movs:
27145 case T_MNEM_cmp:
27146 case T_MNEM_cmn:
27147 newsize = relax_immediate (fragp, 8, 0);
27148 break;
27149 case T_MNEM_b:
27150 newsize = relax_branch (fragp, sec, 11, stretch);
27151 break;
27152 case T_MNEM_bcond:
27153 newsize = relax_branch (fragp, sec, 8, stretch);
27154 break;
27155 case T_MNEM_add_sp:
27156 case T_MNEM_add_pc:
27157 newsize = relax_immediate (fragp, 8, 2);
27158 break;
27159 case T_MNEM_inc_sp:
27160 case T_MNEM_dec_sp:
27161 newsize = relax_immediate (fragp, 7, 2);
27162 break;
27163 case T_MNEM_addi:
27164 case T_MNEM_addis:
27165 case T_MNEM_subi:
27166 case T_MNEM_subis:
27167 newsize = relax_addsub (fragp, sec);
27168 break;
27169 default:
27170 abort ();
27171 }
27172
27173 fragp->fr_var = newsize;
27174 /* Freeze wide instructions that are at or before the same location as
27175 in the previous pass. This avoids infinite loops.
27176 Don't freeze them unconditionally because targets may be artificially
27177 misaligned by the expansion of preceding frags. */
27178 if (stretch <= 0 && newsize > 2)
27179 {
27180 md_convert_frag (sec->owner, sec, fragp);
27181 frag_wane (fragp);
27182 }
27183
27184 return newsize - oldsize;
27185}
27186
27187/* Round up a section size to the appropriate boundary. */
27188
27189valueT
27190md_section_align (segT segment ATTRIBUTE_UNUSED,
27191 valueT size)
27192{
27193 return size;
27194}
27195
27196/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
27197 of an rs_align_code fragment. */
27198
27199void
27200arm_handle_align (fragS * fragP)
27201{
27202 static unsigned char const arm_noop[2][2][4] =
27203 {
27204 { /* ARMv1 */
27205 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
27206 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
27207 },
27208 { /* ARMv6k */
27209 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
27210 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
27211 },
27212 };
27213 static unsigned char const thumb_noop[2][2][2] =
27214 {
27215 { /* Thumb-1 */
27216 {0xc0, 0x46}, /* LE */
27217 {0x46, 0xc0}, /* BE */
27218 },
27219 { /* Thumb-2 */
27220 {0x00, 0xbf}, /* LE */
27221 {0xbf, 0x00} /* BE */
27222 }
27223 };
27224 static unsigned char const wide_thumb_noop[2][4] =
27225 { /* Wide Thumb-2 */
27226 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
27227 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
27228 };
27229
27230 unsigned bytes, fix, noop_size;
27231 char * p;
27232 const unsigned char * noop;
27233 const unsigned char *narrow_noop = NULL;
27234#ifdef OBJ_ELF
27235 enum mstate state;
27236#endif
27237
27238 if (fragP->fr_type != rs_align_code)
27239 return;
27240
27241 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
27242 p = fragP->fr_literal + fragP->fr_fix;
27243 fix = 0;
27244
27245 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
27246 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
27247
27248 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
27249
27250 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
27251 {
27252 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
27253 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
27254 {
27255 narrow_noop = thumb_noop[1][target_big_endian];
27256 noop = wide_thumb_noop[target_big_endian];
27257 }
27258 else
27259 noop = thumb_noop[0][target_big_endian];
27260 noop_size = 2;
27261#ifdef OBJ_ELF
27262 state = MAP_THUMB;
27263#endif
27264 }
27265 else
27266 {
27267 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
27268 ? selected_cpu : arm_arch_none,
27269 arm_ext_v6k) != 0]
27270 [target_big_endian];
27271 noop_size = 4;
27272#ifdef OBJ_ELF
27273 state = MAP_ARM;
27274#endif
27275 }
27276
27277 fragP->fr_var = noop_size;
27278
27279 if (bytes & (noop_size - 1))
27280 {
27281 fix = bytes & (noop_size - 1);
27282#ifdef OBJ_ELF
27283 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
27284#endif
27285 memset (p, 0, fix);
27286 p += fix;
27287 bytes -= fix;
27288 }
27289
27290 if (narrow_noop)
27291 {
27292 if (bytes & noop_size)
27293 {
27294 /* Insert a narrow noop. */
27295 memcpy (p, narrow_noop, noop_size);
27296 p += noop_size;
27297 bytes -= noop_size;
27298 fix += noop_size;
27299 }
27300
27301 /* Use wide noops for the remainder */
27302 noop_size = 4;
27303 }
27304
27305 while (bytes >= noop_size)
27306 {
27307 memcpy (p, noop, noop_size);
27308 p += noop_size;
27309 bytes -= noop_size;
27310 fix += noop_size;
27311 }
27312
27313 fragP->fr_fix += fix;
27314}
27315
27316/* Called from md_do_align. Used to create an alignment
27317 frag in a code section. */
27318
27319void
27320arm_frag_align_code (int n, int max)
27321{
27322 char * p;
27323
27324 /* We assume that there will never be a requirement
27325 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
27326 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
27327 {
27328 char err_msg[128];
27329
27330 sprintf (err_msg,
27331 _("alignments greater than %d bytes not supported in .text sections."),
27332 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
27333 as_fatal ("%s", err_msg);
27334 }
27335
27336 p = frag_var (rs_align_code,
27337 MAX_MEM_FOR_RS_ALIGN_CODE,
27338 1,
27339 (relax_substateT) max,
27340 (symbolS *) NULL,
27341 (offsetT) n,
27342 (char *) NULL);
27343 *p = 0;
27344}
27345
27346/* Perform target specific initialisation of a frag.
27347 Note - despite the name this initialisation is not done when the frag
27348 is created, but only when its type is assigned. A frag can be created
27349 and used a long time before its type is set, so beware of assuming that
27350 this initialisation is performed first. */
27351
27352#ifndef OBJ_ELF
27353void
27354arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
27355{
27356 /* Record whether this frag is in an ARM or a THUMB area. */
27357 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
27358}
27359
27360#else /* OBJ_ELF is defined. */
27361void
27362arm_init_frag (fragS * fragP, int max_chars)
27363{
27364 bfd_boolean frag_thumb_mode;
27365
27366 /* If the current ARM vs THUMB mode has not already
27367 been recorded into this frag then do so now. */
27368 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
27369 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
27370
27371 /* PR 21809: Do not set a mapping state for debug sections
27372 - it just confuses other tools. */
27373 if (bfd_section_flags (now_seg) & SEC_DEBUGGING)
27374 return;
27375
27376 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
27377
27378 /* Record a mapping symbol for alignment frags. We will delete this
27379 later if the alignment ends up empty. */
27380 switch (fragP->fr_type)
27381 {
27382 case rs_align:
27383 case rs_align_test:
27384 case rs_fill:
27385 mapping_state_2 (MAP_DATA, max_chars);
27386 break;
27387 case rs_align_code:
27388 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
27389 break;
27390 default:
27391 break;
27392 }
27393}
27394
27395/* When we change sections we need to issue a new mapping symbol. */
27396
27397void
27398arm_elf_change_section (void)
27399{
27400 /* Link an unlinked unwind index table section to the .text section. */
27401 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
27402 && elf_linked_to_section (now_seg) == NULL)
27403 elf_linked_to_section (now_seg) = text_section;
27404}
27405
27406int
27407arm_elf_section_type (const char * str, size_t len)
27408{
27409 if (len == 5 && strncmp (str, "exidx", 5) == 0)
27410 return SHT_ARM_EXIDX;
27411
27412 return -1;
27413}
27414\f
27415/* Code to deal with unwinding tables. */
27416
27417static void add_unwind_adjustsp (offsetT);
27418
27419/* Generate any deferred unwind frame offset. */
27420
27421static void
27422flush_pending_unwind (void)
27423{
27424 offsetT offset;
27425
27426 offset = unwind.pending_offset;
27427 unwind.pending_offset = 0;
27428 if (offset != 0)
27429 add_unwind_adjustsp (offset);
27430}
27431
27432/* Add an opcode to this list for this function. Two-byte opcodes should
27433 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
27434 order. */
27435
27436static void
27437add_unwind_opcode (valueT op, int length)
27438{
27439 /* Add any deferred stack adjustment. */
27440 if (unwind.pending_offset)
27441 flush_pending_unwind ();
27442
27443 unwind.sp_restored = 0;
27444
27445 if (unwind.opcode_count + length > unwind.opcode_alloc)
27446 {
27447 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
27448 if (unwind.opcodes)
27449 unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
27450 unwind.opcode_alloc);
27451 else
27452 unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
27453 }
27454 while (length > 0)
27455 {
27456 length--;
27457 unwind.opcodes[unwind.opcode_count] = op & 0xff;
27458 op >>= 8;
27459 unwind.opcode_count++;
27460 }
27461}
27462
27463/* Add unwind opcodes to adjust the stack pointer. */
27464
27465static void
27466add_unwind_adjustsp (offsetT offset)
27467{
27468 valueT op;
27469
27470 if (offset > 0x200)
27471 {
27472 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
27473 char bytes[5];
27474 int n;
27475 valueT o;
27476
27477 /* Long form: 0xb2, uleb128. */
27478 /* This might not fit in a word so add the individual bytes,
27479 remembering the list is built in reverse order. */
27480 o = (valueT) ((offset - 0x204) >> 2);
27481 if (o == 0)
27482 add_unwind_opcode (0, 1);
27483
27484 /* Calculate the uleb128 encoding of the offset. */
27485 n = 0;
27486 while (o)
27487 {
27488 bytes[n] = o & 0x7f;
27489 o >>= 7;
27490 if (o)
27491 bytes[n] |= 0x80;
27492 n++;
27493 }
27494 /* Add the insn. */
27495 for (; n; n--)
27496 add_unwind_opcode (bytes[n - 1], 1);
27497 add_unwind_opcode (0xb2, 1);
27498 }
27499 else if (offset > 0x100)
27500 {
27501 /* Two short opcodes. */
27502 add_unwind_opcode (0x3f, 1);
27503 op = (offset - 0x104) >> 2;
27504 add_unwind_opcode (op, 1);
27505 }
27506 else if (offset > 0)
27507 {
27508 /* Short opcode. */
27509 op = (offset - 4) >> 2;
27510 add_unwind_opcode (op, 1);
27511 }
27512 else if (offset < 0)
27513 {
27514 offset = -offset;
27515 while (offset > 0x100)
27516 {
27517 add_unwind_opcode (0x7f, 1);
27518 offset -= 0x100;
27519 }
27520 op = ((offset - 4) >> 2) | 0x40;
27521 add_unwind_opcode (op, 1);
27522 }
27523}
27524
27525/* Finish the list of unwind opcodes for this function. */
27526
27527static void
27528finish_unwind_opcodes (void)
27529{
27530 valueT op;
27531
27532 if (unwind.fp_used)
27533 {
27534 /* Adjust sp as necessary. */
27535 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
27536 flush_pending_unwind ();
27537
27538 /* After restoring sp from the frame pointer. */
27539 op = 0x90 | unwind.fp_reg;
27540 add_unwind_opcode (op, 1);
27541 }
27542 else
27543 flush_pending_unwind ();
27544}
27545
27546
27547/* Start an exception table entry. If idx is nonzero this is an index table
27548 entry. */
27549
27550static void
27551start_unwind_section (const segT text_seg, int idx)
27552{
27553 const char * text_name;
27554 const char * prefix;
27555 const char * prefix_once;
27556 struct elf_section_match match;
27557 char * sec_name;
27558 int type;
27559 int flags;
27560 int linkonce;
27561
27562 if (idx)
27563 {
27564 prefix = ELF_STRING_ARM_unwind;
27565 prefix_once = ELF_STRING_ARM_unwind_once;
27566 type = SHT_ARM_EXIDX;
27567 }
27568 else
27569 {
27570 prefix = ELF_STRING_ARM_unwind_info;
27571 prefix_once = ELF_STRING_ARM_unwind_info_once;
27572 type = SHT_PROGBITS;
27573 }
27574
27575 text_name = segment_name (text_seg);
27576 if (streq (text_name, ".text"))
27577 text_name = "";
27578
27579 if (strncmp (text_name, ".gnu.linkonce.t.",
27580 strlen (".gnu.linkonce.t.")) == 0)
27581 {
27582 prefix = prefix_once;
27583 text_name += strlen (".gnu.linkonce.t.");
27584 }
27585
27586 sec_name = concat (prefix, text_name, (char *) NULL);
27587
27588 flags = SHF_ALLOC;
27589 linkonce = 0;
27590 memset (&match, 0, sizeof (match));
27591
27592 /* Handle COMDAT group. */
27593 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
27594 {
27595 match.group_name = elf_group_name (text_seg);
27596 if (match.group_name == NULL)
27597 {
27598 as_bad (_("Group section `%s' has no group signature"),
27599 segment_name (text_seg));
27600 ignore_rest_of_line ();
27601 return;
27602 }
27603 flags |= SHF_GROUP;
27604 linkonce = 1;
27605 }
27606
27607 obj_elf_change_section (sec_name, type, flags, 0, &match,
27608 linkonce, 0);
27609
27610 /* Set the section link for index tables. */
27611 if (idx)
27612 elf_linked_to_section (now_seg) = text_seg;
27613}
27614
27615
27616/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27617 personality routine data. Returns zero, or the index table value for
27618 an inline entry. */
27619
27620static valueT
27621create_unwind_entry (int have_data)
27622{
27623 int size;
27624 addressT where;
27625 char *ptr;
27626 /* The current word of data. */
27627 valueT data;
27628 /* The number of bytes left in this word. */
27629 int n;
27630
27631 finish_unwind_opcodes ();
27632
27633 /* Remember the current text section. */
27634 unwind.saved_seg = now_seg;
27635 unwind.saved_subseg = now_subseg;
27636
27637 start_unwind_section (now_seg, 0);
27638
27639 if (unwind.personality_routine == NULL)
27640 {
27641 if (unwind.personality_index == -2)
27642 {
27643 if (have_data)
27644 as_bad (_("handlerdata in cantunwind frame"));
27645 return 1; /* EXIDX_CANTUNWIND. */
27646 }
27647
27648 /* Use a default personality routine if none is specified. */
27649 if (unwind.personality_index == -1)
27650 {
27651 if (unwind.opcode_count > 3)
27652 unwind.personality_index = 1;
27653 else
27654 unwind.personality_index = 0;
27655 }
27656
27657 /* Space for the personality routine entry. */
27658 if (unwind.personality_index == 0)
27659 {
27660 if (unwind.opcode_count > 3)
27661 as_bad (_("too many unwind opcodes for personality routine 0"));
27662
27663 if (!have_data)
27664 {
27665 /* All the data is inline in the index table. */
27666 data = 0x80;
27667 n = 3;
27668 while (unwind.opcode_count > 0)
27669 {
27670 unwind.opcode_count--;
27671 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
27672 n--;
27673 }
27674
27675 /* Pad with "finish" opcodes. */
27676 while (n--)
27677 data = (data << 8) | 0xb0;
27678
27679 return data;
27680 }
27681 size = 0;
27682 }
27683 else
27684 /* We get two opcodes "free" in the first word. */
27685 size = unwind.opcode_count - 2;
27686 }
27687 else
27688 {
27689 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27690 if (unwind.personality_index != -1)
27691 {
27692 as_bad (_("attempt to recreate an unwind entry"));
27693 return 1;
27694 }
27695
27696 /* An extra byte is required for the opcode count. */
27697 size = unwind.opcode_count + 1;
27698 }
27699
27700 size = (size + 3) >> 2;
27701 if (size > 0xff)
27702 as_bad (_("too many unwind opcodes"));
27703
27704 frag_align (2, 0, 0);
27705 record_alignment (now_seg, 2);
27706 unwind.table_entry = expr_build_dot ();
27707
27708 /* Allocate the table entry. */
27709 ptr = frag_more ((size << 2) + 4);
27710 /* PR 13449: Zero the table entries in case some of them are not used. */
27711 memset (ptr, 0, (size << 2) + 4);
27712 where = frag_now_fix () - ((size << 2) + 4);
27713
27714 switch (unwind.personality_index)
27715 {
27716 case -1:
27717 /* ??? Should this be a PLT generating relocation? */
27718 /* Custom personality routine. */
27719 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
27720 BFD_RELOC_ARM_PREL31);
27721
27722 where += 4;
27723 ptr += 4;
27724
27725 /* Set the first byte to the number of additional words. */
27726 data = size > 0 ? size - 1 : 0;
27727 n = 3;
27728 break;
27729
27730 /* ABI defined personality routines. */
27731 case 0:
27732 /* Three opcodes bytes are packed into the first word. */
27733 data = 0x80;
27734 n = 3;
27735 break;
27736
27737 case 1:
27738 case 2:
27739 /* The size and first two opcode bytes go in the first word. */
27740 data = ((0x80 + unwind.personality_index) << 8) | size;
27741 n = 2;
27742 break;
27743
27744 default:
27745 /* Should never happen. */
27746 abort ();
27747 }
27748
27749 /* Pack the opcodes into words (MSB first), reversing the list at the same
27750 time. */
27751 while (unwind.opcode_count > 0)
27752 {
27753 if (n == 0)
27754 {
27755 md_number_to_chars (ptr, data, 4);
27756 ptr += 4;
27757 n = 4;
27758 data = 0;
27759 }
27760 unwind.opcode_count--;
27761 n--;
27762 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
27763 }
27764
27765 /* Finish off the last word. */
27766 if (n < 4)
27767 {
27768 /* Pad with "finish" opcodes. */
27769 while (n--)
27770 data = (data << 8) | 0xb0;
27771
27772 md_number_to_chars (ptr, data, 4);
27773 }
27774
27775 if (!have_data)
27776 {
27777 /* Add an empty descriptor if there is no user-specified data. */
27778 ptr = frag_more (4);
27779 md_number_to_chars (ptr, 0, 4);
27780 }
27781
27782 return 0;
27783}
27784
27785
27786/* Initialize the DWARF-2 unwind information for this procedure. */
27787
27788void
27789tc_arm_frame_initial_instructions (void)
27790{
27791 cfi_add_CFA_def_cfa (REG_SP, 0);
27792}
27793#endif /* OBJ_ELF */
27794
27795/* Convert REGNAME to a DWARF-2 register number. */
27796
27797int
27798tc_arm_regname_to_dw2regnum (char *regname)
27799{
27800 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
27801 if (reg != FAIL)
27802 return reg;
27803
27804 /* PR 16694: Allow VFP registers as well. */
27805 reg = arm_reg_parse (&regname, REG_TYPE_VFS);
27806 if (reg != FAIL)
27807 return 64 + reg;
27808
27809 reg = arm_reg_parse (&regname, REG_TYPE_VFD);
27810 if (reg != FAIL)
27811 return reg + 256;
27812
27813 return FAIL;
27814}
27815
27816#ifdef TE_PE
27817void
27818tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
27819{
27820 expressionS exp;
27821
27822 exp.X_op = O_secrel;
27823 exp.X_add_symbol = symbol;
27824 exp.X_add_number = 0;
27825 emit_expr (&exp, size);
27826}
27827#endif
27828
27829/* MD interface: Symbol and relocation handling. */
27830
27831/* Return the address within the segment that a PC-relative fixup is
27832 relative to. For ARM, PC-relative fixups applied to instructions
27833 are generally relative to the location of the fixup plus 8 bytes.
27834 Thumb branches are offset by 4, and Thumb loads relative to PC
27835 require special handling. */
27836
27837long
27838md_pcrel_from_section (fixS * fixP, segT seg)
27839{
27840 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
27841
27842 /* If this is pc-relative and we are going to emit a relocation
27843 then we just want to put out any pipeline compensation that the linker
27844 will need. Otherwise we want to use the calculated base.
27845 For WinCE we skip the bias for externals as well, since this
27846 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27847 if (fixP->fx_pcrel
27848 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
27849 || (arm_force_relocation (fixP)
27850#ifdef TE_WINCE
27851 && !S_IS_EXTERNAL (fixP->fx_addsy)
27852#endif
27853 )))
27854 base = 0;
27855
27856
27857 switch (fixP->fx_r_type)
27858 {
27859 /* PC relative addressing on the Thumb is slightly odd as the
27860 bottom two bits of the PC are forced to zero for the
27861 calculation. This happens *after* application of the
27862 pipeline offset. However, Thumb adrl already adjusts for
27863 this, so we need not do it again. */
27864 case BFD_RELOC_ARM_THUMB_ADD:
27865 return base & ~3;
27866
27867 case BFD_RELOC_ARM_THUMB_OFFSET:
27868 case BFD_RELOC_ARM_T32_OFFSET_IMM:
27869 case BFD_RELOC_ARM_T32_ADD_PC12:
27870 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
27871 return (base + 4) & ~3;
27872
27873 /* Thumb branches are simply offset by +4. */
27874 case BFD_RELOC_THUMB_PCREL_BRANCH5:
27875 case BFD_RELOC_THUMB_PCREL_BRANCH7:
27876 case BFD_RELOC_THUMB_PCREL_BRANCH9:
27877 case BFD_RELOC_THUMB_PCREL_BRANCH12:
27878 case BFD_RELOC_THUMB_PCREL_BRANCH20:
27879 case BFD_RELOC_THUMB_PCREL_BRANCH25:
27880 case BFD_RELOC_THUMB_PCREL_BFCSEL:
27881 case BFD_RELOC_ARM_THUMB_BF17:
27882 case BFD_RELOC_ARM_THUMB_BF19:
27883 case BFD_RELOC_ARM_THUMB_BF13:
27884 case BFD_RELOC_ARM_THUMB_LOOP12:
27885 return base + 4;
27886
27887 case BFD_RELOC_THUMB_PCREL_BRANCH23:
27888 if (fixP->fx_addsy
27889 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27890 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27891 && ARM_IS_FUNC (fixP->fx_addsy)
27892 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27893 base = fixP->fx_where + fixP->fx_frag->fr_address;
27894 return base + 4;
27895
27896 /* BLX is like branches above, but forces the low two bits of PC to
27897 zero. */
27898 case BFD_RELOC_THUMB_PCREL_BLX:
27899 if (fixP->fx_addsy
27900 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27901 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27902 && THUMB_IS_FUNC (fixP->fx_addsy)
27903 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27904 base = fixP->fx_where + fixP->fx_frag->fr_address;
27905 return (base + 4) & ~3;
27906
27907 /* ARM mode branches are offset by +8. However, the Windows CE
27908 loader expects the relocation not to take this into account. */
27909 case BFD_RELOC_ARM_PCREL_BLX:
27910 if (fixP->fx_addsy
27911 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27912 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27913 && ARM_IS_FUNC (fixP->fx_addsy)
27914 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27915 base = fixP->fx_where + fixP->fx_frag->fr_address;
27916 return base + 8;
27917
27918 case BFD_RELOC_ARM_PCREL_CALL:
27919 if (fixP->fx_addsy
27920 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27921 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
27922 && THUMB_IS_FUNC (fixP->fx_addsy)
27923 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27924 base = fixP->fx_where + fixP->fx_frag->fr_address;
27925 return base + 8;
27926
27927 case BFD_RELOC_ARM_PCREL_BRANCH:
27928 case BFD_RELOC_ARM_PCREL_JUMP:
27929 case BFD_RELOC_ARM_PLT32:
27930#ifdef TE_WINCE
27931 /* When handling fixups immediately, because we have already
27932 discovered the value of a symbol, or the address of the frag involved
27933 we must account for the offset by +8, as the OS loader will never see the reloc.
27934 see fixup_segment() in write.c
27935 The S_IS_EXTERNAL test handles the case of global symbols.
27936 Those need the calculated base, not just the pipe compensation the linker will need. */
27937 if (fixP->fx_pcrel
27938 && fixP->fx_addsy != NULL
27939 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27940 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
27941 return base + 8;
27942 return base;
27943#else
27944 return base + 8;
27945#endif
27946
27947
27948 /* ARM mode loads relative to PC are also offset by +8. Unlike
27949 branches, the Windows CE loader *does* expect the relocation
27950 to take this into account. */
27951 case BFD_RELOC_ARM_OFFSET_IMM:
27952 case BFD_RELOC_ARM_OFFSET_IMM8:
27953 case BFD_RELOC_ARM_HWLITERAL:
27954 case BFD_RELOC_ARM_LITERAL:
27955 case BFD_RELOC_ARM_CP_OFF_IMM:
27956 return base + 8;
27957
27958
27959 /* Other PC-relative relocations are un-offset. */
27960 default:
27961 return base;
27962 }
27963}
27964
27965static bfd_boolean flag_warn_syms = TRUE;
27966
27967bfd_boolean
27968arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
27969{
27970 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27971 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27972 does mean that the resulting code might be very confusing to the reader.
27973 Also this warning can be triggered if the user omits an operand before
27974 an immediate address, eg:
27975
27976 LDR =foo
27977
27978 GAS treats this as an assignment of the value of the symbol foo to a
27979 symbol LDR, and so (without this code) it will not issue any kind of
27980 warning or error message.
27981
27982 Note - ARM instructions are case-insensitive but the strings in the hash
27983 table are all stored in lower case, so we must first ensure that name is
27984 lower case too. */
27985 if (flag_warn_syms && arm_ops_hsh)
27986 {
27987 char * nbuf = strdup (name);
27988 char * p;
27989
27990 for (p = nbuf; *p; p++)
27991 *p = TOLOWER (*p);
27992 if (hash_find (arm_ops_hsh, nbuf) != NULL)
27993 {
27994 static struct hash_control * already_warned = NULL;
27995
27996 if (already_warned == NULL)
27997 already_warned = hash_new ();
27998 /* Only warn about the symbol once. To keep the code
27999 simple we let hash_insert do the lookup for us. */
28000 if (hash_insert (already_warned, nbuf, NULL) == NULL)
28001 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
28002 }
28003 else
28004 free (nbuf);
28005 }
28006
28007 return FALSE;
28008}
28009
28010/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28011 Otherwise we have no need to default values of symbols. */
28012
28013symbolS *
28014md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
28015{
28016#ifdef OBJ_ELF
28017 if (name[0] == '_' && name[1] == 'G'
28018 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
28019 {
28020 if (!GOT_symbol)
28021 {
28022 if (symbol_find (name))
28023 as_bad (_("GOT already in the symbol table"));
28024
28025 GOT_symbol = symbol_new (name, undefined_section,
28026 (valueT) 0, & zero_address_frag);
28027 }
28028
28029 return GOT_symbol;
28030 }
28031#endif
28032
28033 return NULL;
28034}
28035
28036/* Subroutine of md_apply_fix. Check to see if an immediate can be
28037 computed as two separate immediate values, added together. We
28038 already know that this value cannot be computed by just one ARM
28039 instruction. */
28040
28041static unsigned int
28042validate_immediate_twopart (unsigned int val,
28043 unsigned int * highpart)
28044{
28045 unsigned int a;
28046 unsigned int i;
28047
28048 for (i = 0; i < 32; i += 2)
28049 if (((a = rotate_left (val, i)) & 0xff) != 0)
28050 {
28051 if (a & 0xff00)
28052 {
28053 if (a & ~ 0xffff)
28054 continue;
28055 * highpart = (a >> 8) | ((i + 24) << 7);
28056 }
28057 else if (a & 0xff0000)
28058 {
28059 if (a & 0xff000000)
28060 continue;
28061 * highpart = (a >> 16) | ((i + 16) << 7);
28062 }
28063 else
28064 {
28065 gas_assert (a & 0xff000000);
28066 * highpart = (a >> 24) | ((i + 8) << 7);
28067 }
28068
28069 return (a & 0xff) | (i << 7);
28070 }
28071
28072 return FAIL;
28073}
28074
28075static int
28076validate_offset_imm (unsigned int val, int hwse)
28077{
28078 if ((hwse && val > 255) || val > 4095)
28079 return FAIL;
28080 return val;
28081}
28082
28083/* Subroutine of md_apply_fix. Do those data_ops which can take a
28084 negative immediate constant by altering the instruction. A bit of
28085 a hack really.
28086 MOV <-> MVN
28087 AND <-> BIC
28088 ADC <-> SBC
28089 by inverting the second operand, and
28090 ADD <-> SUB
28091 CMP <-> CMN
28092 by negating the second operand. */
28093
28094static int
28095negate_data_op (unsigned long * instruction,
28096 unsigned long value)
28097{
28098 int op, new_inst;
28099 unsigned long negated, inverted;
28100
28101 negated = encode_arm_immediate (-value);
28102 inverted = encode_arm_immediate (~value);
28103
28104 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
28105 switch (op)
28106 {
28107 /* First negates. */
28108 case OPCODE_SUB: /* ADD <-> SUB */
28109 new_inst = OPCODE_ADD;
28110 value = negated;
28111 break;
28112
28113 case OPCODE_ADD:
28114 new_inst = OPCODE_SUB;
28115 value = negated;
28116 break;
28117
28118 case OPCODE_CMP: /* CMP <-> CMN */
28119 new_inst = OPCODE_CMN;
28120 value = negated;
28121 break;
28122
28123 case OPCODE_CMN:
28124 new_inst = OPCODE_CMP;
28125 value = negated;
28126 break;
28127
28128 /* Now Inverted ops. */
28129 case OPCODE_MOV: /* MOV <-> MVN */
28130 new_inst = OPCODE_MVN;
28131 value = inverted;
28132 break;
28133
28134 case OPCODE_MVN:
28135 new_inst = OPCODE_MOV;
28136 value = inverted;
28137 break;
28138
28139 case OPCODE_AND: /* AND <-> BIC */
28140 new_inst = OPCODE_BIC;
28141 value = inverted;
28142 break;
28143
28144 case OPCODE_BIC:
28145 new_inst = OPCODE_AND;
28146 value = inverted;
28147 break;
28148
28149 case OPCODE_ADC: /* ADC <-> SBC */
28150 new_inst = OPCODE_SBC;
28151 value = inverted;
28152 break;
28153
28154 case OPCODE_SBC:
28155 new_inst = OPCODE_ADC;
28156 value = inverted;
28157 break;
28158
28159 /* We cannot do anything. */
28160 default:
28161 return FAIL;
28162 }
28163
28164 if (value == (unsigned) FAIL)
28165 return FAIL;
28166
28167 *instruction &= OPCODE_MASK;
28168 *instruction |= new_inst << DATA_OP_SHIFT;
28169 return value;
28170}
28171
28172/* Like negate_data_op, but for Thumb-2. */
28173
28174static unsigned int
28175thumb32_negate_data_op (offsetT *instruction, unsigned int value)
28176{
28177 int op, new_inst;
28178 int rd;
28179 unsigned int negated, inverted;
28180
28181 negated = encode_thumb32_immediate (-value);
28182 inverted = encode_thumb32_immediate (~value);
28183
28184 rd = (*instruction >> 8) & 0xf;
28185 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
28186 switch (op)
28187 {
28188 /* ADD <-> SUB. Includes CMP <-> CMN. */
28189 case T2_OPCODE_SUB:
28190 new_inst = T2_OPCODE_ADD;
28191 value = negated;
28192 break;
28193
28194 case T2_OPCODE_ADD:
28195 new_inst = T2_OPCODE_SUB;
28196 value = negated;
28197 break;
28198
28199 /* ORR <-> ORN. Includes MOV <-> MVN. */
28200 case T2_OPCODE_ORR:
28201 new_inst = T2_OPCODE_ORN;
28202 value = inverted;
28203 break;
28204
28205 case T2_OPCODE_ORN:
28206 new_inst = T2_OPCODE_ORR;
28207 value = inverted;
28208 break;
28209
28210 /* AND <-> BIC. TST has no inverted equivalent. */
28211 case T2_OPCODE_AND:
28212 new_inst = T2_OPCODE_BIC;
28213 if (rd == 15)
28214 value = FAIL;
28215 else
28216 value = inverted;
28217 break;
28218
28219 case T2_OPCODE_BIC:
28220 new_inst = T2_OPCODE_AND;
28221 value = inverted;
28222 break;
28223
28224 /* ADC <-> SBC */
28225 case T2_OPCODE_ADC:
28226 new_inst = T2_OPCODE_SBC;
28227 value = inverted;
28228 break;
28229
28230 case T2_OPCODE_SBC:
28231 new_inst = T2_OPCODE_ADC;
28232 value = inverted;
28233 break;
28234
28235 /* We cannot do anything. */
28236 default:
28237 return FAIL;
28238 }
28239
28240 if (value == (unsigned int)FAIL)
28241 return FAIL;
28242
28243 *instruction &= T2_OPCODE_MASK;
28244 *instruction |= new_inst << T2_DATA_OP_SHIFT;
28245 return value;
28246}
28247
28248/* Read a 32-bit thumb instruction from buf. */
28249
28250static unsigned long
28251get_thumb32_insn (char * buf)
28252{
28253 unsigned long insn;
28254 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
28255 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28256
28257 return insn;
28258}
28259
28260/* We usually want to set the low bit on the address of thumb function
28261 symbols. In particular .word foo - . should have the low bit set.
28262 Generic code tries to fold the difference of two symbols to
28263 a constant. Prevent this and force a relocation when the first symbols
28264 is a thumb function. */
28265
28266bfd_boolean
28267arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
28268{
28269 if (op == O_subtract
28270 && l->X_op == O_symbol
28271 && r->X_op == O_symbol
28272 && THUMB_IS_FUNC (l->X_add_symbol))
28273 {
28274 l->X_op = O_subtract;
28275 l->X_op_symbol = r->X_add_symbol;
28276 l->X_add_number -= r->X_add_number;
28277 return TRUE;
28278 }
28279
28280 /* Process as normal. */
28281 return FALSE;
28282}
28283
28284/* Encode Thumb2 unconditional branches and calls. The encoding
28285 for the 2 are identical for the immediate values. */
28286
28287static void
28288encode_thumb2_b_bl_offset (char * buf, offsetT value)
28289{
28290#define T2I1I2MASK ((1 << 13) | (1 << 11))
28291 offsetT newval;
28292 offsetT newval2;
28293 addressT S, I1, I2, lo, hi;
28294
28295 S = (value >> 24) & 0x01;
28296 I1 = (value >> 23) & 0x01;
28297 I2 = (value >> 22) & 0x01;
28298 hi = (value >> 12) & 0x3ff;
28299 lo = (value >> 1) & 0x7ff;
28300 newval = md_chars_to_number (buf, THUMB_SIZE);
28301 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28302 newval |= (S << 10) | hi;
28303 newval2 &= ~T2I1I2MASK;
28304 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
28305 md_number_to_chars (buf, newval, THUMB_SIZE);
28306 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28307}
28308
28309void
28310md_apply_fix (fixS * fixP,
28311 valueT * valP,
28312 segT seg)
28313{
28314 offsetT value = * valP;
28315 offsetT newval;
28316 unsigned int newimm;
28317 unsigned long temp;
28318 int sign;
28319 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
28320
28321 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
28322
28323 /* Note whether this will delete the relocation. */
28324
28325 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
28326 fixP->fx_done = 1;
28327
28328 /* On a 64-bit host, silently truncate 'value' to 32 bits for
28329 consistency with the behaviour on 32-bit hosts. Remember value
28330 for emit_reloc. */
28331 value &= 0xffffffff;
28332 value ^= 0x80000000;
28333 value -= 0x80000000;
28334
28335 *valP = value;
28336 fixP->fx_addnumber = value;
28337
28338 /* Same treatment for fixP->fx_offset. */
28339 fixP->fx_offset &= 0xffffffff;
28340 fixP->fx_offset ^= 0x80000000;
28341 fixP->fx_offset -= 0x80000000;
28342
28343 switch (fixP->fx_r_type)
28344 {
28345 case BFD_RELOC_NONE:
28346 /* This will need to go in the object file. */
28347 fixP->fx_done = 0;
28348 break;
28349
28350 case BFD_RELOC_ARM_IMMEDIATE:
28351 /* We claim that this fixup has been processed here,
28352 even if in fact we generate an error because we do
28353 not have a reloc for it, so tc_gen_reloc will reject it. */
28354 fixP->fx_done = 1;
28355
28356 if (fixP->fx_addsy)
28357 {
28358 const char *msg = 0;
28359
28360 if (! S_IS_DEFINED (fixP->fx_addsy))
28361 msg = _("undefined symbol %s used as an immediate value");
28362 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
28363 msg = _("symbol %s is in a different section");
28364 else if (S_IS_WEAK (fixP->fx_addsy))
28365 msg = _("symbol %s is weak and may be overridden later");
28366
28367 if (msg)
28368 {
28369 as_bad_where (fixP->fx_file, fixP->fx_line,
28370 msg, S_GET_NAME (fixP->fx_addsy));
28371 break;
28372 }
28373 }
28374
28375 temp = md_chars_to_number (buf, INSN_SIZE);
28376
28377 /* If the offset is negative, we should use encoding A2 for ADR. */
28378 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
28379 newimm = negate_data_op (&temp, value);
28380 else
28381 {
28382 newimm = encode_arm_immediate (value);
28383
28384 /* If the instruction will fail, see if we can fix things up by
28385 changing the opcode. */
28386 if (newimm == (unsigned int) FAIL)
28387 newimm = negate_data_op (&temp, value);
28388 /* MOV accepts both ARM modified immediate (A1 encoding) and
28389 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28390 When disassembling, MOV is preferred when there is no encoding
28391 overlap. */
28392 if (newimm == (unsigned int) FAIL
28393 && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
28394 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
28395 && !((temp >> SBIT_SHIFT) & 0x1)
28396 && value >= 0 && value <= 0xffff)
28397 {
28398 /* Clear bits[23:20] to change encoding from A1 to A2. */
28399 temp &= 0xff0fffff;
28400 /* Encoding high 4bits imm. Code below will encode the remaining
28401 low 12bits. */
28402 temp |= (value & 0x0000f000) << 4;
28403 newimm = value & 0x00000fff;
28404 }
28405 }
28406
28407 if (newimm == (unsigned int) FAIL)
28408 {
28409 as_bad_where (fixP->fx_file, fixP->fx_line,
28410 _("invalid constant (%lx) after fixup"),
28411 (unsigned long) value);
28412 break;
28413 }
28414
28415 newimm |= (temp & 0xfffff000);
28416 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
28417 break;
28418
28419 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
28420 {
28421 unsigned int highpart = 0;
28422 unsigned int newinsn = 0xe1a00000; /* nop. */
28423
28424 if (fixP->fx_addsy)
28425 {
28426 const char *msg = 0;
28427
28428 if (! S_IS_DEFINED (fixP->fx_addsy))
28429 msg = _("undefined symbol %s used as an immediate value");
28430 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
28431 msg = _("symbol %s is in a different section");
28432 else if (S_IS_WEAK (fixP->fx_addsy))
28433 msg = _("symbol %s is weak and may be overridden later");
28434
28435 if (msg)
28436 {
28437 as_bad_where (fixP->fx_file, fixP->fx_line,
28438 msg, S_GET_NAME (fixP->fx_addsy));
28439 break;
28440 }
28441 }
28442
28443 newimm = encode_arm_immediate (value);
28444 temp = md_chars_to_number (buf, INSN_SIZE);
28445
28446 /* If the instruction will fail, see if we can fix things up by
28447 changing the opcode. */
28448 if (newimm == (unsigned int) FAIL
28449 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
28450 {
28451 /* No ? OK - try using two ADD instructions to generate
28452 the value. */
28453 newimm = validate_immediate_twopart (value, & highpart);
28454
28455 /* Yes - then make sure that the second instruction is
28456 also an add. */
28457 if (newimm != (unsigned int) FAIL)
28458 newinsn = temp;
28459 /* Still No ? Try using a negated value. */
28460 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
28461 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
28462 /* Otherwise - give up. */
28463 else
28464 {
28465 as_bad_where (fixP->fx_file, fixP->fx_line,
28466 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28467 (long) value);
28468 break;
28469 }
28470
28471 /* Replace the first operand in the 2nd instruction (which
28472 is the PC) with the destination register. We have
28473 already added in the PC in the first instruction and we
28474 do not want to do it again. */
28475 newinsn &= ~ 0xf0000;
28476 newinsn |= ((newinsn & 0x0f000) << 4);
28477 }
28478
28479 newimm |= (temp & 0xfffff000);
28480 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
28481
28482 highpart |= (newinsn & 0xfffff000);
28483 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
28484 }
28485 break;
28486
28487 case BFD_RELOC_ARM_OFFSET_IMM:
28488 if (!fixP->fx_done && seg->use_rela_p)
28489 value = 0;
28490 /* Fall through. */
28491
28492 case BFD_RELOC_ARM_LITERAL:
28493 sign = value > 0;
28494
28495 if (value < 0)
28496 value = - value;
28497
28498 if (validate_offset_imm (value, 0) == FAIL)
28499 {
28500 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
28501 as_bad_where (fixP->fx_file, fixP->fx_line,
28502 _("invalid literal constant: pool needs to be closer"));
28503 else
28504 as_bad_where (fixP->fx_file, fixP->fx_line,
28505 _("bad immediate value for offset (%ld)"),
28506 (long) value);
28507 break;
28508 }
28509
28510 newval = md_chars_to_number (buf, INSN_SIZE);
28511 if (value == 0)
28512 newval &= 0xfffff000;
28513 else
28514 {
28515 newval &= 0xff7ff000;
28516 newval |= value | (sign ? INDEX_UP : 0);
28517 }
28518 md_number_to_chars (buf, newval, INSN_SIZE);
28519 break;
28520
28521 case BFD_RELOC_ARM_OFFSET_IMM8:
28522 case BFD_RELOC_ARM_HWLITERAL:
28523 sign = value > 0;
28524
28525 if (value < 0)
28526 value = - value;
28527
28528 if (validate_offset_imm (value, 1) == FAIL)
28529 {
28530 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
28531 as_bad_where (fixP->fx_file, fixP->fx_line,
28532 _("invalid literal constant: pool needs to be closer"));
28533 else
28534 as_bad_where (fixP->fx_file, fixP->fx_line,
28535 _("bad immediate value for 8-bit offset (%ld)"),
28536 (long) value);
28537 break;
28538 }
28539
28540 newval = md_chars_to_number (buf, INSN_SIZE);
28541 if (value == 0)
28542 newval &= 0xfffff0f0;
28543 else
28544 {
28545 newval &= 0xff7ff0f0;
28546 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
28547 }
28548 md_number_to_chars (buf, newval, INSN_SIZE);
28549 break;
28550
28551 case BFD_RELOC_ARM_T32_OFFSET_U8:
28552 if (value < 0 || value > 1020 || value % 4 != 0)
28553 as_bad_where (fixP->fx_file, fixP->fx_line,
28554 _("bad immediate value for offset (%ld)"), (long) value);
28555 value /= 4;
28556
28557 newval = md_chars_to_number (buf+2, THUMB_SIZE);
28558 newval |= value;
28559 md_number_to_chars (buf+2, newval, THUMB_SIZE);
28560 break;
28561
28562 case BFD_RELOC_ARM_T32_OFFSET_IMM:
28563 /* This is a complicated relocation used for all varieties of Thumb32
28564 load/store instruction with immediate offset:
28565
28566 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28567 *4, optional writeback(W)
28568 (doubleword load/store)
28569
28570 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28571 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28572 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28573 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28574 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28575
28576 Uppercase letters indicate bits that are already encoded at
28577 this point. Lowercase letters are our problem. For the
28578 second block of instructions, the secondary opcode nybble
28579 (bits 8..11) is present, and bit 23 is zero, even if this is
28580 a PC-relative operation. */
28581 newval = md_chars_to_number (buf, THUMB_SIZE);
28582 newval <<= 16;
28583 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
28584
28585 if ((newval & 0xf0000000) == 0xe0000000)
28586 {
28587 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28588 if (value >= 0)
28589 newval |= (1 << 23);
28590 else
28591 value = -value;
28592 if (value % 4 != 0)
28593 {
28594 as_bad_where (fixP->fx_file, fixP->fx_line,
28595 _("offset not a multiple of 4"));
28596 break;
28597 }
28598 value /= 4;
28599 if (value > 0xff)
28600 {
28601 as_bad_where (fixP->fx_file, fixP->fx_line,
28602 _("offset out of range"));
28603 break;
28604 }
28605 newval &= ~0xff;
28606 }
28607 else if ((newval & 0x000f0000) == 0x000f0000)
28608 {
28609 /* PC-relative, 12-bit offset. */
28610 if (value >= 0)
28611 newval |= (1 << 23);
28612 else
28613 value = -value;
28614 if (value > 0xfff)
28615 {
28616 as_bad_where (fixP->fx_file, fixP->fx_line,
28617 _("offset out of range"));
28618 break;
28619 }
28620 newval &= ~0xfff;
28621 }
28622 else if ((newval & 0x00000100) == 0x00000100)
28623 {
28624 /* Writeback: 8-bit, +/- offset. */
28625 if (value >= 0)
28626 newval |= (1 << 9);
28627 else
28628 value = -value;
28629 if (value > 0xff)
28630 {
28631 as_bad_where (fixP->fx_file, fixP->fx_line,
28632 _("offset out of range"));
28633 break;
28634 }
28635 newval &= ~0xff;
28636 }
28637 else if ((newval & 0x00000f00) == 0x00000e00)
28638 {
28639 /* T-instruction: positive 8-bit offset. */
28640 if (value < 0 || value > 0xff)
28641 {
28642 as_bad_where (fixP->fx_file, fixP->fx_line,
28643 _("offset out of range"));
28644 break;
28645 }
28646 newval &= ~0xff;
28647 newval |= value;
28648 }
28649 else
28650 {
28651 /* Positive 12-bit or negative 8-bit offset. */
28652 int limit;
28653 if (value >= 0)
28654 {
28655 newval |= (1 << 23);
28656 limit = 0xfff;
28657 }
28658 else
28659 {
28660 value = -value;
28661 limit = 0xff;
28662 }
28663 if (value > limit)
28664 {
28665 as_bad_where (fixP->fx_file, fixP->fx_line,
28666 _("offset out of range"));
28667 break;
28668 }
28669 newval &= ~limit;
28670 }
28671
28672 newval |= value;
28673 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
28674 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
28675 break;
28676
28677 case BFD_RELOC_ARM_SHIFT_IMM:
28678 newval = md_chars_to_number (buf, INSN_SIZE);
28679 if (((unsigned long) value) > 32
28680 || (value == 32
28681 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
28682 {
28683 as_bad_where (fixP->fx_file, fixP->fx_line,
28684 _("shift expression is too large"));
28685 break;
28686 }
28687
28688 if (value == 0)
28689 /* Shifts of zero must be done as lsl. */
28690 newval &= ~0x60;
28691 else if (value == 32)
28692 value = 0;
28693 newval &= 0xfffff07f;
28694 newval |= (value & 0x1f) << 7;
28695 md_number_to_chars (buf, newval, INSN_SIZE);
28696 break;
28697
28698 case BFD_RELOC_ARM_T32_IMMEDIATE:
28699 case BFD_RELOC_ARM_T32_ADD_IMM:
28700 case BFD_RELOC_ARM_T32_IMM12:
28701 case BFD_RELOC_ARM_T32_ADD_PC12:
28702 /* We claim that this fixup has been processed here,
28703 even if in fact we generate an error because we do
28704 not have a reloc for it, so tc_gen_reloc will reject it. */
28705 fixP->fx_done = 1;
28706
28707 if (fixP->fx_addsy
28708 && ! S_IS_DEFINED (fixP->fx_addsy))
28709 {
28710 as_bad_where (fixP->fx_file, fixP->fx_line,
28711 _("undefined symbol %s used as an immediate value"),
28712 S_GET_NAME (fixP->fx_addsy));
28713 break;
28714 }
28715
28716 newval = md_chars_to_number (buf, THUMB_SIZE);
28717 newval <<= 16;
28718 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
28719
28720 newimm = FAIL;
28721 if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
28722 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28723 Thumb2 modified immediate encoding (T2). */
28724 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
28725 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
28726 {
28727 newimm = encode_thumb32_immediate (value);
28728 if (newimm == (unsigned int) FAIL)
28729 newimm = thumb32_negate_data_op (&newval, value);
28730 }
28731 if (newimm == (unsigned int) FAIL)
28732 {
28733 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
28734 {
28735 /* Turn add/sum into addw/subw. */
28736 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
28737 newval = (newval & 0xfeffffff) | 0x02000000;
28738 /* No flat 12-bit imm encoding for addsw/subsw. */
28739 if ((newval & 0x00100000) == 0)
28740 {
28741 /* 12 bit immediate for addw/subw. */
28742 if (value < 0)
28743 {
28744 value = -value;
28745 newval ^= 0x00a00000;
28746 }
28747 if (value > 0xfff)
28748 newimm = (unsigned int) FAIL;
28749 else
28750 newimm = value;
28751 }
28752 }
28753 else
28754 {
28755 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28756 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28757 disassembling, MOV is preferred when there is no encoding
28758 overlap. */
28759 if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
28760 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28761 but with the Rn field [19:16] set to 1111. */
28762 && (((newval >> 16) & 0xf) == 0xf)
28763 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
28764 && !((newval >> T2_SBIT_SHIFT) & 0x1)
28765 && value >= 0 && value <= 0xffff)
28766 {
28767 /* Toggle bit[25] to change encoding from T2 to T3. */
28768 newval ^= 1 << 25;
28769 /* Clear bits[19:16]. */
28770 newval &= 0xfff0ffff;
28771 /* Encoding high 4bits imm. Code below will encode the
28772 remaining low 12bits. */
28773 newval |= (value & 0x0000f000) << 4;
28774 newimm = value & 0x00000fff;
28775 }
28776 }
28777 }
28778
28779 if (newimm == (unsigned int)FAIL)
28780 {
28781 as_bad_where (fixP->fx_file, fixP->fx_line,
28782 _("invalid constant (%lx) after fixup"),
28783 (unsigned long) value);
28784 break;
28785 }
28786
28787 newval |= (newimm & 0x800) << 15;
28788 newval |= (newimm & 0x700) << 4;
28789 newval |= (newimm & 0x0ff);
28790
28791 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
28792 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
28793 break;
28794
28795 case BFD_RELOC_ARM_SMC:
28796 if (((unsigned long) value) > 0xf)
28797 as_bad_where (fixP->fx_file, fixP->fx_line,
28798 _("invalid smc expression"));
28799
28800 newval = md_chars_to_number (buf, INSN_SIZE);
28801 newval |= (value & 0xf);
28802 md_number_to_chars (buf, newval, INSN_SIZE);
28803 break;
28804
28805 case BFD_RELOC_ARM_HVC:
28806 if (((unsigned long) value) > 0xffff)
28807 as_bad_where (fixP->fx_file, fixP->fx_line,
28808 _("invalid hvc expression"));
28809 newval = md_chars_to_number (buf, INSN_SIZE);
28810 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
28811 md_number_to_chars (buf, newval, INSN_SIZE);
28812 break;
28813
28814 case BFD_RELOC_ARM_SWI:
28815 if (fixP->tc_fix_data != 0)
28816 {
28817 if (((unsigned long) value) > 0xff)
28818 as_bad_where (fixP->fx_file, fixP->fx_line,
28819 _("invalid swi expression"));
28820 newval = md_chars_to_number (buf, THUMB_SIZE);
28821 newval |= value;
28822 md_number_to_chars (buf, newval, THUMB_SIZE);
28823 }
28824 else
28825 {
28826 if (((unsigned long) value) > 0x00ffffff)
28827 as_bad_where (fixP->fx_file, fixP->fx_line,
28828 _("invalid swi expression"));
28829 newval = md_chars_to_number (buf, INSN_SIZE);
28830 newval |= value;
28831 md_number_to_chars (buf, newval, INSN_SIZE);
28832 }
28833 break;
28834
28835 case BFD_RELOC_ARM_MULTI:
28836 if (((unsigned long) value) > 0xffff)
28837 as_bad_where (fixP->fx_file, fixP->fx_line,
28838 _("invalid expression in load/store multiple"));
28839 newval = value | md_chars_to_number (buf, INSN_SIZE);
28840 md_number_to_chars (buf, newval, INSN_SIZE);
28841 break;
28842
28843#ifdef OBJ_ELF
28844 case BFD_RELOC_ARM_PCREL_CALL:
28845
28846 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
28847 && fixP->fx_addsy
28848 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28849 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28850 && THUMB_IS_FUNC (fixP->fx_addsy))
28851 /* Flip the bl to blx. This is a simple flip
28852 bit here because we generate PCREL_CALL for
28853 unconditional bls. */
28854 {
28855 newval = md_chars_to_number (buf, INSN_SIZE);
28856 newval = newval | 0x10000000;
28857 md_number_to_chars (buf, newval, INSN_SIZE);
28858 temp = 1;
28859 fixP->fx_done = 1;
28860 }
28861 else
28862 temp = 3;
28863 goto arm_branch_common;
28864
28865 case BFD_RELOC_ARM_PCREL_JUMP:
28866 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
28867 && fixP->fx_addsy
28868 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28869 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28870 && THUMB_IS_FUNC (fixP->fx_addsy))
28871 {
28872 /* This would map to a bl<cond>, b<cond>,
28873 b<always> to a Thumb function. We
28874 need to force a relocation for this particular
28875 case. */
28876 newval = md_chars_to_number (buf, INSN_SIZE);
28877 fixP->fx_done = 0;
28878 }
28879 /* Fall through. */
28880
28881 case BFD_RELOC_ARM_PLT32:
28882#endif
28883 case BFD_RELOC_ARM_PCREL_BRANCH:
28884 temp = 3;
28885 goto arm_branch_common;
28886
28887 case BFD_RELOC_ARM_PCREL_BLX:
28888
28889 temp = 1;
28890 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
28891 && fixP->fx_addsy
28892 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28893 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28894 && ARM_IS_FUNC (fixP->fx_addsy))
28895 {
28896 /* Flip the blx to a bl and warn. */
28897 const char *name = S_GET_NAME (fixP->fx_addsy);
28898 newval = 0xeb000000;
28899 as_warn_where (fixP->fx_file, fixP->fx_line,
28900 _("blx to '%s' an ARM ISA state function changed to bl"),
28901 name);
28902 md_number_to_chars (buf, newval, INSN_SIZE);
28903 temp = 3;
28904 fixP->fx_done = 1;
28905 }
28906
28907#ifdef OBJ_ELF
28908 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
28909 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
28910#endif
28911
28912 arm_branch_common:
28913 /* We are going to store value (shifted right by two) in the
28914 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28915 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28916 also be clear. */
28917 if (value & temp)
28918 as_bad_where (fixP->fx_file, fixP->fx_line,
28919 _("misaligned branch destination"));
28920 if ((value & (offsetT)0xfe000000) != (offsetT)0
28921 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
28922 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
28923
28924 if (fixP->fx_done || !seg->use_rela_p)
28925 {
28926 newval = md_chars_to_number (buf, INSN_SIZE);
28927 newval |= (value >> 2) & 0x00ffffff;
28928 /* Set the H bit on BLX instructions. */
28929 if (temp == 1)
28930 {
28931 if (value & 2)
28932 newval |= 0x01000000;
28933 else
28934 newval &= ~0x01000000;
28935 }
28936 md_number_to_chars (buf, newval, INSN_SIZE);
28937 }
28938 break;
28939
28940 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
28941 /* CBZ can only branch forward. */
28942
28943 /* Attempts to use CBZ to branch to the next instruction
28944 (which, strictly speaking, are prohibited) will be turned into
28945 no-ops.
28946
28947 FIXME: It may be better to remove the instruction completely and
28948 perform relaxation. */
28949 if (value == -2)
28950 {
28951 newval = md_chars_to_number (buf, THUMB_SIZE);
28952 newval = 0xbf00; /* NOP encoding T1 */
28953 md_number_to_chars (buf, newval, THUMB_SIZE);
28954 }
28955 else
28956 {
28957 if (value & ~0x7e)
28958 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
28959
28960 if (fixP->fx_done || !seg->use_rela_p)
28961 {
28962 newval = md_chars_to_number (buf, THUMB_SIZE);
28963 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
28964 md_number_to_chars (buf, newval, THUMB_SIZE);
28965 }
28966 }
28967 break;
28968
28969 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
28970 if (out_of_range_p (value, 8))
28971 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
28972
28973 if (fixP->fx_done || !seg->use_rela_p)
28974 {
28975 newval = md_chars_to_number (buf, THUMB_SIZE);
28976 newval |= (value & 0x1ff) >> 1;
28977 md_number_to_chars (buf, newval, THUMB_SIZE);
28978 }
28979 break;
28980
28981 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
28982 if (out_of_range_p (value, 11))
28983 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
28984
28985 if (fixP->fx_done || !seg->use_rela_p)
28986 {
28987 newval = md_chars_to_number (buf, THUMB_SIZE);
28988 newval |= (value & 0xfff) >> 1;
28989 md_number_to_chars (buf, newval, THUMB_SIZE);
28990 }
28991 break;
28992
28993 /* This relocation is misnamed, it should be BRANCH21. */
28994 case BFD_RELOC_THUMB_PCREL_BRANCH20:
28995 if (fixP->fx_addsy
28996 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28997 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28998 && ARM_IS_FUNC (fixP->fx_addsy)
28999 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
29000 {
29001 /* Force a relocation for a branch 20 bits wide. */
29002 fixP->fx_done = 0;
29003 }
29004 if (out_of_range_p (value, 20))
29005 as_bad_where (fixP->fx_file, fixP->fx_line,
29006 _("conditional branch out of range"));
29007
29008 if (fixP->fx_done || !seg->use_rela_p)
29009 {
29010 offsetT newval2;
29011 addressT S, J1, J2, lo, hi;
29012
29013 S = (value & 0x00100000) >> 20;
29014 J2 = (value & 0x00080000) >> 19;
29015 J1 = (value & 0x00040000) >> 18;
29016 hi = (value & 0x0003f000) >> 12;
29017 lo = (value & 0x00000ffe) >> 1;
29018
29019 newval = md_chars_to_number (buf, THUMB_SIZE);
29020 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29021 newval |= (S << 10) | hi;
29022 newval2 |= (J1 << 13) | (J2 << 11) | lo;
29023 md_number_to_chars (buf, newval, THUMB_SIZE);
29024 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29025 }
29026 break;
29027
29028 case BFD_RELOC_THUMB_PCREL_BLX:
29029 /* If there is a blx from a thumb state function to
29030 another thumb function flip this to a bl and warn
29031 about it. */
29032
29033 if (fixP->fx_addsy
29034 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29035 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29036 && THUMB_IS_FUNC (fixP->fx_addsy))
29037 {
29038 const char *name = S_GET_NAME (fixP->fx_addsy);
29039 as_warn_where (fixP->fx_file, fixP->fx_line,
29040 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29041 name);
29042 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29043 newval = newval | 0x1000;
29044 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
29045 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
29046 fixP->fx_done = 1;
29047 }
29048
29049
29050 goto thumb_bl_common;
29051
29052 case BFD_RELOC_THUMB_PCREL_BRANCH23:
29053 /* A bl from Thumb state ISA to an internal ARM state function
29054 is converted to a blx. */
29055 if (fixP->fx_addsy
29056 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29057 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29058 && ARM_IS_FUNC (fixP->fx_addsy)
29059 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
29060 {
29061 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29062 newval = newval & ~0x1000;
29063 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
29064 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
29065 fixP->fx_done = 1;
29066 }
29067
29068 thumb_bl_common:
29069
29070 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
29071 /* For a BLX instruction, make sure that the relocation is rounded up
29072 to a word boundary. This follows the semantics of the instruction
29073 which specifies that bit 1 of the target address will come from bit
29074 1 of the base address. */
29075 value = (value + 3) & ~ 3;
29076
29077#ifdef OBJ_ELF
29078 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
29079 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
29080 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
29081#endif
29082
29083 if (out_of_range_p (value, 22))
29084 {
29085 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
29086 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
29087 else if (out_of_range_p (value, 24))
29088 as_bad_where (fixP->fx_file, fixP->fx_line,
29089 _("Thumb2 branch out of range"));
29090 }
29091
29092 if (fixP->fx_done || !seg->use_rela_p)
29093 encode_thumb2_b_bl_offset (buf, value);
29094
29095 break;
29096
29097 case BFD_RELOC_THUMB_PCREL_BRANCH25:
29098 if (out_of_range_p (value, 24))
29099 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
29100
29101 if (fixP->fx_done || !seg->use_rela_p)
29102 encode_thumb2_b_bl_offset (buf, value);
29103
29104 break;
29105
29106 case BFD_RELOC_8:
29107 if (fixP->fx_done || !seg->use_rela_p)
29108 *buf = value;
29109 break;
29110
29111 case BFD_RELOC_16:
29112 if (fixP->fx_done || !seg->use_rela_p)
29113 md_number_to_chars (buf, value, 2);
29114 break;
29115
29116#ifdef OBJ_ELF
29117 case BFD_RELOC_ARM_TLS_CALL:
29118 case BFD_RELOC_ARM_THM_TLS_CALL:
29119 case BFD_RELOC_ARM_TLS_DESCSEQ:
29120 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
29121 case BFD_RELOC_ARM_TLS_GOTDESC:
29122 case BFD_RELOC_ARM_TLS_GD32:
29123 case BFD_RELOC_ARM_TLS_LE32:
29124 case BFD_RELOC_ARM_TLS_IE32:
29125 case BFD_RELOC_ARM_TLS_LDM32:
29126 case BFD_RELOC_ARM_TLS_LDO32:
29127 S_SET_THREAD_LOCAL (fixP->fx_addsy);
29128 break;
29129
29130 /* Same handling as above, but with the arm_fdpic guard. */
29131 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
29132 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
29133 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
29134 if (arm_fdpic)
29135 {
29136 S_SET_THREAD_LOCAL (fixP->fx_addsy);
29137 }
29138 else
29139 {
29140 as_bad_where (fixP->fx_file, fixP->fx_line,
29141 _("Relocation supported only in FDPIC mode"));
29142 }
29143 break;
29144
29145 case BFD_RELOC_ARM_GOT32:
29146 case BFD_RELOC_ARM_GOTOFF:
29147 break;
29148
29149 case BFD_RELOC_ARM_GOT_PREL:
29150 if (fixP->fx_done || !seg->use_rela_p)
29151 md_number_to_chars (buf, value, 4);
29152 break;
29153
29154 case BFD_RELOC_ARM_TARGET2:
29155 /* TARGET2 is not partial-inplace, so we need to write the
29156 addend here for REL targets, because it won't be written out
29157 during reloc processing later. */
29158 if (fixP->fx_done || !seg->use_rela_p)
29159 md_number_to_chars (buf, fixP->fx_offset, 4);
29160 break;
29161
29162 /* Relocations for FDPIC. */
29163 case BFD_RELOC_ARM_GOTFUNCDESC:
29164 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
29165 case BFD_RELOC_ARM_FUNCDESC:
29166 if (arm_fdpic)
29167 {
29168 if (fixP->fx_done || !seg->use_rela_p)
29169 md_number_to_chars (buf, 0, 4);
29170 }
29171 else
29172 {
29173 as_bad_where (fixP->fx_file, fixP->fx_line,
29174 _("Relocation supported only in FDPIC mode"));
29175 }
29176 break;
29177#endif
29178
29179 case BFD_RELOC_RVA:
29180 case BFD_RELOC_32:
29181 case BFD_RELOC_ARM_TARGET1:
29182 case BFD_RELOC_ARM_ROSEGREL32:
29183 case BFD_RELOC_ARM_SBREL32:
29184 case BFD_RELOC_32_PCREL:
29185#ifdef TE_PE
29186 case BFD_RELOC_32_SECREL:
29187#endif
29188 if (fixP->fx_done || !seg->use_rela_p)
29189#ifdef TE_WINCE
29190 /* For WinCE we only do this for pcrel fixups. */
29191 if (fixP->fx_done || fixP->fx_pcrel)
29192#endif
29193 md_number_to_chars (buf, value, 4);
29194 break;
29195
29196#ifdef OBJ_ELF
29197 case BFD_RELOC_ARM_PREL31:
29198 if (fixP->fx_done || !seg->use_rela_p)
29199 {
29200 newval = md_chars_to_number (buf, 4) & 0x80000000;
29201 if ((value ^ (value >> 1)) & 0x40000000)
29202 {
29203 as_bad_where (fixP->fx_file, fixP->fx_line,
29204 _("rel31 relocation overflow"));
29205 }
29206 newval |= value & 0x7fffffff;
29207 md_number_to_chars (buf, newval, 4);
29208 }
29209 break;
29210#endif
29211
29212 case BFD_RELOC_ARM_CP_OFF_IMM:
29213 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
29214 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM:
29215 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
29216 newval = md_chars_to_number (buf, INSN_SIZE);
29217 else
29218 newval = get_thumb32_insn (buf);
29219 if ((newval & 0x0f200f00) == 0x0d000900)
29220 {
29221 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
29222 has permitted values that are multiples of 2, in the range 0
29223 to 510. */
29224 if (value < -510 || value > 510 || (value & 1))
29225 as_bad_where (fixP->fx_file, fixP->fx_line,
29226 _("co-processor offset out of range"));
29227 }
29228 else if ((newval & 0xfe001f80) == 0xec000f80)
29229 {
29230 if (value < -511 || value > 512 || (value & 3))
29231 as_bad_where (fixP->fx_file, fixP->fx_line,
29232 _("co-processor offset out of range"));
29233 }
29234 else if (value < -1023 || value > 1023 || (value & 3))
29235 as_bad_where (fixP->fx_file, fixP->fx_line,
29236 _("co-processor offset out of range"));
29237 cp_off_common:
29238 sign = value > 0;
29239 if (value < 0)
29240 value = -value;
29241 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
29242 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
29243 newval = md_chars_to_number (buf, INSN_SIZE);
29244 else
29245 newval = get_thumb32_insn (buf);
29246 if (value == 0)
29247 {
29248 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
29249 newval &= 0xffffff80;
29250 else
29251 newval &= 0xffffff00;
29252 }
29253 else
29254 {
29255 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
29256 newval &= 0xff7fff80;
29257 else
29258 newval &= 0xff7fff00;
29259 if ((newval & 0x0f200f00) == 0x0d000900)
29260 {
29261 /* This is a fp16 vstr/vldr.
29262
29263 It requires the immediate offset in the instruction is shifted
29264 left by 1 to be a half-word offset.
29265
29266 Here, left shift by 1 first, and later right shift by 2
29267 should get the right offset. */
29268 value <<= 1;
29269 }
29270 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
29271 }
29272 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
29273 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
29274 md_number_to_chars (buf, newval, INSN_SIZE);
29275 else
29276 put_thumb32_insn (buf, newval);
29277 break;
29278
29279 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
29280 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
29281 if (value < -255 || value > 255)
29282 as_bad_where (fixP->fx_file, fixP->fx_line,
29283 _("co-processor offset out of range"));
29284 value *= 4;
29285 goto cp_off_common;
29286
29287 case BFD_RELOC_ARM_THUMB_OFFSET:
29288 newval = md_chars_to_number (buf, THUMB_SIZE);
29289 /* Exactly what ranges, and where the offset is inserted depends
29290 on the type of instruction, we can establish this from the
29291 top 4 bits. */
29292 switch (newval >> 12)
29293 {
29294 case 4: /* PC load. */
29295 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29296 forced to zero for these loads; md_pcrel_from has already
29297 compensated for this. */
29298 if (value & 3)
29299 as_bad_where (fixP->fx_file, fixP->fx_line,
29300 _("invalid offset, target not word aligned (0x%08lX)"),
29301 (((unsigned long) fixP->fx_frag->fr_address
29302 + (unsigned long) fixP->fx_where) & ~3)
29303 + (unsigned long) value);
29304 else if (get_recorded_alignment (seg) < 2)
29305 as_warn_where (fixP->fx_file, fixP->fx_line,
29306 _("section does not have enough alignment to ensure safe PC-relative loads"));
29307
29308 if (value & ~0x3fc)
29309 as_bad_where (fixP->fx_file, fixP->fx_line,
29310 _("invalid offset, value too big (0x%08lX)"),
29311 (long) value);
29312
29313 newval |= value >> 2;
29314 break;
29315
29316 case 9: /* SP load/store. */
29317 if (value & ~0x3fc)
29318 as_bad_where (fixP->fx_file, fixP->fx_line,
29319 _("invalid offset, value too big (0x%08lX)"),
29320 (long) value);
29321 newval |= value >> 2;
29322 break;
29323
29324 case 6: /* Word load/store. */
29325 if (value & ~0x7c)
29326 as_bad_where (fixP->fx_file, fixP->fx_line,
29327 _("invalid offset, value too big (0x%08lX)"),
29328 (long) value);
29329 newval |= value << 4; /* 6 - 2. */
29330 break;
29331
29332 case 7: /* Byte load/store. */
29333 if (value & ~0x1f)
29334 as_bad_where (fixP->fx_file, fixP->fx_line,
29335 _("invalid offset, value too big (0x%08lX)"),
29336 (long) value);
29337 newval |= value << 6;
29338 break;
29339
29340 case 8: /* Halfword load/store. */
29341 if (value & ~0x3e)
29342 as_bad_where (fixP->fx_file, fixP->fx_line,
29343 _("invalid offset, value too big (0x%08lX)"),
29344 (long) value);
29345 newval |= value << 5; /* 6 - 1. */
29346 break;
29347
29348 default:
29349 as_bad_where (fixP->fx_file, fixP->fx_line,
29350 "Unable to process relocation for thumb opcode: %lx",
29351 (unsigned long) newval);
29352 break;
29353 }
29354 md_number_to_chars (buf, newval, THUMB_SIZE);
29355 break;
29356
29357 case BFD_RELOC_ARM_THUMB_ADD:
29358 /* This is a complicated relocation, since we use it for all of
29359 the following immediate relocations:
29360
29361 3bit ADD/SUB
29362 8bit ADD/SUB
29363 9bit ADD/SUB SP word-aligned
29364 10bit ADD PC/SP word-aligned
29365
29366 The type of instruction being processed is encoded in the
29367 instruction field:
29368
29369 0x8000 SUB
29370 0x00F0 Rd
29371 0x000F Rs
29372 */
29373 newval = md_chars_to_number (buf, THUMB_SIZE);
29374 {
29375 int rd = (newval >> 4) & 0xf;
29376 int rs = newval & 0xf;
29377 int subtract = !!(newval & 0x8000);
29378
29379 /* Check for HI regs, only very restricted cases allowed:
29380 Adjusting SP, and using PC or SP to get an address. */
29381 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
29382 || (rs > 7 && rs != REG_SP && rs != REG_PC))
29383 as_bad_where (fixP->fx_file, fixP->fx_line,
29384 _("invalid Hi register with immediate"));
29385
29386 /* If value is negative, choose the opposite instruction. */
29387 if (value < 0)
29388 {
29389 value = -value;
29390 subtract = !subtract;
29391 if (value < 0)
29392 as_bad_where (fixP->fx_file, fixP->fx_line,
29393 _("immediate value out of range"));
29394 }
29395
29396 if (rd == REG_SP)
29397 {
29398 if (value & ~0x1fc)
29399 as_bad_where (fixP->fx_file, fixP->fx_line,
29400 _("invalid immediate for stack address calculation"));
29401 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
29402 newval |= value >> 2;
29403 }
29404 else if (rs == REG_PC || rs == REG_SP)
29405 {
29406 /* PR gas/18541. If the addition is for a defined symbol
29407 within range of an ADR instruction then accept it. */
29408 if (subtract
29409 && value == 4
29410 && fixP->fx_addsy != NULL)
29411 {
29412 subtract = 0;
29413
29414 if (! S_IS_DEFINED (fixP->fx_addsy)
29415 || S_GET_SEGMENT (fixP->fx_addsy) != seg
29416 || S_IS_WEAK (fixP->fx_addsy))
29417 {
29418 as_bad_where (fixP->fx_file, fixP->fx_line,
29419 _("address calculation needs a strongly defined nearby symbol"));
29420 }
29421 else
29422 {
29423 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
29424
29425 /* Round up to the next 4-byte boundary. */
29426 if (v & 3)
29427 v = (v + 3) & ~ 3;
29428 else
29429 v += 4;
29430 v = S_GET_VALUE (fixP->fx_addsy) - v;
29431
29432 if (v & ~0x3fc)
29433 {
29434 as_bad_where (fixP->fx_file, fixP->fx_line,
29435 _("symbol too far away"));
29436 }
29437 else
29438 {
29439 fixP->fx_done = 1;
29440 value = v;
29441 }
29442 }
29443 }
29444
29445 if (subtract || value & ~0x3fc)
29446 as_bad_where (fixP->fx_file, fixP->fx_line,
29447 _("invalid immediate for address calculation (value = 0x%08lX)"),
29448 (unsigned long) (subtract ? - value : value));
29449 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
29450 newval |= rd << 8;
29451 newval |= value >> 2;
29452 }
29453 else if (rs == rd)
29454 {
29455 if (value & ~0xff)
29456 as_bad_where (fixP->fx_file, fixP->fx_line,
29457 _("immediate value out of range"));
29458 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
29459 newval |= (rd << 8) | value;
29460 }
29461 else
29462 {
29463 if (value & ~0x7)
29464 as_bad_where (fixP->fx_file, fixP->fx_line,
29465 _("immediate value out of range"));
29466 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
29467 newval |= rd | (rs << 3) | (value << 6);
29468 }
29469 }
29470 md_number_to_chars (buf, newval, THUMB_SIZE);
29471 break;
29472
29473 case BFD_RELOC_ARM_THUMB_IMM:
29474 newval = md_chars_to_number (buf, THUMB_SIZE);
29475 if (value < 0 || value > 255)
29476 as_bad_where (fixP->fx_file, fixP->fx_line,
29477 _("invalid immediate: %ld is out of range"),
29478 (long) value);
29479 newval |= value;
29480 md_number_to_chars (buf, newval, THUMB_SIZE);
29481 break;
29482
29483 case BFD_RELOC_ARM_THUMB_SHIFT:
29484 /* 5bit shift value (0..32). LSL cannot take 32. */
29485 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
29486 temp = newval & 0xf800;
29487 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
29488 as_bad_where (fixP->fx_file, fixP->fx_line,
29489 _("invalid shift value: %ld"), (long) value);
29490 /* Shifts of zero must be encoded as LSL. */
29491 if (value == 0)
29492 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
29493 /* Shifts of 32 are encoded as zero. */
29494 else if (value == 32)
29495 value = 0;
29496 newval |= value << 6;
29497 md_number_to_chars (buf, newval, THUMB_SIZE);
29498 break;
29499
29500 case BFD_RELOC_VTABLE_INHERIT:
29501 case BFD_RELOC_VTABLE_ENTRY:
29502 fixP->fx_done = 0;
29503 return;
29504
29505 case BFD_RELOC_ARM_MOVW:
29506 case BFD_RELOC_ARM_MOVT:
29507 case BFD_RELOC_ARM_THUMB_MOVW:
29508 case BFD_RELOC_ARM_THUMB_MOVT:
29509 if (fixP->fx_done || !seg->use_rela_p)
29510 {
29511 /* REL format relocations are limited to a 16-bit addend. */
29512 if (!fixP->fx_done)
29513 {
29514 if (value < -0x8000 || value > 0x7fff)
29515 as_bad_where (fixP->fx_file, fixP->fx_line,
29516 _("offset out of range"));
29517 }
29518 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
29519 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
29520 {
29521 value >>= 16;
29522 }
29523
29524 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
29525 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
29526 {
29527 newval = get_thumb32_insn (buf);
29528 newval &= 0xfbf08f00;
29529 newval |= (value & 0xf000) << 4;
29530 newval |= (value & 0x0800) << 15;
29531 newval |= (value & 0x0700) << 4;
29532 newval |= (value & 0x00ff);
29533 put_thumb32_insn (buf, newval);
29534 }
29535 else
29536 {
29537 newval = md_chars_to_number (buf, 4);
29538 newval &= 0xfff0f000;
29539 newval |= value & 0x0fff;
29540 newval |= (value & 0xf000) << 4;
29541 md_number_to_chars (buf, newval, 4);
29542 }
29543 }
29544 return;
29545
29546 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
29547 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
29548 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
29549 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
29550 gas_assert (!fixP->fx_done);
29551 {
29552 bfd_vma insn;
29553 bfd_boolean is_mov;
29554 bfd_vma encoded_addend = value;
29555
29556 /* Check that addend can be encoded in instruction. */
29557 if (!seg->use_rela_p && (value < 0 || value > 255))
29558 as_bad_where (fixP->fx_file, fixP->fx_line,
29559 _("the offset 0x%08lX is not representable"),
29560 (unsigned long) encoded_addend);
29561
29562 /* Extract the instruction. */
29563 insn = md_chars_to_number (buf, THUMB_SIZE);
29564 is_mov = (insn & 0xf800) == 0x2000;
29565
29566 /* Encode insn. */
29567 if (is_mov)
29568 {
29569 if (!seg->use_rela_p)
29570 insn |= encoded_addend;
29571 }
29572 else
29573 {
29574 int rd, rs;
29575
29576 /* Extract the instruction. */
29577 /* Encoding is the following
29578 0x8000 SUB
29579 0x00F0 Rd
29580 0x000F Rs
29581 */
29582 /* The following conditions must be true :
29583 - ADD
29584 - Rd == Rs
29585 - Rd <= 7
29586 */
29587 rd = (insn >> 4) & 0xf;
29588 rs = insn & 0xf;
29589 if ((insn & 0x8000) || (rd != rs) || rd > 7)
29590 as_bad_where (fixP->fx_file, fixP->fx_line,
29591 _("Unable to process relocation for thumb opcode: %lx"),
29592 (unsigned long) insn);
29593
29594 /* Encode as ADD immediate8 thumb 1 code. */
29595 insn = 0x3000 | (rd << 8);
29596
29597 /* Place the encoded addend into the first 8 bits of the
29598 instruction. */
29599 if (!seg->use_rela_p)
29600 insn |= encoded_addend;
29601 }
29602
29603 /* Update the instruction. */
29604 md_number_to_chars (buf, insn, THUMB_SIZE);
29605 }
29606 break;
29607
29608 case BFD_RELOC_ARM_ALU_PC_G0_NC:
29609 case BFD_RELOC_ARM_ALU_PC_G0:
29610 case BFD_RELOC_ARM_ALU_PC_G1_NC:
29611 case BFD_RELOC_ARM_ALU_PC_G1:
29612 case BFD_RELOC_ARM_ALU_PC_G2:
29613 case BFD_RELOC_ARM_ALU_SB_G0_NC:
29614 case BFD_RELOC_ARM_ALU_SB_G0:
29615 case BFD_RELOC_ARM_ALU_SB_G1_NC:
29616 case BFD_RELOC_ARM_ALU_SB_G1:
29617 case BFD_RELOC_ARM_ALU_SB_G2:
29618 gas_assert (!fixP->fx_done);
29619 if (!seg->use_rela_p)
29620 {
29621 bfd_vma insn;
29622 bfd_vma encoded_addend;
29623 bfd_vma addend_abs = llabs (value);
29624
29625 /* Check that the absolute value of the addend can be
29626 expressed as an 8-bit constant plus a rotation. */
29627 encoded_addend = encode_arm_immediate (addend_abs);
29628 if (encoded_addend == (unsigned int) FAIL)
29629 as_bad_where (fixP->fx_file, fixP->fx_line,
29630 _("the offset 0x%08lX is not representable"),
29631 (unsigned long) addend_abs);
29632
29633 /* Extract the instruction. */
29634 insn = md_chars_to_number (buf, INSN_SIZE);
29635
29636 /* If the addend is positive, use an ADD instruction.
29637 Otherwise use a SUB. Take care not to destroy the S bit. */
29638 insn &= 0xff1fffff;
29639 if (value < 0)
29640 insn |= 1 << 22;
29641 else
29642 insn |= 1 << 23;
29643
29644 /* Place the encoded addend into the first 12 bits of the
29645 instruction. */
29646 insn &= 0xfffff000;
29647 insn |= encoded_addend;
29648
29649 /* Update the instruction. */
29650 md_number_to_chars (buf, insn, INSN_SIZE);
29651 }
29652 break;
29653
29654 case BFD_RELOC_ARM_LDR_PC_G0:
29655 case BFD_RELOC_ARM_LDR_PC_G1:
29656 case BFD_RELOC_ARM_LDR_PC_G2:
29657 case BFD_RELOC_ARM_LDR_SB_G0:
29658 case BFD_RELOC_ARM_LDR_SB_G1:
29659 case BFD_RELOC_ARM_LDR_SB_G2:
29660 gas_assert (!fixP->fx_done);
29661 if (!seg->use_rela_p)
29662 {
29663 bfd_vma insn;
29664 bfd_vma addend_abs = llabs (value);
29665
29666 /* Check that the absolute value of the addend can be
29667 encoded in 12 bits. */
29668 if (addend_abs >= 0x1000)
29669 as_bad_where (fixP->fx_file, fixP->fx_line,
29670 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29671 (unsigned long) addend_abs);
29672
29673 /* Extract the instruction. */
29674 insn = md_chars_to_number (buf, INSN_SIZE);
29675
29676 /* If the addend is negative, clear bit 23 of the instruction.
29677 Otherwise set it. */
29678 if (value < 0)
29679 insn &= ~(1 << 23);
29680 else
29681 insn |= 1 << 23;
29682
29683 /* Place the absolute value of the addend into the first 12 bits
29684 of the instruction. */
29685 insn &= 0xfffff000;
29686 insn |= addend_abs;
29687
29688 /* Update the instruction. */
29689 md_number_to_chars (buf, insn, INSN_SIZE);
29690 }
29691 break;
29692
29693 case BFD_RELOC_ARM_LDRS_PC_G0:
29694 case BFD_RELOC_ARM_LDRS_PC_G1:
29695 case BFD_RELOC_ARM_LDRS_PC_G2:
29696 case BFD_RELOC_ARM_LDRS_SB_G0:
29697 case BFD_RELOC_ARM_LDRS_SB_G1:
29698 case BFD_RELOC_ARM_LDRS_SB_G2:
29699 gas_assert (!fixP->fx_done);
29700 if (!seg->use_rela_p)
29701 {
29702 bfd_vma insn;
29703 bfd_vma addend_abs = llabs (value);
29704
29705 /* Check that the absolute value of the addend can be
29706 encoded in 8 bits. */
29707 if (addend_abs >= 0x100)
29708 as_bad_where (fixP->fx_file, fixP->fx_line,
29709 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29710 (unsigned long) addend_abs);
29711
29712 /* Extract the instruction. */
29713 insn = md_chars_to_number (buf, INSN_SIZE);
29714
29715 /* If the addend is negative, clear bit 23 of the instruction.
29716 Otherwise set it. */
29717 if (value < 0)
29718 insn &= ~(1 << 23);
29719 else
29720 insn |= 1 << 23;
29721
29722 /* Place the first four bits of the absolute value of the addend
29723 into the first 4 bits of the instruction, and the remaining
29724 four into bits 8 .. 11. */
29725 insn &= 0xfffff0f0;
29726 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
29727
29728 /* Update the instruction. */
29729 md_number_to_chars (buf, insn, INSN_SIZE);
29730 }
29731 break;
29732
29733 case BFD_RELOC_ARM_LDC_PC_G0:
29734 case BFD_RELOC_ARM_LDC_PC_G1:
29735 case BFD_RELOC_ARM_LDC_PC_G2:
29736 case BFD_RELOC_ARM_LDC_SB_G0:
29737 case BFD_RELOC_ARM_LDC_SB_G1:
29738 case BFD_RELOC_ARM_LDC_SB_G2:
29739 gas_assert (!fixP->fx_done);
29740 if (!seg->use_rela_p)
29741 {
29742 bfd_vma insn;
29743 bfd_vma addend_abs = llabs (value);
29744
29745 /* Check that the absolute value of the addend is a multiple of
29746 four and, when divided by four, fits in 8 bits. */
29747 if (addend_abs & 0x3)
29748 as_bad_where (fixP->fx_file, fixP->fx_line,
29749 _("bad offset 0x%08lX (must be word-aligned)"),
29750 (unsigned long) addend_abs);
29751
29752 if ((addend_abs >> 2) > 0xff)
29753 as_bad_where (fixP->fx_file, fixP->fx_line,
29754 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29755 (unsigned long) addend_abs);
29756
29757 /* Extract the instruction. */
29758 insn = md_chars_to_number (buf, INSN_SIZE);
29759
29760 /* If the addend is negative, clear bit 23 of the instruction.
29761 Otherwise set it. */
29762 if (value < 0)
29763 insn &= ~(1 << 23);
29764 else
29765 insn |= 1 << 23;
29766
29767 /* Place the addend (divided by four) into the first eight
29768 bits of the instruction. */
29769 insn &= 0xfffffff0;
29770 insn |= addend_abs >> 2;
29771
29772 /* Update the instruction. */
29773 md_number_to_chars (buf, insn, INSN_SIZE);
29774 }
29775 break;
29776
29777 case BFD_RELOC_THUMB_PCREL_BRANCH5:
29778 if (fixP->fx_addsy
29779 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29780 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29781 && ARM_IS_FUNC (fixP->fx_addsy)
29782 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29783 {
29784 /* Force a relocation for a branch 5 bits wide. */
29785 fixP->fx_done = 0;
29786 }
29787 if (v8_1_branch_value_check (value, 5, FALSE) == FAIL)
29788 as_bad_where (fixP->fx_file, fixP->fx_line,
29789 BAD_BRANCH_OFF);
29790
29791 if (fixP->fx_done || !seg->use_rela_p)
29792 {
29793 addressT boff = value >> 1;
29794
29795 newval = md_chars_to_number (buf, THUMB_SIZE);
29796 newval |= (boff << 7);
29797 md_number_to_chars (buf, newval, THUMB_SIZE);
29798 }
29799 break;
29800
29801 case BFD_RELOC_THUMB_PCREL_BFCSEL:
29802 if (fixP->fx_addsy
29803 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29804 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29805 && ARM_IS_FUNC (fixP->fx_addsy)
29806 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29807 {
29808 fixP->fx_done = 0;
29809 }
29810 if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
29811 as_bad_where (fixP->fx_file, fixP->fx_line,
29812 _("branch out of range"));
29813
29814 if (fixP->fx_done || !seg->use_rela_p)
29815 {
29816 newval = md_chars_to_number (buf, THUMB_SIZE);
29817
29818 addressT boff = ((newval & 0x0780) >> 7) << 1;
29819 addressT diff = value - boff;
29820
29821 if (diff == 4)
29822 {
29823 newval |= 1 << 1; /* T bit. */
29824 }
29825 else if (diff != 2)
29826 {
29827 as_bad_where (fixP->fx_file, fixP->fx_line,
29828 _("out of range label-relative fixup value"));
29829 }
29830 md_number_to_chars (buf, newval, THUMB_SIZE);
29831 }
29832 break;
29833
29834 case BFD_RELOC_ARM_THUMB_BF17:
29835 if (fixP->fx_addsy
29836 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29837 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29838 && ARM_IS_FUNC (fixP->fx_addsy)
29839 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29840 {
29841 /* Force a relocation for a branch 17 bits wide. */
29842 fixP->fx_done = 0;
29843 }
29844
29845 if (v8_1_branch_value_check (value, 17, TRUE) == FAIL)
29846 as_bad_where (fixP->fx_file, fixP->fx_line,
29847 BAD_BRANCH_OFF);
29848
29849 if (fixP->fx_done || !seg->use_rela_p)
29850 {
29851 offsetT newval2;
29852 addressT immA, immB, immC;
29853
29854 immA = (value & 0x0001f000) >> 12;
29855 immB = (value & 0x00000ffc) >> 2;
29856 immC = (value & 0x00000002) >> 1;
29857
29858 newval = md_chars_to_number (buf, THUMB_SIZE);
29859 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29860 newval |= immA;
29861 newval2 |= (immC << 11) | (immB << 1);
29862 md_number_to_chars (buf, newval, THUMB_SIZE);
29863 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29864 }
29865 break;
29866
29867 case BFD_RELOC_ARM_THUMB_BF19:
29868 if (fixP->fx_addsy
29869 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29870 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29871 && ARM_IS_FUNC (fixP->fx_addsy)
29872 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29873 {
29874 /* Force a relocation for a branch 19 bits wide. */
29875 fixP->fx_done = 0;
29876 }
29877
29878 if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
29879 as_bad_where (fixP->fx_file, fixP->fx_line,
29880 BAD_BRANCH_OFF);
29881
29882 if (fixP->fx_done || !seg->use_rela_p)
29883 {
29884 offsetT newval2;
29885 addressT immA, immB, immC;
29886
29887 immA = (value & 0x0007f000) >> 12;
29888 immB = (value & 0x00000ffc) >> 2;
29889 immC = (value & 0x00000002) >> 1;
29890
29891 newval = md_chars_to_number (buf, THUMB_SIZE);
29892 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29893 newval |= immA;
29894 newval2 |= (immC << 11) | (immB << 1);
29895 md_number_to_chars (buf, newval, THUMB_SIZE);
29896 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29897 }
29898 break;
29899
29900 case BFD_RELOC_ARM_THUMB_BF13:
29901 if (fixP->fx_addsy
29902 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29903 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29904 && ARM_IS_FUNC (fixP->fx_addsy)
29905 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29906 {
29907 /* Force a relocation for a branch 13 bits wide. */
29908 fixP->fx_done = 0;
29909 }
29910
29911 if (v8_1_branch_value_check (value, 13, TRUE) == FAIL)
29912 as_bad_where (fixP->fx_file, fixP->fx_line,
29913 BAD_BRANCH_OFF);
29914
29915 if (fixP->fx_done || !seg->use_rela_p)
29916 {
29917 offsetT newval2;
29918 addressT immA, immB, immC;
29919
29920 immA = (value & 0x00001000) >> 12;
29921 immB = (value & 0x00000ffc) >> 2;
29922 immC = (value & 0x00000002) >> 1;
29923
29924 newval = md_chars_to_number (buf, THUMB_SIZE);
29925 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29926 newval |= immA;
29927 newval2 |= (immC << 11) | (immB << 1);
29928 md_number_to_chars (buf, newval, THUMB_SIZE);
29929 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29930 }
29931 break;
29932
29933 case BFD_RELOC_ARM_THUMB_LOOP12:
29934 if (fixP->fx_addsy
29935 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29936 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29937 && ARM_IS_FUNC (fixP->fx_addsy)
29938 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29939 {
29940 /* Force a relocation for a branch 12 bits wide. */
29941 fixP->fx_done = 0;
29942 }
29943
29944 bfd_vma insn = get_thumb32_insn (buf);
29945 /* le lr, <label>, le <label> or letp lr, <label> */
29946 if (((insn & 0xffffffff) == 0xf00fc001)
29947 || ((insn & 0xffffffff) == 0xf02fc001)
29948 || ((insn & 0xffffffff) == 0xf01fc001))
29949 value = -value;
29950
29951 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
29952 as_bad_where (fixP->fx_file, fixP->fx_line,
29953 BAD_BRANCH_OFF);
29954 if (fixP->fx_done || !seg->use_rela_p)
29955 {
29956 addressT imml, immh;
29957
29958 immh = (value & 0x00000ffc) >> 2;
29959 imml = (value & 0x00000002) >> 1;
29960
29961 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29962 newval |= (imml << 11) | (immh << 1);
29963 md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
29964 }
29965 break;
29966
29967 case BFD_RELOC_ARM_V4BX:
29968 /* This will need to go in the object file. */
29969 fixP->fx_done = 0;
29970 break;
29971
29972 case BFD_RELOC_UNUSED:
29973 default:
29974 as_bad_where (fixP->fx_file, fixP->fx_line,
29975 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
29976 }
29977}
29978
29979/* Translate internal representation of relocation info to BFD target
29980 format. */
29981
29982arelent *
29983tc_gen_reloc (asection *section, fixS *fixp)
29984{
29985 arelent * reloc;
29986 bfd_reloc_code_real_type code;
29987
29988 reloc = XNEW (arelent);
29989
29990 reloc->sym_ptr_ptr = XNEW (asymbol *);
29991 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
29992 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
29993
29994 if (fixp->fx_pcrel)
29995 {
29996 if (section->use_rela_p)
29997 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
29998 else
29999 fixp->fx_offset = reloc->address;
30000 }
30001 reloc->addend = fixp->fx_offset;
30002
30003 switch (fixp->fx_r_type)
30004 {
30005 case BFD_RELOC_8:
30006 if (fixp->fx_pcrel)
30007 {
30008 code = BFD_RELOC_8_PCREL;
30009 break;
30010 }
30011 /* Fall through. */
30012
30013 case BFD_RELOC_16:
30014 if (fixp->fx_pcrel)
30015 {
30016 code = BFD_RELOC_16_PCREL;
30017 break;
30018 }
30019 /* Fall through. */
30020
30021 case BFD_RELOC_32:
30022 if (fixp->fx_pcrel)
30023 {
30024 code = BFD_RELOC_32_PCREL;
30025 break;
30026 }
30027 /* Fall through. */
30028
30029 case BFD_RELOC_ARM_MOVW:
30030 if (fixp->fx_pcrel)
30031 {
30032 code = BFD_RELOC_ARM_MOVW_PCREL;
30033 break;
30034 }
30035 /* Fall through. */
30036
30037 case BFD_RELOC_ARM_MOVT:
30038 if (fixp->fx_pcrel)
30039 {
30040 code = BFD_RELOC_ARM_MOVT_PCREL;
30041 break;
30042 }
30043 /* Fall through. */
30044
30045 case BFD_RELOC_ARM_THUMB_MOVW:
30046 if (fixp->fx_pcrel)
30047 {
30048 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
30049 break;
30050 }
30051 /* Fall through. */
30052
30053 case BFD_RELOC_ARM_THUMB_MOVT:
30054 if (fixp->fx_pcrel)
30055 {
30056 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
30057 break;
30058 }
30059 /* Fall through. */
30060
30061 case BFD_RELOC_NONE:
30062 case BFD_RELOC_ARM_PCREL_BRANCH:
30063 case BFD_RELOC_ARM_PCREL_BLX:
30064 case BFD_RELOC_RVA:
30065 case BFD_RELOC_THUMB_PCREL_BRANCH7:
30066 case BFD_RELOC_THUMB_PCREL_BRANCH9:
30067 case BFD_RELOC_THUMB_PCREL_BRANCH12:
30068 case BFD_RELOC_THUMB_PCREL_BRANCH20:
30069 case BFD_RELOC_THUMB_PCREL_BRANCH23:
30070 case BFD_RELOC_THUMB_PCREL_BRANCH25:
30071 case BFD_RELOC_VTABLE_ENTRY:
30072 case BFD_RELOC_VTABLE_INHERIT:
30073#ifdef TE_PE
30074 case BFD_RELOC_32_SECREL:
30075#endif
30076 code = fixp->fx_r_type;
30077 break;
30078
30079 case BFD_RELOC_THUMB_PCREL_BLX:
30080#ifdef OBJ_ELF
30081 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
30082 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
30083 else
30084#endif
30085 code = BFD_RELOC_THUMB_PCREL_BLX;
30086 break;
30087
30088 case BFD_RELOC_ARM_LITERAL:
30089 case BFD_RELOC_ARM_HWLITERAL:
30090 /* If this is called then the a literal has
30091 been referenced across a section boundary. */
30092 as_bad_where (fixp->fx_file, fixp->fx_line,
30093 _("literal referenced across section boundary"));
30094 return NULL;
30095
30096#ifdef OBJ_ELF
30097 case BFD_RELOC_ARM_TLS_CALL:
30098 case BFD_RELOC_ARM_THM_TLS_CALL:
30099 case BFD_RELOC_ARM_TLS_DESCSEQ:
30100 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
30101 case BFD_RELOC_ARM_GOT32:
30102 case BFD_RELOC_ARM_GOTOFF:
30103 case BFD_RELOC_ARM_GOT_PREL:
30104 case BFD_RELOC_ARM_PLT32:
30105 case BFD_RELOC_ARM_TARGET1:
30106 case BFD_RELOC_ARM_ROSEGREL32:
30107 case BFD_RELOC_ARM_SBREL32:
30108 case BFD_RELOC_ARM_PREL31:
30109 case BFD_RELOC_ARM_TARGET2:
30110 case BFD_RELOC_ARM_TLS_LDO32:
30111 case BFD_RELOC_ARM_PCREL_CALL:
30112 case BFD_RELOC_ARM_PCREL_JUMP:
30113 case BFD_RELOC_ARM_ALU_PC_G0_NC:
30114 case BFD_RELOC_ARM_ALU_PC_G0:
30115 case BFD_RELOC_ARM_ALU_PC_G1_NC:
30116 case BFD_RELOC_ARM_ALU_PC_G1:
30117 case BFD_RELOC_ARM_ALU_PC_G2:
30118 case BFD_RELOC_ARM_LDR_PC_G0:
30119 case BFD_RELOC_ARM_LDR_PC_G1:
30120 case BFD_RELOC_ARM_LDR_PC_G2:
30121 case BFD_RELOC_ARM_LDRS_PC_G0:
30122 case BFD_RELOC_ARM_LDRS_PC_G1:
30123 case BFD_RELOC_ARM_LDRS_PC_G2:
30124 case BFD_RELOC_ARM_LDC_PC_G0:
30125 case BFD_RELOC_ARM_LDC_PC_G1:
30126 case BFD_RELOC_ARM_LDC_PC_G2:
30127 case BFD_RELOC_ARM_ALU_SB_G0_NC:
30128 case BFD_RELOC_ARM_ALU_SB_G0:
30129 case BFD_RELOC_ARM_ALU_SB_G1_NC:
30130 case BFD_RELOC_ARM_ALU_SB_G1:
30131 case BFD_RELOC_ARM_ALU_SB_G2:
30132 case BFD_RELOC_ARM_LDR_SB_G0:
30133 case BFD_RELOC_ARM_LDR_SB_G1:
30134 case BFD_RELOC_ARM_LDR_SB_G2:
30135 case BFD_RELOC_ARM_LDRS_SB_G0:
30136 case BFD_RELOC_ARM_LDRS_SB_G1:
30137 case BFD_RELOC_ARM_LDRS_SB_G2:
30138 case BFD_RELOC_ARM_LDC_SB_G0:
30139 case BFD_RELOC_ARM_LDC_SB_G1:
30140 case BFD_RELOC_ARM_LDC_SB_G2:
30141 case BFD_RELOC_ARM_V4BX:
30142 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
30143 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
30144 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
30145 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
30146 case BFD_RELOC_ARM_GOTFUNCDESC:
30147 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
30148 case BFD_RELOC_ARM_FUNCDESC:
30149 case BFD_RELOC_ARM_THUMB_BF17:
30150 case BFD_RELOC_ARM_THUMB_BF19:
30151 case BFD_RELOC_ARM_THUMB_BF13:
30152 code = fixp->fx_r_type;
30153 break;
30154
30155 case BFD_RELOC_ARM_TLS_GOTDESC:
30156 case BFD_RELOC_ARM_TLS_GD32:
30157 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
30158 case BFD_RELOC_ARM_TLS_LE32:
30159 case BFD_RELOC_ARM_TLS_IE32:
30160 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
30161 case BFD_RELOC_ARM_TLS_LDM32:
30162 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
30163 /* BFD will include the symbol's address in the addend.
30164 But we don't want that, so subtract it out again here. */
30165 if (!S_IS_COMMON (fixp->fx_addsy))
30166 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
30167 code = fixp->fx_r_type;
30168 break;
30169#endif
30170
30171 case BFD_RELOC_ARM_IMMEDIATE:
30172 as_bad_where (fixp->fx_file, fixp->fx_line,
30173 _("internal relocation (type: IMMEDIATE) not fixed up"));
30174 return NULL;
30175
30176 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
30177 as_bad_where (fixp->fx_file, fixp->fx_line,
30178 _("ADRL used for a symbol not defined in the same file"));
30179 return NULL;
30180
30181 case BFD_RELOC_THUMB_PCREL_BRANCH5:
30182 case BFD_RELOC_THUMB_PCREL_BFCSEL:
30183 case BFD_RELOC_ARM_THUMB_LOOP12:
30184 as_bad_where (fixp->fx_file, fixp->fx_line,
30185 _("%s used for a symbol not defined in the same file"),
30186 bfd_get_reloc_code_name (fixp->fx_r_type));
30187 return NULL;
30188
30189 case BFD_RELOC_ARM_OFFSET_IMM:
30190 if (section->use_rela_p)
30191 {
30192 code = fixp->fx_r_type;
30193 break;
30194 }
30195
30196 if (fixp->fx_addsy != NULL
30197 && !S_IS_DEFINED (fixp->fx_addsy)
30198 && S_IS_LOCAL (fixp->fx_addsy))
30199 {
30200 as_bad_where (fixp->fx_file, fixp->fx_line,
30201 _("undefined local label `%s'"),
30202 S_GET_NAME (fixp->fx_addsy));
30203 return NULL;
30204 }
30205
30206 as_bad_where (fixp->fx_file, fixp->fx_line,
30207 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30208 return NULL;
30209
30210 default:
30211 {
30212 const char * type;
30213
30214 switch (fixp->fx_r_type)
30215 {
30216 case BFD_RELOC_NONE: type = "NONE"; break;
30217 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
30218 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
30219 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
30220 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
30221 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
30222 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
30223 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
30224 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
30225 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
30226 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
30227 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
30228 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
30229 default: type = _("<unknown>"); break;
30230 }
30231 as_bad_where (fixp->fx_file, fixp->fx_line,
30232 _("cannot represent %s relocation in this object file format"),
30233 type);
30234 return NULL;
30235 }
30236 }
30237
30238#ifdef OBJ_ELF
30239 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
30240 && GOT_symbol
30241 && fixp->fx_addsy == GOT_symbol)
30242 {
30243 code = BFD_RELOC_ARM_GOTPC;
30244 reloc->addend = fixp->fx_offset = reloc->address;
30245 }
30246#endif
30247
30248 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
30249
30250 if (reloc->howto == NULL)
30251 {
30252 as_bad_where (fixp->fx_file, fixp->fx_line,
30253 _("cannot represent %s relocation in this object file format"),
30254 bfd_get_reloc_code_name (code));
30255 return NULL;
30256 }
30257
30258 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30259 vtable entry to be used in the relocation's section offset. */
30260 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
30261 reloc->address = fixp->fx_offset;
30262
30263 return reloc;
30264}
30265
30266/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
30267
30268void
30269cons_fix_new_arm (fragS * frag,
30270 int where,
30271 int size,
30272 expressionS * exp,
30273 bfd_reloc_code_real_type reloc)
30274{
30275 int pcrel = 0;
30276
30277 /* Pick a reloc.
30278 FIXME: @@ Should look at CPU word size. */
30279 switch (size)
30280 {
30281 case 1:
30282 reloc = BFD_RELOC_8;
30283 break;
30284 case 2:
30285 reloc = BFD_RELOC_16;
30286 break;
30287 case 4:
30288 default:
30289 reloc = BFD_RELOC_32;
30290 break;
30291 case 8:
30292 reloc = BFD_RELOC_64;
30293 break;
30294 }
30295
30296#ifdef TE_PE
30297 if (exp->X_op == O_secrel)
30298 {
30299 exp->X_op = O_symbol;
30300 reloc = BFD_RELOC_32_SECREL;
30301 }
30302#endif
30303
30304 fix_new_exp (frag, where, size, exp, pcrel, reloc);
30305}
30306
30307#if defined (OBJ_COFF)
30308void
30309arm_validate_fix (fixS * fixP)
30310{
30311 /* If the destination of the branch is a defined symbol which does not have
30312 the THUMB_FUNC attribute, then we must be calling a function which has
30313 the (interfacearm) attribute. We look for the Thumb entry point to that
30314 function and change the branch to refer to that function instead. */
30315 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
30316 && fixP->fx_addsy != NULL
30317 && S_IS_DEFINED (fixP->fx_addsy)
30318 && ! THUMB_IS_FUNC (fixP->fx_addsy))
30319 {
30320 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
30321 }
30322}
30323#endif
30324
30325
30326int
30327arm_force_relocation (struct fix * fixp)
30328{
30329#if defined (OBJ_COFF) && defined (TE_PE)
30330 if (fixp->fx_r_type == BFD_RELOC_RVA)
30331 return 1;
30332#endif
30333
30334 /* In case we have a call or a branch to a function in ARM ISA mode from
30335 a thumb function or vice-versa force the relocation. These relocations
30336 are cleared off for some cores that might have blx and simple transformations
30337 are possible. */
30338
30339#ifdef OBJ_ELF
30340 switch (fixp->fx_r_type)
30341 {
30342 case BFD_RELOC_ARM_PCREL_JUMP:
30343 case BFD_RELOC_ARM_PCREL_CALL:
30344 case BFD_RELOC_THUMB_PCREL_BLX:
30345 if (THUMB_IS_FUNC (fixp->fx_addsy))
30346 return 1;
30347 break;
30348
30349 case BFD_RELOC_ARM_PCREL_BLX:
30350 case BFD_RELOC_THUMB_PCREL_BRANCH25:
30351 case BFD_RELOC_THUMB_PCREL_BRANCH20:
30352 case BFD_RELOC_THUMB_PCREL_BRANCH23:
30353 if (ARM_IS_FUNC (fixp->fx_addsy))
30354 return 1;
30355 break;
30356
30357 default:
30358 break;
30359 }
30360#endif
30361
30362 /* Resolve these relocations even if the symbol is extern or weak.
30363 Technically this is probably wrong due to symbol preemption.
30364 In practice these relocations do not have enough range to be useful
30365 at dynamic link time, and some code (e.g. in the Linux kernel)
30366 expects these references to be resolved. */
30367 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
30368 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
30369 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
30370 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
30371 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
30372 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
30373 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
30374 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH12
30375 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
30376 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
30377 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
30378 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
30379 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
30380 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
30381 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
30382 return 0;
30383
30384 /* Always leave these relocations for the linker. */
30385 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
30386 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
30387 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
30388 return 1;
30389
30390 /* Always generate relocations against function symbols. */
30391 if (fixp->fx_r_type == BFD_RELOC_32
30392 && fixp->fx_addsy
30393 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
30394 return 1;
30395
30396 return generic_force_reloc (fixp);
30397}
30398
30399#if defined (OBJ_ELF) || defined (OBJ_COFF)
30400/* Relocations against function names must be left unadjusted,
30401 so that the linker can use this information to generate interworking
30402 stubs. The MIPS version of this function
30403 also prevents relocations that are mips-16 specific, but I do not
30404 know why it does this.
30405
30406 FIXME:
30407 There is one other problem that ought to be addressed here, but
30408 which currently is not: Taking the address of a label (rather
30409 than a function) and then later jumping to that address. Such
30410 addresses also ought to have their bottom bit set (assuming that
30411 they reside in Thumb code), but at the moment they will not. */
30412
30413bfd_boolean
30414arm_fix_adjustable (fixS * fixP)
30415{
30416 if (fixP->fx_addsy == NULL)
30417 return 1;
30418
30419 /* Preserve relocations against symbols with function type. */
30420 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
30421 return FALSE;
30422
30423 if (THUMB_IS_FUNC (fixP->fx_addsy)
30424 && fixP->fx_subsy == NULL)
30425 return FALSE;
30426
30427 /* We need the symbol name for the VTABLE entries. */
30428 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
30429 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
30430 return FALSE;
30431
30432 /* Don't allow symbols to be discarded on GOT related relocs. */
30433 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
30434 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
30435 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
30436 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
30437 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC
30438 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
30439 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
30440 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC
30441 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
30442 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC
30443 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
30444 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
30445 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
30446 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
30447 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
30448 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
30449 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
30450 return FALSE;
30451
30452 /* Similarly for group relocations. */
30453 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
30454 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
30455 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
30456 return FALSE;
30457
30458 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
30459 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
30460 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
30461 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
30462 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
30463 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
30464 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
30465 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
30466 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
30467 return FALSE;
30468
30469 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30470 offsets, so keep these symbols. */
30471 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30472 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
30473 return FALSE;
30474
30475 return TRUE;
30476}
30477#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30478
30479#ifdef OBJ_ELF
30480const char *
30481elf32_arm_target_format (void)
30482{
30483#ifdef TE_SYMBIAN
30484 return (target_big_endian
30485 ? "elf32-bigarm-symbian"
30486 : "elf32-littlearm-symbian");
30487#elif defined (TE_VXWORKS)
30488 return (target_big_endian
30489 ? "elf32-bigarm-vxworks"
30490 : "elf32-littlearm-vxworks");
30491#elif defined (TE_NACL)
30492 return (target_big_endian
30493 ? "elf32-bigarm-nacl"
30494 : "elf32-littlearm-nacl");
30495#else
30496 if (arm_fdpic)
30497 {
30498 if (target_big_endian)
30499 return "elf32-bigarm-fdpic";
30500 else
30501 return "elf32-littlearm-fdpic";
30502 }
30503 else
30504 {
30505 if (target_big_endian)
30506 return "elf32-bigarm";
30507 else
30508 return "elf32-littlearm";
30509 }
30510#endif
30511}
30512
30513void
30514armelf_frob_symbol (symbolS * symp,
30515 int * puntp)
30516{
30517 elf_frob_symbol (symp, puntp);
30518}
30519#endif
30520
30521/* MD interface: Finalization. */
30522
30523void
30524arm_cleanup (void)
30525{
30526 literal_pool * pool;
30527
30528 /* Ensure that all the predication blocks are properly closed. */
30529 check_pred_blocks_finished ();
30530
30531 for (pool = list_of_pools; pool; pool = pool->next)
30532 {
30533 /* Put it at the end of the relevant section. */
30534 subseg_set (pool->section, pool->sub_section);
30535#ifdef OBJ_ELF
30536 arm_elf_change_section ();
30537#endif
30538 s_ltorg (0);
30539 }
30540}
30541
30542#ifdef OBJ_ELF
30543/* Remove any excess mapping symbols generated for alignment frags in
30544 SEC. We may have created a mapping symbol before a zero byte
30545 alignment; remove it if there's a mapping symbol after the
30546 alignment. */
30547static void
30548check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
30549 void *dummy ATTRIBUTE_UNUSED)
30550{
30551 segment_info_type *seginfo = seg_info (sec);
30552 fragS *fragp;
30553
30554 if (seginfo == NULL || seginfo->frchainP == NULL)
30555 return;
30556
30557 for (fragp = seginfo->frchainP->frch_root;
30558 fragp != NULL;
30559 fragp = fragp->fr_next)
30560 {
30561 symbolS *sym = fragp->tc_frag_data.last_map;
30562 fragS *next = fragp->fr_next;
30563
30564 /* Variable-sized frags have been converted to fixed size by
30565 this point. But if this was variable-sized to start with,
30566 there will be a fixed-size frag after it. So don't handle
30567 next == NULL. */
30568 if (sym == NULL || next == NULL)
30569 continue;
30570
30571 if (S_GET_VALUE (sym) < next->fr_address)
30572 /* Not at the end of this frag. */
30573 continue;
30574 know (S_GET_VALUE (sym) == next->fr_address);
30575
30576 do
30577 {
30578 if (next->tc_frag_data.first_map != NULL)
30579 {
30580 /* Next frag starts with a mapping symbol. Discard this
30581 one. */
30582 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
30583 break;
30584 }
30585
30586 if (next->fr_next == NULL)
30587 {
30588 /* This mapping symbol is at the end of the section. Discard
30589 it. */
30590 know (next->fr_fix == 0 && next->fr_var == 0);
30591 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
30592 break;
30593 }
30594
30595 /* As long as we have empty frags without any mapping symbols,
30596 keep looking. */
30597 /* If the next frag is non-empty and does not start with a
30598 mapping symbol, then this mapping symbol is required. */
30599 if (next->fr_address != next->fr_next->fr_address)
30600 break;
30601
30602 next = next->fr_next;
30603 }
30604 while (next != NULL);
30605 }
30606}
30607#endif
30608
30609/* Adjust the symbol table. This marks Thumb symbols as distinct from
30610 ARM ones. */
30611
30612void
30613arm_adjust_symtab (void)
30614{
30615#ifdef OBJ_COFF
30616 symbolS * sym;
30617
30618 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
30619 {
30620 if (ARM_IS_THUMB (sym))
30621 {
30622 if (THUMB_IS_FUNC (sym))
30623 {
30624 /* Mark the symbol as a Thumb function. */
30625 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
30626 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
30627 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
30628
30629 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
30630 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
30631 else
30632 as_bad (_("%s: unexpected function type: %d"),
30633 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
30634 }
30635 else switch (S_GET_STORAGE_CLASS (sym))
30636 {
30637 case C_EXT:
30638 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
30639 break;
30640 case C_STAT:
30641 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
30642 break;
30643 case C_LABEL:
30644 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
30645 break;
30646 default:
30647 /* Do nothing. */
30648 break;
30649 }
30650 }
30651
30652 if (ARM_IS_INTERWORK (sym))
30653 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
30654 }
30655#endif
30656#ifdef OBJ_ELF
30657 symbolS * sym;
30658 char bind;
30659
30660 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
30661 {
30662 if (ARM_IS_THUMB (sym))
30663 {
30664 elf_symbol_type * elf_sym;
30665
30666 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
30667 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
30668
30669 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
30670 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
30671 {
30672 /* If it's a .thumb_func, declare it as so,
30673 otherwise tag label as .code 16. */
30674 if (THUMB_IS_FUNC (sym))
30675 ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
30676 ST_BRANCH_TO_THUMB);
30677 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
30678 elf_sym->internal_elf_sym.st_info =
30679 ELF_ST_INFO (bind, STT_ARM_16BIT);
30680 }
30681 }
30682 }
30683
30684 /* Remove any overlapping mapping symbols generated by alignment frags. */
30685 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
30686 /* Now do generic ELF adjustments. */
30687 elf_adjust_symtab ();
30688#endif
30689}
30690
30691/* MD interface: Initialization. */
30692
30693static void
30694set_constant_flonums (void)
30695{
30696 int i;
30697
30698 for (i = 0; i < NUM_FLOAT_VALS; i++)
30699 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
30700 abort ();
30701}
30702
30703/* Auto-select Thumb mode if it's the only available instruction set for the
30704 given architecture. */
30705
30706static void
30707autoselect_thumb_from_cpu_variant (void)
30708{
30709 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
30710 opcode_select (16);
30711}
30712
30713void
30714md_begin (void)
30715{
30716 unsigned mach;
30717 unsigned int i;
30718
30719 if ( (arm_ops_hsh = hash_new ()) == NULL
30720 || (arm_cond_hsh = hash_new ()) == NULL
30721 || (arm_vcond_hsh = hash_new ()) == NULL
30722 || (arm_shift_hsh = hash_new ()) == NULL
30723 || (arm_psr_hsh = hash_new ()) == NULL
30724 || (arm_v7m_psr_hsh = hash_new ()) == NULL
30725 || (arm_reg_hsh = hash_new ()) == NULL
30726 || (arm_reloc_hsh = hash_new ()) == NULL
30727 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
30728 as_fatal (_("virtual memory exhausted"));
30729
30730 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
30731 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
30732 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
30733 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
30734 for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++)
30735 hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i));
30736 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
30737 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
30738 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
30739 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
30740 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
30741 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
30742 (void *) (v7m_psrs + i));
30743 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
30744 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
30745 for (i = 0;
30746 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
30747 i++)
30748 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
30749 (void *) (barrier_opt_names + i));
30750#ifdef OBJ_ELF
30751 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
30752 {
30753 struct reloc_entry * entry = reloc_names + i;
30754
30755 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
30756 /* This makes encode_branch() use the EABI versions of this relocation. */
30757 entry->reloc = BFD_RELOC_UNUSED;
30758
30759 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
30760 }
30761#endif
30762
30763 set_constant_flonums ();
30764
30765 /* Set the cpu variant based on the command-line options. We prefer
30766 -mcpu= over -march= if both are set (as for GCC); and we prefer
30767 -mfpu= over any other way of setting the floating point unit.
30768 Use of legacy options with new options are faulted. */
30769 if (legacy_cpu)
30770 {
30771 if (mcpu_cpu_opt || march_cpu_opt)
30772 as_bad (_("use of old and new-style options to set CPU type"));
30773
30774 selected_arch = *legacy_cpu;
30775 }
30776 else if (mcpu_cpu_opt)
30777 {
30778 selected_arch = *mcpu_cpu_opt;
30779 selected_ext = *mcpu_ext_opt;
30780 }
30781 else if (march_cpu_opt)
30782 {
30783 selected_arch = *march_cpu_opt;
30784 selected_ext = *march_ext_opt;
30785 }
30786 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
30787
30788 if (legacy_fpu)
30789 {
30790 if (mfpu_opt)
30791 as_bad (_("use of old and new-style options to set FPU type"));
30792
30793 selected_fpu = *legacy_fpu;
30794 }
30795 else if (mfpu_opt)
30796 selected_fpu = *mfpu_opt;
30797 else
30798 {
30799#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30800 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30801 /* Some environments specify a default FPU. If they don't, infer it
30802 from the processor. */
30803 if (mcpu_fpu_opt)
30804 selected_fpu = *mcpu_fpu_opt;
30805 else if (march_fpu_opt)
30806 selected_fpu = *march_fpu_opt;
30807#else
30808 selected_fpu = fpu_default;
30809#endif
30810 }
30811
30812 if (ARM_FEATURE_ZERO (selected_fpu))
30813 {
30814 if (!no_cpu_selected ())
30815 selected_fpu = fpu_default;
30816 else
30817 selected_fpu = fpu_arch_fpa;
30818 }
30819
30820#ifdef CPU_DEFAULT
30821 if (ARM_FEATURE_ZERO (selected_arch))
30822 {
30823 selected_arch = cpu_default;
30824 selected_cpu = selected_arch;
30825 }
30826 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
30827#else
30828 /* Autodection of feature mode: allow all features in cpu_variant but leave
30829 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30830 after all instruction have been processed and we can decide what CPU
30831 should be selected. */
30832 if (ARM_FEATURE_ZERO (selected_arch))
30833 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
30834 else
30835 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
30836#endif
30837
30838 autoselect_thumb_from_cpu_variant ();
30839
30840 arm_arch_used = thumb_arch_used = arm_arch_none;
30841
30842#if defined OBJ_COFF || defined OBJ_ELF
30843 {
30844 unsigned int flags = 0;
30845
30846#if defined OBJ_ELF
30847 flags = meabi_flags;
30848
30849 switch (meabi_flags)
30850 {
30851 case EF_ARM_EABI_UNKNOWN:
30852#endif
30853 /* Set the flags in the private structure. */
30854 if (uses_apcs_26) flags |= F_APCS26;
30855 if (support_interwork) flags |= F_INTERWORK;
30856 if (uses_apcs_float) flags |= F_APCS_FLOAT;
30857 if (pic_code) flags |= F_PIC;
30858 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
30859 flags |= F_SOFT_FLOAT;
30860
30861 switch (mfloat_abi_opt)
30862 {
30863 case ARM_FLOAT_ABI_SOFT:
30864 case ARM_FLOAT_ABI_SOFTFP:
30865 flags |= F_SOFT_FLOAT;
30866 break;
30867
30868 case ARM_FLOAT_ABI_HARD:
30869 if (flags & F_SOFT_FLOAT)
30870 as_bad (_("hard-float conflicts with specified fpu"));
30871 break;
30872 }
30873
30874 /* Using pure-endian doubles (even if soft-float). */
30875 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
30876 flags |= F_VFP_FLOAT;
30877
30878#if defined OBJ_ELF
30879 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
30880 flags |= EF_ARM_MAVERICK_FLOAT;
30881 break;
30882
30883 case EF_ARM_EABI_VER4:
30884 case EF_ARM_EABI_VER5:
30885 /* No additional flags to set. */
30886 break;
30887
30888 default:
30889 abort ();
30890 }
30891#endif
30892 bfd_set_private_flags (stdoutput, flags);
30893
30894 /* We have run out flags in the COFF header to encode the
30895 status of ATPCS support, so instead we create a dummy,
30896 empty, debug section called .arm.atpcs. */
30897 if (atpcs)
30898 {
30899 asection * sec;
30900
30901 sec = bfd_make_section (stdoutput, ".arm.atpcs");
30902
30903 if (sec != NULL)
30904 {
30905 bfd_set_section_flags (sec, SEC_READONLY | SEC_DEBUGGING);
30906 bfd_set_section_size (sec, 0);
30907 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
30908 }
30909 }
30910 }
30911#endif
30912
30913 /* Record the CPU type as well. */
30914 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
30915 mach = bfd_mach_arm_iWMMXt2;
30916 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
30917 mach = bfd_mach_arm_iWMMXt;
30918 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
30919 mach = bfd_mach_arm_XScale;
30920 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
30921 mach = bfd_mach_arm_ep9312;
30922 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
30923 mach = bfd_mach_arm_5TE;
30924 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
30925 {
30926 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
30927 mach = bfd_mach_arm_5T;
30928 else
30929 mach = bfd_mach_arm_5;
30930 }
30931 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
30932 {
30933 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
30934 mach = bfd_mach_arm_4T;
30935 else
30936 mach = bfd_mach_arm_4;
30937 }
30938 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
30939 mach = bfd_mach_arm_3M;
30940 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
30941 mach = bfd_mach_arm_3;
30942 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
30943 mach = bfd_mach_arm_2a;
30944 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
30945 mach = bfd_mach_arm_2;
30946 else
30947 mach = bfd_mach_arm_unknown;
30948
30949 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
30950}
30951
30952/* Command line processing. */
30953
30954/* md_parse_option
30955 Invocation line includes a switch not recognized by the base assembler.
30956 See if it's a processor-specific option.
30957
30958 This routine is somewhat complicated by the need for backwards
30959 compatibility (since older releases of gcc can't be changed).
30960 The new options try to make the interface as compatible as
30961 possible with GCC.
30962
30963 New options (supported) are:
30964
30965 -mcpu=<cpu name> Assemble for selected processor
30966 -march=<architecture name> Assemble for selected architecture
30967 -mfpu=<fpu architecture> Assemble for selected FPU.
30968 -EB/-mbig-endian Big-endian
30969 -EL/-mlittle-endian Little-endian
30970 -k Generate PIC code
30971 -mthumb Start in Thumb mode
30972 -mthumb-interwork Code supports ARM/Thumb interworking
30973
30974 -m[no-]warn-deprecated Warn about deprecated features
30975 -m[no-]warn-syms Warn when symbols match instructions
30976
30977 For now we will also provide support for:
30978
30979 -mapcs-32 32-bit Program counter
30980 -mapcs-26 26-bit Program counter
30981 -macps-float Floats passed in FP registers
30982 -mapcs-reentrant Reentrant code
30983 -matpcs
30984 (sometime these will probably be replaced with -mapcs=<list of options>
30985 and -matpcs=<list of options>)
30986
30987 The remaining options are only supported for back-wards compatibility.
30988 Cpu variants, the arm part is optional:
30989 -m[arm]1 Currently not supported.
30990 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30991 -m[arm]3 Arm 3 processor
30992 -m[arm]6[xx], Arm 6 processors
30993 -m[arm]7[xx][t][[d]m] Arm 7 processors
30994 -m[arm]8[10] Arm 8 processors
30995 -m[arm]9[20][tdmi] Arm 9 processors
30996 -mstrongarm[110[0]] StrongARM processors
30997 -mxscale XScale processors
30998 -m[arm]v[2345[t[e]]] Arm architectures
30999 -mall All (except the ARM1)
31000 FP variants:
31001 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
31002 -mfpe-old (No float load/store multiples)
31003 -mvfpxd VFP Single precision
31004 -mvfp All VFP
31005 -mno-fpu Disable all floating point instructions
31006
31007 The following CPU names are recognized:
31008 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
31009 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31010 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31011 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31012 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31013 arm10t arm10e, arm1020t, arm1020e, arm10200e,
31014 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
31015
31016 */
31017
31018const char * md_shortopts = "m:k";
31019
31020#ifdef ARM_BI_ENDIAN
31021#define OPTION_EB (OPTION_MD_BASE + 0)
31022#define OPTION_EL (OPTION_MD_BASE + 1)
31023#else
31024#if TARGET_BYTES_BIG_ENDIAN
31025#define OPTION_EB (OPTION_MD_BASE + 0)
31026#else
31027#define OPTION_EL (OPTION_MD_BASE + 1)
31028#endif
31029#endif
31030#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
31031#define OPTION_FDPIC (OPTION_MD_BASE + 3)
31032
31033struct option md_longopts[] =
31034{
31035#ifdef OPTION_EB
31036 {"EB", no_argument, NULL, OPTION_EB},
31037#endif
31038#ifdef OPTION_EL
31039 {"EL", no_argument, NULL, OPTION_EL},
31040#endif
31041 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
31042#ifdef OBJ_ELF
31043 {"fdpic", no_argument, NULL, OPTION_FDPIC},
31044#endif
31045 {NULL, no_argument, NULL, 0}
31046};
31047
31048size_t md_longopts_size = sizeof (md_longopts);
31049
31050struct arm_option_table
31051{
31052 const char * option; /* Option name to match. */
31053 const char * help; /* Help information. */
31054 int * var; /* Variable to change. */
31055 int value; /* What to change it to. */
31056 const char * deprecated; /* If non-null, print this message. */
31057};
31058
31059struct arm_option_table arm_opts[] =
31060{
31061 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
31062 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
31063 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31064 &support_interwork, 1, NULL},
31065 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
31066 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
31067 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
31068 1, NULL},
31069 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
31070 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
31071 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
31072 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
31073 NULL},
31074
31075 /* These are recognized by the assembler, but have no affect on code. */
31076 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
31077 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
31078
31079 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
31080 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31081 &warn_on_deprecated, 0, NULL},
31082
31083 {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31084 " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it, 1, NULL},
31085 {"mno-warn-restrict-it", NULL, &warn_on_restrict_it, 0, NULL},
31086
31087 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
31088 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
31089 {NULL, NULL, NULL, 0, NULL}
31090};
31091
31092struct arm_legacy_option_table
31093{
31094 const char * option; /* Option name to match. */
31095 const arm_feature_set ** var; /* Variable to change. */
31096 const arm_feature_set value; /* What to change it to. */
31097 const char * deprecated; /* If non-null, print this message. */
31098};
31099
31100const struct arm_legacy_option_table arm_legacy_opts[] =
31101{
31102 /* DON'T add any new processors to this list -- we want the whole list
31103 to go away... Add them to the processors table instead. */
31104 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
31105 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
31106 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
31107 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
31108 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
31109 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
31110 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
31111 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
31112 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
31113 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
31114 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
31115 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
31116 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
31117 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
31118 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
31119 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
31120 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
31121 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
31122 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
31123 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
31124 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
31125 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
31126 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
31127 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
31128 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
31129 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
31130 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
31131 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
31132 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
31133 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
31134 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
31135 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
31136 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
31137 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
31138 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
31139 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
31140 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
31141 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
31142 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
31143 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
31144 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
31145 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
31146 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
31147 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
31148 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
31149 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
31150 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31151 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31152 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31153 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31154 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
31155 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
31156 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
31157 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
31158 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
31159 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
31160 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
31161 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
31162 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
31163 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
31164 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
31165 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
31166 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
31167 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
31168 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
31169 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
31170 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
31171 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
31172 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
31173 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
31174 N_("use -mcpu=strongarm110")},
31175 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
31176 N_("use -mcpu=strongarm1100")},
31177 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
31178 N_("use -mcpu=strongarm1110")},
31179 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
31180 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
31181 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
31182
31183 /* Architecture variants -- don't add any more to this list either. */
31184 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
31185 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
31186 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
31187 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
31188 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
31189 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
31190 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
31191 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
31192 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
31193 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
31194 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
31195 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
31196 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
31197 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
31198 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
31199 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
31200 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
31201 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
31202
31203 /* Floating point variants -- don't add any more to this list either. */
31204 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
31205 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
31206 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
31207 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
31208 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
31209
31210 {NULL, NULL, ARM_ARCH_NONE, NULL}
31211};
31212
31213struct arm_cpu_option_table
31214{
31215 const char * name;
31216 size_t name_len;
31217 const arm_feature_set value;
31218 const arm_feature_set ext;
31219 /* For some CPUs we assume an FPU unless the user explicitly sets
31220 -mfpu=... */
31221 const arm_feature_set default_fpu;
31222 /* The canonical name of the CPU, or NULL to use NAME converted to upper
31223 case. */
31224 const char * canonical_name;
31225};
31226
31227/* This list should, at a minimum, contain all the cpu names
31228 recognized by GCC. */
31229#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
31230
31231static const struct arm_cpu_option_table arm_cpus[] =
31232{
31233 ARM_CPU_OPT ("all", NULL, ARM_ANY,
31234 ARM_ARCH_NONE,
31235 FPU_ARCH_FPA),
31236 ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1,
31237 ARM_ARCH_NONE,
31238 FPU_ARCH_FPA),
31239 ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2,
31240 ARM_ARCH_NONE,
31241 FPU_ARCH_FPA),
31242 ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S,
31243 ARM_ARCH_NONE,
31244 FPU_ARCH_FPA),
31245 ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S,
31246 ARM_ARCH_NONE,
31247 FPU_ARCH_FPA),
31248 ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3,
31249 ARM_ARCH_NONE,
31250 FPU_ARCH_FPA),
31251 ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3,
31252 ARM_ARCH_NONE,
31253 FPU_ARCH_FPA),
31254 ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3,
31255 ARM_ARCH_NONE,
31256 FPU_ARCH_FPA),
31257 ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3,
31258 ARM_ARCH_NONE,
31259 FPU_ARCH_FPA),
31260 ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3,
31261 ARM_ARCH_NONE,
31262 FPU_ARCH_FPA),
31263 ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3,
31264 ARM_ARCH_NONE,
31265 FPU_ARCH_FPA),
31266 ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M,
31267 ARM_ARCH_NONE,
31268 FPU_ARCH_FPA),
31269 ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3,
31270 ARM_ARCH_NONE,
31271 FPU_ARCH_FPA),
31272 ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M,
31273 ARM_ARCH_NONE,
31274 FPU_ARCH_FPA),
31275 ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3,
31276 ARM_ARCH_NONE,
31277 FPU_ARCH_FPA),
31278 ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M,
31279 ARM_ARCH_NONE,
31280 FPU_ARCH_FPA),
31281 ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3,
31282 ARM_ARCH_NONE,
31283 FPU_ARCH_FPA),
31284 ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3,
31285 ARM_ARCH_NONE,
31286 FPU_ARCH_FPA),
31287 ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3,
31288 ARM_ARCH_NONE,
31289 FPU_ARCH_FPA),
31290 ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3,
31291 ARM_ARCH_NONE,
31292 FPU_ARCH_FPA),
31293 ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T,
31294 ARM_ARCH_NONE,
31295 FPU_ARCH_FPA),
31296 ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3,
31297 ARM_ARCH_NONE,
31298 FPU_ARCH_FPA),
31299 ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T,
31300 ARM_ARCH_NONE,
31301 FPU_ARCH_FPA),
31302 ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T,
31303 ARM_ARCH_NONE,
31304 FPU_ARCH_FPA),
31305 ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3,
31306 ARM_ARCH_NONE,
31307 FPU_ARCH_FPA),
31308 ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3,
31309 ARM_ARCH_NONE,
31310 FPU_ARCH_FPA),
31311 ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3,
31312 ARM_ARCH_NONE,
31313 FPU_ARCH_FPA),
31314 ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3,
31315 ARM_ARCH_NONE,
31316 FPU_ARCH_FPA),
31317 ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T,
31318 ARM_ARCH_NONE,
31319 FPU_ARCH_FPA),
31320 ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T,
31321 ARM_ARCH_NONE,
31322 FPU_ARCH_FPA),
31323 ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T,
31324 ARM_ARCH_NONE,
31325 FPU_ARCH_FPA),
31326 ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4,
31327 ARM_ARCH_NONE,
31328 FPU_ARCH_FPA),
31329 ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4,
31330 ARM_ARCH_NONE,
31331 FPU_ARCH_FPA),
31332 ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4,
31333 ARM_ARCH_NONE,
31334 FPU_ARCH_FPA),
31335 ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4,
31336 ARM_ARCH_NONE,
31337 FPU_ARCH_FPA),
31338 ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4,
31339 ARM_ARCH_NONE,
31340 FPU_ARCH_FPA),
31341 ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4,
31342 ARM_ARCH_NONE,
31343 FPU_ARCH_FPA),
31344 ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4,
31345 ARM_ARCH_NONE,
31346 FPU_ARCH_FPA),
31347 ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T,
31348 ARM_ARCH_NONE,
31349 FPU_ARCH_FPA),
31350 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T,
31351 ARM_ARCH_NONE,
31352 FPU_ARCH_FPA),
31353 ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T,
31354 ARM_ARCH_NONE,
31355 FPU_ARCH_FPA),
31356 ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T,
31357 ARM_ARCH_NONE,
31358 FPU_ARCH_FPA),
31359 ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T,
31360 ARM_ARCH_NONE,
31361 FPU_ARCH_FPA),
31362 ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T,
31363 ARM_ARCH_NONE,
31364 FPU_ARCH_FPA),
31365 ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4,
31366 ARM_ARCH_NONE,
31367 FPU_ARCH_FPA),
31368 ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4,
31369 ARM_ARCH_NONE,
31370 FPU_ARCH_FPA),
31371
31372 /* For V5 or later processors we default to using VFP; but the user
31373 should really set the FPU type explicitly. */
31374 ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP,
31375 ARM_ARCH_NONE,
31376 FPU_ARCH_VFP_V2),
31377 ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE,
31378 ARM_ARCH_NONE,
31379 FPU_ARCH_VFP_V2),
31380 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ,
31381 ARM_ARCH_NONE,
31382 FPU_ARCH_VFP_V2),
31383 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ,
31384 ARM_ARCH_NONE,
31385 FPU_ARCH_VFP_V2),
31386 ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ,
31387 ARM_ARCH_NONE,
31388 FPU_ARCH_VFP_V2),
31389 ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP,
31390 ARM_ARCH_NONE,
31391 FPU_ARCH_VFP_V2),
31392 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE,
31393 ARM_ARCH_NONE,
31394 FPU_ARCH_VFP_V2),
31395 ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE,
31396 ARM_ARCH_NONE,
31397 FPU_ARCH_VFP_V2),
31398 ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP,
31399 ARM_ARCH_NONE,
31400 FPU_ARCH_VFP_V2),
31401 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE,
31402 ARM_ARCH_NONE,
31403 FPU_ARCH_VFP_V2),
31404 ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE,
31405 ARM_ARCH_NONE,
31406 FPU_ARCH_VFP_V2),
31407 ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE,
31408 ARM_ARCH_NONE,
31409 FPU_ARCH_VFP_V2),
31410 ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T,
31411 ARM_ARCH_NONE,
31412 FPU_ARCH_VFP_V1),
31413 ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T,
31414 ARM_ARCH_NONE,
31415 FPU_ARCH_VFP_V1),
31416 ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE,
31417 ARM_ARCH_NONE,
31418 FPU_ARCH_VFP_V2),
31419 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE,
31420 ARM_ARCH_NONE,
31421 FPU_ARCH_VFP_V2),
31422 ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T,
31423 ARM_ARCH_NONE,
31424 FPU_ARCH_VFP_V1),
31425 ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE,
31426 ARM_ARCH_NONE,
31427 FPU_ARCH_VFP_V2),
31428 ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE,
31429 ARM_ARCH_NONE,
31430 FPU_ARCH_VFP_V2),
31431 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ,
31432 ARM_ARCH_NONE,
31433 FPU_ARCH_VFP_V2),
31434 ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ,
31435 ARM_ARCH_NONE,
31436 FPU_ARCH_VFP_V2),
31437 ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE,
31438 ARM_ARCH_NONE,
31439 FPU_ARCH_VFP_V2),
31440 ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE,
31441 ARM_ARCH_NONE,
31442 FPU_ARCH_VFP_V2),
31443 ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE,
31444 ARM_ARCH_NONE,
31445 FPU_ARCH_VFP_V2),
31446 ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE,
31447 ARM_ARCH_NONE,
31448 FPU_ARCH_VFP_V2),
31449 ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE,
31450 ARM_ARCH_NONE,
31451 FPU_ARCH_VFP_V2),
31452 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6,
31453 ARM_ARCH_NONE,
31454 FPU_NONE),
31455 ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6,
31456 ARM_ARCH_NONE,
31457 FPU_NONE),
31458 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6,
31459 ARM_ARCH_NONE,
31460 FPU_ARCH_VFP_V2),
31461 ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6,
31462 ARM_ARCH_NONE,
31463 FPU_ARCH_VFP_V2),
31464 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K,
31465 ARM_ARCH_NONE,
31466 FPU_ARCH_VFP_V2),
31467 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K,
31468 ARM_ARCH_NONE,
31469 FPU_NONE),
31470 ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2,
31471 ARM_ARCH_NONE,
31472 FPU_NONE),
31473 ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2,
31474 ARM_ARCH_NONE,
31475 FPU_ARCH_VFP_V2),
31476 ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ,
31477 ARM_ARCH_NONE,
31478 FPU_NONE),
31479 ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
31480 ARM_ARCH_NONE,
31481 FPU_ARCH_VFP_V2),
31482 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
31483 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31484 FPU_NONE),
31485 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
31486 ARM_ARCH_NONE,
31487 FPU_ARCH_NEON_VFP_V4),
31488 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
31489 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
31490 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
31491 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
31492 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31493 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
31494 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
31495 ARM_ARCH_NONE,
31496 FPU_ARCH_NEON_VFP_V4),
31497 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
31498 ARM_ARCH_NONE,
31499 FPU_ARCH_NEON_VFP_V4),
31500 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
31501 ARM_ARCH_NONE,
31502 FPU_ARCH_NEON_VFP_V4),
31503 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
31504 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31505 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31506 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
31507 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31508 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31509 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
31510 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31511 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31512 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
31513 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31514 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31515 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
31516 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31517 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31518 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
31519 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31520 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31521 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
31522 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31523 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31524 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
31525 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31526 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31527 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
31528 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31529 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31530 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A,
31531 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31532 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31533 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A,
31534 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31535 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31536 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A,
31537 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31538 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31539 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
31540 ARM_ARCH_NONE,
31541 FPU_NONE),
31542 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
31543 ARM_ARCH_NONE,
31544 FPU_ARCH_VFP_V3D16),
31545 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
31546 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
31547 FPU_NONE),
31548 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
31549 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
31550 FPU_ARCH_VFP_V3D16),
31551 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
31552 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
31553 FPU_ARCH_VFP_V3D16),
31554 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
31555 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31556 FPU_ARCH_NEON_VFP_ARMV8),
31557 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN,
31558 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31559 FPU_NONE),
31560 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
31561 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31562 FPU_NONE),
31563 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
31564 ARM_ARCH_NONE,
31565 FPU_NONE),
31566 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
31567 ARM_ARCH_NONE,
31568 FPU_NONE),
31569 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
31570 ARM_ARCH_NONE,
31571 FPU_NONE),
31572 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
31573 ARM_ARCH_NONE,
31574 FPU_NONE),
31575 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM,
31576 ARM_ARCH_NONE,
31577 FPU_NONE),
31578 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM,
31579 ARM_ARCH_NONE,
31580 FPU_NONE),
31581 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
31582 ARM_ARCH_NONE,
31583 FPU_NONE),
31584 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
31585 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31586 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31587 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
31588 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31589 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31590 /* ??? XSCALE is really an architecture. */
31591 ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
31592 ARM_ARCH_NONE,
31593 FPU_ARCH_VFP_V2),
31594
31595 /* ??? iwmmxt is not a processor. */
31596 ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT,
31597 ARM_ARCH_NONE,
31598 FPU_ARCH_VFP_V2),
31599 ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2,
31600 ARM_ARCH_NONE,
31601 FPU_ARCH_VFP_V2),
31602 ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE,
31603 ARM_ARCH_NONE,
31604 FPU_ARCH_VFP_V2),
31605
31606 /* Maverick. */
31607 ARM_CPU_OPT ("ep9312", "ARM920T",
31608 ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
31609 ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
31610
31611 /* Marvell processors. */
31612 ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
31613 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31614 FPU_ARCH_VFP_V3D16),
31615 ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
31616 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31617 FPU_ARCH_NEON_VFP_V4),
31618
31619 /* APM X-Gene family. */
31620 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
31621 ARM_ARCH_NONE,
31622 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31623 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
31624 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31625 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31626
31627 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
31628};
31629#undef ARM_CPU_OPT
31630
31631struct arm_ext_table
31632{
31633 const char * name;
31634 size_t name_len;
31635 const arm_feature_set merge;
31636 const arm_feature_set clear;
31637};
31638
31639struct arm_arch_option_table
31640{
31641 const char * name;
31642 size_t name_len;
31643 const arm_feature_set value;
31644 const arm_feature_set default_fpu;
31645 const struct arm_ext_table * ext_table;
31646};
31647
31648/* Used to add support for +E and +noE extension. */
31649#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31650/* Used to add support for a +E extension. */
31651#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31652/* Used to add support for a +noE extension. */
31653#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31654
31655#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31656 ~0 & ~FPU_ENDIAN_PURE)
31657
31658static const struct arm_ext_table armv5te_ext_table[] =
31659{
31660 ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
31661 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31662};
31663
31664static const struct arm_ext_table armv7_ext_table[] =
31665{
31666 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
31667 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31668};
31669
31670static const struct arm_ext_table armv7ve_ext_table[] =
31671{
31672 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
31673 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
31674 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
31675 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
31676 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
31677 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */
31678 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
31679
31680 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
31681 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
31682
31683 /* Aliases for +simd. */
31684 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
31685
31686 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31687 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31688 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
31689
31690 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31691};
31692
31693static const struct arm_ext_table armv7a_ext_table[] =
31694{
31695 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
31696 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
31697 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
31698 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
31699 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
31700 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
31701 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
31702
31703 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
31704 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
31705
31706 /* Aliases for +simd. */
31707 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31708 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31709
31710 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
31711 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
31712
31713 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
31714 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
31715 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31716};
31717
31718static const struct arm_ext_table armv7r_ext_table[] =
31719{
31720 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
31721 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */
31722 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
31723 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
31724 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
31725 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
31726 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
31727 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
31728 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31729};
31730
31731static const struct arm_ext_table armv7em_ext_table[] =
31732{
31733 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
31734 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31735 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
31736 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
31737 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
31738 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
31739 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31740};
31741
31742static const struct arm_ext_table armv8a_ext_table[] =
31743{
31744 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC)),
31745 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
31746 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
31747 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31748
31749 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31750 should use the +simd option to turn on FP. */
31751 ARM_REMOVE ("fp", ALL_FP),
31752 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31753 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31754 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31755};
31756
31757
31758static const struct arm_ext_table armv81a_ext_table[] =
31759{
31760 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
31761 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
31762 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31763
31764 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31765 should use the +simd option to turn on FP. */
31766 ARM_REMOVE ("fp", ALL_FP),
31767 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31768 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31769 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31770};
31771
31772static const struct arm_ext_table armv82a_ext_table[] =
31773{
31774 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
31775 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
31776 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
31777 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16)),
31778 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
31779 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
31780 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31781 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31782
31783 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31784 should use the +simd option to turn on FP. */
31785 ARM_REMOVE ("fp", ALL_FP),
31786 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31787 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31788 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31789};
31790
31791static const struct arm_ext_table armv84a_ext_table[] =
31792{
31793 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31794 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
31795 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16)),
31796 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
31797 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
31798 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31799
31800 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31801 should use the +simd option to turn on FP. */
31802 ARM_REMOVE ("fp", ALL_FP),
31803 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31804 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31805 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31806};
31807
31808static const struct arm_ext_table armv85a_ext_table[] =
31809{
31810 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31811 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
31812 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16)),
31813 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
31814 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
31815 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31816
31817 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31818 should use the +simd option to turn on FP. */
31819 ARM_REMOVE ("fp", ALL_FP),
31820 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31821};
31822
31823static const struct arm_ext_table armv86a_ext_table[] =
31824{
31825 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
31826 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31827};
31828
31829#define CDE_EXTENSIONS \
31830 ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
31831 ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
31832 ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
31833 ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
31834 ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
31835 ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
31836 ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
31837 ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
31838
31839static const struct arm_ext_table armv8m_main_ext_table[] =
31840{
31841 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
31842 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
31843 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
31844 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
31845 CDE_EXTENSIONS,
31846 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31847};
31848
31849
31850static const struct arm_ext_table armv8_1m_main_ext_table[] =
31851{
31852 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
31853 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
31854 ARM_EXT ("fp",
31855 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
31856 FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
31857 ALL_FP),
31858 ARM_ADD ("fp.dp",
31859 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
31860 FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
31861 ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP, ARM_EXT2_MVE, 0),
31862 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
31863 ARM_ADD ("mve.fp",
31864 ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP,
31865 ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
31866 FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
31867 CDE_EXTENSIONS,
31868 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31869};
31870
31871#undef CDE_EXTENSIONS
31872
31873static const struct arm_ext_table armv8r_ext_table[] =
31874{
31875 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC)),
31876 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
31877 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
31878 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31879 ARM_REMOVE ("fp", ALL_FP),
31880 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
31881 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31882};
31883
31884/* This list should, at a minimum, contain all the architecture names
31885 recognized by GCC. */
31886#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31887#define ARM_ARCH_OPT2(N, V, DF, ext) \
31888 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31889
31890static const struct arm_arch_option_table arm_archs[] =
31891{
31892 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
31893 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
31894 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
31895 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
31896 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
31897 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
31898 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
31899 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
31900 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
31901 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
31902 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
31903 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
31904 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
31905 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
31906 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te),
31907 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te),
31908 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te),
31909 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
31910 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
31911 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te),
31912 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te),
31913 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31914 kept to preserve existing behaviour. */
31915 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
31916 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
31917 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te),
31918 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te),
31919 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te),
31920 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31921 kept to preserve existing behaviour. */
31922 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
31923 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
31924 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
31925 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
31926 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7),
31927 /* The official spelling of the ARMv7 profile variants is the dashed form.
31928 Accept the non-dashed form for compatibility with old toolchains. */
31929 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
31930 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve),
31931 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
31932 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
31933 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
31934 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
31935 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
31936 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em),
31937 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
31938 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
31939 armv8m_main),
31940 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP,
31941 armv8_1m_main),
31942 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
31943 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
31944 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
31945 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a),
31946 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r),
31947 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a),
31948 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a),
31949 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A, FPU_ARCH_VFP, armv86a),
31950 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
31951 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
31952 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP),
31953 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
31954};
31955#undef ARM_ARCH_OPT
31956
31957/* ISA extensions in the co-processor and main instruction set space. */
31958
31959struct arm_option_extension_value_table
31960{
31961 const char * name;
31962 size_t name_len;
31963 const arm_feature_set merge_value;
31964 const arm_feature_set clear_value;
31965 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31966 indicates that an extension is available for all architectures while
31967 ARM_ANY marks an empty entry. */
31968 const arm_feature_set allowed_archs[2];
31969};
31970
31971/* The following table must be in alphabetical order with a NULL last entry. */
31972
31973#define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31974#define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31975
31976/* DEPRECATED: Refrain from using this table to add any new extensions, instead
31977 use the context sensitive approach using arm_ext_table's. */
31978static const struct arm_option_extension_value_table arm_extensions[] =
31979{
31980 ARM_EXT_OPT ("crc", ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC),
31981 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC),
31982 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
31983 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
31984 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
31985 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
31986 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
31987 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
31988 ARM_ARCH_V8_2A),
31989 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31990 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31991 ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
31992 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
31993 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
31994 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31995 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31996 ARM_ARCH_V8_2A),
31997 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31998 | ARM_EXT2_FP16_FML),
31999 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32000 | ARM_EXT2_FP16_FML),
32001 ARM_ARCH_V8_2A),
32002 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
32003 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
32004 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
32005 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
32006 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
32007 Thumb divide instruction. Due to this having the same name as the
32008 previous entry, this will be ignored when doing command-line parsing and
32009 only considered by build attribute selection code. */
32010 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
32011 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
32012 ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
32013 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
32014 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
32015 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
32016 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
32017 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
32018 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
32019 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
32020 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
32021 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
32022 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
32023 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
32024 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
32025 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
32026 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
32027 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
32028 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
32029 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
32030 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
32031 ARM_ARCH_V8A),
32032 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
32033 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
32034 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
32035 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
32036 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
32037 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
32038 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
32039 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
32040 ARM_ARCH_V8A),
32041 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
32042 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
32043 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
32044 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
32045 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
32046 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
32047 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
32048 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
32049 | ARM_EXT_DIV),
32050 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
32051 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
32052 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
32053 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
32054 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
32055};
32056#undef ARM_EXT_OPT
32057
32058/* ISA floating-point and Advanced SIMD extensions. */
32059struct arm_option_fpu_value_table
32060{
32061 const char * name;
32062 const arm_feature_set value;
32063};
32064
32065/* This list should, at a minimum, contain all the fpu names
32066 recognized by GCC. */
32067static const struct arm_option_fpu_value_table arm_fpus[] =
32068{
32069 {"softfpa", FPU_NONE},
32070 {"fpe", FPU_ARCH_FPE},
32071 {"fpe2", FPU_ARCH_FPE},
32072 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
32073 {"fpa", FPU_ARCH_FPA},
32074 {"fpa10", FPU_ARCH_FPA},
32075 {"fpa11", FPU_ARCH_FPA},
32076 {"arm7500fe", FPU_ARCH_FPA},
32077 {"softvfp", FPU_ARCH_VFP},
32078 {"softvfp+vfp", FPU_ARCH_VFP_V2},
32079 {"vfp", FPU_ARCH_VFP_V2},
32080 {"vfp9", FPU_ARCH_VFP_V2},
32081 {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */
32082 {"vfp10", FPU_ARCH_VFP_V2},
32083 {"vfp10-r0", FPU_ARCH_VFP_V1},
32084 {"vfpxd", FPU_ARCH_VFP_V1xD},
32085 {"vfpv2", FPU_ARCH_VFP_V2},
32086 {"vfpv3", FPU_ARCH_VFP_V3},
32087 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
32088 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
32089 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
32090 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
32091 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
32092 {"arm1020t", FPU_ARCH_VFP_V1},
32093 {"arm1020e", FPU_ARCH_VFP_V2},
32094 {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */
32095 {"arm1136jf-s", FPU_ARCH_VFP_V2},
32096 {"maverick", FPU_ARCH_MAVERICK},
32097 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
32098 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
32099 {"neon-fp16", FPU_ARCH_NEON_FP16},
32100 {"vfpv4", FPU_ARCH_VFP_V4},
32101 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
32102 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
32103 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
32104 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
32105 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
32106 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
32107 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
32108 {"crypto-neon-fp-armv8",
32109 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
32110 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
32111 {"crypto-neon-fp-armv8.1",
32112 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
32113 {NULL, ARM_ARCH_NONE}
32114};
32115
32116struct arm_option_value_table
32117{
32118 const char *name;
32119 long value;
32120};
32121
32122static const struct arm_option_value_table arm_float_abis[] =
32123{
32124 {"hard", ARM_FLOAT_ABI_HARD},
32125 {"softfp", ARM_FLOAT_ABI_SOFTFP},
32126 {"soft", ARM_FLOAT_ABI_SOFT},
32127 {NULL, 0}
32128};
32129
32130#ifdef OBJ_ELF
32131/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
32132static const struct arm_option_value_table arm_eabis[] =
32133{
32134 {"gnu", EF_ARM_EABI_UNKNOWN},
32135 {"4", EF_ARM_EABI_VER4},
32136 {"5", EF_ARM_EABI_VER5},
32137 {NULL, 0}
32138};
32139#endif
32140
32141struct arm_long_option_table
32142{
32143 const char * option; /* Substring to match. */
32144 const char * help; /* Help information. */
32145 int (* func) (const char * subopt); /* Function to decode sub-option. */
32146 const char * deprecated; /* If non-null, print this message. */
32147};
32148
32149static bfd_boolean
32150arm_parse_extension (const char *str, const arm_feature_set *opt_set,
32151 arm_feature_set *ext_set,
32152 const struct arm_ext_table *ext_table)
32153{
32154 /* We insist on extensions being specified in alphabetical order, and with
32155 extensions being added before being removed. We achieve this by having
32156 the global ARM_EXTENSIONS table in alphabetical order, and using the
32157 ADDING_VALUE variable to indicate whether we are adding an extension (1)
32158 or removing it (0) and only allowing it to change in the order
32159 -1 -> 1 -> 0. */
32160 const struct arm_option_extension_value_table * opt = NULL;
32161 const arm_feature_set arm_any = ARM_ANY;
32162 int adding_value = -1;
32163
32164 while (str != NULL && *str != 0)
32165 {
32166 const char *ext;
32167 size_t len;
32168
32169 if (*str != '+')
32170 {
32171 as_bad (_("invalid architectural extension"));
32172 return FALSE;
32173 }
32174
32175 str++;
32176 ext = strchr (str, '+');
32177
32178 if (ext != NULL)
32179 len = ext - str;
32180 else
32181 len = strlen (str);
32182
32183 if (len >= 2 && strncmp (str, "no", 2) == 0)
32184 {
32185 if (adding_value != 0)
32186 {
32187 adding_value = 0;
32188 opt = arm_extensions;
32189 }
32190
32191 len -= 2;
32192 str += 2;
32193 }
32194 else if (len > 0)
32195 {
32196 if (adding_value == -1)
32197 {
32198 adding_value = 1;
32199 opt = arm_extensions;
32200 }
32201 else if (adding_value != 1)
32202 {
32203 as_bad (_("must specify extensions to add before specifying "
32204 "those to remove"));
32205 return FALSE;
32206 }
32207 }
32208
32209 if (len == 0)
32210 {
32211 as_bad (_("missing architectural extension"));
32212 return FALSE;
32213 }
32214
32215 gas_assert (adding_value != -1);
32216 gas_assert (opt != NULL);
32217
32218 if (ext_table != NULL)
32219 {
32220 const struct arm_ext_table * ext_opt = ext_table;
32221 bfd_boolean found = FALSE;
32222 for (; ext_opt->name != NULL; ext_opt++)
32223 if (ext_opt->name_len == len
32224 && strncmp (ext_opt->name, str, len) == 0)
32225 {
32226 if (adding_value)
32227 {
32228 if (ARM_FEATURE_ZERO (ext_opt->merge))
32229 /* TODO: Option not supported. When we remove the
32230 legacy table this case should error out. */
32231 continue;
32232
32233 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
32234 }
32235 else
32236 {
32237 if (ARM_FEATURE_ZERO (ext_opt->clear))
32238 /* TODO: Option not supported. When we remove the
32239 legacy table this case should error out. */
32240 continue;
32241 ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
32242 }
32243 found = TRUE;
32244 break;
32245 }
32246 if (found)
32247 {
32248 str = ext;
32249 continue;
32250 }
32251 }
32252
32253 /* Scan over the options table trying to find an exact match. */
32254 for (; opt->name != NULL; opt++)
32255 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
32256 {
32257 int i, nb_allowed_archs =
32258 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
32259 /* Check we can apply the extension to this architecture. */
32260 for (i = 0; i < nb_allowed_archs; i++)
32261 {
32262 /* Empty entry. */
32263 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
32264 continue;
32265 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
32266 break;
32267 }
32268 if (i == nb_allowed_archs)
32269 {
32270 as_bad (_("extension does not apply to the base architecture"));
32271 return FALSE;
32272 }
32273
32274 /* Add or remove the extension. */
32275 if (adding_value)
32276 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
32277 else
32278 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
32279
32280 /* Allowing Thumb division instructions for ARMv7 in autodetection
32281 rely on this break so that duplicate extensions (extensions
32282 with the same name as a previous extension in the list) are not
32283 considered for command-line parsing. */
32284 break;
32285 }
32286
32287 if (opt->name == NULL)
32288 {
32289 /* Did we fail to find an extension because it wasn't specified in
32290 alphabetical order, or because it does not exist? */
32291
32292 for (opt = arm_extensions; opt->name != NULL; opt++)
32293 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
32294 break;
32295
32296 if (opt->name == NULL)
32297 as_bad (_("unknown architectural extension `%s'"), str);
32298 else
32299 as_bad (_("architectural extensions must be specified in "
32300 "alphabetical order"));
32301
32302 return FALSE;
32303 }
32304 else
32305 {
32306 /* We should skip the extension we've just matched the next time
32307 round. */
32308 opt++;
32309 }
32310
32311 str = ext;
32312 };
32313
32314 return TRUE;
32315}
32316
32317static bfd_boolean
32318arm_parse_fp16_opt (const char *str)
32319{
32320 if (strcasecmp (str, "ieee") == 0)
32321 fp16_format = ARM_FP16_FORMAT_IEEE;
32322 else if (strcasecmp (str, "alternative") == 0)
32323 fp16_format = ARM_FP16_FORMAT_ALTERNATIVE;
32324 else
32325 {
32326 as_bad (_("unrecognised float16 format \"%s\""), str);
32327 return FALSE;
32328 }
32329
32330 return TRUE;
32331}
32332
32333static bfd_boolean
32334arm_parse_cpu (const char *str)
32335{
32336 const struct arm_cpu_option_table *opt;
32337 const char *ext = strchr (str, '+');
32338 size_t len;
32339
32340 if (ext != NULL)
32341 len = ext - str;
32342 else
32343 len = strlen (str);
32344
32345 if (len == 0)
32346 {
32347 as_bad (_("missing cpu name `%s'"), str);
32348 return FALSE;
32349 }
32350
32351 for (opt = arm_cpus; opt->name != NULL; opt++)
32352 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
32353 {
32354 mcpu_cpu_opt = &opt->value;
32355 if (mcpu_ext_opt == NULL)
32356 mcpu_ext_opt = XNEW (arm_feature_set);
32357 *mcpu_ext_opt = opt->ext;
32358 mcpu_fpu_opt = &opt->default_fpu;
32359 if (opt->canonical_name)
32360 {
32361 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
32362 strcpy (selected_cpu_name, opt->canonical_name);
32363 }
32364 else
32365 {
32366 size_t i;
32367
32368 if (len >= sizeof selected_cpu_name)
32369 len = (sizeof selected_cpu_name) - 1;
32370
32371 for (i = 0; i < len; i++)
32372 selected_cpu_name[i] = TOUPPER (opt->name[i]);
32373 selected_cpu_name[i] = 0;
32374 }
32375
32376 if (ext != NULL)
32377 return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
32378
32379 return TRUE;
32380 }
32381
32382 as_bad (_("unknown cpu `%s'"), str);
32383 return FALSE;
32384}
32385
32386static bfd_boolean
32387arm_parse_arch (const char *str)
32388{
32389 const struct arm_arch_option_table *opt;
32390 const char *ext = strchr (str, '+');
32391 size_t len;
32392
32393 if (ext != NULL)
32394 len = ext - str;
32395 else
32396 len = strlen (str);
32397
32398 if (len == 0)
32399 {
32400 as_bad (_("missing architecture name `%s'"), str);
32401 return FALSE;
32402 }
32403
32404 for (opt = arm_archs; opt->name != NULL; opt++)
32405 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
32406 {
32407 march_cpu_opt = &opt->value;
32408 if (march_ext_opt == NULL)
32409 march_ext_opt = XNEW (arm_feature_set);
32410 *march_ext_opt = arm_arch_none;
32411 march_fpu_opt = &opt->default_fpu;
32412 selected_ctx_ext_table = opt->ext_table;
32413 strcpy (selected_cpu_name, opt->name);
32414
32415 if (ext != NULL)
32416 return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
32417 opt->ext_table);
32418
32419 return TRUE;
32420 }
32421
32422 as_bad (_("unknown architecture `%s'\n"), str);
32423 return FALSE;
32424}
32425
32426static bfd_boolean
32427arm_parse_fpu (const char * str)
32428{
32429 const struct arm_option_fpu_value_table * opt;
32430
32431 for (opt = arm_fpus; opt->name != NULL; opt++)
32432 if (streq (opt->name, str))
32433 {
32434 mfpu_opt = &opt->value;
32435 return TRUE;
32436 }
32437
32438 as_bad (_("unknown floating point format `%s'\n"), str);
32439 return FALSE;
32440}
32441
32442static bfd_boolean
32443arm_parse_float_abi (const char * str)
32444{
32445 const struct arm_option_value_table * opt;
32446
32447 for (opt = arm_float_abis; opt->name != NULL; opt++)
32448 if (streq (opt->name, str))
32449 {
32450 mfloat_abi_opt = opt->value;
32451 return TRUE;
32452 }
32453
32454 as_bad (_("unknown floating point abi `%s'\n"), str);
32455 return FALSE;
32456}
32457
32458#ifdef OBJ_ELF
32459static bfd_boolean
32460arm_parse_eabi (const char * str)
32461{
32462 const struct arm_option_value_table *opt;
32463
32464 for (opt = arm_eabis; opt->name != NULL; opt++)
32465 if (streq (opt->name, str))
32466 {
32467 meabi_flags = opt->value;
32468 return TRUE;
32469 }
32470 as_bad (_("unknown EABI `%s'\n"), str);
32471 return FALSE;
32472}
32473#endif
32474
32475static bfd_boolean
32476arm_parse_it_mode (const char * str)
32477{
32478 bfd_boolean ret = TRUE;
32479
32480 if (streq ("arm", str))
32481 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
32482 else if (streq ("thumb", str))
32483 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
32484 else if (streq ("always", str))
32485 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
32486 else if (streq ("never", str))
32487 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
32488 else
32489 {
32490 as_bad (_("unknown implicit IT mode `%s', should be "\
32491 "arm, thumb, always, or never."), str);
32492 ret = FALSE;
32493 }
32494
32495 return ret;
32496}
32497
32498static bfd_boolean
32499arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
32500{
32501 codecomposer_syntax = TRUE;
32502 arm_comment_chars[0] = ';';
32503 arm_line_separator_chars[0] = 0;
32504 return TRUE;
32505}
32506
32507struct arm_long_option_table arm_long_opts[] =
32508{
32509 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
32510 arm_parse_cpu, NULL},
32511 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
32512 arm_parse_arch, NULL},
32513 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
32514 arm_parse_fpu, NULL},
32515 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
32516 arm_parse_float_abi, NULL},
32517#ifdef OBJ_ELF
32518 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
32519 arm_parse_eabi, NULL},
32520#endif
32521 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
32522 arm_parse_it_mode, NULL},
32523 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
32524 arm_ccs_mode, NULL},
32525 {"mfp16-format=",
32526 N_("[ieee|alternative]\n\
32527 set the encoding for half precision floating point "
32528 "numbers to IEEE\n\
32529 or Arm alternative format."),
32530 arm_parse_fp16_opt, NULL },
32531 {NULL, NULL, 0, NULL}
32532};
32533
32534int
32535md_parse_option (int c, const char * arg)
32536{
32537 struct arm_option_table *opt;
32538 const struct arm_legacy_option_table *fopt;
32539 struct arm_long_option_table *lopt;
32540
32541 switch (c)
32542 {
32543#ifdef OPTION_EB
32544 case OPTION_EB:
32545 target_big_endian = 1;
32546 break;
32547#endif
32548
32549#ifdef OPTION_EL
32550 case OPTION_EL:
32551 target_big_endian = 0;
32552 break;
32553#endif
32554
32555 case OPTION_FIX_V4BX:
32556 fix_v4bx = TRUE;
32557 break;
32558
32559#ifdef OBJ_ELF
32560 case OPTION_FDPIC:
32561 arm_fdpic = TRUE;
32562 break;
32563#endif /* OBJ_ELF */
32564
32565 case 'a':
32566 /* Listing option. Just ignore these, we don't support additional
32567 ones. */
32568 return 0;
32569
32570 default:
32571 for (opt = arm_opts; opt->option != NULL; opt++)
32572 {
32573 if (c == opt->option[0]
32574 && ((arg == NULL && opt->option[1] == 0)
32575 || streq (arg, opt->option + 1)))
32576 {
32577 /* If the option is deprecated, tell the user. */
32578 if (warn_on_deprecated && opt->deprecated != NULL)
32579 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
32580 arg ? arg : "", _(opt->deprecated));
32581
32582 if (opt->var != NULL)
32583 *opt->var = opt->value;
32584
32585 return 1;
32586 }
32587 }
32588
32589 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
32590 {
32591 if (c == fopt->option[0]
32592 && ((arg == NULL && fopt->option[1] == 0)
32593 || streq (arg, fopt->option + 1)))
32594 {
32595 /* If the option is deprecated, tell the user. */
32596 if (warn_on_deprecated && fopt->deprecated != NULL)
32597 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
32598 arg ? arg : "", _(fopt->deprecated));
32599
32600 if (fopt->var != NULL)
32601 *fopt->var = &fopt->value;
32602
32603 return 1;
32604 }
32605 }
32606
32607 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
32608 {
32609 /* These options are expected to have an argument. */
32610 if (c == lopt->option[0]
32611 && arg != NULL
32612 && strncmp (arg, lopt->option + 1,
32613 strlen (lopt->option + 1)) == 0)
32614 {
32615 /* If the option is deprecated, tell the user. */
32616 if (warn_on_deprecated && lopt->deprecated != NULL)
32617 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
32618 _(lopt->deprecated));
32619
32620 /* Call the sup-option parser. */
32621 return lopt->func (arg + strlen (lopt->option) - 1);
32622 }
32623 }
32624
32625 return 0;
32626 }
32627
32628 return 1;
32629}
32630
32631void
32632md_show_usage (FILE * fp)
32633{
32634 struct arm_option_table *opt;
32635 struct arm_long_option_table *lopt;
32636
32637 fprintf (fp, _(" ARM-specific assembler options:\n"));
32638
32639 for (opt = arm_opts; opt->option != NULL; opt++)
32640 if (opt->help != NULL)
32641 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
32642
32643 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
32644 if (lopt->help != NULL)
32645 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
32646
32647#ifdef OPTION_EB
32648 fprintf (fp, _("\
32649 -EB assemble code for a big-endian cpu\n"));
32650#endif
32651
32652#ifdef OPTION_EL
32653 fprintf (fp, _("\
32654 -EL assemble code for a little-endian cpu\n"));
32655#endif
32656
32657 fprintf (fp, _("\
32658 --fix-v4bx Allow BX in ARMv4 code\n"));
32659
32660#ifdef OBJ_ELF
32661 fprintf (fp, _("\
32662 --fdpic generate an FDPIC object file\n"));
32663#endif /* OBJ_ELF */
32664}
32665
32666#ifdef OBJ_ELF
32667
32668typedef struct
32669{
32670 int val;
32671 arm_feature_set flags;
32672} cpu_arch_ver_table;
32673
32674/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32675 chronologically for architectures, with an exception for ARMv6-M and
32676 ARMv6S-M due to legacy reasons. No new architecture should have a
32677 special case. This allows for build attribute selection results to be
32678 stable when new architectures are added. */
32679static const cpu_arch_ver_table cpu_arch_ver[] =
32680{
32681 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
32682 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
32683 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
32684 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
32685 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
32686 {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
32687 {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
32688 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
32689 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
32690 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
32691 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
32692 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
32693 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
32694 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
32695 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
32696 {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
32697 {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
32698 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
32699 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
32700 {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
32701 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
32702 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
32703 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
32704 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
32705
32706 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32707 always selected build attributes to match those of ARMv6-M
32708 (resp. ARMv6S-M). However, due to these architectures being a strict
32709 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32710 would be selected when fully respecting chronology of architectures.
32711 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32712 move them before ARMv7 architectures. */
32713 {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
32714 {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
32715
32716 {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
32717 {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
32718 {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
32719 {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
32720 {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
32721 {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
32722 {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
32723 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
32724 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
32725 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
32726 {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
32727 {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
32728 {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
32729 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
32730 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
32731 {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
32732 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_6A},
32733 {-1, ARM_ARCH_NONE}
32734};
32735
32736/* Set an attribute if it has not already been set by the user. */
32737
32738static void
32739aeabi_set_attribute_int (int tag, int value)
32740{
32741 if (tag < 1
32742 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
32743 || !attributes_set_explicitly[tag])
32744 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
32745}
32746
32747static void
32748aeabi_set_attribute_string (int tag, const char *value)
32749{
32750 if (tag < 1
32751 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
32752 || !attributes_set_explicitly[tag])
32753 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
32754}
32755
32756/* Return whether features in the *NEEDED feature set are available via
32757 extensions for the architecture whose feature set is *ARCH_FSET. */
32758
32759static bfd_boolean
32760have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
32761 const arm_feature_set *needed)
32762{
32763 int i, nb_allowed_archs;
32764 arm_feature_set ext_fset;
32765 const struct arm_option_extension_value_table *opt;
32766
32767 ext_fset = arm_arch_none;
32768 for (opt = arm_extensions; opt->name != NULL; opt++)
32769 {
32770 /* Extension does not provide any feature we need. */
32771 if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
32772 continue;
32773
32774 nb_allowed_archs =
32775 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
32776 for (i = 0; i < nb_allowed_archs; i++)
32777 {
32778 /* Empty entry. */
32779 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
32780 break;
32781
32782 /* Extension is available, add it. */
32783 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
32784 ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
32785 }
32786 }
32787
32788 /* Can we enable all features in *needed? */
32789 return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
32790}
32791
32792/* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32793 a given architecture feature set *ARCH_EXT_FSET including extension feature
32794 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32795 - if true, check for an exact match of the architecture modulo extensions;
32796 - otherwise, select build attribute value of the first superset
32797 architecture released so that results remains stable when new architectures
32798 are added.
32799 For -march/-mcpu=all the build attribute value of the most featureful
32800 architecture is returned. Tag_CPU_arch_profile result is returned in
32801 PROFILE. */
32802
32803static int
32804get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
32805 const arm_feature_set *ext_fset,
32806 char *profile, int exact_match)
32807{
32808 arm_feature_set arch_fset;
32809 const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
32810
32811 /* Select most featureful architecture with all its extensions if building
32812 for -march=all as the feature sets used to set build attributes. */
32813 if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
32814 {
32815 /* Force revisiting of decision for each new architecture. */
32816 gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
32817 *profile = 'A';
32818 return TAG_CPU_ARCH_V8;
32819 }
32820
32821 ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
32822
32823 for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
32824 {
32825 arm_feature_set known_arch_fset;
32826
32827 ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
32828 if (exact_match)
32829 {
32830 /* Base architecture match user-specified architecture and
32831 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32832 if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
32833 {
32834 p_ver_ret = p_ver;
32835 goto found;
32836 }
32837 /* Base architecture match user-specified architecture only
32838 (eg. ARMv6-M in the same case as above). Record it in case we
32839 find a match with above condition. */
32840 else if (p_ver_ret == NULL
32841 && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
32842 p_ver_ret = p_ver;
32843 }
32844 else
32845 {
32846
32847 /* Architecture has all features wanted. */
32848 if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
32849 {
32850 arm_feature_set added_fset;
32851
32852 /* Compute features added by this architecture over the one
32853 recorded in p_ver_ret. */
32854 if (p_ver_ret != NULL)
32855 ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
32856 p_ver_ret->flags);
32857 /* First architecture that match incl. with extensions, or the
32858 only difference in features over the recorded match is
32859 features that were optional and are now mandatory. */
32860 if (p_ver_ret == NULL
32861 || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
32862 {
32863 p_ver_ret = p_ver;
32864 goto found;
32865 }
32866 }
32867 else if (p_ver_ret == NULL)
32868 {
32869 arm_feature_set needed_ext_fset;
32870
32871 ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
32872
32873 /* Architecture has all features needed when using some
32874 extensions. Record it and continue searching in case there
32875 exist an architecture providing all needed features without
32876 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32877 OS extension). */
32878 if (have_ext_for_needed_feat_p (&known_arch_fset,
32879 &needed_ext_fset))
32880 p_ver_ret = p_ver;
32881 }
32882 }
32883 }
32884
32885 if (p_ver_ret == NULL)
32886 return -1;
32887
32888 found:
32889 /* Tag_CPU_arch_profile. */
32890 if (!ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8r)
32891 && (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
32892 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
32893 || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
32894 && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only))))
32895 *profile = 'A';
32896 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r)
32897 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8r))
32898 *profile = 'R';
32899 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
32900 *profile = 'M';
32901 else
32902 *profile = '\0';
32903 return p_ver_ret->val;
32904}
32905
32906/* Set the public EABI object attributes. */
32907
32908static void
32909aeabi_set_public_attributes (void)
32910{
32911 char profile = '\0';
32912 int arch = -1;
32913 int virt_sec = 0;
32914 int fp16_optional = 0;
32915 int skip_exact_match = 0;
32916 arm_feature_set flags, flags_arch, flags_ext;
32917
32918 /* Autodetection mode, choose the architecture based the instructions
32919 actually used. */
32920 if (no_cpu_selected ())
32921 {
32922 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
32923
32924 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
32925 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
32926
32927 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
32928 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
32929
32930 /* Code run during relaxation relies on selected_cpu being set. */
32931 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
32932 flags_ext = arm_arch_none;
32933 ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext);
32934 selected_ext = flags_ext;
32935 selected_cpu = flags;
32936 }
32937 /* Otherwise, choose the architecture based on the capabilities of the
32938 requested cpu. */
32939 else
32940 {
32941 ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext);
32942 ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any);
32943 flags_ext = selected_ext;
32944 flags = selected_cpu;
32945 }
32946 ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu);
32947
32948 /* Allow the user to override the reported architecture. */
32949 if (!ARM_FEATURE_ZERO (selected_object_arch))
32950 {
32951 ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any);
32952 flags_ext = arm_arch_none;
32953 }
32954 else
32955 skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
32956
32957 /* When this function is run again after relaxation has happened there is no
32958 way to determine whether an architecture or CPU was specified by the user:
32959 - selected_cpu is set above for relaxation to work;
32960 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32961 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32962 Therefore, if not in -march=all case we first try an exact match and fall
32963 back to autodetection. */
32964 if (!skip_exact_match)
32965 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
32966 if (arch == -1)
32967 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
32968 if (arch == -1)
32969 as_bad (_("no architecture contains all the instructions used\n"));
32970
32971 /* Tag_CPU_name. */
32972 if (selected_cpu_name[0])
32973 {
32974 char *q;
32975
32976 q = selected_cpu_name;
32977 if (strncmp (q, "armv", 4) == 0)
32978 {
32979 int i;
32980
32981 q += 4;
32982 for (i = 0; q[i]; i++)
32983 q[i] = TOUPPER (q[i]);
32984 }
32985 aeabi_set_attribute_string (Tag_CPU_name, q);
32986 }
32987
32988 /* Tag_CPU_arch. */
32989 aeabi_set_attribute_int (Tag_CPU_arch, arch);
32990
32991 /* Tag_CPU_arch_profile. */
32992 if (profile != '\0')
32993 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
32994
32995 /* Tag_DSP_extension. */
32996 if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp))
32997 aeabi_set_attribute_int (Tag_DSP_extension, 1);
32998
32999 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
33000 /* Tag_ARM_ISA_use. */
33001 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
33002 || ARM_FEATURE_ZERO (flags_arch))
33003 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
33004
33005 /* Tag_THUMB_ISA_use. */
33006 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
33007 || ARM_FEATURE_ZERO (flags_arch))
33008 {
33009 int thumb_isa_use;
33010
33011 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
33012 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
33013 thumb_isa_use = 3;
33014 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
33015 thumb_isa_use = 2;
33016 else
33017 thumb_isa_use = 1;
33018 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
33019 }
33020
33021 /* Tag_VFP_arch. */
33022 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
33023 aeabi_set_attribute_int (Tag_VFP_arch,
33024 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
33025 ? 7 : 8);
33026 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
33027 aeabi_set_attribute_int (Tag_VFP_arch,
33028 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
33029 ? 5 : 6);
33030 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
33031 {
33032 fp16_optional = 1;
33033 aeabi_set_attribute_int (Tag_VFP_arch, 3);
33034 }
33035 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
33036 {
33037 aeabi_set_attribute_int (Tag_VFP_arch, 4);
33038 fp16_optional = 1;
33039 }
33040 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
33041 aeabi_set_attribute_int (Tag_VFP_arch, 2);
33042 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
33043 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
33044 aeabi_set_attribute_int (Tag_VFP_arch, 1);
33045
33046 /* Tag_ABI_HardFP_use. */
33047 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
33048 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
33049 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
33050
33051 /* Tag_WMMX_arch. */
33052 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
33053 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
33054 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
33055 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
33056
33057 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
33058 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
33059 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
33060 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
33061 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
33062 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
33063 {
33064 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
33065 {
33066 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
33067 }
33068 else
33069 {
33070 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
33071 fp16_optional = 1;
33072 }
33073 }
33074
33075 if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext))
33076 aeabi_set_attribute_int (Tag_MVE_arch, 2);
33077 else if (ARM_CPU_HAS_FEATURE (flags, mve_ext))
33078 aeabi_set_attribute_int (Tag_MVE_arch, 1);
33079
33080 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
33081 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
33082 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
33083
33084 /* Tag_DIV_use.
33085
33086 We set Tag_DIV_use to two when integer divide instructions have been used
33087 in ARM state, or when Thumb integer divide instructions have been used,
33088 but we have no architecture profile set, nor have we any ARM instructions.
33089
33090 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33091 by the base architecture.
33092
33093 For new architectures we will have to check these tests. */
33094 gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
33095 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
33096 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
33097 aeabi_set_attribute_int (Tag_DIV_use, 0);
33098 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
33099 || (profile == '\0'
33100 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
33101 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
33102 aeabi_set_attribute_int (Tag_DIV_use, 2);
33103
33104 /* Tag_MP_extension_use. */
33105 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
33106 aeabi_set_attribute_int (Tag_MPextension_use, 1);
33107
33108 /* Tag Virtualization_use. */
33109 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
33110 virt_sec |= 1;
33111 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
33112 virt_sec |= 2;
33113 if (virt_sec != 0)
33114 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
33115
33116 if (fp16_format != ARM_FP16_FORMAT_DEFAULT)
33117 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format, fp16_format);
33118}
33119
33120/* Post relaxation hook. Recompute ARM attributes now that relaxation is
33121 finished and free extension feature bits which will not be used anymore. */
33122
33123void
33124arm_md_post_relax (void)
33125{
33126 aeabi_set_public_attributes ();
33127 XDELETE (mcpu_ext_opt);
33128 mcpu_ext_opt = NULL;
33129 XDELETE (march_ext_opt);
33130 march_ext_opt = NULL;
33131}
33132
33133/* Add the default contents for the .ARM.attributes section. */
33134
33135void
33136arm_md_end (void)
33137{
33138 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
33139 return;
33140
33141 aeabi_set_public_attributes ();
33142}
33143#endif /* OBJ_ELF */
33144
33145/* Parse a .cpu directive. */
33146
33147static void
33148s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
33149{
33150 const struct arm_cpu_option_table *opt;
33151 char *name;
33152 char saved_char;
33153
33154 name = input_line_pointer;
33155 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33156 input_line_pointer++;
33157 saved_char = *input_line_pointer;
33158 *input_line_pointer = 0;
33159
33160 /* Skip the first "all" entry. */
33161 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
33162 if (streq (opt->name, name))
33163 {
33164 selected_arch = opt->value;
33165 selected_ext = opt->ext;
33166 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
33167 if (opt->canonical_name)
33168 strcpy (selected_cpu_name, opt->canonical_name);
33169 else
33170 {
33171 int i;
33172 for (i = 0; opt->name[i]; i++)
33173 selected_cpu_name[i] = TOUPPER (opt->name[i]);
33174
33175 selected_cpu_name[i] = 0;
33176 }
33177 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33178
33179 *input_line_pointer = saved_char;
33180 demand_empty_rest_of_line ();
33181 return;
33182 }
33183 as_bad (_("unknown cpu `%s'"), name);
33184 *input_line_pointer = saved_char;
33185 ignore_rest_of_line ();
33186}
33187
33188/* Parse a .arch directive. */
33189
33190static void
33191s_arm_arch (int ignored ATTRIBUTE_UNUSED)
33192{
33193 const struct arm_arch_option_table *opt;
33194 char saved_char;
33195 char *name;
33196
33197 name = input_line_pointer;
33198 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33199 input_line_pointer++;
33200 saved_char = *input_line_pointer;
33201 *input_line_pointer = 0;
33202
33203 /* Skip the first "all" entry. */
33204 for (opt = arm_archs + 1; opt->name != NULL; opt++)
33205 if (streq (opt->name, name))
33206 {
33207 selected_arch = opt->value;
33208 selected_ctx_ext_table = opt->ext_table;
33209 selected_ext = arm_arch_none;
33210 selected_cpu = selected_arch;
33211 strcpy (selected_cpu_name, opt->name);
33212 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33213 *input_line_pointer = saved_char;
33214 demand_empty_rest_of_line ();
33215 return;
33216 }
33217
33218 as_bad (_("unknown architecture `%s'\n"), name);
33219 *input_line_pointer = saved_char;
33220 ignore_rest_of_line ();
33221}
33222
33223/* Parse a .object_arch directive. */
33224
33225static void
33226s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
33227{
33228 const struct arm_arch_option_table *opt;
33229 char saved_char;
33230 char *name;
33231
33232 name = input_line_pointer;
33233 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33234 input_line_pointer++;
33235 saved_char = *input_line_pointer;
33236 *input_line_pointer = 0;
33237
33238 /* Skip the first "all" entry. */
33239 for (opt = arm_archs + 1; opt->name != NULL; opt++)
33240 if (streq (opt->name, name))
33241 {
33242 selected_object_arch = opt->value;
33243 *input_line_pointer = saved_char;
33244 demand_empty_rest_of_line ();
33245 return;
33246 }
33247
33248 as_bad (_("unknown architecture `%s'\n"), name);
33249 *input_line_pointer = saved_char;
33250 ignore_rest_of_line ();
33251}
33252
33253/* Parse a .arch_extension directive. */
33254
33255static void
33256s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
33257{
33258 const struct arm_option_extension_value_table *opt;
33259 char saved_char;
33260 char *name;
33261 int adding_value = 1;
33262
33263 name = input_line_pointer;
33264 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33265 input_line_pointer++;
33266 saved_char = *input_line_pointer;
33267 *input_line_pointer = 0;
33268
33269 if (strlen (name) >= 2
33270 && strncmp (name, "no", 2) == 0)
33271 {
33272 adding_value = 0;
33273 name += 2;
33274 }
33275
33276 /* Check the context specific extension table */
33277 if (selected_ctx_ext_table)
33278 {
33279 const struct arm_ext_table * ext_opt;
33280 for (ext_opt = selected_ctx_ext_table; ext_opt->name != NULL; ext_opt++)
33281 {
33282 if (streq (ext_opt->name, name))
33283 {
33284 if (adding_value)
33285 {
33286 if (ARM_FEATURE_ZERO (ext_opt->merge))
33287 /* TODO: Option not supported. When we remove the
33288 legacy table this case should error out. */
33289 continue;
33290 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
33291 ext_opt->merge);
33292 }
33293 else
33294 ARM_CLEAR_FEATURE (selected_ext, selected_ext, ext_opt->clear);
33295
33296 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
33297 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33298 *input_line_pointer = saved_char;
33299 demand_empty_rest_of_line ();
33300 return;
33301 }
33302 }
33303 }
33304
33305 for (opt = arm_extensions; opt->name != NULL; opt++)
33306 if (streq (opt->name, name))
33307 {
33308 int i, nb_allowed_archs =
33309 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
33310 for (i = 0; i < nb_allowed_archs; i++)
33311 {
33312 /* Empty entry. */
33313 if (ARM_CPU_IS_ANY (opt->allowed_archs[i]))
33314 continue;
33315 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch))
33316 break;
33317 }
33318
33319 if (i == nb_allowed_archs)
33320 {
33321 as_bad (_("architectural extension `%s' is not allowed for the "
33322 "current base architecture"), name);
33323 break;
33324 }
33325
33326 if (adding_value)
33327 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
33328 opt->merge_value);
33329 else
33330 ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value);
33331
33332 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
33333 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33334 *input_line_pointer = saved_char;
33335 demand_empty_rest_of_line ();
33336 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
33337 on this return so that duplicate extensions (extensions with the
33338 same name as a previous extension in the list) are not considered
33339 for command-line parsing. */
33340 return;
33341 }
33342
33343 if (opt->name == NULL)
33344 as_bad (_("unknown architecture extension `%s'\n"), name);
33345
33346 *input_line_pointer = saved_char;
33347 ignore_rest_of_line ();
33348}
33349
33350/* Parse a .fpu directive. */
33351
33352static void
33353s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
33354{
33355 const struct arm_option_fpu_value_table *opt;
33356 char saved_char;
33357 char *name;
33358
33359 name = input_line_pointer;
33360 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33361 input_line_pointer++;
33362 saved_char = *input_line_pointer;
33363 *input_line_pointer = 0;
33364
33365 for (opt = arm_fpus; opt->name != NULL; opt++)
33366 if (streq (opt->name, name))
33367 {
33368 selected_fpu = opt->value;
33369 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, fpu_any);
33370#ifndef CPU_DEFAULT
33371 if (no_cpu_selected ())
33372 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
33373 else
33374#endif
33375 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33376 *input_line_pointer = saved_char;
33377 demand_empty_rest_of_line ();
33378 return;
33379 }
33380
33381 as_bad (_("unknown floating point format `%s'\n"), name);
33382 *input_line_pointer = saved_char;
33383 ignore_rest_of_line ();
33384}
33385
33386/* Copy symbol information. */
33387
33388void
33389arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
33390{
33391 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
33392}
33393
33394#ifdef OBJ_ELF
33395/* Given a symbolic attribute NAME, return the proper integer value.
33396 Returns -1 if the attribute is not known. */
33397
33398int
33399arm_convert_symbolic_attribute (const char *name)
33400{
33401 static const struct
33402 {
33403 const char * name;
33404 const int tag;
33405 }
33406 attribute_table[] =
33407 {
33408 /* When you modify this table you should
33409 also modify the list in doc/c-arm.texi. */
33410#define T(tag) {#tag, tag}
33411 T (Tag_CPU_raw_name),
33412 T (Tag_CPU_name),
33413 T (Tag_CPU_arch),
33414 T (Tag_CPU_arch_profile),
33415 T (Tag_ARM_ISA_use),
33416 T (Tag_THUMB_ISA_use),
33417 T (Tag_FP_arch),
33418 T (Tag_VFP_arch),
33419 T (Tag_WMMX_arch),
33420 T (Tag_Advanced_SIMD_arch),
33421 T (Tag_PCS_config),
33422 T (Tag_ABI_PCS_R9_use),
33423 T (Tag_ABI_PCS_RW_data),
33424 T (Tag_ABI_PCS_RO_data),
33425 T (Tag_ABI_PCS_GOT_use),
33426 T (Tag_ABI_PCS_wchar_t),
33427 T (Tag_ABI_FP_rounding),
33428 T (Tag_ABI_FP_denormal),
33429 T (Tag_ABI_FP_exceptions),
33430 T (Tag_ABI_FP_user_exceptions),
33431 T (Tag_ABI_FP_number_model),
33432 T (Tag_ABI_align_needed),
33433 T (Tag_ABI_align8_needed),
33434 T (Tag_ABI_align_preserved),
33435 T (Tag_ABI_align8_preserved),
33436 T (Tag_ABI_enum_size),
33437 T (Tag_ABI_HardFP_use),
33438 T (Tag_ABI_VFP_args),
33439 T (Tag_ABI_WMMX_args),
33440 T (Tag_ABI_optimization_goals),
33441 T (Tag_ABI_FP_optimization_goals),
33442 T (Tag_compatibility),
33443 T (Tag_CPU_unaligned_access),
33444 T (Tag_FP_HP_extension),
33445 T (Tag_VFP_HP_extension),
33446 T (Tag_ABI_FP_16bit_format),
33447 T (Tag_MPextension_use),
33448 T (Tag_DIV_use),
33449 T (Tag_nodefaults),
33450 T (Tag_also_compatible_with),
33451 T (Tag_conformance),
33452 T (Tag_T2EE_use),
33453 T (Tag_Virtualization_use),
33454 T (Tag_DSP_extension),
33455 T (Tag_MVE_arch),
33456 /* We deliberately do not include Tag_MPextension_use_legacy. */
33457#undef T
33458 };
33459 unsigned int i;
33460
33461 if (name == NULL)
33462 return -1;
33463
33464 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
33465 if (streq (name, attribute_table[i].name))
33466 return attribute_table[i].tag;
33467
33468 return -1;
33469}
33470
33471/* Apply sym value for relocations only in the case that they are for
33472 local symbols in the same segment as the fixup and you have the
33473 respective architectural feature for blx and simple switches. */
33474
33475int
33476arm_apply_sym_value (struct fix * fixP, segT this_seg)
33477{
33478 if (fixP->fx_addsy
33479 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
33480 /* PR 17444: If the local symbol is in a different section then a reloc
33481 will always be generated for it, so applying the symbol value now
33482 will result in a double offset being stored in the relocation. */
33483 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
33484 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
33485 {
33486 switch (fixP->fx_r_type)
33487 {
33488 case BFD_RELOC_ARM_PCREL_BLX:
33489 case BFD_RELOC_THUMB_PCREL_BRANCH23:
33490 if (ARM_IS_FUNC (fixP->fx_addsy))
33491 return 1;
33492 break;
33493
33494 case BFD_RELOC_ARM_PCREL_CALL:
33495 case BFD_RELOC_THUMB_PCREL_BLX:
33496 if (THUMB_IS_FUNC (fixP->fx_addsy))
33497 return 1;
33498 break;
33499
33500 default:
33501 break;
33502 }
33503
33504 }
33505 return 0;
33506}
33507#endif /* OBJ_ELF */
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