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[AArch64] Remove redundant tls relax in elfNN_aarch64_final_link_relocate
[thirdparty/binutils-gdb.git] / gas / config / tc-arm.c
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1/* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
8
9 This file is part of GAS, the GNU Assembler.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
25
26#include "as.h"
27#include <limits.h>
28#include <stdarg.h>
29#define NO_RELOC 0
30#include "safe-ctype.h"
31#include "subsegs.h"
32#include "obstack.h"
33#include "libiberty.h"
34#include "opcode/arm.h"
35
36#ifdef OBJ_ELF
37#include "elf/arm.h"
38#include "dw2gencfi.h"
39#endif
40
41#include "dwarf2dbg.h"
42
43#ifdef OBJ_ELF
44/* Must be at least the size of the largest unwind opcode (currently two). */
45#define ARM_OPCODE_CHUNK_SIZE 8
46
47/* This structure holds the unwinding state. */
48
49static struct
50{
51 symbolS * proc_start;
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
56 segT saved_seg;
57 subsegT saved_subseg;
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
60 int opcode_count;
61 int opcode_alloc;
62 /* The number of bytes pushed to the stack. */
63 offsetT frame_size;
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
70 offsetT fp_offset;
71 int fp_reg;
72 /* Nonzero if an unwind_setfp directive has been seen. */
73 unsigned fp_used:1;
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
76} unwind;
77
78#endif /* OBJ_ELF */
79
80/* Results from operand parsing worker functions. */
81
82typedef enum
83{
84 PARSE_OPERAND_SUCCESS,
85 PARSE_OPERAND_FAIL,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87} parse_operand_result;
88
89enum arm_float_abi
90{
91 ARM_FLOAT_ABI_HARD,
92 ARM_FLOAT_ABI_SOFTFP,
93 ARM_FLOAT_ABI_SOFT
94};
95
96/* Types of processor to assemble for. */
97#ifndef CPU_DEFAULT
98/* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
101
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
104#endif
105
106#ifndef FPU_DEFAULT
107# ifdef TE_LINUX
108# define FPU_DEFAULT FPU_ARCH_FPA
109# elif defined (TE_NetBSD)
110# ifdef OBJ_ELF
111# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
112# else
113 /* Legacy a.out format. */
114# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
115# endif
116# elif defined (TE_VXWORKS)
117# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
118# else
119 /* For backwards compatibility, default to FPA. */
120# define FPU_DEFAULT FPU_ARCH_FPA
121# endif
122#endif /* ifndef FPU_DEFAULT */
123
124#define streq(a, b) (strcmp (a, b) == 0)
125
126static arm_feature_set cpu_variant;
127static arm_feature_set arm_arch_used;
128static arm_feature_set thumb_arch_used;
129
130/* Flags stored in private area of BFD structure. */
131static int uses_apcs_26 = FALSE;
132static int atpcs = FALSE;
133static int support_interwork = FALSE;
134static int uses_apcs_float = FALSE;
135static int pic_code = FALSE;
136static int fix_v4bx = FALSE;
137/* Warn on using deprecated features. */
138static int warn_on_deprecated = TRUE;
139
140/* Understand CodeComposer Studio assembly syntax. */
141bfd_boolean codecomposer_syntax = FALSE;
142
143/* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
145 assembly flags. */
146static const arm_feature_set *legacy_cpu = NULL;
147static const arm_feature_set *legacy_fpu = NULL;
148
149static const arm_feature_set *mcpu_cpu_opt = NULL;
150static const arm_feature_set *mcpu_fpu_opt = NULL;
151static const arm_feature_set *march_cpu_opt = NULL;
152static const arm_feature_set *march_fpu_opt = NULL;
153static const arm_feature_set *mfpu_opt = NULL;
154static const arm_feature_set *object_arch = NULL;
155
156/* Constants for known architecture features. */
157static const arm_feature_set fpu_default = FPU_DEFAULT;
158static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
159static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
161static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
162static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
166
167#ifdef CPU_DEFAULT
168static const arm_feature_set cpu_default = CPU_DEFAULT;
169#endif
170
171static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
172static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
173static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
174static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
175static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
176static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
177static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
178static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
179static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
181static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
182static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
183static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
184static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
185static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
186static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
187static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
188static const arm_feature_set arm_ext_v6m = ARM_FEATURE_CORE_LOW (ARM_EXT_V6M);
189static const arm_feature_set arm_ext_v6_notm =
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
191static const arm_feature_set arm_ext_v6_dsp =
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
193static const arm_feature_set arm_ext_barrier =
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
195static const arm_feature_set arm_ext_msr =
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
197static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
198static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
199static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
200static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
201static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
202static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
203static const arm_feature_set arm_ext_m =
204 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M,
205 ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
206static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
207static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
208static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
209static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
210static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
211static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
212static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
213static const arm_feature_set arm_ext_v8m_main =
214 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
215/* Instructions in ARMv8-M only found in M profile architectures. */
216static const arm_feature_set arm_ext_v8m_m_only =
217 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
218static const arm_feature_set arm_ext_v6t2_v8m =
219 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
220/* Instructions shared between ARMv8-A and ARMv8-M. */
221static const arm_feature_set arm_ext_atomics =
222 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
223/* DSP instructions Tag_DSP_extension refers to. */
224static const arm_feature_set arm_ext_dsp =
225 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
226static const arm_feature_set arm_ext_v8_2 =
227 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
228/* FP16 instructions. */
229static const arm_feature_set arm_ext_fp16 =
230 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
231
232static const arm_feature_set arm_arch_any = ARM_ANY;
233static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
234static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
235static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
236static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
237
238static const arm_feature_set arm_cext_iwmmxt2 =
239 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
240static const arm_feature_set arm_cext_iwmmxt =
241 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
242static const arm_feature_set arm_cext_xscale =
243 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
244static const arm_feature_set arm_cext_maverick =
245 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
246static const arm_feature_set fpu_fpa_ext_v1 =
247 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
248static const arm_feature_set fpu_fpa_ext_v2 =
249 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
250static const arm_feature_set fpu_vfp_ext_v1xd =
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
252static const arm_feature_set fpu_vfp_ext_v1 =
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
254static const arm_feature_set fpu_vfp_ext_v2 =
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
256static const arm_feature_set fpu_vfp_ext_v3xd =
257 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
258static const arm_feature_set fpu_vfp_ext_v3 =
259 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
260static const arm_feature_set fpu_vfp_ext_d32 =
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
262static const arm_feature_set fpu_neon_ext_v1 =
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
264static const arm_feature_set fpu_vfp_v3_or_neon_ext =
265 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
266static const arm_feature_set fpu_vfp_fp16 =
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
268static const arm_feature_set fpu_neon_ext_fma =
269 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
270static const arm_feature_set fpu_vfp_ext_fma =
271 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
272static const arm_feature_set fpu_vfp_ext_armv8 =
273 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
274static const arm_feature_set fpu_vfp_ext_armv8xd =
275 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
276static const arm_feature_set fpu_neon_ext_armv8 =
277 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
278static const arm_feature_set fpu_crypto_ext_armv8 =
279 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
280static const arm_feature_set crc_ext_armv8 =
281 ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
282static const arm_feature_set fpu_neon_ext_v8_1 =
283 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
284
285static int mfloat_abi_opt = -1;
286/* Record user cpu selection for object attributes. */
287static arm_feature_set selected_cpu = ARM_ARCH_NONE;
288/* Must be long enough to hold any of the names in arm_cpus. */
289static char selected_cpu_name[20];
290
291extern FLONUM_TYPE generic_floating_point_number;
292
293/* Return if no cpu was selected on command-line. */
294static bfd_boolean
295no_cpu_selected (void)
296{
297 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
298}
299
300#ifdef OBJ_ELF
301# ifdef EABI_DEFAULT
302static int meabi_flags = EABI_DEFAULT;
303# else
304static int meabi_flags = EF_ARM_EABI_UNKNOWN;
305# endif
306
307static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
308
309bfd_boolean
310arm_is_eabi (void)
311{
312 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
313}
314#endif
315
316#ifdef OBJ_ELF
317/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
318symbolS * GOT_symbol;
319#endif
320
321/* 0: assemble for ARM,
322 1: assemble for Thumb,
323 2: assemble for Thumb even though target CPU does not support thumb
324 instructions. */
325static int thumb_mode = 0;
326/* A value distinct from the possible values for thumb_mode that we
327 can use to record whether thumb_mode has been copied into the
328 tc_frag_data field of a frag. */
329#define MODE_RECORDED (1 << 4)
330
331/* Specifies the intrinsic IT insn behavior mode. */
332enum implicit_it_mode
333{
334 IMPLICIT_IT_MODE_NEVER = 0x00,
335 IMPLICIT_IT_MODE_ARM = 0x01,
336 IMPLICIT_IT_MODE_THUMB = 0x02,
337 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
338};
339static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
340
341/* If unified_syntax is true, we are processing the new unified
342 ARM/Thumb syntax. Important differences from the old ARM mode:
343
344 - Immediate operands do not require a # prefix.
345 - Conditional affixes always appear at the end of the
346 instruction. (For backward compatibility, those instructions
347 that formerly had them in the middle, continue to accept them
348 there.)
349 - The IT instruction may appear, and if it does is validated
350 against subsequent conditional affixes. It does not generate
351 machine code.
352
353 Important differences from the old Thumb mode:
354
355 - Immediate operands do not require a # prefix.
356 - Most of the V6T2 instructions are only available in unified mode.
357 - The .N and .W suffixes are recognized and honored (it is an error
358 if they cannot be honored).
359 - All instructions set the flags if and only if they have an 's' affix.
360 - Conditional affixes may be used. They are validated against
361 preceding IT instructions. Unlike ARM mode, you cannot use a
362 conditional affix except in the scope of an IT instruction. */
363
364static bfd_boolean unified_syntax = FALSE;
365
366/* An immediate operand can start with #, and ld*, st*, pld operands
367 can contain [ and ]. We need to tell APP not to elide whitespace
368 before a [, which can appear as the first operand for pld.
369 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
370const char arm_symbol_chars[] = "#[]{}";
371
372enum neon_el_type
373{
374 NT_invtype,
375 NT_untyped,
376 NT_integer,
377 NT_float,
378 NT_poly,
379 NT_signed,
380 NT_unsigned
381};
382
383struct neon_type_el
384{
385 enum neon_el_type type;
386 unsigned size;
387};
388
389#define NEON_MAX_TYPE_ELS 4
390
391struct neon_type
392{
393 struct neon_type_el el[NEON_MAX_TYPE_ELS];
394 unsigned elems;
395};
396
397enum it_instruction_type
398{
399 OUTSIDE_IT_INSN,
400 INSIDE_IT_INSN,
401 INSIDE_IT_LAST_INSN,
402 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
403 if inside, should be the last one. */
404 NEUTRAL_IT_INSN, /* This could be either inside or outside,
405 i.e. BKPT and NOP. */
406 IT_INSN /* The IT insn has been parsed. */
407};
408
409/* The maximum number of operands we need. */
410#define ARM_IT_MAX_OPERANDS 6
411
412struct arm_it
413{
414 const char * error;
415 unsigned long instruction;
416 int size;
417 int size_req;
418 int cond;
419 /* "uncond_value" is set to the value in place of the conditional field in
420 unconditional versions of the instruction, or -1 if nothing is
421 appropriate. */
422 int uncond_value;
423 struct neon_type vectype;
424 /* This does not indicate an actual NEON instruction, only that
425 the mnemonic accepts neon-style type suffixes. */
426 int is_neon;
427 /* Set to the opcode if the instruction needs relaxation.
428 Zero if the instruction is not relaxed. */
429 unsigned long relax;
430 struct
431 {
432 bfd_reloc_code_real_type type;
433 expressionS exp;
434 int pc_rel;
435 } reloc;
436
437 enum it_instruction_type it_insn_type;
438
439 struct
440 {
441 unsigned reg;
442 signed int imm;
443 struct neon_type_el vectype;
444 unsigned present : 1; /* Operand present. */
445 unsigned isreg : 1; /* Operand was a register. */
446 unsigned immisreg : 1; /* .imm field is a second register. */
447 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
448 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
449 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
450 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
451 instructions. This allows us to disambiguate ARM <-> vector insns. */
452 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
453 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
454 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
455 unsigned issingle : 1; /* Operand is VFP single-precision register. */
456 unsigned hasreloc : 1; /* Operand has relocation suffix. */
457 unsigned writeback : 1; /* Operand has trailing ! */
458 unsigned preind : 1; /* Preindexed address. */
459 unsigned postind : 1; /* Postindexed address. */
460 unsigned negative : 1; /* Index register was negated. */
461 unsigned shifted : 1; /* Shift applied to operation. */
462 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
463 } operands[ARM_IT_MAX_OPERANDS];
464};
465
466static struct arm_it inst;
467
468#define NUM_FLOAT_VALS 8
469
470const char * fp_const[] =
471{
472 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
473};
474
475/* Number of littlenums required to hold an extended precision number. */
476#define MAX_LITTLENUMS 6
477
478LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
479
480#define FAIL (-1)
481#define SUCCESS (0)
482
483#define SUFF_S 1
484#define SUFF_D 2
485#define SUFF_E 3
486#define SUFF_P 4
487
488#define CP_T_X 0x00008000
489#define CP_T_Y 0x00400000
490
491#define CONDS_BIT 0x00100000
492#define LOAD_BIT 0x00100000
493
494#define DOUBLE_LOAD_FLAG 0x00000001
495
496struct asm_cond
497{
498 const char * template_name;
499 unsigned long value;
500};
501
502#define COND_ALWAYS 0xE
503
504struct asm_psr
505{
506 const char * template_name;
507 unsigned long field;
508};
509
510struct asm_barrier_opt
511{
512 const char * template_name;
513 unsigned long value;
514 const arm_feature_set arch;
515};
516
517/* The bit that distinguishes CPSR and SPSR. */
518#define SPSR_BIT (1 << 22)
519
520/* The individual PSR flag bits. */
521#define PSR_c (1 << 16)
522#define PSR_x (1 << 17)
523#define PSR_s (1 << 18)
524#define PSR_f (1 << 19)
525
526struct reloc_entry
527{
528 const char * name;
529 bfd_reloc_code_real_type reloc;
530};
531
532enum vfp_reg_pos
533{
534 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
535 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
536};
537
538enum vfp_ldstm_type
539{
540 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
541};
542
543/* Bits for DEFINED field in neon_typed_alias. */
544#define NTA_HASTYPE 1
545#define NTA_HASINDEX 2
546
547struct neon_typed_alias
548{
549 unsigned char defined;
550 unsigned char index;
551 struct neon_type_el eltype;
552};
553
554/* ARM register categories. This includes coprocessor numbers and various
555 architecture extensions' registers. */
556enum arm_reg_type
557{
558 REG_TYPE_RN,
559 REG_TYPE_CP,
560 REG_TYPE_CN,
561 REG_TYPE_FN,
562 REG_TYPE_VFS,
563 REG_TYPE_VFD,
564 REG_TYPE_NQ,
565 REG_TYPE_VFSD,
566 REG_TYPE_NDQ,
567 REG_TYPE_NSDQ,
568 REG_TYPE_VFC,
569 REG_TYPE_MVF,
570 REG_TYPE_MVD,
571 REG_TYPE_MVFX,
572 REG_TYPE_MVDX,
573 REG_TYPE_MVAX,
574 REG_TYPE_DSPSC,
575 REG_TYPE_MMXWR,
576 REG_TYPE_MMXWC,
577 REG_TYPE_MMXWCG,
578 REG_TYPE_XSCALE,
579 REG_TYPE_RNB
580};
581
582/* Structure for a hash table entry for a register.
583 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
584 information which states whether a vector type or index is specified (for a
585 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
586struct reg_entry
587{
588 const char * name;
589 unsigned int number;
590 unsigned char type;
591 unsigned char builtin;
592 struct neon_typed_alias * neon;
593};
594
595/* Diagnostics used when we don't get a register of the expected type. */
596const char * const reg_expected_msgs[] =
597{
598 N_("ARM register expected"),
599 N_("bad or missing co-processor number"),
600 N_("co-processor register expected"),
601 N_("FPA register expected"),
602 N_("VFP single precision register expected"),
603 N_("VFP/Neon double precision register expected"),
604 N_("Neon quad precision register expected"),
605 N_("VFP single or double precision register expected"),
606 N_("Neon double or quad precision register expected"),
607 N_("VFP single, double or Neon quad precision register expected"),
608 N_("VFP system register expected"),
609 N_("Maverick MVF register expected"),
610 N_("Maverick MVD register expected"),
611 N_("Maverick MVFX register expected"),
612 N_("Maverick MVDX register expected"),
613 N_("Maverick MVAX register expected"),
614 N_("Maverick DSPSC register expected"),
615 N_("iWMMXt data register expected"),
616 N_("iWMMXt control register expected"),
617 N_("iWMMXt scalar register expected"),
618 N_("XScale accumulator register expected"),
619};
620
621/* Some well known registers that we refer to directly elsewhere. */
622#define REG_R12 12
623#define REG_SP 13
624#define REG_LR 14
625#define REG_PC 15
626
627/* ARM instructions take 4bytes in the object file, Thumb instructions
628 take 2: */
629#define INSN_SIZE 4
630
631struct asm_opcode
632{
633 /* Basic string to match. */
634 const char * template_name;
635
636 /* Parameters to instruction. */
637 unsigned int operands[8];
638
639 /* Conditional tag - see opcode_lookup. */
640 unsigned int tag : 4;
641
642 /* Basic instruction code. */
643 unsigned int avalue : 28;
644
645 /* Thumb-format instruction code. */
646 unsigned int tvalue;
647
648 /* Which architecture variant provides this instruction. */
649 const arm_feature_set * avariant;
650 const arm_feature_set * tvariant;
651
652 /* Function to call to encode instruction in ARM format. */
653 void (* aencode) (void);
654
655 /* Function to call to encode instruction in Thumb format. */
656 void (* tencode) (void);
657};
658
659/* Defines for various bits that we will want to toggle. */
660#define INST_IMMEDIATE 0x02000000
661#define OFFSET_REG 0x02000000
662#define HWOFFSET_IMM 0x00400000
663#define SHIFT_BY_REG 0x00000010
664#define PRE_INDEX 0x01000000
665#define INDEX_UP 0x00800000
666#define WRITE_BACK 0x00200000
667#define LDM_TYPE_2_OR_3 0x00400000
668#define CPSI_MMOD 0x00020000
669
670#define LITERAL_MASK 0xf000f000
671#define OPCODE_MASK 0xfe1fffff
672#define V4_STR_BIT 0x00000020
673#define VLDR_VMOV_SAME 0x0040f000
674
675#define T2_SUBS_PC_LR 0xf3de8f00
676
677#define DATA_OP_SHIFT 21
678
679#define T2_OPCODE_MASK 0xfe1fffff
680#define T2_DATA_OP_SHIFT 21
681
682#define A_COND_MASK 0xf0000000
683#define A_PUSH_POP_OP_MASK 0x0fff0000
684
685/* Opcodes for pushing/poping registers to/from the stack. */
686#define A1_OPCODE_PUSH 0x092d0000
687#define A2_OPCODE_PUSH 0x052d0004
688#define A2_OPCODE_POP 0x049d0004
689
690/* Codes to distinguish the arithmetic instructions. */
691#define OPCODE_AND 0
692#define OPCODE_EOR 1
693#define OPCODE_SUB 2
694#define OPCODE_RSB 3
695#define OPCODE_ADD 4
696#define OPCODE_ADC 5
697#define OPCODE_SBC 6
698#define OPCODE_RSC 7
699#define OPCODE_TST 8
700#define OPCODE_TEQ 9
701#define OPCODE_CMP 10
702#define OPCODE_CMN 11
703#define OPCODE_ORR 12
704#define OPCODE_MOV 13
705#define OPCODE_BIC 14
706#define OPCODE_MVN 15
707
708#define T2_OPCODE_AND 0
709#define T2_OPCODE_BIC 1
710#define T2_OPCODE_ORR 2
711#define T2_OPCODE_ORN 3
712#define T2_OPCODE_EOR 4
713#define T2_OPCODE_ADD 8
714#define T2_OPCODE_ADC 10
715#define T2_OPCODE_SBC 11
716#define T2_OPCODE_SUB 13
717#define T2_OPCODE_RSB 14
718
719#define T_OPCODE_MUL 0x4340
720#define T_OPCODE_TST 0x4200
721#define T_OPCODE_CMN 0x42c0
722#define T_OPCODE_NEG 0x4240
723#define T_OPCODE_MVN 0x43c0
724
725#define T_OPCODE_ADD_R3 0x1800
726#define T_OPCODE_SUB_R3 0x1a00
727#define T_OPCODE_ADD_HI 0x4400
728#define T_OPCODE_ADD_ST 0xb000
729#define T_OPCODE_SUB_ST 0xb080
730#define T_OPCODE_ADD_SP 0xa800
731#define T_OPCODE_ADD_PC 0xa000
732#define T_OPCODE_ADD_I8 0x3000
733#define T_OPCODE_SUB_I8 0x3800
734#define T_OPCODE_ADD_I3 0x1c00
735#define T_OPCODE_SUB_I3 0x1e00
736
737#define T_OPCODE_ASR_R 0x4100
738#define T_OPCODE_LSL_R 0x4080
739#define T_OPCODE_LSR_R 0x40c0
740#define T_OPCODE_ROR_R 0x41c0
741#define T_OPCODE_ASR_I 0x1000
742#define T_OPCODE_LSL_I 0x0000
743#define T_OPCODE_LSR_I 0x0800
744
745#define T_OPCODE_MOV_I8 0x2000
746#define T_OPCODE_CMP_I8 0x2800
747#define T_OPCODE_CMP_LR 0x4280
748#define T_OPCODE_MOV_HR 0x4600
749#define T_OPCODE_CMP_HR 0x4500
750
751#define T_OPCODE_LDR_PC 0x4800
752#define T_OPCODE_LDR_SP 0x9800
753#define T_OPCODE_STR_SP 0x9000
754#define T_OPCODE_LDR_IW 0x6800
755#define T_OPCODE_STR_IW 0x6000
756#define T_OPCODE_LDR_IH 0x8800
757#define T_OPCODE_STR_IH 0x8000
758#define T_OPCODE_LDR_IB 0x7800
759#define T_OPCODE_STR_IB 0x7000
760#define T_OPCODE_LDR_RW 0x5800
761#define T_OPCODE_STR_RW 0x5000
762#define T_OPCODE_LDR_RH 0x5a00
763#define T_OPCODE_STR_RH 0x5200
764#define T_OPCODE_LDR_RB 0x5c00
765#define T_OPCODE_STR_RB 0x5400
766
767#define T_OPCODE_PUSH 0xb400
768#define T_OPCODE_POP 0xbc00
769
770#define T_OPCODE_BRANCH 0xe000
771
772#define THUMB_SIZE 2 /* Size of thumb instruction. */
773#define THUMB_PP_PC_LR 0x0100
774#define THUMB_LOAD_BIT 0x0800
775#define THUMB2_LOAD_BIT 0x00100000
776
777#define BAD_ARGS _("bad arguments to instruction")
778#define BAD_SP _("r13 not allowed here")
779#define BAD_PC _("r15 not allowed here")
780#define BAD_COND _("instruction cannot be conditional")
781#define BAD_OVERLAP _("registers may not be the same")
782#define BAD_HIREG _("lo register required")
783#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
784#define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
785#define BAD_BRANCH _("branch must be last instruction in IT block")
786#define BAD_NOT_IT _("instruction not allowed in IT block")
787#define BAD_FPU _("selected FPU does not support instruction")
788#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
789#define BAD_IT_COND _("incorrect condition in IT block")
790#define BAD_IT_IT _("IT falling in the range of a previous IT block")
791#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
792#define BAD_PC_ADDRESSING \
793 _("cannot use register index with PC-relative addressing")
794#define BAD_PC_WRITEBACK \
795 _("cannot use writeback with PC-relative addressing")
796#define BAD_RANGE _("branch out of range")
797#define BAD_FP16 _("selected processor does not support fp16 instruction")
798#define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
799#define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
800
801static struct hash_control * arm_ops_hsh;
802static struct hash_control * arm_cond_hsh;
803static struct hash_control * arm_shift_hsh;
804static struct hash_control * arm_psr_hsh;
805static struct hash_control * arm_v7m_psr_hsh;
806static struct hash_control * arm_reg_hsh;
807static struct hash_control * arm_reloc_hsh;
808static struct hash_control * arm_barrier_opt_hsh;
809
810/* Stuff needed to resolve the label ambiguity
811 As:
812 ...
813 label: <insn>
814 may differ from:
815 ...
816 label:
817 <insn> */
818
819symbolS * last_label_seen;
820static int label_is_thumb_function_name = FALSE;
821
822/* Literal pool structure. Held on a per-section
823 and per-sub-section basis. */
824
825#define MAX_LITERAL_POOL_SIZE 1024
826typedef struct literal_pool
827{
828 expressionS literals [MAX_LITERAL_POOL_SIZE];
829 unsigned int next_free_entry;
830 unsigned int id;
831 symbolS * symbol;
832 segT section;
833 subsegT sub_section;
834#ifdef OBJ_ELF
835 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
836#endif
837 struct literal_pool * next;
838 unsigned int alignment;
839} literal_pool;
840
841/* Pointer to a linked list of literal pools. */
842literal_pool * list_of_pools = NULL;
843
844typedef enum asmfunc_states
845{
846 OUTSIDE_ASMFUNC,
847 WAITING_ASMFUNC_NAME,
848 WAITING_ENDASMFUNC
849} asmfunc_states;
850
851static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
852
853#ifdef OBJ_ELF
854# define now_it seg_info (now_seg)->tc_segment_info_data.current_it
855#else
856static struct current_it now_it;
857#endif
858
859static inline int
860now_it_compatible (int cond)
861{
862 return (cond & ~1) == (now_it.cc & ~1);
863}
864
865static inline int
866conditional_insn (void)
867{
868 return inst.cond != COND_ALWAYS;
869}
870
871static int in_it_block (void);
872
873static int handle_it_state (void);
874
875static void force_automatic_it_block_close (void);
876
877static void it_fsm_post_encode (void);
878
879#define set_it_insn_type(type) \
880 do \
881 { \
882 inst.it_insn_type = type; \
883 if (handle_it_state () == FAIL) \
884 return; \
885 } \
886 while (0)
887
888#define set_it_insn_type_nonvoid(type, failret) \
889 do \
890 { \
891 inst.it_insn_type = type; \
892 if (handle_it_state () == FAIL) \
893 return failret; \
894 } \
895 while(0)
896
897#define set_it_insn_type_last() \
898 do \
899 { \
900 if (inst.cond == COND_ALWAYS) \
901 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
902 else \
903 set_it_insn_type (INSIDE_IT_LAST_INSN); \
904 } \
905 while (0)
906
907/* Pure syntax. */
908
909/* This array holds the chars that always start a comment. If the
910 pre-processor is disabled, these aren't very useful. */
911char arm_comment_chars[] = "@";
912
913/* This array holds the chars that only start a comment at the beginning of
914 a line. If the line seems to have the form '# 123 filename'
915 .line and .file directives will appear in the pre-processed output. */
916/* Note that input_file.c hand checks for '#' at the beginning of the
917 first line of the input file. This is because the compiler outputs
918 #NO_APP at the beginning of its output. */
919/* Also note that comments like this one will always work. */
920const char line_comment_chars[] = "#";
921
922char arm_line_separator_chars[] = ";";
923
924/* Chars that can be used to separate mant
925 from exp in floating point numbers. */
926const char EXP_CHARS[] = "eE";
927
928/* Chars that mean this number is a floating point constant. */
929/* As in 0f12.456 */
930/* or 0d1.2345e12 */
931
932const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
933
934/* Prefix characters that indicate the start of an immediate
935 value. */
936#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
937
938/* Separator character handling. */
939
940#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
941
942static inline int
943skip_past_char (char ** str, char c)
944{
945 /* PR gas/14987: Allow for whitespace before the expected character. */
946 skip_whitespace (*str);
947
948 if (**str == c)
949 {
950 (*str)++;
951 return SUCCESS;
952 }
953 else
954 return FAIL;
955}
956
957#define skip_past_comma(str) skip_past_char (str, ',')
958
959/* Arithmetic expressions (possibly involving symbols). */
960
961/* Return TRUE if anything in the expression is a bignum. */
962
963static int
964walk_no_bignums (symbolS * sp)
965{
966 if (symbol_get_value_expression (sp)->X_op == O_big)
967 return 1;
968
969 if (symbol_get_value_expression (sp)->X_add_symbol)
970 {
971 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
972 || (symbol_get_value_expression (sp)->X_op_symbol
973 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
974 }
975
976 return 0;
977}
978
979static int in_my_get_expression = 0;
980
981/* Third argument to my_get_expression. */
982#define GE_NO_PREFIX 0
983#define GE_IMM_PREFIX 1
984#define GE_OPT_PREFIX 2
985/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
986 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
987#define GE_OPT_PREFIX_BIG 3
988
989static int
990my_get_expression (expressionS * ep, char ** str, int prefix_mode)
991{
992 char * save_in;
993 segT seg;
994
995 /* In unified syntax, all prefixes are optional. */
996 if (unified_syntax)
997 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
998 : GE_OPT_PREFIX;
999
1000 switch (prefix_mode)
1001 {
1002 case GE_NO_PREFIX: break;
1003 case GE_IMM_PREFIX:
1004 if (!is_immediate_prefix (**str))
1005 {
1006 inst.error = _("immediate expression requires a # prefix");
1007 return FAIL;
1008 }
1009 (*str)++;
1010 break;
1011 case GE_OPT_PREFIX:
1012 case GE_OPT_PREFIX_BIG:
1013 if (is_immediate_prefix (**str))
1014 (*str)++;
1015 break;
1016 default: abort ();
1017 }
1018
1019 memset (ep, 0, sizeof (expressionS));
1020
1021 save_in = input_line_pointer;
1022 input_line_pointer = *str;
1023 in_my_get_expression = 1;
1024 seg = expression (ep);
1025 in_my_get_expression = 0;
1026
1027 if (ep->X_op == O_illegal || ep->X_op == O_absent)
1028 {
1029 /* We found a bad or missing expression in md_operand(). */
1030 *str = input_line_pointer;
1031 input_line_pointer = save_in;
1032 if (inst.error == NULL)
1033 inst.error = (ep->X_op == O_absent
1034 ? _("missing expression") :_("bad expression"));
1035 return 1;
1036 }
1037
1038#ifdef OBJ_AOUT
1039 if (seg != absolute_section
1040 && seg != text_section
1041 && seg != data_section
1042 && seg != bss_section
1043 && seg != undefined_section)
1044 {
1045 inst.error = _("bad segment");
1046 *str = input_line_pointer;
1047 input_line_pointer = save_in;
1048 return 1;
1049 }
1050#else
1051 (void) seg;
1052#endif
1053
1054 /* Get rid of any bignums now, so that we don't generate an error for which
1055 we can't establish a line number later on. Big numbers are never valid
1056 in instructions, which is where this routine is always called. */
1057 if (prefix_mode != GE_OPT_PREFIX_BIG
1058 && (ep->X_op == O_big
1059 || (ep->X_add_symbol
1060 && (walk_no_bignums (ep->X_add_symbol)
1061 || (ep->X_op_symbol
1062 && walk_no_bignums (ep->X_op_symbol))))))
1063 {
1064 inst.error = _("invalid constant");
1065 *str = input_line_pointer;
1066 input_line_pointer = save_in;
1067 return 1;
1068 }
1069
1070 *str = input_line_pointer;
1071 input_line_pointer = save_in;
1072 return 0;
1073}
1074
1075/* Turn a string in input_line_pointer into a floating point constant
1076 of type TYPE, and store the appropriate bytes in *LITP. The number
1077 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1078 returned, or NULL on OK.
1079
1080 Note that fp constants aren't represent in the normal way on the ARM.
1081 In big endian mode, things are as expected. However, in little endian
1082 mode fp constants are big-endian word-wise, and little-endian byte-wise
1083 within the words. For example, (double) 1.1 in big endian mode is
1084 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1085 the byte sequence 99 99 f1 3f 9a 99 99 99.
1086
1087 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1088
1089const char *
1090md_atof (int type, char * litP, int * sizeP)
1091{
1092 int prec;
1093 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1094 char *t;
1095 int i;
1096
1097 switch (type)
1098 {
1099 case 'f':
1100 case 'F':
1101 case 's':
1102 case 'S':
1103 prec = 2;
1104 break;
1105
1106 case 'd':
1107 case 'D':
1108 case 'r':
1109 case 'R':
1110 prec = 4;
1111 break;
1112
1113 case 'x':
1114 case 'X':
1115 prec = 5;
1116 break;
1117
1118 case 'p':
1119 case 'P':
1120 prec = 5;
1121 break;
1122
1123 default:
1124 *sizeP = 0;
1125 return _("Unrecognized or unsupported floating point constant");
1126 }
1127
1128 t = atof_ieee (input_line_pointer, type, words);
1129 if (t)
1130 input_line_pointer = t;
1131 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1132
1133 if (target_big_endian)
1134 {
1135 for (i = 0; i < prec; i++)
1136 {
1137 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1138 litP += sizeof (LITTLENUM_TYPE);
1139 }
1140 }
1141 else
1142 {
1143 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1144 for (i = prec - 1; i >= 0; i--)
1145 {
1146 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1147 litP += sizeof (LITTLENUM_TYPE);
1148 }
1149 else
1150 /* For a 4 byte float the order of elements in `words' is 1 0.
1151 For an 8 byte float the order is 1 0 3 2. */
1152 for (i = 0; i < prec; i += 2)
1153 {
1154 md_number_to_chars (litP, (valueT) words[i + 1],
1155 sizeof (LITTLENUM_TYPE));
1156 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1157 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1158 litP += 2 * sizeof (LITTLENUM_TYPE);
1159 }
1160 }
1161
1162 return NULL;
1163}
1164
1165/* We handle all bad expressions here, so that we can report the faulty
1166 instruction in the error message. */
1167void
1168md_operand (expressionS * exp)
1169{
1170 if (in_my_get_expression)
1171 exp->X_op = O_illegal;
1172}
1173
1174/* Immediate values. */
1175
1176/* Generic immediate-value read function for use in directives.
1177 Accepts anything that 'expression' can fold to a constant.
1178 *val receives the number. */
1179#ifdef OBJ_ELF
1180static int
1181immediate_for_directive (int *val)
1182{
1183 expressionS exp;
1184 exp.X_op = O_illegal;
1185
1186 if (is_immediate_prefix (*input_line_pointer))
1187 {
1188 input_line_pointer++;
1189 expression (&exp);
1190 }
1191
1192 if (exp.X_op != O_constant)
1193 {
1194 as_bad (_("expected #constant"));
1195 ignore_rest_of_line ();
1196 return FAIL;
1197 }
1198 *val = exp.X_add_number;
1199 return SUCCESS;
1200}
1201#endif
1202
1203/* Register parsing. */
1204
1205/* Generic register parser. CCP points to what should be the
1206 beginning of a register name. If it is indeed a valid register
1207 name, advance CCP over it and return the reg_entry structure;
1208 otherwise return NULL. Does not issue diagnostics. */
1209
1210static struct reg_entry *
1211arm_reg_parse_multi (char **ccp)
1212{
1213 char *start = *ccp;
1214 char *p;
1215 struct reg_entry *reg;
1216
1217 skip_whitespace (start);
1218
1219#ifdef REGISTER_PREFIX
1220 if (*start != REGISTER_PREFIX)
1221 return NULL;
1222 start++;
1223#endif
1224#ifdef OPTIONAL_REGISTER_PREFIX
1225 if (*start == OPTIONAL_REGISTER_PREFIX)
1226 start++;
1227#endif
1228
1229 p = start;
1230 if (!ISALPHA (*p) || !is_name_beginner (*p))
1231 return NULL;
1232
1233 do
1234 p++;
1235 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1236
1237 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1238
1239 if (!reg)
1240 return NULL;
1241
1242 *ccp = p;
1243 return reg;
1244}
1245
1246static int
1247arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1248 enum arm_reg_type type)
1249{
1250 /* Alternative syntaxes are accepted for a few register classes. */
1251 switch (type)
1252 {
1253 case REG_TYPE_MVF:
1254 case REG_TYPE_MVD:
1255 case REG_TYPE_MVFX:
1256 case REG_TYPE_MVDX:
1257 /* Generic coprocessor register names are allowed for these. */
1258 if (reg && reg->type == REG_TYPE_CN)
1259 return reg->number;
1260 break;
1261
1262 case REG_TYPE_CP:
1263 /* For backward compatibility, a bare number is valid here. */
1264 {
1265 unsigned long processor = strtoul (start, ccp, 10);
1266 if (*ccp != start && processor <= 15)
1267 return processor;
1268 }
1269
1270 case REG_TYPE_MMXWC:
1271 /* WC includes WCG. ??? I'm not sure this is true for all
1272 instructions that take WC registers. */
1273 if (reg && reg->type == REG_TYPE_MMXWCG)
1274 return reg->number;
1275 break;
1276
1277 default:
1278 break;
1279 }
1280
1281 return FAIL;
1282}
1283
1284/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1285 return value is the register number or FAIL. */
1286
1287static int
1288arm_reg_parse (char **ccp, enum arm_reg_type type)
1289{
1290 char *start = *ccp;
1291 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1292 int ret;
1293
1294 /* Do not allow a scalar (reg+index) to parse as a register. */
1295 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1296 return FAIL;
1297
1298 if (reg && reg->type == type)
1299 return reg->number;
1300
1301 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1302 return ret;
1303
1304 *ccp = start;
1305 return FAIL;
1306}
1307
1308/* Parse a Neon type specifier. *STR should point at the leading '.'
1309 character. Does no verification at this stage that the type fits the opcode
1310 properly. E.g.,
1311
1312 .i32.i32.s16
1313 .s32.f32
1314 .u16
1315
1316 Can all be legally parsed by this function.
1317
1318 Fills in neon_type struct pointer with parsed information, and updates STR
1319 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1320 type, FAIL if not. */
1321
1322static int
1323parse_neon_type (struct neon_type *type, char **str)
1324{
1325 char *ptr = *str;
1326
1327 if (type)
1328 type->elems = 0;
1329
1330 while (type->elems < NEON_MAX_TYPE_ELS)
1331 {
1332 enum neon_el_type thistype = NT_untyped;
1333 unsigned thissize = -1u;
1334
1335 if (*ptr != '.')
1336 break;
1337
1338 ptr++;
1339
1340 /* Just a size without an explicit type. */
1341 if (ISDIGIT (*ptr))
1342 goto parsesize;
1343
1344 switch (TOLOWER (*ptr))
1345 {
1346 case 'i': thistype = NT_integer; break;
1347 case 'f': thistype = NT_float; break;
1348 case 'p': thistype = NT_poly; break;
1349 case 's': thistype = NT_signed; break;
1350 case 'u': thistype = NT_unsigned; break;
1351 case 'd':
1352 thistype = NT_float;
1353 thissize = 64;
1354 ptr++;
1355 goto done;
1356 default:
1357 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1358 return FAIL;
1359 }
1360
1361 ptr++;
1362
1363 /* .f is an abbreviation for .f32. */
1364 if (thistype == NT_float && !ISDIGIT (*ptr))
1365 thissize = 32;
1366 else
1367 {
1368 parsesize:
1369 thissize = strtoul (ptr, &ptr, 10);
1370
1371 if (thissize != 8 && thissize != 16 && thissize != 32
1372 && thissize != 64)
1373 {
1374 as_bad (_("bad size %d in type specifier"), thissize);
1375 return FAIL;
1376 }
1377 }
1378
1379 done:
1380 if (type)
1381 {
1382 type->el[type->elems].type = thistype;
1383 type->el[type->elems].size = thissize;
1384 type->elems++;
1385 }
1386 }
1387
1388 /* Empty/missing type is not a successful parse. */
1389 if (type->elems == 0)
1390 return FAIL;
1391
1392 *str = ptr;
1393
1394 return SUCCESS;
1395}
1396
1397/* Errors may be set multiple times during parsing or bit encoding
1398 (particularly in the Neon bits), but usually the earliest error which is set
1399 will be the most meaningful. Avoid overwriting it with later (cascading)
1400 errors by calling this function. */
1401
1402static void
1403first_error (const char *err)
1404{
1405 if (!inst.error)
1406 inst.error = err;
1407}
1408
1409/* Parse a single type, e.g. ".s32", leading period included. */
1410static int
1411parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1412{
1413 char *str = *ccp;
1414 struct neon_type optype;
1415
1416 if (*str == '.')
1417 {
1418 if (parse_neon_type (&optype, &str) == SUCCESS)
1419 {
1420 if (optype.elems == 1)
1421 *vectype = optype.el[0];
1422 else
1423 {
1424 first_error (_("only one type should be specified for operand"));
1425 return FAIL;
1426 }
1427 }
1428 else
1429 {
1430 first_error (_("vector type expected"));
1431 return FAIL;
1432 }
1433 }
1434 else
1435 return FAIL;
1436
1437 *ccp = str;
1438
1439 return SUCCESS;
1440}
1441
1442/* Special meanings for indices (which have a range of 0-7), which will fit into
1443 a 4-bit integer. */
1444
1445#define NEON_ALL_LANES 15
1446#define NEON_INTERLEAVE_LANES 14
1447
1448/* Parse either a register or a scalar, with an optional type. Return the
1449 register number, and optionally fill in the actual type of the register
1450 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1451 type/index information in *TYPEINFO. */
1452
1453static int
1454parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1455 enum arm_reg_type *rtype,
1456 struct neon_typed_alias *typeinfo)
1457{
1458 char *str = *ccp;
1459 struct reg_entry *reg = arm_reg_parse_multi (&str);
1460 struct neon_typed_alias atype;
1461 struct neon_type_el parsetype;
1462
1463 atype.defined = 0;
1464 atype.index = -1;
1465 atype.eltype.type = NT_invtype;
1466 atype.eltype.size = -1;
1467
1468 /* Try alternate syntax for some types of register. Note these are mutually
1469 exclusive with the Neon syntax extensions. */
1470 if (reg == NULL)
1471 {
1472 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1473 if (altreg != FAIL)
1474 *ccp = str;
1475 if (typeinfo)
1476 *typeinfo = atype;
1477 return altreg;
1478 }
1479
1480 /* Undo polymorphism when a set of register types may be accepted. */
1481 if ((type == REG_TYPE_NDQ
1482 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1483 || (type == REG_TYPE_VFSD
1484 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1485 || (type == REG_TYPE_NSDQ
1486 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1487 || reg->type == REG_TYPE_NQ))
1488 || (type == REG_TYPE_MMXWC
1489 && (reg->type == REG_TYPE_MMXWCG)))
1490 type = (enum arm_reg_type) reg->type;
1491
1492 if (type != reg->type)
1493 return FAIL;
1494
1495 if (reg->neon)
1496 atype = *reg->neon;
1497
1498 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1499 {
1500 if ((atype.defined & NTA_HASTYPE) != 0)
1501 {
1502 first_error (_("can't redefine type for operand"));
1503 return FAIL;
1504 }
1505 atype.defined |= NTA_HASTYPE;
1506 atype.eltype = parsetype;
1507 }
1508
1509 if (skip_past_char (&str, '[') == SUCCESS)
1510 {
1511 if (type != REG_TYPE_VFD)
1512 {
1513 first_error (_("only D registers may be indexed"));
1514 return FAIL;
1515 }
1516
1517 if ((atype.defined & NTA_HASINDEX) != 0)
1518 {
1519 first_error (_("can't change index for operand"));
1520 return FAIL;
1521 }
1522
1523 atype.defined |= NTA_HASINDEX;
1524
1525 if (skip_past_char (&str, ']') == SUCCESS)
1526 atype.index = NEON_ALL_LANES;
1527 else
1528 {
1529 expressionS exp;
1530
1531 my_get_expression (&exp, &str, GE_NO_PREFIX);
1532
1533 if (exp.X_op != O_constant)
1534 {
1535 first_error (_("constant expression required"));
1536 return FAIL;
1537 }
1538
1539 if (skip_past_char (&str, ']') == FAIL)
1540 return FAIL;
1541
1542 atype.index = exp.X_add_number;
1543 }
1544 }
1545
1546 if (typeinfo)
1547 *typeinfo = atype;
1548
1549 if (rtype)
1550 *rtype = type;
1551
1552 *ccp = str;
1553
1554 return reg->number;
1555}
1556
1557/* Like arm_reg_parse, but allow allow the following extra features:
1558 - If RTYPE is non-zero, return the (possibly restricted) type of the
1559 register (e.g. Neon double or quad reg when either has been requested).
1560 - If this is a Neon vector type with additional type information, fill
1561 in the struct pointed to by VECTYPE (if non-NULL).
1562 This function will fault on encountering a scalar. */
1563
1564static int
1565arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1566 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1567{
1568 struct neon_typed_alias atype;
1569 char *str = *ccp;
1570 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1571
1572 if (reg == FAIL)
1573 return FAIL;
1574
1575 /* Do not allow regname(... to parse as a register. */
1576 if (*str == '(')
1577 return FAIL;
1578
1579 /* Do not allow a scalar (reg+index) to parse as a register. */
1580 if ((atype.defined & NTA_HASINDEX) != 0)
1581 {
1582 first_error (_("register operand expected, but got scalar"));
1583 return FAIL;
1584 }
1585
1586 if (vectype)
1587 *vectype = atype.eltype;
1588
1589 *ccp = str;
1590
1591 return reg;
1592}
1593
1594#define NEON_SCALAR_REG(X) ((X) >> 4)
1595#define NEON_SCALAR_INDEX(X) ((X) & 15)
1596
1597/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1598 have enough information to be able to do a good job bounds-checking. So, we
1599 just do easy checks here, and do further checks later. */
1600
1601static int
1602parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1603{
1604 int reg;
1605 char *str = *ccp;
1606 struct neon_typed_alias atype;
1607
1608 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1609
1610 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1611 return FAIL;
1612
1613 if (atype.index == NEON_ALL_LANES)
1614 {
1615 first_error (_("scalar must have an index"));
1616 return FAIL;
1617 }
1618 else if (atype.index >= 64 / elsize)
1619 {
1620 first_error (_("scalar index out of range"));
1621 return FAIL;
1622 }
1623
1624 if (type)
1625 *type = atype.eltype;
1626
1627 *ccp = str;
1628
1629 return reg * 16 + atype.index;
1630}
1631
1632/* Parse an ARM register list. Returns the bitmask, or FAIL. */
1633
1634static long
1635parse_reg_list (char ** strp)
1636{
1637 char * str = * strp;
1638 long range = 0;
1639 int another_range;
1640
1641 /* We come back here if we get ranges concatenated by '+' or '|'. */
1642 do
1643 {
1644 skip_whitespace (str);
1645
1646 another_range = 0;
1647
1648 if (*str == '{')
1649 {
1650 int in_range = 0;
1651 int cur_reg = -1;
1652
1653 str++;
1654 do
1655 {
1656 int reg;
1657
1658 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1659 {
1660 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1661 return FAIL;
1662 }
1663
1664 if (in_range)
1665 {
1666 int i;
1667
1668 if (reg <= cur_reg)
1669 {
1670 first_error (_("bad range in register list"));
1671 return FAIL;
1672 }
1673
1674 for (i = cur_reg + 1; i < reg; i++)
1675 {
1676 if (range & (1 << i))
1677 as_tsktsk
1678 (_("Warning: duplicated register (r%d) in register list"),
1679 i);
1680 else
1681 range |= 1 << i;
1682 }
1683 in_range = 0;
1684 }
1685
1686 if (range & (1 << reg))
1687 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1688 reg);
1689 else if (reg <= cur_reg)
1690 as_tsktsk (_("Warning: register range not in ascending order"));
1691
1692 range |= 1 << reg;
1693 cur_reg = reg;
1694 }
1695 while (skip_past_comma (&str) != FAIL
1696 || (in_range = 1, *str++ == '-'));
1697 str--;
1698
1699 if (skip_past_char (&str, '}') == FAIL)
1700 {
1701 first_error (_("missing `}'"));
1702 return FAIL;
1703 }
1704 }
1705 else
1706 {
1707 expressionS exp;
1708
1709 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1710 return FAIL;
1711
1712 if (exp.X_op == O_constant)
1713 {
1714 if (exp.X_add_number
1715 != (exp.X_add_number & 0x0000ffff))
1716 {
1717 inst.error = _("invalid register mask");
1718 return FAIL;
1719 }
1720
1721 if ((range & exp.X_add_number) != 0)
1722 {
1723 int regno = range & exp.X_add_number;
1724
1725 regno &= -regno;
1726 regno = (1 << regno) - 1;
1727 as_tsktsk
1728 (_("Warning: duplicated register (r%d) in register list"),
1729 regno);
1730 }
1731
1732 range |= exp.X_add_number;
1733 }
1734 else
1735 {
1736 if (inst.reloc.type != 0)
1737 {
1738 inst.error = _("expression too complex");
1739 return FAIL;
1740 }
1741
1742 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1743 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1744 inst.reloc.pc_rel = 0;
1745 }
1746 }
1747
1748 if (*str == '|' || *str == '+')
1749 {
1750 str++;
1751 another_range = 1;
1752 }
1753 }
1754 while (another_range);
1755
1756 *strp = str;
1757 return range;
1758}
1759
1760/* Types of registers in a list. */
1761
1762enum reg_list_els
1763{
1764 REGLIST_VFP_S,
1765 REGLIST_VFP_D,
1766 REGLIST_NEON_D
1767};
1768
1769/* Parse a VFP register list. If the string is invalid return FAIL.
1770 Otherwise return the number of registers, and set PBASE to the first
1771 register. Parses registers of type ETYPE.
1772 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1773 - Q registers can be used to specify pairs of D registers
1774 - { } can be omitted from around a singleton register list
1775 FIXME: This is not implemented, as it would require backtracking in
1776 some cases, e.g.:
1777 vtbl.8 d3,d4,d5
1778 This could be done (the meaning isn't really ambiguous), but doesn't
1779 fit in well with the current parsing framework.
1780 - 32 D registers may be used (also true for VFPv3).
1781 FIXME: Types are ignored in these register lists, which is probably a
1782 bug. */
1783
1784static int
1785parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1786{
1787 char *str = *ccp;
1788 int base_reg;
1789 int new_base;
1790 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1791 int max_regs = 0;
1792 int count = 0;
1793 int warned = 0;
1794 unsigned long mask = 0;
1795 int i;
1796
1797 if (skip_past_char (&str, '{') == FAIL)
1798 {
1799 inst.error = _("expecting {");
1800 return FAIL;
1801 }
1802
1803 switch (etype)
1804 {
1805 case REGLIST_VFP_S:
1806 regtype = REG_TYPE_VFS;
1807 max_regs = 32;
1808 break;
1809
1810 case REGLIST_VFP_D:
1811 regtype = REG_TYPE_VFD;
1812 break;
1813
1814 case REGLIST_NEON_D:
1815 regtype = REG_TYPE_NDQ;
1816 break;
1817 }
1818
1819 if (etype != REGLIST_VFP_S)
1820 {
1821 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1822 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1823 {
1824 max_regs = 32;
1825 if (thumb_mode)
1826 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1827 fpu_vfp_ext_d32);
1828 else
1829 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1830 fpu_vfp_ext_d32);
1831 }
1832 else
1833 max_regs = 16;
1834 }
1835
1836 base_reg = max_regs;
1837
1838 do
1839 {
1840 int setmask = 1, addregs = 1;
1841
1842 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
1843
1844 if (new_base == FAIL)
1845 {
1846 first_error (_(reg_expected_msgs[regtype]));
1847 return FAIL;
1848 }
1849
1850 if (new_base >= max_regs)
1851 {
1852 first_error (_("register out of range in list"));
1853 return FAIL;
1854 }
1855
1856 /* Note: a value of 2 * n is returned for the register Q<n>. */
1857 if (regtype == REG_TYPE_NQ)
1858 {
1859 setmask = 3;
1860 addregs = 2;
1861 }
1862
1863 if (new_base < base_reg)
1864 base_reg = new_base;
1865
1866 if (mask & (setmask << new_base))
1867 {
1868 first_error (_("invalid register list"));
1869 return FAIL;
1870 }
1871
1872 if ((mask >> new_base) != 0 && ! warned)
1873 {
1874 as_tsktsk (_("register list not in ascending order"));
1875 warned = 1;
1876 }
1877
1878 mask |= setmask << new_base;
1879 count += addregs;
1880
1881 if (*str == '-') /* We have the start of a range expression */
1882 {
1883 int high_range;
1884
1885 str++;
1886
1887 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1888 == FAIL)
1889 {
1890 inst.error = gettext (reg_expected_msgs[regtype]);
1891 return FAIL;
1892 }
1893
1894 if (high_range >= max_regs)
1895 {
1896 first_error (_("register out of range in list"));
1897 return FAIL;
1898 }
1899
1900 if (regtype == REG_TYPE_NQ)
1901 high_range = high_range + 1;
1902
1903 if (high_range <= new_base)
1904 {
1905 inst.error = _("register range not in ascending order");
1906 return FAIL;
1907 }
1908
1909 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1910 {
1911 if (mask & (setmask << new_base))
1912 {
1913 inst.error = _("invalid register list");
1914 return FAIL;
1915 }
1916
1917 mask |= setmask << new_base;
1918 count += addregs;
1919 }
1920 }
1921 }
1922 while (skip_past_comma (&str) != FAIL);
1923
1924 str++;
1925
1926 /* Sanity check -- should have raised a parse error above. */
1927 if (count == 0 || count > max_regs)
1928 abort ();
1929
1930 *pbase = base_reg;
1931
1932 /* Final test -- the registers must be consecutive. */
1933 mask >>= base_reg;
1934 for (i = 0; i < count; i++)
1935 {
1936 if ((mask & (1u << i)) == 0)
1937 {
1938 inst.error = _("non-contiguous register range");
1939 return FAIL;
1940 }
1941 }
1942
1943 *ccp = str;
1944
1945 return count;
1946}
1947
1948/* True if two alias types are the same. */
1949
1950static bfd_boolean
1951neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1952{
1953 if (!a && !b)
1954 return TRUE;
1955
1956 if (!a || !b)
1957 return FALSE;
1958
1959 if (a->defined != b->defined)
1960 return FALSE;
1961
1962 if ((a->defined & NTA_HASTYPE) != 0
1963 && (a->eltype.type != b->eltype.type
1964 || a->eltype.size != b->eltype.size))
1965 return FALSE;
1966
1967 if ((a->defined & NTA_HASINDEX) != 0
1968 && (a->index != b->index))
1969 return FALSE;
1970
1971 return TRUE;
1972}
1973
1974/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1975 The base register is put in *PBASE.
1976 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1977 the return value.
1978 The register stride (minus one) is put in bit 4 of the return value.
1979 Bits [6:5] encode the list length (minus one).
1980 The type of the list elements is put in *ELTYPE, if non-NULL. */
1981
1982#define NEON_LANE(X) ((X) & 0xf)
1983#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1984#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1985
1986static int
1987parse_neon_el_struct_list (char **str, unsigned *pbase,
1988 struct neon_type_el *eltype)
1989{
1990 char *ptr = *str;
1991 int base_reg = -1;
1992 int reg_incr = -1;
1993 int count = 0;
1994 int lane = -1;
1995 int leading_brace = 0;
1996 enum arm_reg_type rtype = REG_TYPE_NDQ;
1997 const char *const incr_error = _("register stride must be 1 or 2");
1998 const char *const type_error = _("mismatched element/structure types in list");
1999 struct neon_typed_alias firsttype;
2000 firsttype.defined = 0;
2001 firsttype.eltype.type = NT_invtype;
2002 firsttype.eltype.size = -1;
2003 firsttype.index = -1;
2004
2005 if (skip_past_char (&ptr, '{') == SUCCESS)
2006 leading_brace = 1;
2007
2008 do
2009 {
2010 struct neon_typed_alias atype;
2011 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2012
2013 if (getreg == FAIL)
2014 {
2015 first_error (_(reg_expected_msgs[rtype]));
2016 return FAIL;
2017 }
2018
2019 if (base_reg == -1)
2020 {
2021 base_reg = getreg;
2022 if (rtype == REG_TYPE_NQ)
2023 {
2024 reg_incr = 1;
2025 }
2026 firsttype = atype;
2027 }
2028 else if (reg_incr == -1)
2029 {
2030 reg_incr = getreg - base_reg;
2031 if (reg_incr < 1 || reg_incr > 2)
2032 {
2033 first_error (_(incr_error));
2034 return FAIL;
2035 }
2036 }
2037 else if (getreg != base_reg + reg_incr * count)
2038 {
2039 first_error (_(incr_error));
2040 return FAIL;
2041 }
2042
2043 if (! neon_alias_types_same (&atype, &firsttype))
2044 {
2045 first_error (_(type_error));
2046 return FAIL;
2047 }
2048
2049 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2050 modes. */
2051 if (ptr[0] == '-')
2052 {
2053 struct neon_typed_alias htype;
2054 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2055 if (lane == -1)
2056 lane = NEON_INTERLEAVE_LANES;
2057 else if (lane != NEON_INTERLEAVE_LANES)
2058 {
2059 first_error (_(type_error));
2060 return FAIL;
2061 }
2062 if (reg_incr == -1)
2063 reg_incr = 1;
2064 else if (reg_incr != 1)
2065 {
2066 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2067 return FAIL;
2068 }
2069 ptr++;
2070 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2071 if (hireg == FAIL)
2072 {
2073 first_error (_(reg_expected_msgs[rtype]));
2074 return FAIL;
2075 }
2076 if (! neon_alias_types_same (&htype, &firsttype))
2077 {
2078 first_error (_(type_error));
2079 return FAIL;
2080 }
2081 count += hireg + dregs - getreg;
2082 continue;
2083 }
2084
2085 /* If we're using Q registers, we can't use [] or [n] syntax. */
2086 if (rtype == REG_TYPE_NQ)
2087 {
2088 count += 2;
2089 continue;
2090 }
2091
2092 if ((atype.defined & NTA_HASINDEX) != 0)
2093 {
2094 if (lane == -1)
2095 lane = atype.index;
2096 else if (lane != atype.index)
2097 {
2098 first_error (_(type_error));
2099 return FAIL;
2100 }
2101 }
2102 else if (lane == -1)
2103 lane = NEON_INTERLEAVE_LANES;
2104 else if (lane != NEON_INTERLEAVE_LANES)
2105 {
2106 first_error (_(type_error));
2107 return FAIL;
2108 }
2109 count++;
2110 }
2111 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2112
2113 /* No lane set by [x]. We must be interleaving structures. */
2114 if (lane == -1)
2115 lane = NEON_INTERLEAVE_LANES;
2116
2117 /* Sanity check. */
2118 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2119 || (count > 1 && reg_incr == -1))
2120 {
2121 first_error (_("error parsing element/structure list"));
2122 return FAIL;
2123 }
2124
2125 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2126 {
2127 first_error (_("expected }"));
2128 return FAIL;
2129 }
2130
2131 if (reg_incr == -1)
2132 reg_incr = 1;
2133
2134 if (eltype)
2135 *eltype = firsttype.eltype;
2136
2137 *pbase = base_reg;
2138 *str = ptr;
2139
2140 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2141}
2142
2143/* Parse an explicit relocation suffix on an expression. This is
2144 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2145 arm_reloc_hsh contains no entries, so this function can only
2146 succeed if there is no () after the word. Returns -1 on error,
2147 BFD_RELOC_UNUSED if there wasn't any suffix. */
2148
2149static int
2150parse_reloc (char **str)
2151{
2152 struct reloc_entry *r;
2153 char *p, *q;
2154
2155 if (**str != '(')
2156 return BFD_RELOC_UNUSED;
2157
2158 p = *str + 1;
2159 q = p;
2160
2161 while (*q && *q != ')' && *q != ',')
2162 q++;
2163 if (*q != ')')
2164 return -1;
2165
2166 if ((r = (struct reloc_entry *)
2167 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2168 return -1;
2169
2170 *str = q + 1;
2171 return r->reloc;
2172}
2173
2174/* Directives: register aliases. */
2175
2176static struct reg_entry *
2177insert_reg_alias (char *str, unsigned number, int type)
2178{
2179 struct reg_entry *new_reg;
2180 const char *name;
2181
2182 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2183 {
2184 if (new_reg->builtin)
2185 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2186
2187 /* Only warn about a redefinition if it's not defined as the
2188 same register. */
2189 else if (new_reg->number != number || new_reg->type != type)
2190 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2191
2192 return NULL;
2193 }
2194
2195 name = xstrdup (str);
2196 new_reg = XNEW (struct reg_entry);
2197
2198 new_reg->name = name;
2199 new_reg->number = number;
2200 new_reg->type = type;
2201 new_reg->builtin = FALSE;
2202 new_reg->neon = NULL;
2203
2204 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2205 abort ();
2206
2207 return new_reg;
2208}
2209
2210static void
2211insert_neon_reg_alias (char *str, int number, int type,
2212 struct neon_typed_alias *atype)
2213{
2214 struct reg_entry *reg = insert_reg_alias (str, number, type);
2215
2216 if (!reg)
2217 {
2218 first_error (_("attempt to redefine typed alias"));
2219 return;
2220 }
2221
2222 if (atype)
2223 {
2224 reg->neon = XNEW (struct neon_typed_alias);
2225 *reg->neon = *atype;
2226 }
2227}
2228
2229/* Look for the .req directive. This is of the form:
2230
2231 new_register_name .req existing_register_name
2232
2233 If we find one, or if it looks sufficiently like one that we want to
2234 handle any error here, return TRUE. Otherwise return FALSE. */
2235
2236static bfd_boolean
2237create_register_alias (char * newname, char *p)
2238{
2239 struct reg_entry *old;
2240 char *oldname, *nbuf;
2241 size_t nlen;
2242
2243 /* The input scrubber ensures that whitespace after the mnemonic is
2244 collapsed to single spaces. */
2245 oldname = p;
2246 if (strncmp (oldname, " .req ", 6) != 0)
2247 return FALSE;
2248
2249 oldname += 6;
2250 if (*oldname == '\0')
2251 return FALSE;
2252
2253 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2254 if (!old)
2255 {
2256 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2257 return TRUE;
2258 }
2259
2260 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2261 the desired alias name, and p points to its end. If not, then
2262 the desired alias name is in the global original_case_string. */
2263#ifdef TC_CASE_SENSITIVE
2264 nlen = p - newname;
2265#else
2266 newname = original_case_string;
2267 nlen = strlen (newname);
2268#endif
2269
2270 nbuf = xmalloc (nlen + 1);
2271 memcpy (nbuf, newname, nlen);
2272 nbuf[nlen] = '\0';
2273
2274 /* Create aliases under the new name as stated; an all-lowercase
2275 version of the new name; and an all-uppercase version of the new
2276 name. */
2277 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2278 {
2279 for (p = nbuf; *p; p++)
2280 *p = TOUPPER (*p);
2281
2282 if (strncmp (nbuf, newname, nlen))
2283 {
2284 /* If this attempt to create an additional alias fails, do not bother
2285 trying to create the all-lower case alias. We will fail and issue
2286 a second, duplicate error message. This situation arises when the
2287 programmer does something like:
2288 foo .req r0
2289 Foo .req r1
2290 The second .req creates the "Foo" alias but then fails to create
2291 the artificial FOO alias because it has already been created by the
2292 first .req. */
2293 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2294 {
2295 free (nbuf);
2296 return TRUE;
2297 }
2298 }
2299
2300 for (p = nbuf; *p; p++)
2301 *p = TOLOWER (*p);
2302
2303 if (strncmp (nbuf, newname, nlen))
2304 insert_reg_alias (nbuf, old->number, old->type);
2305 }
2306
2307 free (nbuf);
2308 return TRUE;
2309}
2310
2311/* Create a Neon typed/indexed register alias using directives, e.g.:
2312 X .dn d5.s32[1]
2313 Y .qn 6.s16
2314 Z .dn d7
2315 T .dn Z[0]
2316 These typed registers can be used instead of the types specified after the
2317 Neon mnemonic, so long as all operands given have types. Types can also be
2318 specified directly, e.g.:
2319 vadd d0.s32, d1.s32, d2.s32 */
2320
2321static bfd_boolean
2322create_neon_reg_alias (char *newname, char *p)
2323{
2324 enum arm_reg_type basetype;
2325 struct reg_entry *basereg;
2326 struct reg_entry mybasereg;
2327 struct neon_type ntype;
2328 struct neon_typed_alias typeinfo;
2329 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2330 int namelen;
2331
2332 typeinfo.defined = 0;
2333 typeinfo.eltype.type = NT_invtype;
2334 typeinfo.eltype.size = -1;
2335 typeinfo.index = -1;
2336
2337 nameend = p;
2338
2339 if (strncmp (p, " .dn ", 5) == 0)
2340 basetype = REG_TYPE_VFD;
2341 else if (strncmp (p, " .qn ", 5) == 0)
2342 basetype = REG_TYPE_NQ;
2343 else
2344 return FALSE;
2345
2346 p += 5;
2347
2348 if (*p == '\0')
2349 return FALSE;
2350
2351 basereg = arm_reg_parse_multi (&p);
2352
2353 if (basereg && basereg->type != basetype)
2354 {
2355 as_bad (_("bad type for register"));
2356 return FALSE;
2357 }
2358
2359 if (basereg == NULL)
2360 {
2361 expressionS exp;
2362 /* Try parsing as an integer. */
2363 my_get_expression (&exp, &p, GE_NO_PREFIX);
2364 if (exp.X_op != O_constant)
2365 {
2366 as_bad (_("expression must be constant"));
2367 return FALSE;
2368 }
2369 basereg = &mybasereg;
2370 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2371 : exp.X_add_number;
2372 basereg->neon = 0;
2373 }
2374
2375 if (basereg->neon)
2376 typeinfo = *basereg->neon;
2377
2378 if (parse_neon_type (&ntype, &p) == SUCCESS)
2379 {
2380 /* We got a type. */
2381 if (typeinfo.defined & NTA_HASTYPE)
2382 {
2383 as_bad (_("can't redefine the type of a register alias"));
2384 return FALSE;
2385 }
2386
2387 typeinfo.defined |= NTA_HASTYPE;
2388 if (ntype.elems != 1)
2389 {
2390 as_bad (_("you must specify a single type only"));
2391 return FALSE;
2392 }
2393 typeinfo.eltype = ntype.el[0];
2394 }
2395
2396 if (skip_past_char (&p, '[') == SUCCESS)
2397 {
2398 expressionS exp;
2399 /* We got a scalar index. */
2400
2401 if (typeinfo.defined & NTA_HASINDEX)
2402 {
2403 as_bad (_("can't redefine the index of a scalar alias"));
2404 return FALSE;
2405 }
2406
2407 my_get_expression (&exp, &p, GE_NO_PREFIX);
2408
2409 if (exp.X_op != O_constant)
2410 {
2411 as_bad (_("scalar index must be constant"));
2412 return FALSE;
2413 }
2414
2415 typeinfo.defined |= NTA_HASINDEX;
2416 typeinfo.index = exp.X_add_number;
2417
2418 if (skip_past_char (&p, ']') == FAIL)
2419 {
2420 as_bad (_("expecting ]"));
2421 return FALSE;
2422 }
2423 }
2424
2425 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2426 the desired alias name, and p points to its end. If not, then
2427 the desired alias name is in the global original_case_string. */
2428#ifdef TC_CASE_SENSITIVE
2429 namelen = nameend - newname;
2430#else
2431 newname = original_case_string;
2432 namelen = strlen (newname);
2433#endif
2434
2435 namebuf = xmalloc (namelen + 1);
2436 strncpy (namebuf, newname, namelen);
2437 namebuf[namelen] = '\0';
2438
2439 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2440 typeinfo.defined != 0 ? &typeinfo : NULL);
2441
2442 /* Insert name in all uppercase. */
2443 for (p = namebuf; *p; p++)
2444 *p = TOUPPER (*p);
2445
2446 if (strncmp (namebuf, newname, namelen))
2447 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2448 typeinfo.defined != 0 ? &typeinfo : NULL);
2449
2450 /* Insert name in all lowercase. */
2451 for (p = namebuf; *p; p++)
2452 *p = TOLOWER (*p);
2453
2454 if (strncmp (namebuf, newname, namelen))
2455 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2456 typeinfo.defined != 0 ? &typeinfo : NULL);
2457
2458 free (namebuf);
2459 return TRUE;
2460}
2461
2462/* Should never be called, as .req goes between the alias and the
2463 register name, not at the beginning of the line. */
2464
2465static void
2466s_req (int a ATTRIBUTE_UNUSED)
2467{
2468 as_bad (_("invalid syntax for .req directive"));
2469}
2470
2471static void
2472s_dn (int a ATTRIBUTE_UNUSED)
2473{
2474 as_bad (_("invalid syntax for .dn directive"));
2475}
2476
2477static void
2478s_qn (int a ATTRIBUTE_UNUSED)
2479{
2480 as_bad (_("invalid syntax for .qn directive"));
2481}
2482
2483/* The .unreq directive deletes an alias which was previously defined
2484 by .req. For example:
2485
2486 my_alias .req r11
2487 .unreq my_alias */
2488
2489static void
2490s_unreq (int a ATTRIBUTE_UNUSED)
2491{
2492 char * name;
2493 char saved_char;
2494
2495 name = input_line_pointer;
2496
2497 while (*input_line_pointer != 0
2498 && *input_line_pointer != ' '
2499 && *input_line_pointer != '\n')
2500 ++input_line_pointer;
2501
2502 saved_char = *input_line_pointer;
2503 *input_line_pointer = 0;
2504
2505 if (!*name)
2506 as_bad (_("invalid syntax for .unreq directive"));
2507 else
2508 {
2509 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2510 name);
2511
2512 if (!reg)
2513 as_bad (_("unknown register alias '%s'"), name);
2514 else if (reg->builtin)
2515 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2516 name);
2517 else
2518 {
2519 char * p;
2520 char * nbuf;
2521
2522 hash_delete (arm_reg_hsh, name, FALSE);
2523 free ((char *) reg->name);
2524 if (reg->neon)
2525 free (reg->neon);
2526 free (reg);
2527
2528 /* Also locate the all upper case and all lower case versions.
2529 Do not complain if we cannot find one or the other as it
2530 was probably deleted above. */
2531
2532 nbuf = strdup (name);
2533 for (p = nbuf; *p; p++)
2534 *p = TOUPPER (*p);
2535 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2536 if (reg)
2537 {
2538 hash_delete (arm_reg_hsh, nbuf, FALSE);
2539 free ((char *) reg->name);
2540 if (reg->neon)
2541 free (reg->neon);
2542 free (reg);
2543 }
2544
2545 for (p = nbuf; *p; p++)
2546 *p = TOLOWER (*p);
2547 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2548 if (reg)
2549 {
2550 hash_delete (arm_reg_hsh, nbuf, FALSE);
2551 free ((char *) reg->name);
2552 if (reg->neon)
2553 free (reg->neon);
2554 free (reg);
2555 }
2556
2557 free (nbuf);
2558 }
2559 }
2560
2561 *input_line_pointer = saved_char;
2562 demand_empty_rest_of_line ();
2563}
2564
2565/* Directives: Instruction set selection. */
2566
2567#ifdef OBJ_ELF
2568/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2569 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2570 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2571 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2572
2573/* Create a new mapping symbol for the transition to STATE. */
2574
2575static void
2576make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2577{
2578 symbolS * symbolP;
2579 const char * symname;
2580 int type;
2581
2582 switch (state)
2583 {
2584 case MAP_DATA:
2585 symname = "$d";
2586 type = BSF_NO_FLAGS;
2587 break;
2588 case MAP_ARM:
2589 symname = "$a";
2590 type = BSF_NO_FLAGS;
2591 break;
2592 case MAP_THUMB:
2593 symname = "$t";
2594 type = BSF_NO_FLAGS;
2595 break;
2596 default:
2597 abort ();
2598 }
2599
2600 symbolP = symbol_new (symname, now_seg, value, frag);
2601 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2602
2603 switch (state)
2604 {
2605 case MAP_ARM:
2606 THUMB_SET_FUNC (symbolP, 0);
2607 ARM_SET_THUMB (symbolP, 0);
2608 ARM_SET_INTERWORK (symbolP, support_interwork);
2609 break;
2610
2611 case MAP_THUMB:
2612 THUMB_SET_FUNC (symbolP, 1);
2613 ARM_SET_THUMB (symbolP, 1);
2614 ARM_SET_INTERWORK (symbolP, support_interwork);
2615 break;
2616
2617 case MAP_DATA:
2618 default:
2619 break;
2620 }
2621
2622 /* Save the mapping symbols for future reference. Also check that
2623 we do not place two mapping symbols at the same offset within a
2624 frag. We'll handle overlap between frags in
2625 check_mapping_symbols.
2626
2627 If .fill or other data filling directive generates zero sized data,
2628 the mapping symbol for the following code will have the same value
2629 as the one generated for the data filling directive. In this case,
2630 we replace the old symbol with the new one at the same address. */
2631 if (value == 0)
2632 {
2633 if (frag->tc_frag_data.first_map != NULL)
2634 {
2635 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2636 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2637 }
2638 frag->tc_frag_data.first_map = symbolP;
2639 }
2640 if (frag->tc_frag_data.last_map != NULL)
2641 {
2642 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2643 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2644 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2645 }
2646 frag->tc_frag_data.last_map = symbolP;
2647}
2648
2649/* We must sometimes convert a region marked as code to data during
2650 code alignment, if an odd number of bytes have to be padded. The
2651 code mapping symbol is pushed to an aligned address. */
2652
2653static void
2654insert_data_mapping_symbol (enum mstate state,
2655 valueT value, fragS *frag, offsetT bytes)
2656{
2657 /* If there was already a mapping symbol, remove it. */
2658 if (frag->tc_frag_data.last_map != NULL
2659 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2660 {
2661 symbolS *symp = frag->tc_frag_data.last_map;
2662
2663 if (value == 0)
2664 {
2665 know (frag->tc_frag_data.first_map == symp);
2666 frag->tc_frag_data.first_map = NULL;
2667 }
2668 frag->tc_frag_data.last_map = NULL;
2669 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2670 }
2671
2672 make_mapping_symbol (MAP_DATA, value, frag);
2673 make_mapping_symbol (state, value + bytes, frag);
2674}
2675
2676static void mapping_state_2 (enum mstate state, int max_chars);
2677
2678/* Set the mapping state to STATE. Only call this when about to
2679 emit some STATE bytes to the file. */
2680
2681#define TRANSITION(from, to) (mapstate == (from) && state == (to))
2682void
2683mapping_state (enum mstate state)
2684{
2685 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2686
2687 if (mapstate == state)
2688 /* The mapping symbol has already been emitted.
2689 There is nothing else to do. */
2690 return;
2691
2692 if (state == MAP_ARM || state == MAP_THUMB)
2693 /* PR gas/12931
2694 All ARM instructions require 4-byte alignment.
2695 (Almost) all Thumb instructions require 2-byte alignment.
2696
2697 When emitting instructions into any section, mark the section
2698 appropriately.
2699
2700 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2701 but themselves require 2-byte alignment; this applies to some
2702 PC- relative forms. However, these cases will invovle implicit
2703 literal pool generation or an explicit .align >=2, both of
2704 which will cause the section to me marked with sufficient
2705 alignment. Thus, we don't handle those cases here. */
2706 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2707
2708 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2709 /* This case will be evaluated later. */
2710 return;
2711
2712 mapping_state_2 (state, 0);
2713}
2714
2715/* Same as mapping_state, but MAX_CHARS bytes have already been
2716 allocated. Put the mapping symbol that far back. */
2717
2718static void
2719mapping_state_2 (enum mstate state, int max_chars)
2720{
2721 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2722
2723 if (!SEG_NORMAL (now_seg))
2724 return;
2725
2726 if (mapstate == state)
2727 /* The mapping symbol has already been emitted.
2728 There is nothing else to do. */
2729 return;
2730
2731 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2732 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2733 {
2734 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2735 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2736
2737 if (add_symbol)
2738 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2739 }
2740
2741 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2742 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2743}
2744#undef TRANSITION
2745#else
2746#define mapping_state(x) ((void)0)
2747#define mapping_state_2(x, y) ((void)0)
2748#endif
2749
2750/* Find the real, Thumb encoded start of a Thumb function. */
2751
2752#ifdef OBJ_COFF
2753static symbolS *
2754find_real_start (symbolS * symbolP)
2755{
2756 char * real_start;
2757 const char * name = S_GET_NAME (symbolP);
2758 symbolS * new_target;
2759
2760 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2761#define STUB_NAME ".real_start_of"
2762
2763 if (name == NULL)
2764 abort ();
2765
2766 /* The compiler may generate BL instructions to local labels because
2767 it needs to perform a branch to a far away location. These labels
2768 do not have a corresponding ".real_start_of" label. We check
2769 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2770 the ".real_start_of" convention for nonlocal branches. */
2771 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2772 return symbolP;
2773
2774 real_start = concat (STUB_NAME, name, NULL);
2775 new_target = symbol_find (real_start);
2776 free (real_start);
2777
2778 if (new_target == NULL)
2779 {
2780 as_warn (_("Failed to find real start of function: %s\n"), name);
2781 new_target = symbolP;
2782 }
2783
2784 return new_target;
2785}
2786#endif
2787
2788static void
2789opcode_select (int width)
2790{
2791 switch (width)
2792 {
2793 case 16:
2794 if (! thumb_mode)
2795 {
2796 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2797 as_bad (_("selected processor does not support THUMB opcodes"));
2798
2799 thumb_mode = 1;
2800 /* No need to force the alignment, since we will have been
2801 coming from ARM mode, which is word-aligned. */
2802 record_alignment (now_seg, 1);
2803 }
2804 break;
2805
2806 case 32:
2807 if (thumb_mode)
2808 {
2809 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2810 as_bad (_("selected processor does not support ARM opcodes"));
2811
2812 thumb_mode = 0;
2813
2814 if (!need_pass_2)
2815 frag_align (2, 0, 0);
2816
2817 record_alignment (now_seg, 1);
2818 }
2819 break;
2820
2821 default:
2822 as_bad (_("invalid instruction size selected (%d)"), width);
2823 }
2824}
2825
2826static void
2827s_arm (int ignore ATTRIBUTE_UNUSED)
2828{
2829 opcode_select (32);
2830 demand_empty_rest_of_line ();
2831}
2832
2833static void
2834s_thumb (int ignore ATTRIBUTE_UNUSED)
2835{
2836 opcode_select (16);
2837 demand_empty_rest_of_line ();
2838}
2839
2840static void
2841s_code (int unused ATTRIBUTE_UNUSED)
2842{
2843 int temp;
2844
2845 temp = get_absolute_expression ();
2846 switch (temp)
2847 {
2848 case 16:
2849 case 32:
2850 opcode_select (temp);
2851 break;
2852
2853 default:
2854 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2855 }
2856}
2857
2858static void
2859s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2860{
2861 /* If we are not already in thumb mode go into it, EVEN if
2862 the target processor does not support thumb instructions.
2863 This is used by gcc/config/arm/lib1funcs.asm for example
2864 to compile interworking support functions even if the
2865 target processor should not support interworking. */
2866 if (! thumb_mode)
2867 {
2868 thumb_mode = 2;
2869 record_alignment (now_seg, 1);
2870 }
2871
2872 demand_empty_rest_of_line ();
2873}
2874
2875static void
2876s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2877{
2878 s_thumb (0);
2879
2880 /* The following label is the name/address of the start of a Thumb function.
2881 We need to know this for the interworking support. */
2882 label_is_thumb_function_name = TRUE;
2883}
2884
2885/* Perform a .set directive, but also mark the alias as
2886 being a thumb function. */
2887
2888static void
2889s_thumb_set (int equiv)
2890{
2891 /* XXX the following is a duplicate of the code for s_set() in read.c
2892 We cannot just call that code as we need to get at the symbol that
2893 is created. */
2894 char * name;
2895 char delim;
2896 char * end_name;
2897 symbolS * symbolP;
2898
2899 /* Especial apologies for the random logic:
2900 This just grew, and could be parsed much more simply!
2901 Dean - in haste. */
2902 delim = get_symbol_name (& name);
2903 end_name = input_line_pointer;
2904 (void) restore_line_pointer (delim);
2905
2906 if (*input_line_pointer != ',')
2907 {
2908 *end_name = 0;
2909 as_bad (_("expected comma after name \"%s\""), name);
2910 *end_name = delim;
2911 ignore_rest_of_line ();
2912 return;
2913 }
2914
2915 input_line_pointer++;
2916 *end_name = 0;
2917
2918 if (name[0] == '.' && name[1] == '\0')
2919 {
2920 /* XXX - this should not happen to .thumb_set. */
2921 abort ();
2922 }
2923
2924 if ((symbolP = symbol_find (name)) == NULL
2925 && (symbolP = md_undefined_symbol (name)) == NULL)
2926 {
2927#ifndef NO_LISTING
2928 /* When doing symbol listings, play games with dummy fragments living
2929 outside the normal fragment chain to record the file and line info
2930 for this symbol. */
2931 if (listing & LISTING_SYMBOLS)
2932 {
2933 extern struct list_info_struct * listing_tail;
2934 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2935
2936 memset (dummy_frag, 0, sizeof (fragS));
2937 dummy_frag->fr_type = rs_fill;
2938 dummy_frag->line = listing_tail;
2939 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2940 dummy_frag->fr_symbol = symbolP;
2941 }
2942 else
2943#endif
2944 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2945
2946#ifdef OBJ_COFF
2947 /* "set" symbols are local unless otherwise specified. */
2948 SF_SET_LOCAL (symbolP);
2949#endif /* OBJ_COFF */
2950 } /* Make a new symbol. */
2951
2952 symbol_table_insert (symbolP);
2953
2954 * end_name = delim;
2955
2956 if (equiv
2957 && S_IS_DEFINED (symbolP)
2958 && S_GET_SEGMENT (symbolP) != reg_section)
2959 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2960
2961 pseudo_set (symbolP);
2962
2963 demand_empty_rest_of_line ();
2964
2965 /* XXX Now we come to the Thumb specific bit of code. */
2966
2967 THUMB_SET_FUNC (symbolP, 1);
2968 ARM_SET_THUMB (symbolP, 1);
2969#if defined OBJ_ELF || defined OBJ_COFF
2970 ARM_SET_INTERWORK (symbolP, support_interwork);
2971#endif
2972}
2973
2974/* Directives: Mode selection. */
2975
2976/* .syntax [unified|divided] - choose the new unified syntax
2977 (same for Arm and Thumb encoding, modulo slight differences in what
2978 can be represented) or the old divergent syntax for each mode. */
2979static void
2980s_syntax (int unused ATTRIBUTE_UNUSED)
2981{
2982 char *name, delim;
2983
2984 delim = get_symbol_name (& name);
2985
2986 if (!strcasecmp (name, "unified"))
2987 unified_syntax = TRUE;
2988 else if (!strcasecmp (name, "divided"))
2989 unified_syntax = FALSE;
2990 else
2991 {
2992 as_bad (_("unrecognized syntax mode \"%s\""), name);
2993 return;
2994 }
2995 (void) restore_line_pointer (delim);
2996 demand_empty_rest_of_line ();
2997}
2998
2999/* Directives: sectioning and alignment. */
3000
3001static void
3002s_bss (int ignore ATTRIBUTE_UNUSED)
3003{
3004 /* We don't support putting frags in the BSS segment, we fake it by
3005 marking in_bss, then looking at s_skip for clues. */
3006 subseg_set (bss_section, 0);
3007 demand_empty_rest_of_line ();
3008
3009#ifdef md_elf_section_change_hook
3010 md_elf_section_change_hook ();
3011#endif
3012}
3013
3014static void
3015s_even (int ignore ATTRIBUTE_UNUSED)
3016{
3017 /* Never make frag if expect extra pass. */
3018 if (!need_pass_2)
3019 frag_align (1, 0, 0);
3020
3021 record_alignment (now_seg, 1);
3022
3023 demand_empty_rest_of_line ();
3024}
3025
3026/* Directives: CodeComposer Studio. */
3027
3028/* .ref (for CodeComposer Studio syntax only). */
3029static void
3030s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3031{
3032 if (codecomposer_syntax)
3033 ignore_rest_of_line ();
3034 else
3035 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3036}
3037
3038/* If name is not NULL, then it is used for marking the beginning of a
3039 function, wherease if it is NULL then it means the function end. */
3040static void
3041asmfunc_debug (const char * name)
3042{
3043 static const char * last_name = NULL;
3044
3045 if (name != NULL)
3046 {
3047 gas_assert (last_name == NULL);
3048 last_name = name;
3049
3050 if (debug_type == DEBUG_STABS)
3051 stabs_generate_asm_func (name, name);
3052 }
3053 else
3054 {
3055 gas_assert (last_name != NULL);
3056
3057 if (debug_type == DEBUG_STABS)
3058 stabs_generate_asm_endfunc (last_name, last_name);
3059
3060 last_name = NULL;
3061 }
3062}
3063
3064static void
3065s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3066{
3067 if (codecomposer_syntax)
3068 {
3069 switch (asmfunc_state)
3070 {
3071 case OUTSIDE_ASMFUNC:
3072 asmfunc_state = WAITING_ASMFUNC_NAME;
3073 break;
3074
3075 case WAITING_ASMFUNC_NAME:
3076 as_bad (_(".asmfunc repeated."));
3077 break;
3078
3079 case WAITING_ENDASMFUNC:
3080 as_bad (_(".asmfunc without function."));
3081 break;
3082 }
3083 demand_empty_rest_of_line ();
3084 }
3085 else
3086 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3087}
3088
3089static void
3090s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3091{
3092 if (codecomposer_syntax)
3093 {
3094 switch (asmfunc_state)
3095 {
3096 case OUTSIDE_ASMFUNC:
3097 as_bad (_(".endasmfunc without a .asmfunc."));
3098 break;
3099
3100 case WAITING_ASMFUNC_NAME:
3101 as_bad (_(".endasmfunc without function."));
3102 break;
3103
3104 case WAITING_ENDASMFUNC:
3105 asmfunc_state = OUTSIDE_ASMFUNC;
3106 asmfunc_debug (NULL);
3107 break;
3108 }
3109 demand_empty_rest_of_line ();
3110 }
3111 else
3112 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3113}
3114
3115static void
3116s_ccs_def (int name)
3117{
3118 if (codecomposer_syntax)
3119 s_globl (name);
3120 else
3121 as_bad (_(".def pseudo-op only available with -mccs flag."));
3122}
3123
3124/* Directives: Literal pools. */
3125
3126static literal_pool *
3127find_literal_pool (void)
3128{
3129 literal_pool * pool;
3130
3131 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3132 {
3133 if (pool->section == now_seg
3134 && pool->sub_section == now_subseg)
3135 break;
3136 }
3137
3138 return pool;
3139}
3140
3141static literal_pool *
3142find_or_make_literal_pool (void)
3143{
3144 /* Next literal pool ID number. */
3145 static unsigned int latest_pool_num = 1;
3146 literal_pool * pool;
3147
3148 pool = find_literal_pool ();
3149
3150 if (pool == NULL)
3151 {
3152 /* Create a new pool. */
3153 pool = XNEW (literal_pool);
3154 if (! pool)
3155 return NULL;
3156
3157 pool->next_free_entry = 0;
3158 pool->section = now_seg;
3159 pool->sub_section = now_subseg;
3160 pool->next = list_of_pools;
3161 pool->symbol = NULL;
3162 pool->alignment = 2;
3163
3164 /* Add it to the list. */
3165 list_of_pools = pool;
3166 }
3167
3168 /* New pools, and emptied pools, will have a NULL symbol. */
3169 if (pool->symbol == NULL)
3170 {
3171 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3172 (valueT) 0, &zero_address_frag);
3173 pool->id = latest_pool_num ++;
3174 }
3175
3176 /* Done. */
3177 return pool;
3178}
3179
3180/* Add the literal in the global 'inst'
3181 structure to the relevant literal pool. */
3182
3183static int
3184add_to_lit_pool (unsigned int nbytes)
3185{
3186#define PADDING_SLOT 0x1
3187#define LIT_ENTRY_SIZE_MASK 0xFF
3188 literal_pool * pool;
3189 unsigned int entry, pool_size = 0;
3190 bfd_boolean padding_slot_p = FALSE;
3191 unsigned imm1 = 0;
3192 unsigned imm2 = 0;
3193
3194 if (nbytes == 8)
3195 {
3196 imm1 = inst.operands[1].imm;
3197 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3198 : inst.reloc.exp.X_unsigned ? 0
3199 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
3200 if (target_big_endian)
3201 {
3202 imm1 = imm2;
3203 imm2 = inst.operands[1].imm;
3204 }
3205 }
3206
3207 pool = find_or_make_literal_pool ();
3208
3209 /* Check if this literal value is already in the pool. */
3210 for (entry = 0; entry < pool->next_free_entry; entry ++)
3211 {
3212 if (nbytes == 4)
3213 {
3214 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3215 && (inst.reloc.exp.X_op == O_constant)
3216 && (pool->literals[entry].X_add_number
3217 == inst.reloc.exp.X_add_number)
3218 && (pool->literals[entry].X_md == nbytes)
3219 && (pool->literals[entry].X_unsigned
3220 == inst.reloc.exp.X_unsigned))
3221 break;
3222
3223 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3224 && (inst.reloc.exp.X_op == O_symbol)
3225 && (pool->literals[entry].X_add_number
3226 == inst.reloc.exp.X_add_number)
3227 && (pool->literals[entry].X_add_symbol
3228 == inst.reloc.exp.X_add_symbol)
3229 && (pool->literals[entry].X_op_symbol
3230 == inst.reloc.exp.X_op_symbol)
3231 && (pool->literals[entry].X_md == nbytes))
3232 break;
3233 }
3234 else if ((nbytes == 8)
3235 && !(pool_size & 0x7)
3236 && ((entry + 1) != pool->next_free_entry)
3237 && (pool->literals[entry].X_op == O_constant)
3238 && (pool->literals[entry].X_add_number == (offsetT) imm1)
3239 && (pool->literals[entry].X_unsigned
3240 == inst.reloc.exp.X_unsigned)
3241 && (pool->literals[entry + 1].X_op == O_constant)
3242 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
3243 && (pool->literals[entry + 1].X_unsigned
3244 == inst.reloc.exp.X_unsigned))
3245 break;
3246
3247 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3248 if (padding_slot_p && (nbytes == 4))
3249 break;
3250
3251 pool_size += 4;
3252 }
3253
3254 /* Do we need to create a new entry? */
3255 if (entry == pool->next_free_entry)
3256 {
3257 if (entry >= MAX_LITERAL_POOL_SIZE)
3258 {
3259 inst.error = _("literal pool overflow");
3260 return FAIL;
3261 }
3262
3263 if (nbytes == 8)
3264 {
3265 /* For 8-byte entries, we align to an 8-byte boundary,
3266 and split it into two 4-byte entries, because on 32-bit
3267 host, 8-byte constants are treated as big num, thus
3268 saved in "generic_bignum" which will be overwritten
3269 by later assignments.
3270
3271 We also need to make sure there is enough space for
3272 the split.
3273
3274 We also check to make sure the literal operand is a
3275 constant number. */
3276 if (!(inst.reloc.exp.X_op == O_constant
3277 || inst.reloc.exp.X_op == O_big))
3278 {
3279 inst.error = _("invalid type for literal pool");
3280 return FAIL;
3281 }
3282 else if (pool_size & 0x7)
3283 {
3284 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3285 {
3286 inst.error = _("literal pool overflow");
3287 return FAIL;
3288 }
3289
3290 pool->literals[entry] = inst.reloc.exp;
3291 pool->literals[entry].X_add_number = 0;
3292 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3293 pool->next_free_entry += 1;
3294 pool_size += 4;
3295 }
3296 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3297 {
3298 inst.error = _("literal pool overflow");
3299 return FAIL;
3300 }
3301
3302 pool->literals[entry] = inst.reloc.exp;
3303 pool->literals[entry].X_op = O_constant;
3304 pool->literals[entry].X_add_number = imm1;
3305 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3306 pool->literals[entry++].X_md = 4;
3307 pool->literals[entry] = inst.reloc.exp;
3308 pool->literals[entry].X_op = O_constant;
3309 pool->literals[entry].X_add_number = imm2;
3310 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3311 pool->literals[entry].X_md = 4;
3312 pool->alignment = 3;
3313 pool->next_free_entry += 1;
3314 }
3315 else
3316 {
3317 pool->literals[entry] = inst.reloc.exp;
3318 pool->literals[entry].X_md = 4;
3319 }
3320
3321#ifdef OBJ_ELF
3322 /* PR ld/12974: Record the location of the first source line to reference
3323 this entry in the literal pool. If it turns out during linking that the
3324 symbol does not exist we will be able to give an accurate line number for
3325 the (first use of the) missing reference. */
3326 if (debug_type == DEBUG_DWARF2)
3327 dwarf2_where (pool->locs + entry);
3328#endif
3329 pool->next_free_entry += 1;
3330 }
3331 else if (padding_slot_p)
3332 {
3333 pool->literals[entry] = inst.reloc.exp;
3334 pool->literals[entry].X_md = nbytes;
3335 }
3336
3337 inst.reloc.exp.X_op = O_symbol;
3338 inst.reloc.exp.X_add_number = pool_size;
3339 inst.reloc.exp.X_add_symbol = pool->symbol;
3340
3341 return SUCCESS;
3342}
3343
3344bfd_boolean
3345tc_start_label_without_colon (void)
3346{
3347 bfd_boolean ret = TRUE;
3348
3349 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3350 {
3351 const char *label = input_line_pointer;
3352
3353 while (!is_end_of_line[(int) label[-1]])
3354 --label;
3355
3356 if (*label == '.')
3357 {
3358 as_bad (_("Invalid label '%s'"), label);
3359 ret = FALSE;
3360 }
3361
3362 asmfunc_debug (label);
3363
3364 asmfunc_state = WAITING_ENDASMFUNC;
3365 }
3366
3367 return ret;
3368}
3369
3370/* Can't use symbol_new here, so have to create a symbol and then at
3371 a later date assign it a value. Thats what these functions do. */
3372
3373static void
3374symbol_locate (symbolS * symbolP,
3375 const char * name, /* It is copied, the caller can modify. */
3376 segT segment, /* Segment identifier (SEG_<something>). */
3377 valueT valu, /* Symbol value. */
3378 fragS * frag) /* Associated fragment. */
3379{
3380 size_t name_length;
3381 char * preserved_copy_of_name;
3382
3383 name_length = strlen (name) + 1; /* +1 for \0. */
3384 obstack_grow (&notes, name, name_length);
3385 preserved_copy_of_name = (char *) obstack_finish (&notes);
3386
3387#ifdef tc_canonicalize_symbol_name
3388 preserved_copy_of_name =
3389 tc_canonicalize_symbol_name (preserved_copy_of_name);
3390#endif
3391
3392 S_SET_NAME (symbolP, preserved_copy_of_name);
3393
3394 S_SET_SEGMENT (symbolP, segment);
3395 S_SET_VALUE (symbolP, valu);
3396 symbol_clear_list_pointers (symbolP);
3397
3398 symbol_set_frag (symbolP, frag);
3399
3400 /* Link to end of symbol chain. */
3401 {
3402 extern int symbol_table_frozen;
3403
3404 if (symbol_table_frozen)
3405 abort ();
3406 }
3407
3408 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3409
3410 obj_symbol_new_hook (symbolP);
3411
3412#ifdef tc_symbol_new_hook
3413 tc_symbol_new_hook (symbolP);
3414#endif
3415
3416#ifdef DEBUG_SYMS
3417 verify_symbol_chain (symbol_rootP, symbol_lastP);
3418#endif /* DEBUG_SYMS */
3419}
3420
3421static void
3422s_ltorg (int ignored ATTRIBUTE_UNUSED)
3423{
3424 unsigned int entry;
3425 literal_pool * pool;
3426 char sym_name[20];
3427
3428 pool = find_literal_pool ();
3429 if (pool == NULL
3430 || pool->symbol == NULL
3431 || pool->next_free_entry == 0)
3432 return;
3433
3434 /* Align pool as you have word accesses.
3435 Only make a frag if we have to. */
3436 if (!need_pass_2)
3437 frag_align (pool->alignment, 0, 0);
3438
3439 record_alignment (now_seg, 2);
3440
3441#ifdef OBJ_ELF
3442 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3443 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
3444#endif
3445 sprintf (sym_name, "$$lit_\002%x", pool->id);
3446
3447 symbol_locate (pool->symbol, sym_name, now_seg,
3448 (valueT) frag_now_fix (), frag_now);
3449 symbol_table_insert (pool->symbol);
3450
3451 ARM_SET_THUMB (pool->symbol, thumb_mode);
3452
3453#if defined OBJ_COFF || defined OBJ_ELF
3454 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3455#endif
3456
3457 for (entry = 0; entry < pool->next_free_entry; entry ++)
3458 {
3459#ifdef OBJ_ELF
3460 if (debug_type == DEBUG_DWARF2)
3461 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3462#endif
3463 /* First output the expression in the instruction to the pool. */
3464 emit_expr (&(pool->literals[entry]),
3465 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
3466 }
3467
3468 /* Mark the pool as empty. */
3469 pool->next_free_entry = 0;
3470 pool->symbol = NULL;
3471}
3472
3473#ifdef OBJ_ELF
3474/* Forward declarations for functions below, in the MD interface
3475 section. */
3476static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3477static valueT create_unwind_entry (int);
3478static void start_unwind_section (const segT, int);
3479static void add_unwind_opcode (valueT, int);
3480static void flush_pending_unwind (void);
3481
3482/* Directives: Data. */
3483
3484static void
3485s_arm_elf_cons (int nbytes)
3486{
3487 expressionS exp;
3488
3489#ifdef md_flush_pending_output
3490 md_flush_pending_output ();
3491#endif
3492
3493 if (is_it_end_of_statement ())
3494 {
3495 demand_empty_rest_of_line ();
3496 return;
3497 }
3498
3499#ifdef md_cons_align
3500 md_cons_align (nbytes);
3501#endif
3502
3503 mapping_state (MAP_DATA);
3504 do
3505 {
3506 int reloc;
3507 char *base = input_line_pointer;
3508
3509 expression (& exp);
3510
3511 if (exp.X_op != O_symbol)
3512 emit_expr (&exp, (unsigned int) nbytes);
3513 else
3514 {
3515 char *before_reloc = input_line_pointer;
3516 reloc = parse_reloc (&input_line_pointer);
3517 if (reloc == -1)
3518 {
3519 as_bad (_("unrecognized relocation suffix"));
3520 ignore_rest_of_line ();
3521 return;
3522 }
3523 else if (reloc == BFD_RELOC_UNUSED)
3524 emit_expr (&exp, (unsigned int) nbytes);
3525 else
3526 {
3527 reloc_howto_type *howto = (reloc_howto_type *)
3528 bfd_reloc_type_lookup (stdoutput,
3529 (bfd_reloc_code_real_type) reloc);
3530 int size = bfd_get_reloc_size (howto);
3531
3532 if (reloc == BFD_RELOC_ARM_PLT32)
3533 {
3534 as_bad (_("(plt) is only valid on branch targets"));
3535 reloc = BFD_RELOC_UNUSED;
3536 size = 0;
3537 }
3538
3539 if (size > nbytes)
3540 as_bad (_("%s relocations do not fit in %d bytes"),
3541 howto->name, nbytes);
3542 else
3543 {
3544 /* We've parsed an expression stopping at O_symbol.
3545 But there may be more expression left now that we
3546 have parsed the relocation marker. Parse it again.
3547 XXX Surely there is a cleaner way to do this. */
3548 char *p = input_line_pointer;
3549 int offset;
3550 char *save_buf = XNEWVEC (char, input_line_pointer - base);
3551
3552 memcpy (save_buf, base, input_line_pointer - base);
3553 memmove (base + (input_line_pointer - before_reloc),
3554 base, before_reloc - base);
3555
3556 input_line_pointer = base + (input_line_pointer-before_reloc);
3557 expression (&exp);
3558 memcpy (base, save_buf, p - base);
3559
3560 offset = nbytes - size;
3561 p = frag_more (nbytes);
3562 memset (p, 0, nbytes);
3563 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3564 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3565 free (save_buf);
3566 }
3567 }
3568 }
3569 }
3570 while (*input_line_pointer++ == ',');
3571
3572 /* Put terminator back into stream. */
3573 input_line_pointer --;
3574 demand_empty_rest_of_line ();
3575}
3576
3577/* Emit an expression containing a 32-bit thumb instruction.
3578 Implementation based on put_thumb32_insn. */
3579
3580static void
3581emit_thumb32_expr (expressionS * exp)
3582{
3583 expressionS exp_high = *exp;
3584
3585 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3586 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3587 exp->X_add_number &= 0xffff;
3588 emit_expr (exp, (unsigned int) THUMB_SIZE);
3589}
3590
3591/* Guess the instruction size based on the opcode. */
3592
3593static int
3594thumb_insn_size (int opcode)
3595{
3596 if ((unsigned int) opcode < 0xe800u)
3597 return 2;
3598 else if ((unsigned int) opcode >= 0xe8000000u)
3599 return 4;
3600 else
3601 return 0;
3602}
3603
3604static bfd_boolean
3605emit_insn (expressionS *exp, int nbytes)
3606{
3607 int size = 0;
3608
3609 if (exp->X_op == O_constant)
3610 {
3611 size = nbytes;
3612
3613 if (size == 0)
3614 size = thumb_insn_size (exp->X_add_number);
3615
3616 if (size != 0)
3617 {
3618 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3619 {
3620 as_bad (_(".inst.n operand too big. "\
3621 "Use .inst.w instead"));
3622 size = 0;
3623 }
3624 else
3625 {
3626 if (now_it.state == AUTOMATIC_IT_BLOCK)
3627 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3628 else
3629 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3630
3631 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3632 emit_thumb32_expr (exp);
3633 else
3634 emit_expr (exp, (unsigned int) size);
3635
3636 it_fsm_post_encode ();
3637 }
3638 }
3639 else
3640 as_bad (_("cannot determine Thumb instruction size. " \
3641 "Use .inst.n/.inst.w instead"));
3642 }
3643 else
3644 as_bad (_("constant expression required"));
3645
3646 return (size != 0);
3647}
3648
3649/* Like s_arm_elf_cons but do not use md_cons_align and
3650 set the mapping state to MAP_ARM/MAP_THUMB. */
3651
3652static void
3653s_arm_elf_inst (int nbytes)
3654{
3655 if (is_it_end_of_statement ())
3656 {
3657 demand_empty_rest_of_line ();
3658 return;
3659 }
3660
3661 /* Calling mapping_state () here will not change ARM/THUMB,
3662 but will ensure not to be in DATA state. */
3663
3664 if (thumb_mode)
3665 mapping_state (MAP_THUMB);
3666 else
3667 {
3668 if (nbytes != 0)
3669 {
3670 as_bad (_("width suffixes are invalid in ARM mode"));
3671 ignore_rest_of_line ();
3672 return;
3673 }
3674
3675 nbytes = 4;
3676
3677 mapping_state (MAP_ARM);
3678 }
3679
3680 do
3681 {
3682 expressionS exp;
3683
3684 expression (& exp);
3685
3686 if (! emit_insn (& exp, nbytes))
3687 {
3688 ignore_rest_of_line ();
3689 return;
3690 }
3691 }
3692 while (*input_line_pointer++ == ',');
3693
3694 /* Put terminator back into stream. */
3695 input_line_pointer --;
3696 demand_empty_rest_of_line ();
3697}
3698
3699/* Parse a .rel31 directive. */
3700
3701static void
3702s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3703{
3704 expressionS exp;
3705 char *p;
3706 valueT highbit;
3707
3708 highbit = 0;
3709 if (*input_line_pointer == '1')
3710 highbit = 0x80000000;
3711 else if (*input_line_pointer != '0')
3712 as_bad (_("expected 0 or 1"));
3713
3714 input_line_pointer++;
3715 if (*input_line_pointer != ',')
3716 as_bad (_("missing comma"));
3717 input_line_pointer++;
3718
3719#ifdef md_flush_pending_output
3720 md_flush_pending_output ();
3721#endif
3722
3723#ifdef md_cons_align
3724 md_cons_align (4);
3725#endif
3726
3727 mapping_state (MAP_DATA);
3728
3729 expression (&exp);
3730
3731 p = frag_more (4);
3732 md_number_to_chars (p, highbit, 4);
3733 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3734 BFD_RELOC_ARM_PREL31);
3735
3736 demand_empty_rest_of_line ();
3737}
3738
3739/* Directives: AEABI stack-unwind tables. */
3740
3741/* Parse an unwind_fnstart directive. Simply records the current location. */
3742
3743static void
3744s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3745{
3746 demand_empty_rest_of_line ();
3747 if (unwind.proc_start)
3748 {
3749 as_bad (_("duplicate .fnstart directive"));
3750 return;
3751 }
3752
3753 /* Mark the start of the function. */
3754 unwind.proc_start = expr_build_dot ();
3755
3756 /* Reset the rest of the unwind info. */
3757 unwind.opcode_count = 0;
3758 unwind.table_entry = NULL;
3759 unwind.personality_routine = NULL;
3760 unwind.personality_index = -1;
3761 unwind.frame_size = 0;
3762 unwind.fp_offset = 0;
3763 unwind.fp_reg = REG_SP;
3764 unwind.fp_used = 0;
3765 unwind.sp_restored = 0;
3766}
3767
3768
3769/* Parse a handlerdata directive. Creates the exception handling table entry
3770 for the function. */
3771
3772static void
3773s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3774{
3775 demand_empty_rest_of_line ();
3776 if (!unwind.proc_start)
3777 as_bad (MISSING_FNSTART);
3778
3779 if (unwind.table_entry)
3780 as_bad (_("duplicate .handlerdata directive"));
3781
3782 create_unwind_entry (1);
3783}
3784
3785/* Parse an unwind_fnend directive. Generates the index table entry. */
3786
3787static void
3788s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3789{
3790 long where;
3791 char *ptr;
3792 valueT val;
3793 unsigned int marked_pr_dependency;
3794
3795 demand_empty_rest_of_line ();
3796
3797 if (!unwind.proc_start)
3798 {
3799 as_bad (_(".fnend directive without .fnstart"));
3800 return;
3801 }
3802
3803 /* Add eh table entry. */
3804 if (unwind.table_entry == NULL)
3805 val = create_unwind_entry (0);
3806 else
3807 val = 0;
3808
3809 /* Add index table entry. This is two words. */
3810 start_unwind_section (unwind.saved_seg, 1);
3811 frag_align (2, 0, 0);
3812 record_alignment (now_seg, 2);
3813
3814 ptr = frag_more (8);
3815 memset (ptr, 0, 8);
3816 where = frag_now_fix () - 8;
3817
3818 /* Self relative offset of the function start. */
3819 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3820 BFD_RELOC_ARM_PREL31);
3821
3822 /* Indicate dependency on EHABI-defined personality routines to the
3823 linker, if it hasn't been done already. */
3824 marked_pr_dependency
3825 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3826 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3827 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3828 {
3829 static const char *const name[] =
3830 {
3831 "__aeabi_unwind_cpp_pr0",
3832 "__aeabi_unwind_cpp_pr1",
3833 "__aeabi_unwind_cpp_pr2"
3834 };
3835 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3836 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3837 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3838 |= 1 << unwind.personality_index;
3839 }
3840
3841 if (val)
3842 /* Inline exception table entry. */
3843 md_number_to_chars (ptr + 4, val, 4);
3844 else
3845 /* Self relative offset of the table entry. */
3846 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3847 BFD_RELOC_ARM_PREL31);
3848
3849 /* Restore the original section. */
3850 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3851
3852 unwind.proc_start = NULL;
3853}
3854
3855
3856/* Parse an unwind_cantunwind directive. */
3857
3858static void
3859s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3860{
3861 demand_empty_rest_of_line ();
3862 if (!unwind.proc_start)
3863 as_bad (MISSING_FNSTART);
3864
3865 if (unwind.personality_routine || unwind.personality_index != -1)
3866 as_bad (_("personality routine specified for cantunwind frame"));
3867
3868 unwind.personality_index = -2;
3869}
3870
3871
3872/* Parse a personalityindex directive. */
3873
3874static void
3875s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3876{
3877 expressionS exp;
3878
3879 if (!unwind.proc_start)
3880 as_bad (MISSING_FNSTART);
3881
3882 if (unwind.personality_routine || unwind.personality_index != -1)
3883 as_bad (_("duplicate .personalityindex directive"));
3884
3885 expression (&exp);
3886
3887 if (exp.X_op != O_constant
3888 || exp.X_add_number < 0 || exp.X_add_number > 15)
3889 {
3890 as_bad (_("bad personality routine number"));
3891 ignore_rest_of_line ();
3892 return;
3893 }
3894
3895 unwind.personality_index = exp.X_add_number;
3896
3897 demand_empty_rest_of_line ();
3898}
3899
3900
3901/* Parse a personality directive. */
3902
3903static void
3904s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3905{
3906 char *name, *p, c;
3907
3908 if (!unwind.proc_start)
3909 as_bad (MISSING_FNSTART);
3910
3911 if (unwind.personality_routine || unwind.personality_index != -1)
3912 as_bad (_("duplicate .personality directive"));
3913
3914 c = get_symbol_name (& name);
3915 p = input_line_pointer;
3916 if (c == '"')
3917 ++ input_line_pointer;
3918 unwind.personality_routine = symbol_find_or_make (name);
3919 *p = c;
3920 demand_empty_rest_of_line ();
3921}
3922
3923
3924/* Parse a directive saving core registers. */
3925
3926static void
3927s_arm_unwind_save_core (void)
3928{
3929 valueT op;
3930 long range;
3931 int n;
3932
3933 range = parse_reg_list (&input_line_pointer);
3934 if (range == FAIL)
3935 {
3936 as_bad (_("expected register list"));
3937 ignore_rest_of_line ();
3938 return;
3939 }
3940
3941 demand_empty_rest_of_line ();
3942
3943 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3944 into .unwind_save {..., sp...}. We aren't bothered about the value of
3945 ip because it is clobbered by calls. */
3946 if (unwind.sp_restored && unwind.fp_reg == 12
3947 && (range & 0x3000) == 0x1000)
3948 {
3949 unwind.opcode_count--;
3950 unwind.sp_restored = 0;
3951 range = (range | 0x2000) & ~0x1000;
3952 unwind.pending_offset = 0;
3953 }
3954
3955 /* Pop r4-r15. */
3956 if (range & 0xfff0)
3957 {
3958 /* See if we can use the short opcodes. These pop a block of up to 8
3959 registers starting with r4, plus maybe r14. */
3960 for (n = 0; n < 8; n++)
3961 {
3962 /* Break at the first non-saved register. */
3963 if ((range & (1 << (n + 4))) == 0)
3964 break;
3965 }
3966 /* See if there are any other bits set. */
3967 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3968 {
3969 /* Use the long form. */
3970 op = 0x8000 | ((range >> 4) & 0xfff);
3971 add_unwind_opcode (op, 2);
3972 }
3973 else
3974 {
3975 /* Use the short form. */
3976 if (range & 0x4000)
3977 op = 0xa8; /* Pop r14. */
3978 else
3979 op = 0xa0; /* Do not pop r14. */
3980 op |= (n - 1);
3981 add_unwind_opcode (op, 1);
3982 }
3983 }
3984
3985 /* Pop r0-r3. */
3986 if (range & 0xf)
3987 {
3988 op = 0xb100 | (range & 0xf);
3989 add_unwind_opcode (op, 2);
3990 }
3991
3992 /* Record the number of bytes pushed. */
3993 for (n = 0; n < 16; n++)
3994 {
3995 if (range & (1 << n))
3996 unwind.frame_size += 4;
3997 }
3998}
3999
4000
4001/* Parse a directive saving FPA registers. */
4002
4003static void
4004s_arm_unwind_save_fpa (int reg)
4005{
4006 expressionS exp;
4007 int num_regs;
4008 valueT op;
4009
4010 /* Get Number of registers to transfer. */
4011 if (skip_past_comma (&input_line_pointer) != FAIL)
4012 expression (&exp);
4013 else
4014 exp.X_op = O_illegal;
4015
4016 if (exp.X_op != O_constant)
4017 {
4018 as_bad (_("expected , <constant>"));
4019 ignore_rest_of_line ();
4020 return;
4021 }
4022
4023 num_regs = exp.X_add_number;
4024
4025 if (num_regs < 1 || num_regs > 4)
4026 {
4027 as_bad (_("number of registers must be in the range [1:4]"));
4028 ignore_rest_of_line ();
4029 return;
4030 }
4031
4032 demand_empty_rest_of_line ();
4033
4034 if (reg == 4)
4035 {
4036 /* Short form. */
4037 op = 0xb4 | (num_regs - 1);
4038 add_unwind_opcode (op, 1);
4039 }
4040 else
4041 {
4042 /* Long form. */
4043 op = 0xc800 | (reg << 4) | (num_regs - 1);
4044 add_unwind_opcode (op, 2);
4045 }
4046 unwind.frame_size += num_regs * 12;
4047}
4048
4049
4050/* Parse a directive saving VFP registers for ARMv6 and above. */
4051
4052static void
4053s_arm_unwind_save_vfp_armv6 (void)
4054{
4055 int count;
4056 unsigned int start;
4057 valueT op;
4058 int num_vfpv3_regs = 0;
4059 int num_regs_below_16;
4060
4061 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
4062 if (count == FAIL)
4063 {
4064 as_bad (_("expected register list"));
4065 ignore_rest_of_line ();
4066 return;
4067 }
4068
4069 demand_empty_rest_of_line ();
4070
4071 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4072 than FSTMX/FLDMX-style ones). */
4073
4074 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4075 if (start >= 16)
4076 num_vfpv3_regs = count;
4077 else if (start + count > 16)
4078 num_vfpv3_regs = start + count - 16;
4079
4080 if (num_vfpv3_regs > 0)
4081 {
4082 int start_offset = start > 16 ? start - 16 : 0;
4083 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4084 add_unwind_opcode (op, 2);
4085 }
4086
4087 /* Generate opcode for registers numbered in the range 0 .. 15. */
4088 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
4089 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
4090 if (num_regs_below_16 > 0)
4091 {
4092 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4093 add_unwind_opcode (op, 2);
4094 }
4095
4096 unwind.frame_size += count * 8;
4097}
4098
4099
4100/* Parse a directive saving VFP registers for pre-ARMv6. */
4101
4102static void
4103s_arm_unwind_save_vfp (void)
4104{
4105 int count;
4106 unsigned int reg;
4107 valueT op;
4108
4109 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D);
4110 if (count == FAIL)
4111 {
4112 as_bad (_("expected register list"));
4113 ignore_rest_of_line ();
4114 return;
4115 }
4116
4117 demand_empty_rest_of_line ();
4118
4119 if (reg == 8)
4120 {
4121 /* Short form. */
4122 op = 0xb8 | (count - 1);
4123 add_unwind_opcode (op, 1);
4124 }
4125 else
4126 {
4127 /* Long form. */
4128 op = 0xb300 | (reg << 4) | (count - 1);
4129 add_unwind_opcode (op, 2);
4130 }
4131 unwind.frame_size += count * 8 + 4;
4132}
4133
4134
4135/* Parse a directive saving iWMMXt data registers. */
4136
4137static void
4138s_arm_unwind_save_mmxwr (void)
4139{
4140 int reg;
4141 int hi_reg;
4142 int i;
4143 unsigned mask = 0;
4144 valueT op;
4145
4146 if (*input_line_pointer == '{')
4147 input_line_pointer++;
4148
4149 do
4150 {
4151 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4152
4153 if (reg == FAIL)
4154 {
4155 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4156 goto error;
4157 }
4158
4159 if (mask >> reg)
4160 as_tsktsk (_("register list not in ascending order"));
4161 mask |= 1 << reg;
4162
4163 if (*input_line_pointer == '-')
4164 {
4165 input_line_pointer++;
4166 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4167 if (hi_reg == FAIL)
4168 {
4169 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4170 goto error;
4171 }
4172 else if (reg >= hi_reg)
4173 {
4174 as_bad (_("bad register range"));
4175 goto error;
4176 }
4177 for (; reg < hi_reg; reg++)
4178 mask |= 1 << reg;
4179 }
4180 }
4181 while (skip_past_comma (&input_line_pointer) != FAIL);
4182
4183 skip_past_char (&input_line_pointer, '}');
4184
4185 demand_empty_rest_of_line ();
4186
4187 /* Generate any deferred opcodes because we're going to be looking at
4188 the list. */
4189 flush_pending_unwind ();
4190
4191 for (i = 0; i < 16; i++)
4192 {
4193 if (mask & (1 << i))
4194 unwind.frame_size += 8;
4195 }
4196
4197 /* Attempt to combine with a previous opcode. We do this because gcc
4198 likes to output separate unwind directives for a single block of
4199 registers. */
4200 if (unwind.opcode_count > 0)
4201 {
4202 i = unwind.opcodes[unwind.opcode_count - 1];
4203 if ((i & 0xf8) == 0xc0)
4204 {
4205 i &= 7;
4206 /* Only merge if the blocks are contiguous. */
4207 if (i < 6)
4208 {
4209 if ((mask & 0xfe00) == (1 << 9))
4210 {
4211 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4212 unwind.opcode_count--;
4213 }
4214 }
4215 else if (i == 6 && unwind.opcode_count >= 2)
4216 {
4217 i = unwind.opcodes[unwind.opcode_count - 2];
4218 reg = i >> 4;
4219 i &= 0xf;
4220
4221 op = 0xffff << (reg - 1);
4222 if (reg > 0
4223 && ((mask & op) == (1u << (reg - 1))))
4224 {
4225 op = (1 << (reg + i + 1)) - 1;
4226 op &= ~((1 << reg) - 1);
4227 mask |= op;
4228 unwind.opcode_count -= 2;
4229 }
4230 }
4231 }
4232 }
4233
4234 hi_reg = 15;
4235 /* We want to generate opcodes in the order the registers have been
4236 saved, ie. descending order. */
4237 for (reg = 15; reg >= -1; reg--)
4238 {
4239 /* Save registers in blocks. */
4240 if (reg < 0
4241 || !(mask & (1 << reg)))
4242 {
4243 /* We found an unsaved reg. Generate opcodes to save the
4244 preceding block. */
4245 if (reg != hi_reg)
4246 {
4247 if (reg == 9)
4248 {
4249 /* Short form. */
4250 op = 0xc0 | (hi_reg - 10);
4251 add_unwind_opcode (op, 1);
4252 }
4253 else
4254 {
4255 /* Long form. */
4256 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4257 add_unwind_opcode (op, 2);
4258 }
4259 }
4260 hi_reg = reg - 1;
4261 }
4262 }
4263
4264 return;
4265error:
4266 ignore_rest_of_line ();
4267}
4268
4269static void
4270s_arm_unwind_save_mmxwcg (void)
4271{
4272 int reg;
4273 int hi_reg;
4274 unsigned mask = 0;
4275 valueT op;
4276
4277 if (*input_line_pointer == '{')
4278 input_line_pointer++;
4279
4280 skip_whitespace (input_line_pointer);
4281
4282 do
4283 {
4284 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4285
4286 if (reg == FAIL)
4287 {
4288 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4289 goto error;
4290 }
4291
4292 reg -= 8;
4293 if (mask >> reg)
4294 as_tsktsk (_("register list not in ascending order"));
4295 mask |= 1 << reg;
4296
4297 if (*input_line_pointer == '-')
4298 {
4299 input_line_pointer++;
4300 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4301 if (hi_reg == FAIL)
4302 {
4303 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4304 goto error;
4305 }
4306 else if (reg >= hi_reg)
4307 {
4308 as_bad (_("bad register range"));
4309 goto error;
4310 }
4311 for (; reg < hi_reg; reg++)
4312 mask |= 1 << reg;
4313 }
4314 }
4315 while (skip_past_comma (&input_line_pointer) != FAIL);
4316
4317 skip_past_char (&input_line_pointer, '}');
4318
4319 demand_empty_rest_of_line ();
4320
4321 /* Generate any deferred opcodes because we're going to be looking at
4322 the list. */
4323 flush_pending_unwind ();
4324
4325 for (reg = 0; reg < 16; reg++)
4326 {
4327 if (mask & (1 << reg))
4328 unwind.frame_size += 4;
4329 }
4330 op = 0xc700 | mask;
4331 add_unwind_opcode (op, 2);
4332 return;
4333error:
4334 ignore_rest_of_line ();
4335}
4336
4337
4338/* Parse an unwind_save directive.
4339 If the argument is non-zero, this is a .vsave directive. */
4340
4341static void
4342s_arm_unwind_save (int arch_v6)
4343{
4344 char *peek;
4345 struct reg_entry *reg;
4346 bfd_boolean had_brace = FALSE;
4347
4348 if (!unwind.proc_start)
4349 as_bad (MISSING_FNSTART);
4350
4351 /* Figure out what sort of save we have. */
4352 peek = input_line_pointer;
4353
4354 if (*peek == '{')
4355 {
4356 had_brace = TRUE;
4357 peek++;
4358 }
4359
4360 reg = arm_reg_parse_multi (&peek);
4361
4362 if (!reg)
4363 {
4364 as_bad (_("register expected"));
4365 ignore_rest_of_line ();
4366 return;
4367 }
4368
4369 switch (reg->type)
4370 {
4371 case REG_TYPE_FN:
4372 if (had_brace)
4373 {
4374 as_bad (_("FPA .unwind_save does not take a register list"));
4375 ignore_rest_of_line ();
4376 return;
4377 }
4378 input_line_pointer = peek;
4379 s_arm_unwind_save_fpa (reg->number);
4380 return;
4381
4382 case REG_TYPE_RN:
4383 s_arm_unwind_save_core ();
4384 return;
4385
4386 case REG_TYPE_VFD:
4387 if (arch_v6)
4388 s_arm_unwind_save_vfp_armv6 ();
4389 else
4390 s_arm_unwind_save_vfp ();
4391 return;
4392
4393 case REG_TYPE_MMXWR:
4394 s_arm_unwind_save_mmxwr ();
4395 return;
4396
4397 case REG_TYPE_MMXWCG:
4398 s_arm_unwind_save_mmxwcg ();
4399 return;
4400
4401 default:
4402 as_bad (_(".unwind_save does not support this kind of register"));
4403 ignore_rest_of_line ();
4404 }
4405}
4406
4407
4408/* Parse an unwind_movsp directive. */
4409
4410static void
4411s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4412{
4413 int reg;
4414 valueT op;
4415 int offset;
4416
4417 if (!unwind.proc_start)
4418 as_bad (MISSING_FNSTART);
4419
4420 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4421 if (reg == FAIL)
4422 {
4423 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4424 ignore_rest_of_line ();
4425 return;
4426 }
4427
4428 /* Optional constant. */
4429 if (skip_past_comma (&input_line_pointer) != FAIL)
4430 {
4431 if (immediate_for_directive (&offset) == FAIL)
4432 return;
4433 }
4434 else
4435 offset = 0;
4436
4437 demand_empty_rest_of_line ();
4438
4439 if (reg == REG_SP || reg == REG_PC)
4440 {
4441 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4442 return;
4443 }
4444
4445 if (unwind.fp_reg != REG_SP)
4446 as_bad (_("unexpected .unwind_movsp directive"));
4447
4448 /* Generate opcode to restore the value. */
4449 op = 0x90 | reg;
4450 add_unwind_opcode (op, 1);
4451
4452 /* Record the information for later. */
4453 unwind.fp_reg = reg;
4454 unwind.fp_offset = unwind.frame_size - offset;
4455 unwind.sp_restored = 1;
4456}
4457
4458/* Parse an unwind_pad directive. */
4459
4460static void
4461s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4462{
4463 int offset;
4464
4465 if (!unwind.proc_start)
4466 as_bad (MISSING_FNSTART);
4467
4468 if (immediate_for_directive (&offset) == FAIL)
4469 return;
4470
4471 if (offset & 3)
4472 {
4473 as_bad (_("stack increment must be multiple of 4"));
4474 ignore_rest_of_line ();
4475 return;
4476 }
4477
4478 /* Don't generate any opcodes, just record the details for later. */
4479 unwind.frame_size += offset;
4480 unwind.pending_offset += offset;
4481
4482 demand_empty_rest_of_line ();
4483}
4484
4485/* Parse an unwind_setfp directive. */
4486
4487static void
4488s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4489{
4490 int sp_reg;
4491 int fp_reg;
4492 int offset;
4493
4494 if (!unwind.proc_start)
4495 as_bad (MISSING_FNSTART);
4496
4497 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4498 if (skip_past_comma (&input_line_pointer) == FAIL)
4499 sp_reg = FAIL;
4500 else
4501 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4502
4503 if (fp_reg == FAIL || sp_reg == FAIL)
4504 {
4505 as_bad (_("expected <reg>, <reg>"));
4506 ignore_rest_of_line ();
4507 return;
4508 }
4509
4510 /* Optional constant. */
4511 if (skip_past_comma (&input_line_pointer) != FAIL)
4512 {
4513 if (immediate_for_directive (&offset) == FAIL)
4514 return;
4515 }
4516 else
4517 offset = 0;
4518
4519 demand_empty_rest_of_line ();
4520
4521 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4522 {
4523 as_bad (_("register must be either sp or set by a previous"
4524 "unwind_movsp directive"));
4525 return;
4526 }
4527
4528 /* Don't generate any opcodes, just record the information for later. */
4529 unwind.fp_reg = fp_reg;
4530 unwind.fp_used = 1;
4531 if (sp_reg == REG_SP)
4532 unwind.fp_offset = unwind.frame_size - offset;
4533 else
4534 unwind.fp_offset -= offset;
4535}
4536
4537/* Parse an unwind_raw directive. */
4538
4539static void
4540s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4541{
4542 expressionS exp;
4543 /* This is an arbitrary limit. */
4544 unsigned char op[16];
4545 int count;
4546
4547 if (!unwind.proc_start)
4548 as_bad (MISSING_FNSTART);
4549
4550 expression (&exp);
4551 if (exp.X_op == O_constant
4552 && skip_past_comma (&input_line_pointer) != FAIL)
4553 {
4554 unwind.frame_size += exp.X_add_number;
4555 expression (&exp);
4556 }
4557 else
4558 exp.X_op = O_illegal;
4559
4560 if (exp.X_op != O_constant)
4561 {
4562 as_bad (_("expected <offset>, <opcode>"));
4563 ignore_rest_of_line ();
4564 return;
4565 }
4566
4567 count = 0;
4568
4569 /* Parse the opcode. */
4570 for (;;)
4571 {
4572 if (count >= 16)
4573 {
4574 as_bad (_("unwind opcode too long"));
4575 ignore_rest_of_line ();
4576 }
4577 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4578 {
4579 as_bad (_("invalid unwind opcode"));
4580 ignore_rest_of_line ();
4581 return;
4582 }
4583 op[count++] = exp.X_add_number;
4584
4585 /* Parse the next byte. */
4586 if (skip_past_comma (&input_line_pointer) == FAIL)
4587 break;
4588
4589 expression (&exp);
4590 }
4591
4592 /* Add the opcode bytes in reverse order. */
4593 while (count--)
4594 add_unwind_opcode (op[count], 1);
4595
4596 demand_empty_rest_of_line ();
4597}
4598
4599
4600/* Parse a .eabi_attribute directive. */
4601
4602static void
4603s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4604{
4605 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4606
4607 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4608 attributes_set_explicitly[tag] = 1;
4609}
4610
4611/* Emit a tls fix for the symbol. */
4612
4613static void
4614s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4615{
4616 char *p;
4617 expressionS exp;
4618#ifdef md_flush_pending_output
4619 md_flush_pending_output ();
4620#endif
4621
4622#ifdef md_cons_align
4623 md_cons_align (4);
4624#endif
4625
4626 /* Since we're just labelling the code, there's no need to define a
4627 mapping symbol. */
4628 expression (&exp);
4629 p = obstack_next_free (&frchain_now->frch_obstack);
4630 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4631 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4632 : BFD_RELOC_ARM_TLS_DESCSEQ);
4633}
4634#endif /* OBJ_ELF */
4635
4636static void s_arm_arch (int);
4637static void s_arm_object_arch (int);
4638static void s_arm_cpu (int);
4639static void s_arm_fpu (int);
4640static void s_arm_arch_extension (int);
4641
4642#ifdef TE_PE
4643
4644static void
4645pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4646{
4647 expressionS exp;
4648
4649 do
4650 {
4651 expression (&exp);
4652 if (exp.X_op == O_symbol)
4653 exp.X_op = O_secrel;
4654
4655 emit_expr (&exp, 4);
4656 }
4657 while (*input_line_pointer++ == ',');
4658
4659 input_line_pointer--;
4660 demand_empty_rest_of_line ();
4661}
4662#endif /* TE_PE */
4663
4664/* This table describes all the machine specific pseudo-ops the assembler
4665 has to support. The fields are:
4666 pseudo-op name without dot
4667 function to call to execute this pseudo-op
4668 Integer arg to pass to the function. */
4669
4670const pseudo_typeS md_pseudo_table[] =
4671{
4672 /* Never called because '.req' does not start a line. */
4673 { "req", s_req, 0 },
4674 /* Following two are likewise never called. */
4675 { "dn", s_dn, 0 },
4676 { "qn", s_qn, 0 },
4677 { "unreq", s_unreq, 0 },
4678 { "bss", s_bss, 0 },
4679 { "align", s_align_ptwo, 2 },
4680 { "arm", s_arm, 0 },
4681 { "thumb", s_thumb, 0 },
4682 { "code", s_code, 0 },
4683 { "force_thumb", s_force_thumb, 0 },
4684 { "thumb_func", s_thumb_func, 0 },
4685 { "thumb_set", s_thumb_set, 0 },
4686 { "even", s_even, 0 },
4687 { "ltorg", s_ltorg, 0 },
4688 { "pool", s_ltorg, 0 },
4689 { "syntax", s_syntax, 0 },
4690 { "cpu", s_arm_cpu, 0 },
4691 { "arch", s_arm_arch, 0 },
4692 { "object_arch", s_arm_object_arch, 0 },
4693 { "fpu", s_arm_fpu, 0 },
4694 { "arch_extension", s_arm_arch_extension, 0 },
4695#ifdef OBJ_ELF
4696 { "word", s_arm_elf_cons, 4 },
4697 { "long", s_arm_elf_cons, 4 },
4698 { "inst.n", s_arm_elf_inst, 2 },
4699 { "inst.w", s_arm_elf_inst, 4 },
4700 { "inst", s_arm_elf_inst, 0 },
4701 { "rel31", s_arm_rel31, 0 },
4702 { "fnstart", s_arm_unwind_fnstart, 0 },
4703 { "fnend", s_arm_unwind_fnend, 0 },
4704 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4705 { "personality", s_arm_unwind_personality, 0 },
4706 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4707 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4708 { "save", s_arm_unwind_save, 0 },
4709 { "vsave", s_arm_unwind_save, 1 },
4710 { "movsp", s_arm_unwind_movsp, 0 },
4711 { "pad", s_arm_unwind_pad, 0 },
4712 { "setfp", s_arm_unwind_setfp, 0 },
4713 { "unwind_raw", s_arm_unwind_raw, 0 },
4714 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4715 { "tlsdescseq", s_arm_tls_descseq, 0 },
4716#else
4717 { "word", cons, 4},
4718
4719 /* These are used for dwarf. */
4720 {"2byte", cons, 2},
4721 {"4byte", cons, 4},
4722 {"8byte", cons, 8},
4723 /* These are used for dwarf2. */
4724 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4725 { "loc", dwarf2_directive_loc, 0 },
4726 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4727#endif
4728 { "extend", float_cons, 'x' },
4729 { "ldouble", float_cons, 'x' },
4730 { "packed", float_cons, 'p' },
4731#ifdef TE_PE
4732 {"secrel32", pe_directive_secrel, 0},
4733#endif
4734
4735 /* These are for compatibility with CodeComposer Studio. */
4736 {"ref", s_ccs_ref, 0},
4737 {"def", s_ccs_def, 0},
4738 {"asmfunc", s_ccs_asmfunc, 0},
4739 {"endasmfunc", s_ccs_endasmfunc, 0},
4740
4741 { 0, 0, 0 }
4742};
4743\f
4744/* Parser functions used exclusively in instruction operands. */
4745
4746/* Generic immediate-value read function for use in insn parsing.
4747 STR points to the beginning of the immediate (the leading #);
4748 VAL receives the value; if the value is outside [MIN, MAX]
4749 issue an error. PREFIX_OPT is true if the immediate prefix is
4750 optional. */
4751
4752static int
4753parse_immediate (char **str, int *val, int min, int max,
4754 bfd_boolean prefix_opt)
4755{
4756 expressionS exp;
4757 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4758 if (exp.X_op != O_constant)
4759 {
4760 inst.error = _("constant expression required");
4761 return FAIL;
4762 }
4763
4764 if (exp.X_add_number < min || exp.X_add_number > max)
4765 {
4766 inst.error = _("immediate value out of range");
4767 return FAIL;
4768 }
4769
4770 *val = exp.X_add_number;
4771 return SUCCESS;
4772}
4773
4774/* Less-generic immediate-value read function with the possibility of loading a
4775 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4776 instructions. Puts the result directly in inst.operands[i]. */
4777
4778static int
4779parse_big_immediate (char **str, int i, expressionS *in_exp,
4780 bfd_boolean allow_symbol_p)
4781{
4782 expressionS exp;
4783 expressionS *exp_p = in_exp ? in_exp : &exp;
4784 char *ptr = *str;
4785
4786 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
4787
4788 if (exp_p->X_op == O_constant)
4789 {
4790 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
4791 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4792 O_constant. We have to be careful not to break compilation for
4793 32-bit X_add_number, though. */
4794 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4795 {
4796 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4797 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
4798 & 0xffffffff);
4799 inst.operands[i].regisimm = 1;
4800 }
4801 }
4802 else if (exp_p->X_op == O_big
4803 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
4804 {
4805 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4806
4807 /* Bignums have their least significant bits in
4808 generic_bignum[0]. Make sure we put 32 bits in imm and
4809 32 bits in reg, in a (hopefully) portable way. */
4810 gas_assert (parts != 0);
4811
4812 /* Make sure that the number is not too big.
4813 PR 11972: Bignums can now be sign-extended to the
4814 size of a .octa so check that the out of range bits
4815 are all zero or all one. */
4816 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
4817 {
4818 LITTLENUM_TYPE m = -1;
4819
4820 if (generic_bignum[parts * 2] != 0
4821 && generic_bignum[parts * 2] != m)
4822 return FAIL;
4823
4824 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
4825 if (generic_bignum[j] != generic_bignum[j-1])
4826 return FAIL;
4827 }
4828
4829 inst.operands[i].imm = 0;
4830 for (j = 0; j < parts; j++, idx++)
4831 inst.operands[i].imm |= generic_bignum[idx]
4832 << (LITTLENUM_NUMBER_OF_BITS * j);
4833 inst.operands[i].reg = 0;
4834 for (j = 0; j < parts; j++, idx++)
4835 inst.operands[i].reg |= generic_bignum[idx]
4836 << (LITTLENUM_NUMBER_OF_BITS * j);
4837 inst.operands[i].regisimm = 1;
4838 }
4839 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
4840 return FAIL;
4841
4842 *str = ptr;
4843
4844 return SUCCESS;
4845}
4846
4847/* Returns the pseudo-register number of an FPA immediate constant,
4848 or FAIL if there isn't a valid constant here. */
4849
4850static int
4851parse_fpa_immediate (char ** str)
4852{
4853 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4854 char * save_in;
4855 expressionS exp;
4856 int i;
4857 int j;
4858
4859 /* First try and match exact strings, this is to guarantee
4860 that some formats will work even for cross assembly. */
4861
4862 for (i = 0; fp_const[i]; i++)
4863 {
4864 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4865 {
4866 char *start = *str;
4867
4868 *str += strlen (fp_const[i]);
4869 if (is_end_of_line[(unsigned char) **str])
4870 return i + 8;
4871 *str = start;
4872 }
4873 }
4874
4875 /* Just because we didn't get a match doesn't mean that the constant
4876 isn't valid, just that it is in a format that we don't
4877 automatically recognize. Try parsing it with the standard
4878 expression routines. */
4879
4880 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4881
4882 /* Look for a raw floating point number. */
4883 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4884 && is_end_of_line[(unsigned char) *save_in])
4885 {
4886 for (i = 0; i < NUM_FLOAT_VALS; i++)
4887 {
4888 for (j = 0; j < MAX_LITTLENUMS; j++)
4889 {
4890 if (words[j] != fp_values[i][j])
4891 break;
4892 }
4893
4894 if (j == MAX_LITTLENUMS)
4895 {
4896 *str = save_in;
4897 return i + 8;
4898 }
4899 }
4900 }
4901
4902 /* Try and parse a more complex expression, this will probably fail
4903 unless the code uses a floating point prefix (eg "0f"). */
4904 save_in = input_line_pointer;
4905 input_line_pointer = *str;
4906 if (expression (&exp) == absolute_section
4907 && exp.X_op == O_big
4908 && exp.X_add_number < 0)
4909 {
4910 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4911 Ditto for 15. */
4912#define X_PRECISION 5
4913#define E_PRECISION 15L
4914 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
4915 {
4916 for (i = 0; i < NUM_FLOAT_VALS; i++)
4917 {
4918 for (j = 0; j < MAX_LITTLENUMS; j++)
4919 {
4920 if (words[j] != fp_values[i][j])
4921 break;
4922 }
4923
4924 if (j == MAX_LITTLENUMS)
4925 {
4926 *str = input_line_pointer;
4927 input_line_pointer = save_in;
4928 return i + 8;
4929 }
4930 }
4931 }
4932 }
4933
4934 *str = input_line_pointer;
4935 input_line_pointer = save_in;
4936 inst.error = _("invalid FPA immediate expression");
4937 return FAIL;
4938}
4939
4940/* Returns 1 if a number has "quarter-precision" float format
4941 0baBbbbbbc defgh000 00000000 00000000. */
4942
4943static int
4944is_quarter_float (unsigned imm)
4945{
4946 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4947 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4948}
4949
4950
4951/* Detect the presence of a floating point or integer zero constant,
4952 i.e. #0.0 or #0. */
4953
4954static bfd_boolean
4955parse_ifimm_zero (char **in)
4956{
4957 int error_code;
4958
4959 if (!is_immediate_prefix (**in))
4960 return FALSE;
4961
4962 ++*in;
4963
4964 /* Accept #0x0 as a synonym for #0. */
4965 if (strncmp (*in, "0x", 2) == 0)
4966 {
4967 int val;
4968 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
4969 return FALSE;
4970 return TRUE;
4971 }
4972
4973 error_code = atof_generic (in, ".", EXP_CHARS,
4974 &generic_floating_point_number);
4975
4976 if (!error_code
4977 && generic_floating_point_number.sign == '+'
4978 && (generic_floating_point_number.low
4979 > generic_floating_point_number.leader))
4980 return TRUE;
4981
4982 return FALSE;
4983}
4984
4985/* Parse an 8-bit "quarter-precision" floating point number of the form:
4986 0baBbbbbbc defgh000 00000000 00000000.
4987 The zero and minus-zero cases need special handling, since they can't be
4988 encoded in the "quarter-precision" float format, but can nonetheless be
4989 loaded as integer constants. */
4990
4991static unsigned
4992parse_qfloat_immediate (char **ccp, int *immed)
4993{
4994 char *str = *ccp;
4995 char *fpnum;
4996 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4997 int found_fpchar = 0;
4998
4999 skip_past_char (&str, '#');
5000
5001 /* We must not accidentally parse an integer as a floating-point number. Make
5002 sure that the value we parse is not an integer by checking for special
5003 characters '.' or 'e'.
5004 FIXME: This is a horrible hack, but doing better is tricky because type
5005 information isn't in a very usable state at parse time. */
5006 fpnum = str;
5007 skip_whitespace (fpnum);
5008
5009 if (strncmp (fpnum, "0x", 2) == 0)
5010 return FAIL;
5011 else
5012 {
5013 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
5014 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5015 {
5016 found_fpchar = 1;
5017 break;
5018 }
5019
5020 if (!found_fpchar)
5021 return FAIL;
5022 }
5023
5024 if ((str = atof_ieee (str, 's', words)) != NULL)
5025 {
5026 unsigned fpword = 0;
5027 int i;
5028
5029 /* Our FP word must be 32 bits (single-precision FP). */
5030 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
5031 {
5032 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5033 fpword |= words[i];
5034 }
5035
5036 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
5037 *immed = fpword;
5038 else
5039 return FAIL;
5040
5041 *ccp = str;
5042
5043 return SUCCESS;
5044 }
5045
5046 return FAIL;
5047}
5048
5049/* Shift operands. */
5050enum shift_kind
5051{
5052 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
5053};
5054
5055struct asm_shift_name
5056{
5057 const char *name;
5058 enum shift_kind kind;
5059};
5060
5061/* Third argument to parse_shift. */
5062enum parse_shift_mode
5063{
5064 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5065 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5066 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5067 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5068 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
5069};
5070
5071/* Parse a <shift> specifier on an ARM data processing instruction.
5072 This has three forms:
5073
5074 (LSL|LSR|ASL|ASR|ROR) Rs
5075 (LSL|LSR|ASL|ASR|ROR) #imm
5076 RRX
5077
5078 Note that ASL is assimilated to LSL in the instruction encoding, and
5079 RRX to ROR #0 (which cannot be written as such). */
5080
5081static int
5082parse_shift (char **str, int i, enum parse_shift_mode mode)
5083{
5084 const struct asm_shift_name *shift_name;
5085 enum shift_kind shift;
5086 char *s = *str;
5087 char *p = s;
5088 int reg;
5089
5090 for (p = *str; ISALPHA (*p); p++)
5091 ;
5092
5093 if (p == *str)
5094 {
5095 inst.error = _("shift expression expected");
5096 return FAIL;
5097 }
5098
5099 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
5100 p - *str);
5101
5102 if (shift_name == NULL)
5103 {
5104 inst.error = _("shift expression expected");
5105 return FAIL;
5106 }
5107
5108 shift = shift_name->kind;
5109
5110 switch (mode)
5111 {
5112 case NO_SHIFT_RESTRICT:
5113 case SHIFT_IMMEDIATE: break;
5114
5115 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5116 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5117 {
5118 inst.error = _("'LSL' or 'ASR' required");
5119 return FAIL;
5120 }
5121 break;
5122
5123 case SHIFT_LSL_IMMEDIATE:
5124 if (shift != SHIFT_LSL)
5125 {
5126 inst.error = _("'LSL' required");
5127 return FAIL;
5128 }
5129 break;
5130
5131 case SHIFT_ASR_IMMEDIATE:
5132 if (shift != SHIFT_ASR)
5133 {
5134 inst.error = _("'ASR' required");
5135 return FAIL;
5136 }
5137 break;
5138
5139 default: abort ();
5140 }
5141
5142 if (shift != SHIFT_RRX)
5143 {
5144 /* Whitespace can appear here if the next thing is a bare digit. */
5145 skip_whitespace (p);
5146
5147 if (mode == NO_SHIFT_RESTRICT
5148 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5149 {
5150 inst.operands[i].imm = reg;
5151 inst.operands[i].immisreg = 1;
5152 }
5153 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5154 return FAIL;
5155 }
5156 inst.operands[i].shift_kind = shift;
5157 inst.operands[i].shifted = 1;
5158 *str = p;
5159 return SUCCESS;
5160}
5161
5162/* Parse a <shifter_operand> for an ARM data processing instruction:
5163
5164 #<immediate>
5165 #<immediate>, <rotate>
5166 <Rm>
5167 <Rm>, <shift>
5168
5169 where <shift> is defined by parse_shift above, and <rotate> is a
5170 multiple of 2 between 0 and 30. Validation of immediate operands
5171 is deferred to md_apply_fix. */
5172
5173static int
5174parse_shifter_operand (char **str, int i)
5175{
5176 int value;
5177 expressionS exp;
5178
5179 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
5180 {
5181 inst.operands[i].reg = value;
5182 inst.operands[i].isreg = 1;
5183
5184 /* parse_shift will override this if appropriate */
5185 inst.reloc.exp.X_op = O_constant;
5186 inst.reloc.exp.X_add_number = 0;
5187
5188 if (skip_past_comma (str) == FAIL)
5189 return SUCCESS;
5190
5191 /* Shift operation on register. */
5192 return parse_shift (str, i, NO_SHIFT_RESTRICT);
5193 }
5194
5195 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
5196 return FAIL;
5197
5198 if (skip_past_comma (str) == SUCCESS)
5199 {
5200 /* #x, y -- ie explicit rotation by Y. */
5201 if (my_get_expression (&exp, str, GE_NO_PREFIX))
5202 return FAIL;
5203
5204 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
5205 {
5206 inst.error = _("constant expression expected");
5207 return FAIL;
5208 }
5209
5210 value = exp.X_add_number;
5211 if (value < 0 || value > 30 || value % 2 != 0)
5212 {
5213 inst.error = _("invalid rotation");
5214 return FAIL;
5215 }
5216 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
5217 {
5218 inst.error = _("invalid constant");
5219 return FAIL;
5220 }
5221
5222 /* Encode as specified. */
5223 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
5224 return SUCCESS;
5225 }
5226
5227 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5228 inst.reloc.pc_rel = 0;
5229 return SUCCESS;
5230}
5231
5232/* Group relocation information. Each entry in the table contains the
5233 textual name of the relocation as may appear in assembler source
5234 and must end with a colon.
5235 Along with this textual name are the relocation codes to be used if
5236 the corresponding instruction is an ALU instruction (ADD or SUB only),
5237 an LDR, an LDRS, or an LDC. */
5238
5239struct group_reloc_table_entry
5240{
5241 const char *name;
5242 int alu_code;
5243 int ldr_code;
5244 int ldrs_code;
5245 int ldc_code;
5246};
5247
5248typedef enum
5249{
5250 /* Varieties of non-ALU group relocation. */
5251
5252 GROUP_LDR,
5253 GROUP_LDRS,
5254 GROUP_LDC
5255} group_reloc_type;
5256
5257static struct group_reloc_table_entry group_reloc_table[] =
5258 { /* Program counter relative: */
5259 { "pc_g0_nc",
5260 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5261 0, /* LDR */
5262 0, /* LDRS */
5263 0 }, /* LDC */
5264 { "pc_g0",
5265 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5266 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5267 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5268 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5269 { "pc_g1_nc",
5270 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5271 0, /* LDR */
5272 0, /* LDRS */
5273 0 }, /* LDC */
5274 { "pc_g1",
5275 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5276 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5277 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5278 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5279 { "pc_g2",
5280 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5281 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5282 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5283 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5284 /* Section base relative */
5285 { "sb_g0_nc",
5286 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5287 0, /* LDR */
5288 0, /* LDRS */
5289 0 }, /* LDC */
5290 { "sb_g0",
5291 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5292 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5293 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5294 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5295 { "sb_g1_nc",
5296 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5297 0, /* LDR */
5298 0, /* LDRS */
5299 0 }, /* LDC */
5300 { "sb_g1",
5301 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5302 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5303 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5304 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5305 { "sb_g2",
5306 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5307 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5308 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5309 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5310 /* Absolute thumb alu relocations. */
5311 { "lower0_7",
5312 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5313 0, /* LDR. */
5314 0, /* LDRS. */
5315 0 }, /* LDC. */
5316 { "lower8_15",
5317 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5318 0, /* LDR. */
5319 0, /* LDRS. */
5320 0 }, /* LDC. */
5321 { "upper0_7",
5322 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5323 0, /* LDR. */
5324 0, /* LDRS. */
5325 0 }, /* LDC. */
5326 { "upper8_15",
5327 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5328 0, /* LDR. */
5329 0, /* LDRS. */
5330 0 } }; /* LDC. */
5331
5332/* Given the address of a pointer pointing to the textual name of a group
5333 relocation as may appear in assembler source, attempt to find its details
5334 in group_reloc_table. The pointer will be updated to the character after
5335 the trailing colon. On failure, FAIL will be returned; SUCCESS
5336 otherwise. On success, *entry will be updated to point at the relevant
5337 group_reloc_table entry. */
5338
5339static int
5340find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5341{
5342 unsigned int i;
5343 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5344 {
5345 int length = strlen (group_reloc_table[i].name);
5346
5347 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5348 && (*str)[length] == ':')
5349 {
5350 *out = &group_reloc_table[i];
5351 *str += (length + 1);
5352 return SUCCESS;
5353 }
5354 }
5355
5356 return FAIL;
5357}
5358
5359/* Parse a <shifter_operand> for an ARM data processing instruction
5360 (as for parse_shifter_operand) where group relocations are allowed:
5361
5362 #<immediate>
5363 #<immediate>, <rotate>
5364 #:<group_reloc>:<expression>
5365 <Rm>
5366 <Rm>, <shift>
5367
5368 where <group_reloc> is one of the strings defined in group_reloc_table.
5369 The hashes are optional.
5370
5371 Everything else is as for parse_shifter_operand. */
5372
5373static parse_operand_result
5374parse_shifter_operand_group_reloc (char **str, int i)
5375{
5376 /* Determine if we have the sequence of characters #: or just :
5377 coming next. If we do, then we check for a group relocation.
5378 If we don't, punt the whole lot to parse_shifter_operand. */
5379
5380 if (((*str)[0] == '#' && (*str)[1] == ':')
5381 || (*str)[0] == ':')
5382 {
5383 struct group_reloc_table_entry *entry;
5384
5385 if ((*str)[0] == '#')
5386 (*str) += 2;
5387 else
5388 (*str)++;
5389
5390 /* Try to parse a group relocation. Anything else is an error. */
5391 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5392 {
5393 inst.error = _("unknown group relocation");
5394 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5395 }
5396
5397 /* We now have the group relocation table entry corresponding to
5398 the name in the assembler source. Next, we parse the expression. */
5399 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5400 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5401
5402 /* Record the relocation type (always the ALU variant here). */
5403 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5404 gas_assert (inst.reloc.type != 0);
5405
5406 return PARSE_OPERAND_SUCCESS;
5407 }
5408 else
5409 return parse_shifter_operand (str, i) == SUCCESS
5410 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5411
5412 /* Never reached. */
5413}
5414
5415/* Parse a Neon alignment expression. Information is written to
5416 inst.operands[i]. We assume the initial ':' has been skipped.
5417
5418 align .imm = align << 8, .immisalign=1, .preind=0 */
5419static parse_operand_result
5420parse_neon_alignment (char **str, int i)
5421{
5422 char *p = *str;
5423 expressionS exp;
5424
5425 my_get_expression (&exp, &p, GE_NO_PREFIX);
5426
5427 if (exp.X_op != O_constant)
5428 {
5429 inst.error = _("alignment must be constant");
5430 return PARSE_OPERAND_FAIL;
5431 }
5432
5433 inst.operands[i].imm = exp.X_add_number << 8;
5434 inst.operands[i].immisalign = 1;
5435 /* Alignments are not pre-indexes. */
5436 inst.operands[i].preind = 0;
5437
5438 *str = p;
5439 return PARSE_OPERAND_SUCCESS;
5440}
5441
5442/* Parse all forms of an ARM address expression. Information is written
5443 to inst.operands[i] and/or inst.reloc.
5444
5445 Preindexed addressing (.preind=1):
5446
5447 [Rn, #offset] .reg=Rn .reloc.exp=offset
5448 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5449 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5450 .shift_kind=shift .reloc.exp=shift_imm
5451
5452 These three may have a trailing ! which causes .writeback to be set also.
5453
5454 Postindexed addressing (.postind=1, .writeback=1):
5455
5456 [Rn], #offset .reg=Rn .reloc.exp=offset
5457 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5458 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5459 .shift_kind=shift .reloc.exp=shift_imm
5460
5461 Unindexed addressing (.preind=0, .postind=0):
5462
5463 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5464
5465 Other:
5466
5467 [Rn]{!} shorthand for [Rn,#0]{!}
5468 =immediate .isreg=0 .reloc.exp=immediate
5469 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5470
5471 It is the caller's responsibility to check for addressing modes not
5472 supported by the instruction, and to set inst.reloc.type. */
5473
5474static parse_operand_result
5475parse_address_main (char **str, int i, int group_relocations,
5476 group_reloc_type group_type)
5477{
5478 char *p = *str;
5479 int reg;
5480
5481 if (skip_past_char (&p, '[') == FAIL)
5482 {
5483 if (skip_past_char (&p, '=') == FAIL)
5484 {
5485 /* Bare address - translate to PC-relative offset. */
5486 inst.reloc.pc_rel = 1;
5487 inst.operands[i].reg = REG_PC;
5488 inst.operands[i].isreg = 1;
5489 inst.operands[i].preind = 1;
5490
5491 if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG))
5492 return PARSE_OPERAND_FAIL;
5493 }
5494 else if (parse_big_immediate (&p, i, &inst.reloc.exp,
5495 /*allow_symbol_p=*/TRUE))
5496 return PARSE_OPERAND_FAIL;
5497
5498 *str = p;
5499 return PARSE_OPERAND_SUCCESS;
5500 }
5501
5502 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5503 skip_whitespace (p);
5504
5505 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5506 {
5507 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5508 return PARSE_OPERAND_FAIL;
5509 }
5510 inst.operands[i].reg = reg;
5511 inst.operands[i].isreg = 1;
5512
5513 if (skip_past_comma (&p) == SUCCESS)
5514 {
5515 inst.operands[i].preind = 1;
5516
5517 if (*p == '+') p++;
5518 else if (*p == '-') p++, inst.operands[i].negative = 1;
5519
5520 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5521 {
5522 inst.operands[i].imm = reg;
5523 inst.operands[i].immisreg = 1;
5524
5525 if (skip_past_comma (&p) == SUCCESS)
5526 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5527 return PARSE_OPERAND_FAIL;
5528 }
5529 else if (skip_past_char (&p, ':') == SUCCESS)
5530 {
5531 /* FIXME: '@' should be used here, but it's filtered out by generic
5532 code before we get to see it here. This may be subject to
5533 change. */
5534 parse_operand_result result = parse_neon_alignment (&p, i);
5535
5536 if (result != PARSE_OPERAND_SUCCESS)
5537 return result;
5538 }
5539 else
5540 {
5541 if (inst.operands[i].negative)
5542 {
5543 inst.operands[i].negative = 0;
5544 p--;
5545 }
5546
5547 if (group_relocations
5548 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5549 {
5550 struct group_reloc_table_entry *entry;
5551
5552 /* Skip over the #: or : sequence. */
5553 if (*p == '#')
5554 p += 2;
5555 else
5556 p++;
5557
5558 /* Try to parse a group relocation. Anything else is an
5559 error. */
5560 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5561 {
5562 inst.error = _("unknown group relocation");
5563 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5564 }
5565
5566 /* We now have the group relocation table entry corresponding to
5567 the name in the assembler source. Next, we parse the
5568 expression. */
5569 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5570 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5571
5572 /* Record the relocation type. */
5573 switch (group_type)
5574 {
5575 case GROUP_LDR:
5576 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5577 break;
5578
5579 case GROUP_LDRS:
5580 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5581 break;
5582
5583 case GROUP_LDC:
5584 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5585 break;
5586
5587 default:
5588 gas_assert (0);
5589 }
5590
5591 if (inst.reloc.type == 0)
5592 {
5593 inst.error = _("this group relocation is not allowed on this instruction");
5594 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5595 }
5596 }
5597 else
5598 {
5599 char *q = p;
5600 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5601 return PARSE_OPERAND_FAIL;
5602 /* If the offset is 0, find out if it's a +0 or -0. */
5603 if (inst.reloc.exp.X_op == O_constant
5604 && inst.reloc.exp.X_add_number == 0)
5605 {
5606 skip_whitespace (q);
5607 if (*q == '#')
5608 {
5609 q++;
5610 skip_whitespace (q);
5611 }
5612 if (*q == '-')
5613 inst.operands[i].negative = 1;
5614 }
5615 }
5616 }
5617 }
5618 else if (skip_past_char (&p, ':') == SUCCESS)
5619 {
5620 /* FIXME: '@' should be used here, but it's filtered out by generic code
5621 before we get to see it here. This may be subject to change. */
5622 parse_operand_result result = parse_neon_alignment (&p, i);
5623
5624 if (result != PARSE_OPERAND_SUCCESS)
5625 return result;
5626 }
5627
5628 if (skip_past_char (&p, ']') == FAIL)
5629 {
5630 inst.error = _("']' expected");
5631 return PARSE_OPERAND_FAIL;
5632 }
5633
5634 if (skip_past_char (&p, '!') == SUCCESS)
5635 inst.operands[i].writeback = 1;
5636
5637 else if (skip_past_comma (&p) == SUCCESS)
5638 {
5639 if (skip_past_char (&p, '{') == SUCCESS)
5640 {
5641 /* [Rn], {expr} - unindexed, with option */
5642 if (parse_immediate (&p, &inst.operands[i].imm,
5643 0, 255, TRUE) == FAIL)
5644 return PARSE_OPERAND_FAIL;
5645
5646 if (skip_past_char (&p, '}') == FAIL)
5647 {
5648 inst.error = _("'}' expected at end of 'option' field");
5649 return PARSE_OPERAND_FAIL;
5650 }
5651 if (inst.operands[i].preind)
5652 {
5653 inst.error = _("cannot combine index with option");
5654 return PARSE_OPERAND_FAIL;
5655 }
5656 *str = p;
5657 return PARSE_OPERAND_SUCCESS;
5658 }
5659 else
5660 {
5661 inst.operands[i].postind = 1;
5662 inst.operands[i].writeback = 1;
5663
5664 if (inst.operands[i].preind)
5665 {
5666 inst.error = _("cannot combine pre- and post-indexing");
5667 return PARSE_OPERAND_FAIL;
5668 }
5669
5670 if (*p == '+') p++;
5671 else if (*p == '-') p++, inst.operands[i].negative = 1;
5672
5673 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5674 {
5675 /* We might be using the immediate for alignment already. If we
5676 are, OR the register number into the low-order bits. */
5677 if (inst.operands[i].immisalign)
5678 inst.operands[i].imm |= reg;
5679 else
5680 inst.operands[i].imm = reg;
5681 inst.operands[i].immisreg = 1;
5682
5683 if (skip_past_comma (&p) == SUCCESS)
5684 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5685 return PARSE_OPERAND_FAIL;
5686 }
5687 else
5688 {
5689 char *q = p;
5690 if (inst.operands[i].negative)
5691 {
5692 inst.operands[i].negative = 0;
5693 p--;
5694 }
5695 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5696 return PARSE_OPERAND_FAIL;
5697 /* If the offset is 0, find out if it's a +0 or -0. */
5698 if (inst.reloc.exp.X_op == O_constant
5699 && inst.reloc.exp.X_add_number == 0)
5700 {
5701 skip_whitespace (q);
5702 if (*q == '#')
5703 {
5704 q++;
5705 skip_whitespace (q);
5706 }
5707 if (*q == '-')
5708 inst.operands[i].negative = 1;
5709 }
5710 }
5711 }
5712 }
5713
5714 /* If at this point neither .preind nor .postind is set, we have a
5715 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5716 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5717 {
5718 inst.operands[i].preind = 1;
5719 inst.reloc.exp.X_op = O_constant;
5720 inst.reloc.exp.X_add_number = 0;
5721 }
5722 *str = p;
5723 return PARSE_OPERAND_SUCCESS;
5724}
5725
5726static int
5727parse_address (char **str, int i)
5728{
5729 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5730 ? SUCCESS : FAIL;
5731}
5732
5733static parse_operand_result
5734parse_address_group_reloc (char **str, int i, group_reloc_type type)
5735{
5736 return parse_address_main (str, i, 1, type);
5737}
5738
5739/* Parse an operand for a MOVW or MOVT instruction. */
5740static int
5741parse_half (char **str)
5742{
5743 char * p;
5744
5745 p = *str;
5746 skip_past_char (&p, '#');
5747 if (strncasecmp (p, ":lower16:", 9) == 0)
5748 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5749 else if (strncasecmp (p, ":upper16:", 9) == 0)
5750 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5751
5752 if (inst.reloc.type != BFD_RELOC_UNUSED)
5753 {
5754 p += 9;
5755 skip_whitespace (p);
5756 }
5757
5758 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5759 return FAIL;
5760
5761 if (inst.reloc.type == BFD_RELOC_UNUSED)
5762 {
5763 if (inst.reloc.exp.X_op != O_constant)
5764 {
5765 inst.error = _("constant expression expected");
5766 return FAIL;
5767 }
5768 if (inst.reloc.exp.X_add_number < 0
5769 || inst.reloc.exp.X_add_number > 0xffff)
5770 {
5771 inst.error = _("immediate value out of range");
5772 return FAIL;
5773 }
5774 }
5775 *str = p;
5776 return SUCCESS;
5777}
5778
5779/* Miscellaneous. */
5780
5781/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5782 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5783static int
5784parse_psr (char **str, bfd_boolean lhs)
5785{
5786 char *p;
5787 unsigned long psr_field;
5788 const struct asm_psr *psr;
5789 char *start;
5790 bfd_boolean is_apsr = FALSE;
5791 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5792
5793 /* PR gas/12698: If the user has specified -march=all then m_profile will
5794 be TRUE, but we want to ignore it in this case as we are building for any
5795 CPU type, including non-m variants. */
5796 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
5797 m_profile = FALSE;
5798
5799 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5800 feature for ease of use and backwards compatibility. */
5801 p = *str;
5802 if (strncasecmp (p, "SPSR", 4) == 0)
5803 {
5804 if (m_profile)
5805 goto unsupported_psr;
5806
5807 psr_field = SPSR_BIT;
5808 }
5809 else if (strncasecmp (p, "CPSR", 4) == 0)
5810 {
5811 if (m_profile)
5812 goto unsupported_psr;
5813
5814 psr_field = 0;
5815 }
5816 else if (strncasecmp (p, "APSR", 4) == 0)
5817 {
5818 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5819 and ARMv7-R architecture CPUs. */
5820 is_apsr = TRUE;
5821 psr_field = 0;
5822 }
5823 else if (m_profile)
5824 {
5825 start = p;
5826 do
5827 p++;
5828 while (ISALNUM (*p) || *p == '_');
5829
5830 if (strncasecmp (start, "iapsr", 5) == 0
5831 || strncasecmp (start, "eapsr", 5) == 0
5832 || strncasecmp (start, "xpsr", 4) == 0
5833 || strncasecmp (start, "psr", 3) == 0)
5834 p = start + strcspn (start, "rR") + 1;
5835
5836 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5837 p - start);
5838
5839 if (!psr)
5840 return FAIL;
5841
5842 /* If APSR is being written, a bitfield may be specified. Note that
5843 APSR itself is handled above. */
5844 if (psr->field <= 3)
5845 {
5846 psr_field = psr->field;
5847 is_apsr = TRUE;
5848 goto check_suffix;
5849 }
5850
5851 *str = p;
5852 /* M-profile MSR instructions have the mask field set to "10", except
5853 *PSR variants which modify APSR, which may use a different mask (and
5854 have been handled already). Do that by setting the PSR_f field
5855 here. */
5856 return psr->field | (lhs ? PSR_f : 0);
5857 }
5858 else
5859 goto unsupported_psr;
5860
5861 p += 4;
5862check_suffix:
5863 if (*p == '_')
5864 {
5865 /* A suffix follows. */
5866 p++;
5867 start = p;
5868
5869 do
5870 p++;
5871 while (ISALNUM (*p) || *p == '_');
5872
5873 if (is_apsr)
5874 {
5875 /* APSR uses a notation for bits, rather than fields. */
5876 unsigned int nzcvq_bits = 0;
5877 unsigned int g_bit = 0;
5878 char *bit;
5879
5880 for (bit = start; bit != p; bit++)
5881 {
5882 switch (TOLOWER (*bit))
5883 {
5884 case 'n':
5885 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5886 break;
5887
5888 case 'z':
5889 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5890 break;
5891
5892 case 'c':
5893 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5894 break;
5895
5896 case 'v':
5897 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5898 break;
5899
5900 case 'q':
5901 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5902 break;
5903
5904 case 'g':
5905 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5906 break;
5907
5908 default:
5909 inst.error = _("unexpected bit specified after APSR");
5910 return FAIL;
5911 }
5912 }
5913
5914 if (nzcvq_bits == 0x1f)
5915 psr_field |= PSR_f;
5916
5917 if (g_bit == 0x1)
5918 {
5919 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5920 {
5921 inst.error = _("selected processor does not "
5922 "support DSP extension");
5923 return FAIL;
5924 }
5925
5926 psr_field |= PSR_s;
5927 }
5928
5929 if ((nzcvq_bits & 0x20) != 0
5930 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5931 || (g_bit & 0x2) != 0)
5932 {
5933 inst.error = _("bad bitmask specified after APSR");
5934 return FAIL;
5935 }
5936 }
5937 else
5938 {
5939 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5940 p - start);
5941 if (!psr)
5942 goto error;
5943
5944 psr_field |= psr->field;
5945 }
5946 }
5947 else
5948 {
5949 if (ISALNUM (*p))
5950 goto error; /* Garbage after "[CS]PSR". */
5951
5952 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5953 is deprecated, but allow it anyway. */
5954 if (is_apsr && lhs)
5955 {
5956 psr_field |= PSR_f;
5957 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5958 "deprecated"));
5959 }
5960 else if (!m_profile)
5961 /* These bits are never right for M-profile devices: don't set them
5962 (only code paths which read/write APSR reach here). */
5963 psr_field |= (PSR_c | PSR_f);
5964 }
5965 *str = p;
5966 return psr_field;
5967
5968 unsupported_psr:
5969 inst.error = _("selected processor does not support requested special "
5970 "purpose register");
5971 return FAIL;
5972
5973 error:
5974 inst.error = _("flag for {c}psr instruction expected");
5975 return FAIL;
5976}
5977
5978/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5979 value suitable for splatting into the AIF field of the instruction. */
5980
5981static int
5982parse_cps_flags (char **str)
5983{
5984 int val = 0;
5985 int saw_a_flag = 0;
5986 char *s = *str;
5987
5988 for (;;)
5989 switch (*s++)
5990 {
5991 case '\0': case ',':
5992 goto done;
5993
5994 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5995 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5996 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5997
5998 default:
5999 inst.error = _("unrecognized CPS flag");
6000 return FAIL;
6001 }
6002
6003 done:
6004 if (saw_a_flag == 0)
6005 {
6006 inst.error = _("missing CPS flags");
6007 return FAIL;
6008 }
6009
6010 *str = s - 1;
6011 return val;
6012}
6013
6014/* Parse an endian specifier ("BE" or "LE", case insensitive);
6015 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6016
6017static int
6018parse_endian_specifier (char **str)
6019{
6020 int little_endian;
6021 char *s = *str;
6022
6023 if (strncasecmp (s, "BE", 2))
6024 little_endian = 0;
6025 else if (strncasecmp (s, "LE", 2))
6026 little_endian = 1;
6027 else
6028 {
6029 inst.error = _("valid endian specifiers are be or le");
6030 return FAIL;
6031 }
6032
6033 if (ISALNUM (s[2]) || s[2] == '_')
6034 {
6035 inst.error = _("valid endian specifiers are be or le");
6036 return FAIL;
6037 }
6038
6039 *str = s + 2;
6040 return little_endian;
6041}
6042
6043/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6044 value suitable for poking into the rotate field of an sxt or sxta
6045 instruction, or FAIL on error. */
6046
6047static int
6048parse_ror (char **str)
6049{
6050 int rot;
6051 char *s = *str;
6052
6053 if (strncasecmp (s, "ROR", 3) == 0)
6054 s += 3;
6055 else
6056 {
6057 inst.error = _("missing rotation field after comma");
6058 return FAIL;
6059 }
6060
6061 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6062 return FAIL;
6063
6064 switch (rot)
6065 {
6066 case 0: *str = s; return 0x0;
6067 case 8: *str = s; return 0x1;
6068 case 16: *str = s; return 0x2;
6069 case 24: *str = s; return 0x3;
6070
6071 default:
6072 inst.error = _("rotation can only be 0, 8, 16, or 24");
6073 return FAIL;
6074 }
6075}
6076
6077/* Parse a conditional code (from conds[] below). The value returned is in the
6078 range 0 .. 14, or FAIL. */
6079static int
6080parse_cond (char **str)
6081{
6082 char *q;
6083 const struct asm_cond *c;
6084 int n;
6085 /* Condition codes are always 2 characters, so matching up to
6086 3 characters is sufficient. */
6087 char cond[3];
6088
6089 q = *str;
6090 n = 0;
6091 while (ISALPHA (*q) && n < 3)
6092 {
6093 cond[n] = TOLOWER (*q);
6094 q++;
6095 n++;
6096 }
6097
6098 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
6099 if (!c)
6100 {
6101 inst.error = _("condition required");
6102 return FAIL;
6103 }
6104
6105 *str = q;
6106 return c->value;
6107}
6108
6109/* Record a use of the given feature. */
6110static void
6111record_feature_use (const arm_feature_set *feature)
6112{
6113 if (thumb_mode)
6114 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
6115 else
6116 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
6117}
6118
6119/* If the given feature available in the selected CPU, mark it as used.
6120 Returns TRUE iff feature is available. */
6121static bfd_boolean
6122mark_feature_used (const arm_feature_set *feature)
6123{
6124 /* Ensure the option is valid on the current architecture. */
6125 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
6126 return FALSE;
6127
6128 /* Add the appropriate architecture feature for the barrier option used.
6129 */
6130 record_feature_use (feature);
6131
6132 return TRUE;
6133}
6134
6135/* Parse an option for a barrier instruction. Returns the encoding for the
6136 option, or FAIL. */
6137static int
6138parse_barrier (char **str)
6139{
6140 char *p, *q;
6141 const struct asm_barrier_opt *o;
6142
6143 p = q = *str;
6144 while (ISALPHA (*q))
6145 q++;
6146
6147 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
6148 q - p);
6149 if (!o)
6150 return FAIL;
6151
6152 if (!mark_feature_used (&o->arch))
6153 return FAIL;
6154
6155 *str = q;
6156 return o->value;
6157}
6158
6159/* Parse the operands of a table branch instruction. Similar to a memory
6160 operand. */
6161static int
6162parse_tb (char **str)
6163{
6164 char * p = *str;
6165 int reg;
6166
6167 if (skip_past_char (&p, '[') == FAIL)
6168 {
6169 inst.error = _("'[' expected");
6170 return FAIL;
6171 }
6172
6173 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6174 {
6175 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6176 return FAIL;
6177 }
6178 inst.operands[0].reg = reg;
6179
6180 if (skip_past_comma (&p) == FAIL)
6181 {
6182 inst.error = _("',' expected");
6183 return FAIL;
6184 }
6185
6186 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6187 {
6188 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6189 return FAIL;
6190 }
6191 inst.operands[0].imm = reg;
6192
6193 if (skip_past_comma (&p) == SUCCESS)
6194 {
6195 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6196 return FAIL;
6197 if (inst.reloc.exp.X_add_number != 1)
6198 {
6199 inst.error = _("invalid shift");
6200 return FAIL;
6201 }
6202 inst.operands[0].shifted = 1;
6203 }
6204
6205 if (skip_past_char (&p, ']') == FAIL)
6206 {
6207 inst.error = _("']' expected");
6208 return FAIL;
6209 }
6210 *str = p;
6211 return SUCCESS;
6212}
6213
6214/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6215 information on the types the operands can take and how they are encoded.
6216 Up to four operands may be read; this function handles setting the
6217 ".present" field for each read operand itself.
6218 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6219 else returns FAIL. */
6220
6221static int
6222parse_neon_mov (char **str, int *which_operand)
6223{
6224 int i = *which_operand, val;
6225 enum arm_reg_type rtype;
6226 char *ptr = *str;
6227 struct neon_type_el optype;
6228
6229 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6230 {
6231 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6232 inst.operands[i].reg = val;
6233 inst.operands[i].isscalar = 1;
6234 inst.operands[i].vectype = optype;
6235 inst.operands[i++].present = 1;
6236
6237 if (skip_past_comma (&ptr) == FAIL)
6238 goto wanted_comma;
6239
6240 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6241 goto wanted_arm;
6242
6243 inst.operands[i].reg = val;
6244 inst.operands[i].isreg = 1;
6245 inst.operands[i].present = 1;
6246 }
6247 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6248 != FAIL)
6249 {
6250 /* Cases 0, 1, 2, 3, 5 (D only). */
6251 if (skip_past_comma (&ptr) == FAIL)
6252 goto wanted_comma;
6253
6254 inst.operands[i].reg = val;
6255 inst.operands[i].isreg = 1;
6256 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6257 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6258 inst.operands[i].isvec = 1;
6259 inst.operands[i].vectype = optype;
6260 inst.operands[i++].present = 1;
6261
6262 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6263 {
6264 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6265 Case 13: VMOV <Sd>, <Rm> */
6266 inst.operands[i].reg = val;
6267 inst.operands[i].isreg = 1;
6268 inst.operands[i].present = 1;
6269
6270 if (rtype == REG_TYPE_NQ)
6271 {
6272 first_error (_("can't use Neon quad register here"));
6273 return FAIL;
6274 }
6275 else if (rtype != REG_TYPE_VFS)
6276 {
6277 i++;
6278 if (skip_past_comma (&ptr) == FAIL)
6279 goto wanted_comma;
6280 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6281 goto wanted_arm;
6282 inst.operands[i].reg = val;
6283 inst.operands[i].isreg = 1;
6284 inst.operands[i].present = 1;
6285 }
6286 }
6287 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6288 &optype)) != FAIL)
6289 {
6290 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6291 Case 1: VMOV<c><q> <Dd>, <Dm>
6292 Case 8: VMOV.F32 <Sd>, <Sm>
6293 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6294
6295 inst.operands[i].reg = val;
6296 inst.operands[i].isreg = 1;
6297 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6298 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6299 inst.operands[i].isvec = 1;
6300 inst.operands[i].vectype = optype;
6301 inst.operands[i].present = 1;
6302
6303 if (skip_past_comma (&ptr) == SUCCESS)
6304 {
6305 /* Case 15. */
6306 i++;
6307
6308 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6309 goto wanted_arm;
6310
6311 inst.operands[i].reg = val;
6312 inst.operands[i].isreg = 1;
6313 inst.operands[i++].present = 1;
6314
6315 if (skip_past_comma (&ptr) == FAIL)
6316 goto wanted_comma;
6317
6318 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6319 goto wanted_arm;
6320
6321 inst.operands[i].reg = val;
6322 inst.operands[i].isreg = 1;
6323 inst.operands[i].present = 1;
6324 }
6325 }
6326 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6327 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6328 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6329 Case 10: VMOV.F32 <Sd>, #<imm>
6330 Case 11: VMOV.F64 <Dd>, #<imm> */
6331 inst.operands[i].immisfloat = 1;
6332 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6333 == SUCCESS)
6334 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6335 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6336 ;
6337 else
6338 {
6339 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6340 return FAIL;
6341 }
6342 }
6343 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6344 {
6345 /* Cases 6, 7. */
6346 inst.operands[i].reg = val;
6347 inst.operands[i].isreg = 1;
6348 inst.operands[i++].present = 1;
6349
6350 if (skip_past_comma (&ptr) == FAIL)
6351 goto wanted_comma;
6352
6353 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6354 {
6355 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6356 inst.operands[i].reg = val;
6357 inst.operands[i].isscalar = 1;
6358 inst.operands[i].present = 1;
6359 inst.operands[i].vectype = optype;
6360 }
6361 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6362 {
6363 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6364 inst.operands[i].reg = val;
6365 inst.operands[i].isreg = 1;
6366 inst.operands[i++].present = 1;
6367
6368 if (skip_past_comma (&ptr) == FAIL)
6369 goto wanted_comma;
6370
6371 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6372 == FAIL)
6373 {
6374 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6375 return FAIL;
6376 }
6377
6378 inst.operands[i].reg = val;
6379 inst.operands[i].isreg = 1;
6380 inst.operands[i].isvec = 1;
6381 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6382 inst.operands[i].vectype = optype;
6383 inst.operands[i].present = 1;
6384
6385 if (rtype == REG_TYPE_VFS)
6386 {
6387 /* Case 14. */
6388 i++;
6389 if (skip_past_comma (&ptr) == FAIL)
6390 goto wanted_comma;
6391 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6392 &optype)) == FAIL)
6393 {
6394 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6395 return FAIL;
6396 }
6397 inst.operands[i].reg = val;
6398 inst.operands[i].isreg = 1;
6399 inst.operands[i].isvec = 1;
6400 inst.operands[i].issingle = 1;
6401 inst.operands[i].vectype = optype;
6402 inst.operands[i].present = 1;
6403 }
6404 }
6405 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6406 != FAIL)
6407 {
6408 /* Case 13. */
6409 inst.operands[i].reg = val;
6410 inst.operands[i].isreg = 1;
6411 inst.operands[i].isvec = 1;
6412 inst.operands[i].issingle = 1;
6413 inst.operands[i].vectype = optype;
6414 inst.operands[i].present = 1;
6415 }
6416 }
6417 else
6418 {
6419 first_error (_("parse error"));
6420 return FAIL;
6421 }
6422
6423 /* Successfully parsed the operands. Update args. */
6424 *which_operand = i;
6425 *str = ptr;
6426 return SUCCESS;
6427
6428 wanted_comma:
6429 first_error (_("expected comma"));
6430 return FAIL;
6431
6432 wanted_arm:
6433 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6434 return FAIL;
6435}
6436
6437/* Use this macro when the operand constraints are different
6438 for ARM and THUMB (e.g. ldrd). */
6439#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6440 ((arm_operand) | ((thumb_operand) << 16))
6441
6442/* Matcher codes for parse_operands. */
6443enum operand_parse_code
6444{
6445 OP_stop, /* end of line */
6446
6447 OP_RR, /* ARM register */
6448 OP_RRnpc, /* ARM register, not r15 */
6449 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6450 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6451 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6452 optional trailing ! */
6453 OP_RRw, /* ARM register, not r15, optional trailing ! */
6454 OP_RCP, /* Coprocessor number */
6455 OP_RCN, /* Coprocessor register */
6456 OP_RF, /* FPA register */
6457 OP_RVS, /* VFP single precision register */
6458 OP_RVD, /* VFP double precision register (0..15) */
6459 OP_RND, /* Neon double precision register (0..31) */
6460 OP_RNQ, /* Neon quad precision register */
6461 OP_RVSD, /* VFP single or double precision register */
6462 OP_RNDQ, /* Neon double or quad precision register */
6463 OP_RNSDQ, /* Neon single, double or quad precision register */
6464 OP_RNSC, /* Neon scalar D[X] */
6465 OP_RVC, /* VFP control register */
6466 OP_RMF, /* Maverick F register */
6467 OP_RMD, /* Maverick D register */
6468 OP_RMFX, /* Maverick FX register */
6469 OP_RMDX, /* Maverick DX register */
6470 OP_RMAX, /* Maverick AX register */
6471 OP_RMDS, /* Maverick DSPSC register */
6472 OP_RIWR, /* iWMMXt wR register */
6473 OP_RIWC, /* iWMMXt wC register */
6474 OP_RIWG, /* iWMMXt wCG register */
6475 OP_RXA, /* XScale accumulator register */
6476
6477 OP_REGLST, /* ARM register list */
6478 OP_VRSLST, /* VFP single-precision register list */
6479 OP_VRDLST, /* VFP double-precision register list */
6480 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6481 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6482 OP_NSTRLST, /* Neon element/structure list */
6483
6484 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6485 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6486 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
6487 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6488 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6489 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6490 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6491 OP_VMOV, /* Neon VMOV operands. */
6492 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6493 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6494 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6495
6496 OP_I0, /* immediate zero */
6497 OP_I7, /* immediate value 0 .. 7 */
6498 OP_I15, /* 0 .. 15 */
6499 OP_I16, /* 1 .. 16 */
6500 OP_I16z, /* 0 .. 16 */
6501 OP_I31, /* 0 .. 31 */
6502 OP_I31w, /* 0 .. 31, optional trailing ! */
6503 OP_I32, /* 1 .. 32 */
6504 OP_I32z, /* 0 .. 32 */
6505 OP_I63, /* 0 .. 63 */
6506 OP_I63s, /* -64 .. 63 */
6507 OP_I64, /* 1 .. 64 */
6508 OP_I64z, /* 0 .. 64 */
6509 OP_I255, /* 0 .. 255 */
6510
6511 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6512 OP_I7b, /* 0 .. 7 */
6513 OP_I15b, /* 0 .. 15 */
6514 OP_I31b, /* 0 .. 31 */
6515
6516 OP_SH, /* shifter operand */
6517 OP_SHG, /* shifter operand with possible group relocation */
6518 OP_ADDR, /* Memory address expression (any mode) */
6519 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6520 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6521 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6522 OP_EXP, /* arbitrary expression */
6523 OP_EXPi, /* same, with optional immediate prefix */
6524 OP_EXPr, /* same, with optional relocation suffix */
6525 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6526
6527 OP_CPSF, /* CPS flags */
6528 OP_ENDI, /* Endianness specifier */
6529 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6530 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6531 OP_COND, /* conditional code */
6532 OP_TB, /* Table branch. */
6533
6534 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6535
6536 OP_RRnpc_I0, /* ARM register or literal 0 */
6537 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6538 OP_RR_EXi, /* ARM register or expression with imm prefix */
6539 OP_RF_IF, /* FPA register or immediate */
6540 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6541 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6542
6543 /* Optional operands. */
6544 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6545 OP_oI31b, /* 0 .. 31 */
6546 OP_oI32b, /* 1 .. 32 */
6547 OP_oI32z, /* 0 .. 32 */
6548 OP_oIffffb, /* 0 .. 65535 */
6549 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6550
6551 OP_oRR, /* ARM register */
6552 OP_oRRnpc, /* ARM register, not the PC */
6553 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6554 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6555 OP_oRND, /* Optional Neon double precision register */
6556 OP_oRNQ, /* Optional Neon quad precision register */
6557 OP_oRNDQ, /* Optional Neon double or quad precision register */
6558 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6559 OP_oSHll, /* LSL immediate */
6560 OP_oSHar, /* ASR immediate */
6561 OP_oSHllar, /* LSL or ASR immediate */
6562 OP_oROR, /* ROR 0/8/16/24 */
6563 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6564
6565 /* Some pre-defined mixed (ARM/THUMB) operands. */
6566 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6567 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6568 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6569
6570 OP_FIRST_OPTIONAL = OP_oI7b
6571};
6572
6573/* Generic instruction operand parser. This does no encoding and no
6574 semantic validation; it merely squirrels values away in the inst
6575 structure. Returns SUCCESS or FAIL depending on whether the
6576 specified grammar matched. */
6577static int
6578parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6579{
6580 unsigned const int *upat = pattern;
6581 char *backtrack_pos = 0;
6582 const char *backtrack_error = 0;
6583 int i, val = 0, backtrack_index = 0;
6584 enum arm_reg_type rtype;
6585 parse_operand_result result;
6586 unsigned int op_parse_code;
6587
6588#define po_char_or_fail(chr) \
6589 do \
6590 { \
6591 if (skip_past_char (&str, chr) == FAIL) \
6592 goto bad_args; \
6593 } \
6594 while (0)
6595
6596#define po_reg_or_fail(regtype) \
6597 do \
6598 { \
6599 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6600 & inst.operands[i].vectype); \
6601 if (val == FAIL) \
6602 { \
6603 first_error (_(reg_expected_msgs[regtype])); \
6604 goto failure; \
6605 } \
6606 inst.operands[i].reg = val; \
6607 inst.operands[i].isreg = 1; \
6608 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6609 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6610 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6611 || rtype == REG_TYPE_VFD \
6612 || rtype == REG_TYPE_NQ); \
6613 } \
6614 while (0)
6615
6616#define po_reg_or_goto(regtype, label) \
6617 do \
6618 { \
6619 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6620 & inst.operands[i].vectype); \
6621 if (val == FAIL) \
6622 goto label; \
6623 \
6624 inst.operands[i].reg = val; \
6625 inst.operands[i].isreg = 1; \
6626 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6627 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6628 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6629 || rtype == REG_TYPE_VFD \
6630 || rtype == REG_TYPE_NQ); \
6631 } \
6632 while (0)
6633
6634#define po_imm_or_fail(min, max, popt) \
6635 do \
6636 { \
6637 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6638 goto failure; \
6639 inst.operands[i].imm = val; \
6640 } \
6641 while (0)
6642
6643#define po_scalar_or_goto(elsz, label) \
6644 do \
6645 { \
6646 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6647 if (val == FAIL) \
6648 goto label; \
6649 inst.operands[i].reg = val; \
6650 inst.operands[i].isscalar = 1; \
6651 } \
6652 while (0)
6653
6654#define po_misc_or_fail(expr) \
6655 do \
6656 { \
6657 if (expr) \
6658 goto failure; \
6659 } \
6660 while (0)
6661
6662#define po_misc_or_fail_no_backtrack(expr) \
6663 do \
6664 { \
6665 result = expr; \
6666 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6667 backtrack_pos = 0; \
6668 if (result != PARSE_OPERAND_SUCCESS) \
6669 goto failure; \
6670 } \
6671 while (0)
6672
6673#define po_barrier_or_imm(str) \
6674 do \
6675 { \
6676 val = parse_barrier (&str); \
6677 if (val == FAIL && ! ISALPHA (*str)) \
6678 goto immediate; \
6679 if (val == FAIL \
6680 /* ISB can only take SY as an option. */ \
6681 || ((inst.instruction & 0xf0) == 0x60 \
6682 && val != 0xf)) \
6683 { \
6684 inst.error = _("invalid barrier type"); \
6685 backtrack_pos = 0; \
6686 goto failure; \
6687 } \
6688 } \
6689 while (0)
6690
6691 skip_whitespace (str);
6692
6693 for (i = 0; upat[i] != OP_stop; i++)
6694 {
6695 op_parse_code = upat[i];
6696 if (op_parse_code >= 1<<16)
6697 op_parse_code = thumb ? (op_parse_code >> 16)
6698 : (op_parse_code & ((1<<16)-1));
6699
6700 if (op_parse_code >= OP_FIRST_OPTIONAL)
6701 {
6702 /* Remember where we are in case we need to backtrack. */
6703 gas_assert (!backtrack_pos);
6704 backtrack_pos = str;
6705 backtrack_error = inst.error;
6706 backtrack_index = i;
6707 }
6708
6709 if (i > 0 && (i > 1 || inst.operands[0].present))
6710 po_char_or_fail (',');
6711
6712 switch (op_parse_code)
6713 {
6714 /* Registers */
6715 case OP_oRRnpc:
6716 case OP_oRRnpcsp:
6717 case OP_RRnpc:
6718 case OP_RRnpcsp:
6719 case OP_oRR:
6720 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6721 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6722 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6723 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6724 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6725 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6726 case OP_oRND:
6727 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6728 case OP_RVC:
6729 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6730 break;
6731 /* Also accept generic coprocessor regs for unknown registers. */
6732 coproc_reg:
6733 po_reg_or_fail (REG_TYPE_CN);
6734 break;
6735 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6736 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6737 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6738 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6739 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6740 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6741 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6742 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6743 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6744 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6745 case OP_oRNQ:
6746 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6747 case OP_oRNDQ:
6748 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6749 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6750 case OP_oRNSDQ:
6751 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6752
6753 /* Neon scalar. Using an element size of 8 means that some invalid
6754 scalars are accepted here, so deal with those in later code. */
6755 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6756
6757 case OP_RNDQ_I0:
6758 {
6759 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6760 break;
6761 try_imm0:
6762 po_imm_or_fail (0, 0, TRUE);
6763 }
6764 break;
6765
6766 case OP_RVSD_I0:
6767 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6768 break;
6769
6770 case OP_RSVD_FI0:
6771 {
6772 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
6773 break;
6774 try_ifimm0:
6775 if (parse_ifimm_zero (&str))
6776 inst.operands[i].imm = 0;
6777 else
6778 {
6779 inst.error
6780 = _("only floating point zero is allowed as immediate value");
6781 goto failure;
6782 }
6783 }
6784 break;
6785
6786 case OP_RR_RNSC:
6787 {
6788 po_scalar_or_goto (8, try_rr);
6789 break;
6790 try_rr:
6791 po_reg_or_fail (REG_TYPE_RN);
6792 }
6793 break;
6794
6795 case OP_RNSDQ_RNSC:
6796 {
6797 po_scalar_or_goto (8, try_nsdq);
6798 break;
6799 try_nsdq:
6800 po_reg_or_fail (REG_TYPE_NSDQ);
6801 }
6802 break;
6803
6804 case OP_RNDQ_RNSC:
6805 {
6806 po_scalar_or_goto (8, try_ndq);
6807 break;
6808 try_ndq:
6809 po_reg_or_fail (REG_TYPE_NDQ);
6810 }
6811 break;
6812
6813 case OP_RND_RNSC:
6814 {
6815 po_scalar_or_goto (8, try_vfd);
6816 break;
6817 try_vfd:
6818 po_reg_or_fail (REG_TYPE_VFD);
6819 }
6820 break;
6821
6822 case OP_VMOV:
6823 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6824 not careful then bad things might happen. */
6825 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6826 break;
6827
6828 case OP_RNDQ_Ibig:
6829 {
6830 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6831 break;
6832 try_immbig:
6833 /* There's a possibility of getting a 64-bit immediate here, so
6834 we need special handling. */
6835 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
6836 == FAIL)
6837 {
6838 inst.error = _("immediate value is out of range");
6839 goto failure;
6840 }
6841 }
6842 break;
6843
6844 case OP_RNDQ_I63b:
6845 {
6846 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6847 break;
6848 try_shimm:
6849 po_imm_or_fail (0, 63, TRUE);
6850 }
6851 break;
6852
6853 case OP_RRnpcb:
6854 po_char_or_fail ('[');
6855 po_reg_or_fail (REG_TYPE_RN);
6856 po_char_or_fail (']');
6857 break;
6858
6859 case OP_RRnpctw:
6860 case OP_RRw:
6861 case OP_oRRw:
6862 po_reg_or_fail (REG_TYPE_RN);
6863 if (skip_past_char (&str, '!') == SUCCESS)
6864 inst.operands[i].writeback = 1;
6865 break;
6866
6867 /* Immediates */
6868 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6869 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6870 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6871 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6872 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6873 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6874 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6875 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6876 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6877 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6878 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6879 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6880
6881 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6882 case OP_oI7b:
6883 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6884 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6885 case OP_oI31b:
6886 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6887 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6888 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6889 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6890
6891 /* Immediate variants */
6892 case OP_oI255c:
6893 po_char_or_fail ('{');
6894 po_imm_or_fail (0, 255, TRUE);
6895 po_char_or_fail ('}');
6896 break;
6897
6898 case OP_I31w:
6899 /* The expression parser chokes on a trailing !, so we have
6900 to find it first and zap it. */
6901 {
6902 char *s = str;
6903 while (*s && *s != ',')
6904 s++;
6905 if (s[-1] == '!')
6906 {
6907 s[-1] = '\0';
6908 inst.operands[i].writeback = 1;
6909 }
6910 po_imm_or_fail (0, 31, TRUE);
6911 if (str == s - 1)
6912 str = s;
6913 }
6914 break;
6915
6916 /* Expressions */
6917 case OP_EXPi: EXPi:
6918 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6919 GE_OPT_PREFIX));
6920 break;
6921
6922 case OP_EXP:
6923 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6924 GE_NO_PREFIX));
6925 break;
6926
6927 case OP_EXPr: EXPr:
6928 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6929 GE_NO_PREFIX));
6930 if (inst.reloc.exp.X_op == O_symbol)
6931 {
6932 val = parse_reloc (&str);
6933 if (val == -1)
6934 {
6935 inst.error = _("unrecognized relocation suffix");
6936 goto failure;
6937 }
6938 else if (val != BFD_RELOC_UNUSED)
6939 {
6940 inst.operands[i].imm = val;
6941 inst.operands[i].hasreloc = 1;
6942 }
6943 }
6944 break;
6945
6946 /* Operand for MOVW or MOVT. */
6947 case OP_HALF:
6948 po_misc_or_fail (parse_half (&str));
6949 break;
6950
6951 /* Register or expression. */
6952 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6953 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6954
6955 /* Register or immediate. */
6956 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6957 I0: po_imm_or_fail (0, 0, FALSE); break;
6958
6959 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6960 IF:
6961 if (!is_immediate_prefix (*str))
6962 goto bad_args;
6963 str++;
6964 val = parse_fpa_immediate (&str);
6965 if (val == FAIL)
6966 goto failure;
6967 /* FPA immediates are encoded as registers 8-15.
6968 parse_fpa_immediate has already applied the offset. */
6969 inst.operands[i].reg = val;
6970 inst.operands[i].isreg = 1;
6971 break;
6972
6973 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6974 I32z: po_imm_or_fail (0, 32, FALSE); break;
6975
6976 /* Two kinds of register. */
6977 case OP_RIWR_RIWC:
6978 {
6979 struct reg_entry *rege = arm_reg_parse_multi (&str);
6980 if (!rege
6981 || (rege->type != REG_TYPE_MMXWR
6982 && rege->type != REG_TYPE_MMXWC
6983 && rege->type != REG_TYPE_MMXWCG))
6984 {
6985 inst.error = _("iWMMXt data or control register expected");
6986 goto failure;
6987 }
6988 inst.operands[i].reg = rege->number;
6989 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6990 }
6991 break;
6992
6993 case OP_RIWC_RIWG:
6994 {
6995 struct reg_entry *rege = arm_reg_parse_multi (&str);
6996 if (!rege
6997 || (rege->type != REG_TYPE_MMXWC
6998 && rege->type != REG_TYPE_MMXWCG))
6999 {
7000 inst.error = _("iWMMXt control register expected");
7001 goto failure;
7002 }
7003 inst.operands[i].reg = rege->number;
7004 inst.operands[i].isreg = 1;
7005 }
7006 break;
7007
7008 /* Misc */
7009 case OP_CPSF: val = parse_cps_flags (&str); break;
7010 case OP_ENDI: val = parse_endian_specifier (&str); break;
7011 case OP_oROR: val = parse_ror (&str); break;
7012 case OP_COND: val = parse_cond (&str); break;
7013 case OP_oBARRIER_I15:
7014 po_barrier_or_imm (str); break;
7015 immediate:
7016 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
7017 goto failure;
7018 break;
7019
7020 case OP_wPSR:
7021 case OP_rPSR:
7022 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7023 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7024 {
7025 inst.error = _("Banked registers are not available with this "
7026 "architecture.");
7027 goto failure;
7028 }
7029 break;
7030 try_psr:
7031 val = parse_psr (&str, op_parse_code == OP_wPSR);
7032 break;
7033
7034 case OP_APSR_RR:
7035 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7036 break;
7037 try_apsr:
7038 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7039 instruction). */
7040 if (strncasecmp (str, "APSR_", 5) == 0)
7041 {
7042 unsigned found = 0;
7043 str += 5;
7044 while (found < 15)
7045 switch (*str++)
7046 {
7047 case 'c': found = (found & 1) ? 16 : found | 1; break;
7048 case 'n': found = (found & 2) ? 16 : found | 2; break;
7049 case 'z': found = (found & 4) ? 16 : found | 4; break;
7050 case 'v': found = (found & 8) ? 16 : found | 8; break;
7051 default: found = 16;
7052 }
7053 if (found != 15)
7054 goto failure;
7055 inst.operands[i].isvec = 1;
7056 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7057 inst.operands[i].reg = REG_PC;
7058 }
7059 else
7060 goto failure;
7061 break;
7062
7063 case OP_TB:
7064 po_misc_or_fail (parse_tb (&str));
7065 break;
7066
7067 /* Register lists. */
7068 case OP_REGLST:
7069 val = parse_reg_list (&str);
7070 if (*str == '^')
7071 {
7072 inst.operands[i].writeback = 1;
7073 str++;
7074 }
7075 break;
7076
7077 case OP_VRSLST:
7078 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
7079 break;
7080
7081 case OP_VRDLST:
7082 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
7083 break;
7084
7085 case OP_VRSDLST:
7086 /* Allow Q registers too. */
7087 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7088 REGLIST_NEON_D);
7089 if (val == FAIL)
7090 {
7091 inst.error = NULL;
7092 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7093 REGLIST_VFP_S);
7094 inst.operands[i].issingle = 1;
7095 }
7096 break;
7097
7098 case OP_NRDLST:
7099 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7100 REGLIST_NEON_D);
7101 break;
7102
7103 case OP_NSTRLST:
7104 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7105 &inst.operands[i].vectype);
7106 break;
7107
7108 /* Addressing modes */
7109 case OP_ADDR:
7110 po_misc_or_fail (parse_address (&str, i));
7111 break;
7112
7113 case OP_ADDRGLDR:
7114 po_misc_or_fail_no_backtrack (
7115 parse_address_group_reloc (&str, i, GROUP_LDR));
7116 break;
7117
7118 case OP_ADDRGLDRS:
7119 po_misc_or_fail_no_backtrack (
7120 parse_address_group_reloc (&str, i, GROUP_LDRS));
7121 break;
7122
7123 case OP_ADDRGLDC:
7124 po_misc_or_fail_no_backtrack (
7125 parse_address_group_reloc (&str, i, GROUP_LDC));
7126 break;
7127
7128 case OP_SH:
7129 po_misc_or_fail (parse_shifter_operand (&str, i));
7130 break;
7131
7132 case OP_SHG:
7133 po_misc_or_fail_no_backtrack (
7134 parse_shifter_operand_group_reloc (&str, i));
7135 break;
7136
7137 case OP_oSHll:
7138 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7139 break;
7140
7141 case OP_oSHar:
7142 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7143 break;
7144
7145 case OP_oSHllar:
7146 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7147 break;
7148
7149 default:
7150 as_fatal (_("unhandled operand code %d"), op_parse_code);
7151 }
7152
7153 /* Various value-based sanity checks and shared operations. We
7154 do not signal immediate failures for the register constraints;
7155 this allows a syntax error to take precedence. */
7156 switch (op_parse_code)
7157 {
7158 case OP_oRRnpc:
7159 case OP_RRnpc:
7160 case OP_RRnpcb:
7161 case OP_RRw:
7162 case OP_oRRw:
7163 case OP_RRnpc_I0:
7164 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7165 inst.error = BAD_PC;
7166 break;
7167
7168 case OP_oRRnpcsp:
7169 case OP_RRnpcsp:
7170 if (inst.operands[i].isreg)
7171 {
7172 if (inst.operands[i].reg == REG_PC)
7173 inst.error = BAD_PC;
7174 else if (inst.operands[i].reg == REG_SP)
7175 inst.error = BAD_SP;
7176 }
7177 break;
7178
7179 case OP_RRnpctw:
7180 if (inst.operands[i].isreg
7181 && inst.operands[i].reg == REG_PC
7182 && (inst.operands[i].writeback || thumb))
7183 inst.error = BAD_PC;
7184 break;
7185
7186 case OP_CPSF:
7187 case OP_ENDI:
7188 case OP_oROR:
7189 case OP_wPSR:
7190 case OP_rPSR:
7191 case OP_COND:
7192 case OP_oBARRIER_I15:
7193 case OP_REGLST:
7194 case OP_VRSLST:
7195 case OP_VRDLST:
7196 case OP_VRSDLST:
7197 case OP_NRDLST:
7198 case OP_NSTRLST:
7199 if (val == FAIL)
7200 goto failure;
7201 inst.operands[i].imm = val;
7202 break;
7203
7204 default:
7205 break;
7206 }
7207
7208 /* If we get here, this operand was successfully parsed. */
7209 inst.operands[i].present = 1;
7210 continue;
7211
7212 bad_args:
7213 inst.error = BAD_ARGS;
7214
7215 failure:
7216 if (!backtrack_pos)
7217 {
7218 /* The parse routine should already have set inst.error, but set a
7219 default here just in case. */
7220 if (!inst.error)
7221 inst.error = _("syntax error");
7222 return FAIL;
7223 }
7224
7225 /* Do not backtrack over a trailing optional argument that
7226 absorbed some text. We will only fail again, with the
7227 'garbage following instruction' error message, which is
7228 probably less helpful than the current one. */
7229 if (backtrack_index == i && backtrack_pos != str
7230 && upat[i+1] == OP_stop)
7231 {
7232 if (!inst.error)
7233 inst.error = _("syntax error");
7234 return FAIL;
7235 }
7236
7237 /* Try again, skipping the optional argument at backtrack_pos. */
7238 str = backtrack_pos;
7239 inst.error = backtrack_error;
7240 inst.operands[backtrack_index].present = 0;
7241 i = backtrack_index;
7242 backtrack_pos = 0;
7243 }
7244
7245 /* Check that we have parsed all the arguments. */
7246 if (*str != '\0' && !inst.error)
7247 inst.error = _("garbage following instruction");
7248
7249 return inst.error ? FAIL : SUCCESS;
7250}
7251
7252#undef po_char_or_fail
7253#undef po_reg_or_fail
7254#undef po_reg_or_goto
7255#undef po_imm_or_fail
7256#undef po_scalar_or_fail
7257#undef po_barrier_or_imm
7258
7259/* Shorthand macro for instruction encoding functions issuing errors. */
7260#define constraint(expr, err) \
7261 do \
7262 { \
7263 if (expr) \
7264 { \
7265 inst.error = err; \
7266 return; \
7267 } \
7268 } \
7269 while (0)
7270
7271/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7272 instructions are unpredictable if these registers are used. This
7273 is the BadReg predicate in ARM's Thumb-2 documentation. */
7274#define reject_bad_reg(reg) \
7275 do \
7276 if (reg == REG_SP || reg == REG_PC) \
7277 { \
7278 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7279 return; \
7280 } \
7281 while (0)
7282
7283/* If REG is R13 (the stack pointer), warn that its use is
7284 deprecated. */
7285#define warn_deprecated_sp(reg) \
7286 do \
7287 if (warn_on_deprecated && reg == REG_SP) \
7288 as_tsktsk (_("use of r13 is deprecated")); \
7289 while (0)
7290
7291/* Functions for operand encoding. ARM, then Thumb. */
7292
7293#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7294
7295/* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7296
7297 The only binary encoding difference is the Coprocessor number. Coprocessor
7298 9 is used for half-precision calculations or conversions. The format of the
7299 instruction is the same as the equivalent Coprocessor 10 instuction that
7300 exists for Single-Precision operation. */
7301
7302static void
7303do_scalar_fp16_v82_encode (void)
7304{
7305 if (inst.cond != COND_ALWAYS)
7306 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7307 " the behaviour is UNPREDICTABLE"));
7308 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
7309 _(BAD_FP16));
7310
7311 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
7312 mark_feature_used (&arm_ext_fp16);
7313}
7314
7315/* If VAL can be encoded in the immediate field of an ARM instruction,
7316 return the encoded form. Otherwise, return FAIL. */
7317
7318static unsigned int
7319encode_arm_immediate (unsigned int val)
7320{
7321 unsigned int a, i;
7322
7323 if (val <= 0xff)
7324 return val;
7325
7326 for (i = 2; i < 32; i += 2)
7327 if ((a = rotate_left (val, i)) <= 0xff)
7328 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
7329
7330 return FAIL;
7331}
7332
7333/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7334 return the encoded form. Otherwise, return FAIL. */
7335static unsigned int
7336encode_thumb32_immediate (unsigned int val)
7337{
7338 unsigned int a, i;
7339
7340 if (val <= 0xff)
7341 return val;
7342
7343 for (i = 1; i <= 24; i++)
7344 {
7345 a = val >> i;
7346 if ((val & ~(0xff << i)) == 0)
7347 return ((val >> i) & 0x7f) | ((32 - i) << 7);
7348 }
7349
7350 a = val & 0xff;
7351 if (val == ((a << 16) | a))
7352 return 0x100 | a;
7353 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
7354 return 0x300 | a;
7355
7356 a = val & 0xff00;
7357 if (val == ((a << 16) | a))
7358 return 0x200 | (a >> 8);
7359
7360 return FAIL;
7361}
7362/* Encode a VFP SP or DP register number into inst.instruction. */
7363
7364static void
7365encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
7366{
7367 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
7368 && reg > 15)
7369 {
7370 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
7371 {
7372 if (thumb_mode)
7373 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7374 fpu_vfp_ext_d32);
7375 else
7376 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7377 fpu_vfp_ext_d32);
7378 }
7379 else
7380 {
7381 first_error (_("D register out of range for selected VFP version"));
7382 return;
7383 }
7384 }
7385
7386 switch (pos)
7387 {
7388 case VFP_REG_Sd:
7389 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7390 break;
7391
7392 case VFP_REG_Sn:
7393 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7394 break;
7395
7396 case VFP_REG_Sm:
7397 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7398 break;
7399
7400 case VFP_REG_Dd:
7401 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7402 break;
7403
7404 case VFP_REG_Dn:
7405 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7406 break;
7407
7408 case VFP_REG_Dm:
7409 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7410 break;
7411
7412 default:
7413 abort ();
7414 }
7415}
7416
7417/* Encode a <shift> in an ARM-format instruction. The immediate,
7418 if any, is handled by md_apply_fix. */
7419static void
7420encode_arm_shift (int i)
7421{
7422 if (inst.operands[i].shift_kind == SHIFT_RRX)
7423 inst.instruction |= SHIFT_ROR << 5;
7424 else
7425 {
7426 inst.instruction |= inst.operands[i].shift_kind << 5;
7427 if (inst.operands[i].immisreg)
7428 {
7429 inst.instruction |= SHIFT_BY_REG;
7430 inst.instruction |= inst.operands[i].imm << 8;
7431 }
7432 else
7433 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7434 }
7435}
7436
7437static void
7438encode_arm_shifter_operand (int i)
7439{
7440 if (inst.operands[i].isreg)
7441 {
7442 inst.instruction |= inst.operands[i].reg;
7443 encode_arm_shift (i);
7444 }
7445 else
7446 {
7447 inst.instruction |= INST_IMMEDIATE;
7448 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7449 inst.instruction |= inst.operands[i].imm;
7450 }
7451}
7452
7453/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7454static void
7455encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7456{
7457 /* PR 14260:
7458 Generate an error if the operand is not a register. */
7459 constraint (!inst.operands[i].isreg,
7460 _("Instruction does not support =N addresses"));
7461
7462 inst.instruction |= inst.operands[i].reg << 16;
7463
7464 if (inst.operands[i].preind)
7465 {
7466 if (is_t)
7467 {
7468 inst.error = _("instruction does not accept preindexed addressing");
7469 return;
7470 }
7471 inst.instruction |= PRE_INDEX;
7472 if (inst.operands[i].writeback)
7473 inst.instruction |= WRITE_BACK;
7474
7475 }
7476 else if (inst.operands[i].postind)
7477 {
7478 gas_assert (inst.operands[i].writeback);
7479 if (is_t)
7480 inst.instruction |= WRITE_BACK;
7481 }
7482 else /* unindexed - only for coprocessor */
7483 {
7484 inst.error = _("instruction does not accept unindexed addressing");
7485 return;
7486 }
7487
7488 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7489 && (((inst.instruction & 0x000f0000) >> 16)
7490 == ((inst.instruction & 0x0000f000) >> 12)))
7491 as_warn ((inst.instruction & LOAD_BIT)
7492 ? _("destination register same as write-back base")
7493 : _("source register same as write-back base"));
7494}
7495
7496/* inst.operands[i] was set up by parse_address. Encode it into an
7497 ARM-format mode 2 load or store instruction. If is_t is true,
7498 reject forms that cannot be used with a T instruction (i.e. not
7499 post-indexed). */
7500static void
7501encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7502{
7503 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7504
7505 encode_arm_addr_mode_common (i, is_t);
7506
7507 if (inst.operands[i].immisreg)
7508 {
7509 constraint ((inst.operands[i].imm == REG_PC
7510 || (is_pc && inst.operands[i].writeback)),
7511 BAD_PC_ADDRESSING);
7512 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7513 inst.instruction |= inst.operands[i].imm;
7514 if (!inst.operands[i].negative)
7515 inst.instruction |= INDEX_UP;
7516 if (inst.operands[i].shifted)
7517 {
7518 if (inst.operands[i].shift_kind == SHIFT_RRX)
7519 inst.instruction |= SHIFT_ROR << 5;
7520 else
7521 {
7522 inst.instruction |= inst.operands[i].shift_kind << 5;
7523 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7524 }
7525 }
7526 }
7527 else /* immediate offset in inst.reloc */
7528 {
7529 if (is_pc && !inst.reloc.pc_rel)
7530 {
7531 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7532
7533 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7534 cannot use PC in addressing.
7535 PC cannot be used in writeback addressing, either. */
7536 constraint ((is_t || inst.operands[i].writeback),
7537 BAD_PC_ADDRESSING);
7538
7539 /* Use of PC in str is deprecated for ARMv7. */
7540 if (warn_on_deprecated
7541 && !is_load
7542 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7543 as_tsktsk (_("use of PC in this instruction is deprecated"));
7544 }
7545
7546 if (inst.reloc.type == BFD_RELOC_UNUSED)
7547 {
7548 /* Prefer + for zero encoded value. */
7549 if (!inst.operands[i].negative)
7550 inst.instruction |= INDEX_UP;
7551 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7552 }
7553 }
7554}
7555
7556/* inst.operands[i] was set up by parse_address. Encode it into an
7557 ARM-format mode 3 load or store instruction. Reject forms that
7558 cannot be used with such instructions. If is_t is true, reject
7559 forms that cannot be used with a T instruction (i.e. not
7560 post-indexed). */
7561static void
7562encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7563{
7564 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7565 {
7566 inst.error = _("instruction does not accept scaled register index");
7567 return;
7568 }
7569
7570 encode_arm_addr_mode_common (i, is_t);
7571
7572 if (inst.operands[i].immisreg)
7573 {
7574 constraint ((inst.operands[i].imm == REG_PC
7575 || (is_t && inst.operands[i].reg == REG_PC)),
7576 BAD_PC_ADDRESSING);
7577 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7578 BAD_PC_WRITEBACK);
7579 inst.instruction |= inst.operands[i].imm;
7580 if (!inst.operands[i].negative)
7581 inst.instruction |= INDEX_UP;
7582 }
7583 else /* immediate offset in inst.reloc */
7584 {
7585 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7586 && inst.operands[i].writeback),
7587 BAD_PC_WRITEBACK);
7588 inst.instruction |= HWOFFSET_IMM;
7589 if (inst.reloc.type == BFD_RELOC_UNUSED)
7590 {
7591 /* Prefer + for zero encoded value. */
7592 if (!inst.operands[i].negative)
7593 inst.instruction |= INDEX_UP;
7594
7595 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7596 }
7597 }
7598}
7599
7600/* Write immediate bits [7:0] to the following locations:
7601
7602 |28/24|23 19|18 16|15 4|3 0|
7603 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7604
7605 This function is used by VMOV/VMVN/VORR/VBIC. */
7606
7607static void
7608neon_write_immbits (unsigned immbits)
7609{
7610 inst.instruction |= immbits & 0xf;
7611 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
7612 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
7613}
7614
7615/* Invert low-order SIZE bits of XHI:XLO. */
7616
7617static void
7618neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
7619{
7620 unsigned immlo = xlo ? *xlo : 0;
7621 unsigned immhi = xhi ? *xhi : 0;
7622
7623 switch (size)
7624 {
7625 case 8:
7626 immlo = (~immlo) & 0xff;
7627 break;
7628
7629 case 16:
7630 immlo = (~immlo) & 0xffff;
7631 break;
7632
7633 case 64:
7634 immhi = (~immhi) & 0xffffffff;
7635 /* fall through. */
7636
7637 case 32:
7638 immlo = (~immlo) & 0xffffffff;
7639 break;
7640
7641 default:
7642 abort ();
7643 }
7644
7645 if (xlo)
7646 *xlo = immlo;
7647
7648 if (xhi)
7649 *xhi = immhi;
7650}
7651
7652/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7653 A, B, C, D. */
7654
7655static int
7656neon_bits_same_in_bytes (unsigned imm)
7657{
7658 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
7659 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
7660 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
7661 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
7662}
7663
7664/* For immediate of above form, return 0bABCD. */
7665
7666static unsigned
7667neon_squash_bits (unsigned imm)
7668{
7669 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
7670 | ((imm & 0x01000000) >> 21);
7671}
7672
7673/* Compress quarter-float representation to 0b...000 abcdefgh. */
7674
7675static unsigned
7676neon_qfloat_bits (unsigned imm)
7677{
7678 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
7679}
7680
7681/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7682 the instruction. *OP is passed as the initial value of the op field, and
7683 may be set to a different value depending on the constant (i.e.
7684 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7685 MVN). If the immediate looks like a repeated pattern then also
7686 try smaller element sizes. */
7687
7688static int
7689neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
7690 unsigned *immbits, int *op, int size,
7691 enum neon_el_type type)
7692{
7693 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7694 float. */
7695 if (type == NT_float && !float_p)
7696 return FAIL;
7697
7698 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
7699 {
7700 if (size != 32 || *op == 1)
7701 return FAIL;
7702 *immbits = neon_qfloat_bits (immlo);
7703 return 0xf;
7704 }
7705
7706 if (size == 64)
7707 {
7708 if (neon_bits_same_in_bytes (immhi)
7709 && neon_bits_same_in_bytes (immlo))
7710 {
7711 if (*op == 1)
7712 return FAIL;
7713 *immbits = (neon_squash_bits (immhi) << 4)
7714 | neon_squash_bits (immlo);
7715 *op = 1;
7716 return 0xe;
7717 }
7718
7719 if (immhi != immlo)
7720 return FAIL;
7721 }
7722
7723 if (size >= 32)
7724 {
7725 if (immlo == (immlo & 0x000000ff))
7726 {
7727 *immbits = immlo;
7728 return 0x0;
7729 }
7730 else if (immlo == (immlo & 0x0000ff00))
7731 {
7732 *immbits = immlo >> 8;
7733 return 0x2;
7734 }
7735 else if (immlo == (immlo & 0x00ff0000))
7736 {
7737 *immbits = immlo >> 16;
7738 return 0x4;
7739 }
7740 else if (immlo == (immlo & 0xff000000))
7741 {
7742 *immbits = immlo >> 24;
7743 return 0x6;
7744 }
7745 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
7746 {
7747 *immbits = (immlo >> 8) & 0xff;
7748 return 0xc;
7749 }
7750 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
7751 {
7752 *immbits = (immlo >> 16) & 0xff;
7753 return 0xd;
7754 }
7755
7756 if ((immlo & 0xffff) != (immlo >> 16))
7757 return FAIL;
7758 immlo &= 0xffff;
7759 }
7760
7761 if (size >= 16)
7762 {
7763 if (immlo == (immlo & 0x000000ff))
7764 {
7765 *immbits = immlo;
7766 return 0x8;
7767 }
7768 else if (immlo == (immlo & 0x0000ff00))
7769 {
7770 *immbits = immlo >> 8;
7771 return 0xa;
7772 }
7773
7774 if ((immlo & 0xff) != (immlo >> 8))
7775 return FAIL;
7776 immlo &= 0xff;
7777 }
7778
7779 if (immlo == (immlo & 0x000000ff))
7780 {
7781 /* Don't allow MVN with 8-bit immediate. */
7782 if (*op == 1)
7783 return FAIL;
7784 *immbits = immlo;
7785 return 0xe;
7786 }
7787
7788 return FAIL;
7789}
7790
7791#if defined BFD_HOST_64_BIT
7792/* Returns TRUE if double precision value V may be cast
7793 to single precision without loss of accuracy. */
7794
7795static bfd_boolean
7796is_double_a_single (bfd_int64_t v)
7797{
7798 int exp = (int)((v >> 52) & 0x7FF);
7799 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
7800
7801 return (exp == 0 || exp == 0x7FF
7802 || (exp >= 1023 - 126 && exp <= 1023 + 127))
7803 && (mantissa & 0x1FFFFFFFl) == 0;
7804}
7805
7806/* Returns a double precision value casted to single precision
7807 (ignoring the least significant bits in exponent and mantissa). */
7808
7809static int
7810double_to_single (bfd_int64_t v)
7811{
7812 int sign = (int) ((v >> 63) & 1l);
7813 int exp = (int) ((v >> 52) & 0x7FF);
7814 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
7815
7816 if (exp == 0x7FF)
7817 exp = 0xFF;
7818 else
7819 {
7820 exp = exp - 1023 + 127;
7821 if (exp >= 0xFF)
7822 {
7823 /* Infinity. */
7824 exp = 0x7F;
7825 mantissa = 0;
7826 }
7827 else if (exp < 0)
7828 {
7829 /* No denormalized numbers. */
7830 exp = 0;
7831 mantissa = 0;
7832 }
7833 }
7834 mantissa >>= 29;
7835 return (sign << 31) | (exp << 23) | mantissa;
7836}
7837#endif /* BFD_HOST_64_BIT */
7838
7839enum lit_type
7840{
7841 CONST_THUMB,
7842 CONST_ARM,
7843 CONST_VEC
7844};
7845
7846static void do_vfp_nsyn_opcode (const char *);
7847
7848/* inst.reloc.exp describes an "=expr" load pseudo-operation.
7849 Determine whether it can be performed with a move instruction; if
7850 it can, convert inst.instruction to that move instruction and
7851 return TRUE; if it can't, convert inst.instruction to a literal-pool
7852 load and return FALSE. If this is not a valid thing to do in the
7853 current context, set inst.error and return TRUE.
7854
7855 inst.operands[i] describes the destination register. */
7856
7857static bfd_boolean
7858move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
7859{
7860 unsigned long tbit;
7861 bfd_boolean thumb_p = (t == CONST_THUMB);
7862 bfd_boolean arm_p = (t == CONST_ARM);
7863
7864 if (thumb_p)
7865 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7866 else
7867 tbit = LOAD_BIT;
7868
7869 if ((inst.instruction & tbit) == 0)
7870 {
7871 inst.error = _("invalid pseudo operation");
7872 return TRUE;
7873 }
7874
7875 if (inst.reloc.exp.X_op != O_constant
7876 && inst.reloc.exp.X_op != O_symbol
7877 && inst.reloc.exp.X_op != O_big)
7878 {
7879 inst.error = _("constant expression expected");
7880 return TRUE;
7881 }
7882
7883 if (inst.reloc.exp.X_op == O_constant
7884 || inst.reloc.exp.X_op == O_big)
7885 {
7886#if defined BFD_HOST_64_BIT
7887 bfd_int64_t v;
7888#else
7889 offsetT v;
7890#endif
7891 if (inst.reloc.exp.X_op == O_big)
7892 {
7893 LITTLENUM_TYPE w[X_PRECISION];
7894 LITTLENUM_TYPE * l;
7895
7896 if (inst.reloc.exp.X_add_number == -1)
7897 {
7898 gen_to_words (w, X_PRECISION, E_PRECISION);
7899 l = w;
7900 /* FIXME: Should we check words w[2..5] ? */
7901 }
7902 else
7903 l = generic_bignum;
7904
7905#if defined BFD_HOST_64_BIT
7906 v =
7907 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
7908 << LITTLENUM_NUMBER_OF_BITS)
7909 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
7910 << LITTLENUM_NUMBER_OF_BITS)
7911 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
7912 << LITTLENUM_NUMBER_OF_BITS)
7913 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
7914#else
7915 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
7916 | (l[0] & LITTLENUM_MASK);
7917#endif
7918 }
7919 else
7920 v = inst.reloc.exp.X_add_number;
7921
7922 if (!inst.operands[i].issingle)
7923 {
7924 if (thumb_p)
7925 {
7926 /* This can be encoded only for a low register. */
7927 if ((v & ~0xFF) == 0 && (inst.operands[i].reg < 8))
7928 {
7929 /* This can be done with a mov(1) instruction. */
7930 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7931 inst.instruction |= v;
7932 return TRUE;
7933 }
7934
7935 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
7936 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
7937 {
7938 /* Check if on thumb2 it can be done with a mov.w, mvn or
7939 movw instruction. */
7940 unsigned int newimm;
7941 bfd_boolean isNegated;
7942
7943 newimm = encode_thumb32_immediate (v);
7944 if (newimm != (unsigned int) FAIL)
7945 isNegated = FALSE;
7946 else
7947 {
7948 newimm = encode_thumb32_immediate (~v);
7949 if (newimm != (unsigned int) FAIL)
7950 isNegated = TRUE;
7951 }
7952
7953 /* The number can be loaded with a mov.w or mvn
7954 instruction. */
7955 if (newimm != (unsigned int) FAIL
7956 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
7957 {
7958 inst.instruction = (0xf04f0000 /* MOV.W. */
7959 | (inst.operands[i].reg << 8));
7960 /* Change to MOVN. */
7961 inst.instruction |= (isNegated ? 0x200000 : 0);
7962 inst.instruction |= (newimm & 0x800) << 15;
7963 inst.instruction |= (newimm & 0x700) << 4;
7964 inst.instruction |= (newimm & 0x0ff);
7965 return TRUE;
7966 }
7967 /* The number can be loaded with a movw instruction. */
7968 else if ((v & ~0xFFFF) == 0
7969 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
7970 {
7971 int imm = v & 0xFFFF;
7972
7973 inst.instruction = 0xf2400000; /* MOVW. */
7974 inst.instruction |= (inst.operands[i].reg << 8);
7975 inst.instruction |= (imm & 0xf000) << 4;
7976 inst.instruction |= (imm & 0x0800) << 15;
7977 inst.instruction |= (imm & 0x0700) << 4;
7978 inst.instruction |= (imm & 0x00ff);
7979 return TRUE;
7980 }
7981 }
7982 }
7983 else if (arm_p)
7984 {
7985 int value = encode_arm_immediate (v);
7986
7987 if (value != FAIL)
7988 {
7989 /* This can be done with a mov instruction. */
7990 inst.instruction &= LITERAL_MASK;
7991 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7992 inst.instruction |= value & 0xfff;
7993 return TRUE;
7994 }
7995
7996 value = encode_arm_immediate (~ v);
7997 if (value != FAIL)
7998 {
7999 /* This can be done with a mvn instruction. */
8000 inst.instruction &= LITERAL_MASK;
8001 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8002 inst.instruction |= value & 0xfff;
8003 return TRUE;
8004 }
8005 }
8006 else if (t == CONST_VEC)
8007 {
8008 int op = 0;
8009 unsigned immbits = 0;
8010 unsigned immlo = inst.operands[1].imm;
8011 unsigned immhi = inst.operands[1].regisimm
8012 ? inst.operands[1].reg
8013 : inst.reloc.exp.X_unsigned
8014 ? 0
8015 : ((bfd_int64_t)((int) immlo)) >> 32;
8016 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8017 &op, 64, NT_invtype);
8018
8019 if (cmode == FAIL)
8020 {
8021 neon_invert_size (&immlo, &immhi, 64);
8022 op = !op;
8023 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8024 &op, 64, NT_invtype);
8025 }
8026
8027 if (cmode != FAIL)
8028 {
8029 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8030 | (1 << 23)
8031 | (cmode << 8)
8032 | (op << 5)
8033 | (1 << 4);
8034
8035 /* Fill other bits in vmov encoding for both thumb and arm. */
8036 if (thumb_mode)
8037 inst.instruction |= (0x7U << 29) | (0xF << 24);
8038 else
8039 inst.instruction |= (0xFU << 28) | (0x1 << 25);
8040 neon_write_immbits (immbits);
8041 return TRUE;
8042 }
8043 }
8044 }
8045
8046 if (t == CONST_VEC)
8047 {
8048 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8049 if (inst.operands[i].issingle
8050 && is_quarter_float (inst.operands[1].imm)
8051 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
8052 {
8053 inst.operands[1].imm =
8054 neon_qfloat_bits (v);
8055 do_vfp_nsyn_opcode ("fconsts");
8056 return TRUE;
8057 }
8058
8059 /* If our host does not support a 64-bit type then we cannot perform
8060 the following optimization. This mean that there will be a
8061 discrepancy between the output produced by an assembler built for
8062 a 32-bit-only host and the output produced from a 64-bit host, but
8063 this cannot be helped. */
8064#if defined BFD_HOST_64_BIT
8065 else if (!inst.operands[1].issingle
8066 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
8067 {
8068 if (is_double_a_single (v)
8069 && is_quarter_float (double_to_single (v)))
8070 {
8071 inst.operands[1].imm =
8072 neon_qfloat_bits (double_to_single (v));
8073 do_vfp_nsyn_opcode ("fconstd");
8074 return TRUE;
8075 }
8076 }
8077#endif
8078 }
8079 }
8080
8081 if (add_to_lit_pool ((!inst.operands[i].isvec
8082 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8083 return TRUE;
8084
8085 inst.operands[1].reg = REG_PC;
8086 inst.operands[1].isreg = 1;
8087 inst.operands[1].preind = 1;
8088 inst.reloc.pc_rel = 1;
8089 inst.reloc.type = (thumb_p
8090 ? BFD_RELOC_ARM_THUMB_OFFSET
8091 : (mode_3
8092 ? BFD_RELOC_ARM_HWLITERAL
8093 : BFD_RELOC_ARM_LITERAL));
8094 return FALSE;
8095}
8096
8097/* inst.operands[i] was set up by parse_address. Encode it into an
8098 ARM-format instruction. Reject all forms which cannot be encoded
8099 into a coprocessor load/store instruction. If wb_ok is false,
8100 reject use of writeback; if unind_ok is false, reject use of
8101 unindexed addressing. If reloc_override is not 0, use it instead
8102 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8103 (in which case it is preserved). */
8104
8105static int
8106encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
8107{
8108 if (!inst.operands[i].isreg)
8109 {
8110 /* PR 18256 */
8111 if (! inst.operands[0].isvec)
8112 {
8113 inst.error = _("invalid co-processor operand");
8114 return FAIL;
8115 }
8116 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
8117 return SUCCESS;
8118 }
8119
8120 inst.instruction |= inst.operands[i].reg << 16;
8121
8122 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8123
8124 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8125 {
8126 gas_assert (!inst.operands[i].writeback);
8127 if (!unind_ok)
8128 {
8129 inst.error = _("instruction does not support unindexed addressing");
8130 return FAIL;
8131 }
8132 inst.instruction |= inst.operands[i].imm;
8133 inst.instruction |= INDEX_UP;
8134 return SUCCESS;
8135 }
8136
8137 if (inst.operands[i].preind)
8138 inst.instruction |= PRE_INDEX;
8139
8140 if (inst.operands[i].writeback)
8141 {
8142 if (inst.operands[i].reg == REG_PC)
8143 {
8144 inst.error = _("pc may not be used with write-back");
8145 return FAIL;
8146 }
8147 if (!wb_ok)
8148 {
8149 inst.error = _("instruction does not support writeback");
8150 return FAIL;
8151 }
8152 inst.instruction |= WRITE_BACK;
8153 }
8154
8155 if (reloc_override)
8156 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
8157 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
8158 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
8159 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
8160 {
8161 if (thumb_mode)
8162 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8163 else
8164 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
8165 }
8166
8167 /* Prefer + for zero encoded value. */
8168 if (!inst.operands[i].negative)
8169 inst.instruction |= INDEX_UP;
8170
8171 return SUCCESS;
8172}
8173
8174/* Functions for instruction encoding, sorted by sub-architecture.
8175 First some generics; their names are taken from the conventional
8176 bit positions for register arguments in ARM format instructions. */
8177
8178static void
8179do_noargs (void)
8180{
8181}
8182
8183static void
8184do_rd (void)
8185{
8186 inst.instruction |= inst.operands[0].reg << 12;
8187}
8188
8189static void
8190do_rn (void)
8191{
8192 inst.instruction |= inst.operands[0].reg << 16;
8193}
8194
8195static void
8196do_rd_rm (void)
8197{
8198 inst.instruction |= inst.operands[0].reg << 12;
8199 inst.instruction |= inst.operands[1].reg;
8200}
8201
8202static void
8203do_rm_rn (void)
8204{
8205 inst.instruction |= inst.operands[0].reg;
8206 inst.instruction |= inst.operands[1].reg << 16;
8207}
8208
8209static void
8210do_rd_rn (void)
8211{
8212 inst.instruction |= inst.operands[0].reg << 12;
8213 inst.instruction |= inst.operands[1].reg << 16;
8214}
8215
8216static void
8217do_rn_rd (void)
8218{
8219 inst.instruction |= inst.operands[0].reg << 16;
8220 inst.instruction |= inst.operands[1].reg << 12;
8221}
8222
8223static void
8224do_tt (void)
8225{
8226 inst.instruction |= inst.operands[0].reg << 8;
8227 inst.instruction |= inst.operands[1].reg << 16;
8228}
8229
8230static bfd_boolean
8231check_obsolete (const arm_feature_set *feature, const char *msg)
8232{
8233 if (ARM_CPU_IS_ANY (cpu_variant))
8234 {
8235 as_tsktsk ("%s", msg);
8236 return TRUE;
8237 }
8238 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
8239 {
8240 as_bad ("%s", msg);
8241 return TRUE;
8242 }
8243
8244 return FALSE;
8245}
8246
8247static void
8248do_rd_rm_rn (void)
8249{
8250 unsigned Rn = inst.operands[2].reg;
8251 /* Enforce restrictions on SWP instruction. */
8252 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
8253 {
8254 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8255 _("Rn must not overlap other operands"));
8256
8257 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8258 */
8259 if (!check_obsolete (&arm_ext_v8,
8260 _("swp{b} use is obsoleted for ARMv8 and later"))
8261 && warn_on_deprecated
8262 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
8263 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8264 }
8265
8266 inst.instruction |= inst.operands[0].reg << 12;
8267 inst.instruction |= inst.operands[1].reg;
8268 inst.instruction |= Rn << 16;
8269}
8270
8271static void
8272do_rd_rn_rm (void)
8273{
8274 inst.instruction |= inst.operands[0].reg << 12;
8275 inst.instruction |= inst.operands[1].reg << 16;
8276 inst.instruction |= inst.operands[2].reg;
8277}
8278
8279static void
8280do_rm_rd_rn (void)
8281{
8282 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
8283 constraint (((inst.reloc.exp.X_op != O_constant
8284 && inst.reloc.exp.X_op != O_illegal)
8285 || inst.reloc.exp.X_add_number != 0),
8286 BAD_ADDR_MODE);
8287 inst.instruction |= inst.operands[0].reg;
8288 inst.instruction |= inst.operands[1].reg << 12;
8289 inst.instruction |= inst.operands[2].reg << 16;
8290}
8291
8292static void
8293do_imm0 (void)
8294{
8295 inst.instruction |= inst.operands[0].imm;
8296}
8297
8298static void
8299do_rd_cpaddr (void)
8300{
8301 inst.instruction |= inst.operands[0].reg << 12;
8302 encode_arm_cp_address (1, TRUE, TRUE, 0);
8303}
8304
8305/* ARM instructions, in alphabetical order by function name (except
8306 that wrapper functions appear immediately after the function they
8307 wrap). */
8308
8309/* This is a pseudo-op of the form "adr rd, label" to be converted
8310 into a relative address of the form "add rd, pc, #label-.-8". */
8311
8312static void
8313do_adr (void)
8314{
8315 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
8316
8317 /* Frag hacking will turn this into a sub instruction if the offset turns
8318 out to be negative. */
8319 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8320 inst.reloc.pc_rel = 1;
8321 inst.reloc.exp.X_add_number -= 8;
8322}
8323
8324/* This is a pseudo-op of the form "adrl rd, label" to be converted
8325 into a relative address of the form:
8326 add rd, pc, #low(label-.-8)"
8327 add rd, rd, #high(label-.-8)" */
8328
8329static void
8330do_adrl (void)
8331{
8332 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
8333
8334 /* Frag hacking will turn this into a sub instruction if the offset turns
8335 out to be negative. */
8336 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
8337 inst.reloc.pc_rel = 1;
8338 inst.size = INSN_SIZE * 2;
8339 inst.reloc.exp.X_add_number -= 8;
8340}
8341
8342static void
8343do_arit (void)
8344{
8345 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8346 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
8347 THUMB1_RELOC_ONLY);
8348 if (!inst.operands[1].present)
8349 inst.operands[1].reg = inst.operands[0].reg;
8350 inst.instruction |= inst.operands[0].reg << 12;
8351 inst.instruction |= inst.operands[1].reg << 16;
8352 encode_arm_shifter_operand (2);
8353}
8354
8355static void
8356do_barrier (void)
8357{
8358 if (inst.operands[0].present)
8359 inst.instruction |= inst.operands[0].imm;
8360 else
8361 inst.instruction |= 0xf;
8362}
8363
8364static void
8365do_bfc (void)
8366{
8367 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8368 constraint (msb > 32, _("bit-field extends past end of register"));
8369 /* The instruction encoding stores the LSB and MSB,
8370 not the LSB and width. */
8371 inst.instruction |= inst.operands[0].reg << 12;
8372 inst.instruction |= inst.operands[1].imm << 7;
8373 inst.instruction |= (msb - 1) << 16;
8374}
8375
8376static void
8377do_bfi (void)
8378{
8379 unsigned int msb;
8380
8381 /* #0 in second position is alternative syntax for bfc, which is
8382 the same instruction but with REG_PC in the Rm field. */
8383 if (!inst.operands[1].isreg)
8384 inst.operands[1].reg = REG_PC;
8385
8386 msb = inst.operands[2].imm + inst.operands[3].imm;
8387 constraint (msb > 32, _("bit-field extends past end of register"));
8388 /* The instruction encoding stores the LSB and MSB,
8389 not the LSB and width. */
8390 inst.instruction |= inst.operands[0].reg << 12;
8391 inst.instruction |= inst.operands[1].reg;
8392 inst.instruction |= inst.operands[2].imm << 7;
8393 inst.instruction |= (msb - 1) << 16;
8394}
8395
8396static void
8397do_bfx (void)
8398{
8399 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8400 _("bit-field extends past end of register"));
8401 inst.instruction |= inst.operands[0].reg << 12;
8402 inst.instruction |= inst.operands[1].reg;
8403 inst.instruction |= inst.operands[2].imm << 7;
8404 inst.instruction |= (inst.operands[3].imm - 1) << 16;
8405}
8406
8407/* ARM V5 breakpoint instruction (argument parse)
8408 BKPT <16 bit unsigned immediate>
8409 Instruction is not conditional.
8410 The bit pattern given in insns[] has the COND_ALWAYS condition,
8411 and it is an error if the caller tried to override that. */
8412
8413static void
8414do_bkpt (void)
8415{
8416 /* Top 12 of 16 bits to bits 19:8. */
8417 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
8418
8419 /* Bottom 4 of 16 bits to bits 3:0. */
8420 inst.instruction |= inst.operands[0].imm & 0xf;
8421}
8422
8423static void
8424encode_branch (int default_reloc)
8425{
8426 if (inst.operands[0].hasreloc)
8427 {
8428 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
8429 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
8430 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8431 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
8432 ? BFD_RELOC_ARM_PLT32
8433 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
8434 }
8435 else
8436 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
8437 inst.reloc.pc_rel = 1;
8438}
8439
8440static void
8441do_branch (void)
8442{
8443#ifdef OBJ_ELF
8444 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8445 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8446 else
8447#endif
8448 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
8449}
8450
8451static void
8452do_bl (void)
8453{
8454#ifdef OBJ_ELF
8455 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8456 {
8457 if (inst.cond == COND_ALWAYS)
8458 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
8459 else
8460 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8461 }
8462 else
8463#endif
8464 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
8465}
8466
8467/* ARM V5 branch-link-exchange instruction (argument parse)
8468 BLX <target_addr> ie BLX(1)
8469 BLX{<condition>} <Rm> ie BLX(2)
8470 Unfortunately, there are two different opcodes for this mnemonic.
8471 So, the insns[].value is not used, and the code here zaps values
8472 into inst.instruction.
8473 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8474
8475static void
8476do_blx (void)
8477{
8478 if (inst.operands[0].isreg)
8479 {
8480 /* Arg is a register; the opcode provided by insns[] is correct.
8481 It is not illegal to do "blx pc", just useless. */
8482 if (inst.operands[0].reg == REG_PC)
8483 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8484
8485 inst.instruction |= inst.operands[0].reg;
8486 }
8487 else
8488 {
8489 /* Arg is an address; this instruction cannot be executed
8490 conditionally, and the opcode must be adjusted.
8491 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8492 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8493 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8494 inst.instruction = 0xfa000000;
8495 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
8496 }
8497}
8498
8499static void
8500do_bx (void)
8501{
8502 bfd_boolean want_reloc;
8503
8504 if (inst.operands[0].reg == REG_PC)
8505 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8506
8507 inst.instruction |= inst.operands[0].reg;
8508 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8509 it is for ARMv4t or earlier. */
8510 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
8511 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
8512 want_reloc = TRUE;
8513
8514#ifdef OBJ_ELF
8515 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
8516#endif
8517 want_reloc = FALSE;
8518
8519 if (want_reloc)
8520 inst.reloc.type = BFD_RELOC_ARM_V4BX;
8521}
8522
8523
8524/* ARM v5TEJ. Jump to Jazelle code. */
8525
8526static void
8527do_bxj (void)
8528{
8529 if (inst.operands[0].reg == REG_PC)
8530 as_tsktsk (_("use of r15 in bxj is not really useful"));
8531
8532 inst.instruction |= inst.operands[0].reg;
8533}
8534
8535/* Co-processor data operation:
8536 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8537 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8538static void
8539do_cdp (void)
8540{
8541 inst.instruction |= inst.operands[0].reg << 8;
8542 inst.instruction |= inst.operands[1].imm << 20;
8543 inst.instruction |= inst.operands[2].reg << 12;
8544 inst.instruction |= inst.operands[3].reg << 16;
8545 inst.instruction |= inst.operands[4].reg;
8546 inst.instruction |= inst.operands[5].imm << 5;
8547}
8548
8549static void
8550do_cmp (void)
8551{
8552 inst.instruction |= inst.operands[0].reg << 16;
8553 encode_arm_shifter_operand (1);
8554}
8555
8556/* Transfer between coprocessor and ARM registers.
8557 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8558 MRC2
8559 MCR{cond}
8560 MCR2
8561
8562 No special properties. */
8563
8564struct deprecated_coproc_regs_s
8565{
8566 unsigned cp;
8567 int opc1;
8568 unsigned crn;
8569 unsigned crm;
8570 int opc2;
8571 arm_feature_set deprecated;
8572 arm_feature_set obsoleted;
8573 const char *dep_msg;
8574 const char *obs_msg;
8575};
8576
8577#define DEPR_ACCESS_V8 \
8578 N_("This coprocessor register access is deprecated in ARMv8")
8579
8580/* Table of all deprecated coprocessor registers. */
8581static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
8582{
8583 {15, 0, 7, 10, 5, /* CP15DMB. */
8584 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8585 DEPR_ACCESS_V8, NULL},
8586 {15, 0, 7, 10, 4, /* CP15DSB. */
8587 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8588 DEPR_ACCESS_V8, NULL},
8589 {15, 0, 7, 5, 4, /* CP15ISB. */
8590 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8591 DEPR_ACCESS_V8, NULL},
8592 {14, 6, 1, 0, 0, /* TEEHBR. */
8593 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8594 DEPR_ACCESS_V8, NULL},
8595 {14, 6, 0, 0, 0, /* TEECR. */
8596 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8597 DEPR_ACCESS_V8, NULL},
8598};
8599
8600#undef DEPR_ACCESS_V8
8601
8602static const size_t deprecated_coproc_reg_count =
8603 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
8604
8605static void
8606do_co_reg (void)
8607{
8608 unsigned Rd;
8609 size_t i;
8610
8611 Rd = inst.operands[2].reg;
8612 if (thumb_mode)
8613 {
8614 if (inst.instruction == 0xee000010
8615 || inst.instruction == 0xfe000010)
8616 /* MCR, MCR2 */
8617 reject_bad_reg (Rd);
8618 else
8619 /* MRC, MRC2 */
8620 constraint (Rd == REG_SP, BAD_SP);
8621 }
8622 else
8623 {
8624 /* MCR */
8625 if (inst.instruction == 0xe000010)
8626 constraint (Rd == REG_PC, BAD_PC);
8627 }
8628
8629 for (i = 0; i < deprecated_coproc_reg_count; ++i)
8630 {
8631 const struct deprecated_coproc_regs_s *r =
8632 deprecated_coproc_regs + i;
8633
8634 if (inst.operands[0].reg == r->cp
8635 && inst.operands[1].imm == r->opc1
8636 && inst.operands[3].reg == r->crn
8637 && inst.operands[4].reg == r->crm
8638 && inst.operands[5].imm == r->opc2)
8639 {
8640 if (! ARM_CPU_IS_ANY (cpu_variant)
8641 && warn_on_deprecated
8642 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
8643 as_tsktsk ("%s", r->dep_msg);
8644 }
8645 }
8646
8647 inst.instruction |= inst.operands[0].reg << 8;
8648 inst.instruction |= inst.operands[1].imm << 21;
8649 inst.instruction |= Rd << 12;
8650 inst.instruction |= inst.operands[3].reg << 16;
8651 inst.instruction |= inst.operands[4].reg;
8652 inst.instruction |= inst.operands[5].imm << 5;
8653}
8654
8655/* Transfer between coprocessor register and pair of ARM registers.
8656 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8657 MCRR2
8658 MRRC{cond}
8659 MRRC2
8660
8661 Two XScale instructions are special cases of these:
8662
8663 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8664 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8665
8666 Result unpredictable if Rd or Rn is R15. */
8667
8668static void
8669do_co_reg2c (void)
8670{
8671 unsigned Rd, Rn;
8672
8673 Rd = inst.operands[2].reg;
8674 Rn = inst.operands[3].reg;
8675
8676 if (thumb_mode)
8677 {
8678 reject_bad_reg (Rd);
8679 reject_bad_reg (Rn);
8680 }
8681 else
8682 {
8683 constraint (Rd == REG_PC, BAD_PC);
8684 constraint (Rn == REG_PC, BAD_PC);
8685 }
8686
8687 inst.instruction |= inst.operands[0].reg << 8;
8688 inst.instruction |= inst.operands[1].imm << 4;
8689 inst.instruction |= Rd << 12;
8690 inst.instruction |= Rn << 16;
8691 inst.instruction |= inst.operands[4].reg;
8692}
8693
8694static void
8695do_cpsi (void)
8696{
8697 inst.instruction |= inst.operands[0].imm << 6;
8698 if (inst.operands[1].present)
8699 {
8700 inst.instruction |= CPSI_MMOD;
8701 inst.instruction |= inst.operands[1].imm;
8702 }
8703}
8704
8705static void
8706do_dbg (void)
8707{
8708 inst.instruction |= inst.operands[0].imm;
8709}
8710
8711static void
8712do_div (void)
8713{
8714 unsigned Rd, Rn, Rm;
8715
8716 Rd = inst.operands[0].reg;
8717 Rn = (inst.operands[1].present
8718 ? inst.operands[1].reg : Rd);
8719 Rm = inst.operands[2].reg;
8720
8721 constraint ((Rd == REG_PC), BAD_PC);
8722 constraint ((Rn == REG_PC), BAD_PC);
8723 constraint ((Rm == REG_PC), BAD_PC);
8724
8725 inst.instruction |= Rd << 16;
8726 inst.instruction |= Rn << 0;
8727 inst.instruction |= Rm << 8;
8728}
8729
8730static void
8731do_it (void)
8732{
8733 /* There is no IT instruction in ARM mode. We
8734 process it to do the validation as if in
8735 thumb mode, just in case the code gets
8736 assembled for thumb using the unified syntax. */
8737
8738 inst.size = 0;
8739 if (unified_syntax)
8740 {
8741 set_it_insn_type (IT_INSN);
8742 now_it.mask = (inst.instruction & 0xf) | 0x10;
8743 now_it.cc = inst.operands[0].imm;
8744 }
8745}
8746
8747/* If there is only one register in the register list,
8748 then return its register number. Otherwise return -1. */
8749static int
8750only_one_reg_in_list (int range)
8751{
8752 int i = ffs (range) - 1;
8753 return (i > 15 || range != (1 << i)) ? -1 : i;
8754}
8755
8756static void
8757encode_ldmstm(int from_push_pop_mnem)
8758{
8759 int base_reg = inst.operands[0].reg;
8760 int range = inst.operands[1].imm;
8761 int one_reg;
8762
8763 inst.instruction |= base_reg << 16;
8764 inst.instruction |= range;
8765
8766 if (inst.operands[1].writeback)
8767 inst.instruction |= LDM_TYPE_2_OR_3;
8768
8769 if (inst.operands[0].writeback)
8770 {
8771 inst.instruction |= WRITE_BACK;
8772 /* Check for unpredictable uses of writeback. */
8773 if (inst.instruction & LOAD_BIT)
8774 {
8775 /* Not allowed in LDM type 2. */
8776 if ((inst.instruction & LDM_TYPE_2_OR_3)
8777 && ((range & (1 << REG_PC)) == 0))
8778 as_warn (_("writeback of base register is UNPREDICTABLE"));
8779 /* Only allowed if base reg not in list for other types. */
8780 else if (range & (1 << base_reg))
8781 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8782 }
8783 else /* STM. */
8784 {
8785 /* Not allowed for type 2. */
8786 if (inst.instruction & LDM_TYPE_2_OR_3)
8787 as_warn (_("writeback of base register is UNPREDICTABLE"));
8788 /* Only allowed if base reg not in list, or first in list. */
8789 else if ((range & (1 << base_reg))
8790 && (range & ((1 << base_reg) - 1)))
8791 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8792 }
8793 }
8794
8795 /* If PUSH/POP has only one register, then use the A2 encoding. */
8796 one_reg = only_one_reg_in_list (range);
8797 if (from_push_pop_mnem && one_reg >= 0)
8798 {
8799 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
8800
8801 inst.instruction &= A_COND_MASK;
8802 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
8803 inst.instruction |= one_reg << 12;
8804 }
8805}
8806
8807static void
8808do_ldmstm (void)
8809{
8810 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
8811}
8812
8813/* ARMv5TE load-consecutive (argument parse)
8814 Mode is like LDRH.
8815
8816 LDRccD R, mode
8817 STRccD R, mode. */
8818
8819static void
8820do_ldrd (void)
8821{
8822 constraint (inst.operands[0].reg % 2 != 0,
8823 _("first transfer register must be even"));
8824 constraint (inst.operands[1].present
8825 && inst.operands[1].reg != inst.operands[0].reg + 1,
8826 _("can only transfer two consecutive registers"));
8827 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8828 constraint (!inst.operands[2].isreg, _("'[' expected"));
8829
8830 if (!inst.operands[1].present)
8831 inst.operands[1].reg = inst.operands[0].reg + 1;
8832
8833 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8834 register and the first register written; we have to diagnose
8835 overlap between the base and the second register written here. */
8836
8837 if (inst.operands[2].reg == inst.operands[1].reg
8838 && (inst.operands[2].writeback || inst.operands[2].postind))
8839 as_warn (_("base register written back, and overlaps "
8840 "second transfer register"));
8841
8842 if (!(inst.instruction & V4_STR_BIT))
8843 {
8844 /* For an index-register load, the index register must not overlap the
8845 destination (even if not write-back). */
8846 if (inst.operands[2].immisreg
8847 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8848 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8849 as_warn (_("index register overlaps transfer register"));
8850 }
8851 inst.instruction |= inst.operands[0].reg << 12;
8852 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8853}
8854
8855static void
8856do_ldrex (void)
8857{
8858 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8859 || inst.operands[1].postind || inst.operands[1].writeback
8860 || inst.operands[1].immisreg || inst.operands[1].shifted
8861 || inst.operands[1].negative
8862 /* This can arise if the programmer has written
8863 strex rN, rM, foo
8864 or if they have mistakenly used a register name as the last
8865 operand, eg:
8866 strex rN, rM, rX
8867 It is very difficult to distinguish between these two cases
8868 because "rX" might actually be a label. ie the register
8869 name has been occluded by a symbol of the same name. So we
8870 just generate a general 'bad addressing mode' type error
8871 message and leave it up to the programmer to discover the
8872 true cause and fix their mistake. */
8873 || (inst.operands[1].reg == REG_PC),
8874 BAD_ADDR_MODE);
8875
8876 constraint (inst.reloc.exp.X_op != O_constant
8877 || inst.reloc.exp.X_add_number != 0,
8878 _("offset must be zero in ARM encoding"));
8879
8880 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8881
8882 inst.instruction |= inst.operands[0].reg << 12;
8883 inst.instruction |= inst.operands[1].reg << 16;
8884 inst.reloc.type = BFD_RELOC_UNUSED;
8885}
8886
8887static void
8888do_ldrexd (void)
8889{
8890 constraint (inst.operands[0].reg % 2 != 0,
8891 _("even register required"));
8892 constraint (inst.operands[1].present
8893 && inst.operands[1].reg != inst.operands[0].reg + 1,
8894 _("can only load two consecutive registers"));
8895 /* If op 1 were present and equal to PC, this function wouldn't
8896 have been called in the first place. */
8897 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8898
8899 inst.instruction |= inst.operands[0].reg << 12;
8900 inst.instruction |= inst.operands[2].reg << 16;
8901}
8902
8903/* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8904 which is not a multiple of four is UNPREDICTABLE. */
8905static void
8906check_ldr_r15_aligned (void)
8907{
8908 constraint (!(inst.operands[1].immisreg)
8909 && (inst.operands[0].reg == REG_PC
8910 && inst.operands[1].reg == REG_PC
8911 && (inst.reloc.exp.X_add_number & 0x3)),
8912 _("ldr to register 15 must be 4-byte alligned"));
8913}
8914
8915static void
8916do_ldst (void)
8917{
8918 inst.instruction |= inst.operands[0].reg << 12;
8919 if (!inst.operands[1].isreg)
8920 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
8921 return;
8922 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8923 check_ldr_r15_aligned ();
8924}
8925
8926static void
8927do_ldstt (void)
8928{
8929 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8930 reject [Rn,...]. */
8931 if (inst.operands[1].preind)
8932 {
8933 constraint (inst.reloc.exp.X_op != O_constant
8934 || inst.reloc.exp.X_add_number != 0,
8935 _("this instruction requires a post-indexed address"));
8936
8937 inst.operands[1].preind = 0;
8938 inst.operands[1].postind = 1;
8939 inst.operands[1].writeback = 1;
8940 }
8941 inst.instruction |= inst.operands[0].reg << 12;
8942 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8943}
8944
8945/* Halfword and signed-byte load/store operations. */
8946
8947static void
8948do_ldstv4 (void)
8949{
8950 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8951 inst.instruction |= inst.operands[0].reg << 12;
8952 if (!inst.operands[1].isreg)
8953 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
8954 return;
8955 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8956}
8957
8958static void
8959do_ldsttv4 (void)
8960{
8961 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8962 reject [Rn,...]. */
8963 if (inst.operands[1].preind)
8964 {
8965 constraint (inst.reloc.exp.X_op != O_constant
8966 || inst.reloc.exp.X_add_number != 0,
8967 _("this instruction requires a post-indexed address"));
8968
8969 inst.operands[1].preind = 0;
8970 inst.operands[1].postind = 1;
8971 inst.operands[1].writeback = 1;
8972 }
8973 inst.instruction |= inst.operands[0].reg << 12;
8974 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8975}
8976
8977/* Co-processor register load/store.
8978 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8979static void
8980do_lstc (void)
8981{
8982 inst.instruction |= inst.operands[0].reg << 8;
8983 inst.instruction |= inst.operands[1].reg << 12;
8984 encode_arm_cp_address (2, TRUE, TRUE, 0);
8985}
8986
8987static void
8988do_mlas (void)
8989{
8990 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8991 if (inst.operands[0].reg == inst.operands[1].reg
8992 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8993 && !(inst.instruction & 0x00400000))
8994 as_tsktsk (_("Rd and Rm should be different in mla"));
8995
8996 inst.instruction |= inst.operands[0].reg << 16;
8997 inst.instruction |= inst.operands[1].reg;
8998 inst.instruction |= inst.operands[2].reg << 8;
8999 inst.instruction |= inst.operands[3].reg << 12;
9000}
9001
9002static void
9003do_mov (void)
9004{
9005 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9006 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9007 THUMB1_RELOC_ONLY);
9008 inst.instruction |= inst.operands[0].reg << 12;
9009 encode_arm_shifter_operand (1);
9010}
9011
9012/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9013static void
9014do_mov16 (void)
9015{
9016 bfd_vma imm;
9017 bfd_boolean top;
9018
9019 top = (inst.instruction & 0x00400000) != 0;
9020 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
9021 _(":lower16: not allowed this instruction"));
9022 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
9023 _(":upper16: not allowed instruction"));
9024 inst.instruction |= inst.operands[0].reg << 12;
9025 if (inst.reloc.type == BFD_RELOC_UNUSED)
9026 {
9027 imm = inst.reloc.exp.X_add_number;
9028 /* The value is in two pieces: 0:11, 16:19. */
9029 inst.instruction |= (imm & 0x00000fff);
9030 inst.instruction |= (imm & 0x0000f000) << 4;
9031 }
9032}
9033
9034static int
9035do_vfp_nsyn_mrs (void)
9036{
9037 if (inst.operands[0].isvec)
9038 {
9039 if (inst.operands[1].reg != 1)
9040 first_error (_("operand 1 must be FPSCR"));
9041 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9042 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9043 do_vfp_nsyn_opcode ("fmstat");
9044 }
9045 else if (inst.operands[1].isvec)
9046 do_vfp_nsyn_opcode ("fmrx");
9047 else
9048 return FAIL;
9049
9050 return SUCCESS;
9051}
9052
9053static int
9054do_vfp_nsyn_msr (void)
9055{
9056 if (inst.operands[0].isvec)
9057 do_vfp_nsyn_opcode ("fmxr");
9058 else
9059 return FAIL;
9060
9061 return SUCCESS;
9062}
9063
9064static void
9065do_vmrs (void)
9066{
9067 unsigned Rt = inst.operands[0].reg;
9068
9069 if (thumb_mode && Rt == REG_SP)
9070 {
9071 inst.error = BAD_SP;
9072 return;
9073 }
9074
9075 /* APSR_ sets isvec. All other refs to PC are illegal. */
9076 if (!inst.operands[0].isvec && Rt == REG_PC)
9077 {
9078 inst.error = BAD_PC;
9079 return;
9080 }
9081
9082 /* If we get through parsing the register name, we just insert the number
9083 generated into the instruction without further validation. */
9084 inst.instruction |= (inst.operands[1].reg << 16);
9085 inst.instruction |= (Rt << 12);
9086}
9087
9088static void
9089do_vmsr (void)
9090{
9091 unsigned Rt = inst.operands[1].reg;
9092
9093 if (thumb_mode)
9094 reject_bad_reg (Rt);
9095 else if (Rt == REG_PC)
9096 {
9097 inst.error = BAD_PC;
9098 return;
9099 }
9100
9101 /* If we get through parsing the register name, we just insert the number
9102 generated into the instruction without further validation. */
9103 inst.instruction |= (inst.operands[0].reg << 16);
9104 inst.instruction |= (Rt << 12);
9105}
9106
9107static void
9108do_mrs (void)
9109{
9110 unsigned br;
9111
9112 if (do_vfp_nsyn_mrs () == SUCCESS)
9113 return;
9114
9115 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9116 inst.instruction |= inst.operands[0].reg << 12;
9117
9118 if (inst.operands[1].isreg)
9119 {
9120 br = inst.operands[1].reg;
9121 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
9122 as_bad (_("bad register for mrs"));
9123 }
9124 else
9125 {
9126 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9127 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
9128 != (PSR_c|PSR_f),
9129 _("'APSR', 'CPSR' or 'SPSR' expected"));
9130 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
9131 }
9132
9133 inst.instruction |= br;
9134}
9135
9136/* Two possible forms:
9137 "{C|S}PSR_<field>, Rm",
9138 "{C|S}PSR_f, #expression". */
9139
9140static void
9141do_msr (void)
9142{
9143 if (do_vfp_nsyn_msr () == SUCCESS)
9144 return;
9145
9146 inst.instruction |= inst.operands[0].imm;
9147 if (inst.operands[1].isreg)
9148 inst.instruction |= inst.operands[1].reg;
9149 else
9150 {
9151 inst.instruction |= INST_IMMEDIATE;
9152 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
9153 inst.reloc.pc_rel = 0;
9154 }
9155}
9156
9157static void
9158do_mul (void)
9159{
9160 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
9161
9162 if (!inst.operands[2].present)
9163 inst.operands[2].reg = inst.operands[0].reg;
9164 inst.instruction |= inst.operands[0].reg << 16;
9165 inst.instruction |= inst.operands[1].reg;
9166 inst.instruction |= inst.operands[2].reg << 8;
9167
9168 if (inst.operands[0].reg == inst.operands[1].reg
9169 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9170 as_tsktsk (_("Rd and Rm should be different in mul"));
9171}
9172
9173/* Long Multiply Parser
9174 UMULL RdLo, RdHi, Rm, Rs
9175 SMULL RdLo, RdHi, Rm, Rs
9176 UMLAL RdLo, RdHi, Rm, Rs
9177 SMLAL RdLo, RdHi, Rm, Rs. */
9178
9179static void
9180do_mull (void)
9181{
9182 inst.instruction |= inst.operands[0].reg << 12;
9183 inst.instruction |= inst.operands[1].reg << 16;
9184 inst.instruction |= inst.operands[2].reg;
9185 inst.instruction |= inst.operands[3].reg << 8;
9186
9187 /* rdhi and rdlo must be different. */
9188 if (inst.operands[0].reg == inst.operands[1].reg)
9189 as_tsktsk (_("rdhi and rdlo must be different"));
9190
9191 /* rdhi, rdlo and rm must all be different before armv6. */
9192 if ((inst.operands[0].reg == inst.operands[2].reg
9193 || inst.operands[1].reg == inst.operands[2].reg)
9194 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9195 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9196}
9197
9198static void
9199do_nop (void)
9200{
9201 if (inst.operands[0].present
9202 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
9203 {
9204 /* Architectural NOP hints are CPSR sets with no bits selected. */
9205 inst.instruction &= 0xf0000000;
9206 inst.instruction |= 0x0320f000;
9207 if (inst.operands[0].present)
9208 inst.instruction |= inst.operands[0].imm;
9209 }
9210}
9211
9212/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9213 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9214 Condition defaults to COND_ALWAYS.
9215 Error if Rd, Rn or Rm are R15. */
9216
9217static void
9218do_pkhbt (void)
9219{
9220 inst.instruction |= inst.operands[0].reg << 12;
9221 inst.instruction |= inst.operands[1].reg << 16;
9222 inst.instruction |= inst.operands[2].reg;
9223 if (inst.operands[3].present)
9224 encode_arm_shift (3);
9225}
9226
9227/* ARM V6 PKHTB (Argument Parse). */
9228
9229static void
9230do_pkhtb (void)
9231{
9232 if (!inst.operands[3].present)
9233 {
9234 /* If the shift specifier is omitted, turn the instruction
9235 into pkhbt rd, rm, rn. */
9236 inst.instruction &= 0xfff00010;
9237 inst.instruction |= inst.operands[0].reg << 12;
9238 inst.instruction |= inst.operands[1].reg;
9239 inst.instruction |= inst.operands[2].reg << 16;
9240 }
9241 else
9242 {
9243 inst.instruction |= inst.operands[0].reg << 12;
9244 inst.instruction |= inst.operands[1].reg << 16;
9245 inst.instruction |= inst.operands[2].reg;
9246 encode_arm_shift (3);
9247 }
9248}
9249
9250/* ARMv5TE: Preload-Cache
9251 MP Extensions: Preload for write
9252
9253 PLD(W) <addr_mode>
9254
9255 Syntactically, like LDR with B=1, W=0, L=1. */
9256
9257static void
9258do_pld (void)
9259{
9260 constraint (!inst.operands[0].isreg,
9261 _("'[' expected after PLD mnemonic"));
9262 constraint (inst.operands[0].postind,
9263 _("post-indexed expression used in preload instruction"));
9264 constraint (inst.operands[0].writeback,
9265 _("writeback used in preload instruction"));
9266 constraint (!inst.operands[0].preind,
9267 _("unindexed addressing used in preload instruction"));
9268 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9269}
9270
9271/* ARMv7: PLI <addr_mode> */
9272static void
9273do_pli (void)
9274{
9275 constraint (!inst.operands[0].isreg,
9276 _("'[' expected after PLI mnemonic"));
9277 constraint (inst.operands[0].postind,
9278 _("post-indexed expression used in preload instruction"));
9279 constraint (inst.operands[0].writeback,
9280 _("writeback used in preload instruction"));
9281 constraint (!inst.operands[0].preind,
9282 _("unindexed addressing used in preload instruction"));
9283 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9284 inst.instruction &= ~PRE_INDEX;
9285}
9286
9287static void
9288do_push_pop (void)
9289{
9290 constraint (inst.operands[0].writeback,
9291 _("push/pop do not support {reglist}^"));
9292 inst.operands[1] = inst.operands[0];
9293 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
9294 inst.operands[0].isreg = 1;
9295 inst.operands[0].writeback = 1;
9296 inst.operands[0].reg = REG_SP;
9297 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
9298}
9299
9300/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9301 word at the specified address and the following word
9302 respectively.
9303 Unconditionally executed.
9304 Error if Rn is R15. */
9305
9306static void
9307do_rfe (void)
9308{
9309 inst.instruction |= inst.operands[0].reg << 16;
9310 if (inst.operands[0].writeback)
9311 inst.instruction |= WRITE_BACK;
9312}
9313
9314/* ARM V6 ssat (argument parse). */
9315
9316static void
9317do_ssat (void)
9318{
9319 inst.instruction |= inst.operands[0].reg << 12;
9320 inst.instruction |= (inst.operands[1].imm - 1) << 16;
9321 inst.instruction |= inst.operands[2].reg;
9322
9323 if (inst.operands[3].present)
9324 encode_arm_shift (3);
9325}
9326
9327/* ARM V6 usat (argument parse). */
9328
9329static void
9330do_usat (void)
9331{
9332 inst.instruction |= inst.operands[0].reg << 12;
9333 inst.instruction |= inst.operands[1].imm << 16;
9334 inst.instruction |= inst.operands[2].reg;
9335
9336 if (inst.operands[3].present)
9337 encode_arm_shift (3);
9338}
9339
9340/* ARM V6 ssat16 (argument parse). */
9341
9342static void
9343do_ssat16 (void)
9344{
9345 inst.instruction |= inst.operands[0].reg << 12;
9346 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
9347 inst.instruction |= inst.operands[2].reg;
9348}
9349
9350static void
9351do_usat16 (void)
9352{
9353 inst.instruction |= inst.operands[0].reg << 12;
9354 inst.instruction |= inst.operands[1].imm << 16;
9355 inst.instruction |= inst.operands[2].reg;
9356}
9357
9358/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9359 preserving the other bits.
9360
9361 setend <endian_specifier>, where <endian_specifier> is either
9362 BE or LE. */
9363
9364static void
9365do_setend (void)
9366{
9367 if (warn_on_deprecated
9368 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
9369 as_tsktsk (_("setend use is deprecated for ARMv8"));
9370
9371 if (inst.operands[0].imm)
9372 inst.instruction |= 0x200;
9373}
9374
9375static void
9376do_shift (void)
9377{
9378 unsigned int Rm = (inst.operands[1].present
9379 ? inst.operands[1].reg
9380 : inst.operands[0].reg);
9381
9382 inst.instruction |= inst.operands[0].reg << 12;
9383 inst.instruction |= Rm;
9384 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
9385 {
9386 inst.instruction |= inst.operands[2].reg << 8;
9387 inst.instruction |= SHIFT_BY_REG;
9388 /* PR 12854: Error on extraneous shifts. */
9389 constraint (inst.operands[2].shifted,
9390 _("extraneous shift as part of operand to shift insn"));
9391 }
9392 else
9393 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
9394}
9395
9396static void
9397do_smc (void)
9398{
9399 inst.reloc.type = BFD_RELOC_ARM_SMC;
9400 inst.reloc.pc_rel = 0;
9401}
9402
9403static void
9404do_hvc (void)
9405{
9406 inst.reloc.type = BFD_RELOC_ARM_HVC;
9407 inst.reloc.pc_rel = 0;
9408}
9409
9410static void
9411do_swi (void)
9412{
9413 inst.reloc.type = BFD_RELOC_ARM_SWI;
9414 inst.reloc.pc_rel = 0;
9415}
9416
9417static void
9418do_setpan (void)
9419{
9420 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
9421 _("selected processor does not support SETPAN instruction"));
9422
9423 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
9424}
9425
9426static void
9427do_t_setpan (void)
9428{
9429 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
9430 _("selected processor does not support SETPAN instruction"));
9431
9432 inst.instruction |= (inst.operands[0].imm << 3);
9433}
9434
9435/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9436 SMLAxy{cond} Rd,Rm,Rs,Rn
9437 SMLAWy{cond} Rd,Rm,Rs,Rn
9438 Error if any register is R15. */
9439
9440static void
9441do_smla (void)
9442{
9443 inst.instruction |= inst.operands[0].reg << 16;
9444 inst.instruction |= inst.operands[1].reg;
9445 inst.instruction |= inst.operands[2].reg << 8;
9446 inst.instruction |= inst.operands[3].reg << 12;
9447}
9448
9449/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9450 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9451 Error if any register is R15.
9452 Warning if Rdlo == Rdhi. */
9453
9454static void
9455do_smlal (void)
9456{
9457 inst.instruction |= inst.operands[0].reg << 12;
9458 inst.instruction |= inst.operands[1].reg << 16;
9459 inst.instruction |= inst.operands[2].reg;
9460 inst.instruction |= inst.operands[3].reg << 8;
9461
9462 if (inst.operands[0].reg == inst.operands[1].reg)
9463 as_tsktsk (_("rdhi and rdlo must be different"));
9464}
9465
9466/* ARM V5E (El Segundo) signed-multiply (argument parse)
9467 SMULxy{cond} Rd,Rm,Rs
9468 Error if any register is R15. */
9469
9470static void
9471do_smul (void)
9472{
9473 inst.instruction |= inst.operands[0].reg << 16;
9474 inst.instruction |= inst.operands[1].reg;
9475 inst.instruction |= inst.operands[2].reg << 8;
9476}
9477
9478/* ARM V6 srs (argument parse). The variable fields in the encoding are
9479 the same for both ARM and Thumb-2. */
9480
9481static void
9482do_srs (void)
9483{
9484 int reg;
9485
9486 if (inst.operands[0].present)
9487 {
9488 reg = inst.operands[0].reg;
9489 constraint (reg != REG_SP, _("SRS base register must be r13"));
9490 }
9491 else
9492 reg = REG_SP;
9493
9494 inst.instruction |= reg << 16;
9495 inst.instruction |= inst.operands[1].imm;
9496 if (inst.operands[0].writeback || inst.operands[1].writeback)
9497 inst.instruction |= WRITE_BACK;
9498}
9499
9500/* ARM V6 strex (argument parse). */
9501
9502static void
9503do_strex (void)
9504{
9505 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9506 || inst.operands[2].postind || inst.operands[2].writeback
9507 || inst.operands[2].immisreg || inst.operands[2].shifted
9508 || inst.operands[2].negative
9509 /* See comment in do_ldrex(). */
9510 || (inst.operands[2].reg == REG_PC),
9511 BAD_ADDR_MODE);
9512
9513 constraint (inst.operands[0].reg == inst.operands[1].reg
9514 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9515
9516 constraint (inst.reloc.exp.X_op != O_constant
9517 || inst.reloc.exp.X_add_number != 0,
9518 _("offset must be zero in ARM encoding"));
9519
9520 inst.instruction |= inst.operands[0].reg << 12;
9521 inst.instruction |= inst.operands[1].reg;
9522 inst.instruction |= inst.operands[2].reg << 16;
9523 inst.reloc.type = BFD_RELOC_UNUSED;
9524}
9525
9526static void
9527do_t_strexbh (void)
9528{
9529 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9530 || inst.operands[2].postind || inst.operands[2].writeback
9531 || inst.operands[2].immisreg || inst.operands[2].shifted
9532 || inst.operands[2].negative,
9533 BAD_ADDR_MODE);
9534
9535 constraint (inst.operands[0].reg == inst.operands[1].reg
9536 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9537
9538 do_rm_rd_rn ();
9539}
9540
9541static void
9542do_strexd (void)
9543{
9544 constraint (inst.operands[1].reg % 2 != 0,
9545 _("even register required"));
9546 constraint (inst.operands[2].present
9547 && inst.operands[2].reg != inst.operands[1].reg + 1,
9548 _("can only store two consecutive registers"));
9549 /* If op 2 were present and equal to PC, this function wouldn't
9550 have been called in the first place. */
9551 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
9552
9553 constraint (inst.operands[0].reg == inst.operands[1].reg
9554 || inst.operands[0].reg == inst.operands[1].reg + 1
9555 || inst.operands[0].reg == inst.operands[3].reg,
9556 BAD_OVERLAP);
9557
9558 inst.instruction |= inst.operands[0].reg << 12;
9559 inst.instruction |= inst.operands[1].reg;
9560 inst.instruction |= inst.operands[3].reg << 16;
9561}
9562
9563/* ARM V8 STRL. */
9564static void
9565do_stlex (void)
9566{
9567 constraint (inst.operands[0].reg == inst.operands[1].reg
9568 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9569
9570 do_rd_rm_rn ();
9571}
9572
9573static void
9574do_t_stlex (void)
9575{
9576 constraint (inst.operands[0].reg == inst.operands[1].reg
9577 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9578
9579 do_rm_rd_rn ();
9580}
9581
9582/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9583 extends it to 32-bits, and adds the result to a value in another
9584 register. You can specify a rotation by 0, 8, 16, or 24 bits
9585 before extracting the 16-bit value.
9586 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9587 Condition defaults to COND_ALWAYS.
9588 Error if any register uses R15. */
9589
9590static void
9591do_sxtah (void)
9592{
9593 inst.instruction |= inst.operands[0].reg << 12;
9594 inst.instruction |= inst.operands[1].reg << 16;
9595 inst.instruction |= inst.operands[2].reg;
9596 inst.instruction |= inst.operands[3].imm << 10;
9597}
9598
9599/* ARM V6 SXTH.
9600
9601 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9602 Condition defaults to COND_ALWAYS.
9603 Error if any register uses R15. */
9604
9605static void
9606do_sxth (void)
9607{
9608 inst.instruction |= inst.operands[0].reg << 12;
9609 inst.instruction |= inst.operands[1].reg;
9610 inst.instruction |= inst.operands[2].imm << 10;
9611}
9612\f
9613/* VFP instructions. In a logical order: SP variant first, monad
9614 before dyad, arithmetic then move then load/store. */
9615
9616static void
9617do_vfp_sp_monadic (void)
9618{
9619 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9620 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
9621}
9622
9623static void
9624do_vfp_sp_dyadic (void)
9625{
9626 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9627 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
9628 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
9629}
9630
9631static void
9632do_vfp_sp_compare_z (void)
9633{
9634 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9635}
9636
9637static void
9638do_vfp_dp_sp_cvt (void)
9639{
9640 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9641 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
9642}
9643
9644static void
9645do_vfp_sp_dp_cvt (void)
9646{
9647 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9648 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
9649}
9650
9651static void
9652do_vfp_reg_from_sp (void)
9653{
9654 inst.instruction |= inst.operands[0].reg << 12;
9655 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
9656}
9657
9658static void
9659do_vfp_reg2_from_sp2 (void)
9660{
9661 constraint (inst.operands[2].imm != 2,
9662 _("only two consecutive VFP SP registers allowed here"));
9663 inst.instruction |= inst.operands[0].reg << 12;
9664 inst.instruction |= inst.operands[1].reg << 16;
9665 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
9666}
9667
9668static void
9669do_vfp_sp_from_reg (void)
9670{
9671 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
9672 inst.instruction |= inst.operands[1].reg << 12;
9673}
9674
9675static void
9676do_vfp_sp2_from_reg2 (void)
9677{
9678 constraint (inst.operands[0].imm != 2,
9679 _("only two consecutive VFP SP registers allowed here"));
9680 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
9681 inst.instruction |= inst.operands[1].reg << 12;
9682 inst.instruction |= inst.operands[2].reg << 16;
9683}
9684
9685static void
9686do_vfp_sp_ldst (void)
9687{
9688 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9689 encode_arm_cp_address (1, FALSE, TRUE, 0);
9690}
9691
9692static void
9693do_vfp_dp_ldst (void)
9694{
9695 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9696 encode_arm_cp_address (1, FALSE, TRUE, 0);
9697}
9698
9699
9700static void
9701vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
9702{
9703 if (inst.operands[0].writeback)
9704 inst.instruction |= WRITE_BACK;
9705 else
9706 constraint (ldstm_type != VFP_LDSTMIA,
9707 _("this addressing mode requires base-register writeback"));
9708 inst.instruction |= inst.operands[0].reg << 16;
9709 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
9710 inst.instruction |= inst.operands[1].imm;
9711}
9712
9713static void
9714vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
9715{
9716 int count;
9717
9718 if (inst.operands[0].writeback)
9719 inst.instruction |= WRITE_BACK;
9720 else
9721 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
9722 _("this addressing mode requires base-register writeback"));
9723
9724 inst.instruction |= inst.operands[0].reg << 16;
9725 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9726
9727 count = inst.operands[1].imm << 1;
9728 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
9729 count += 1;
9730
9731 inst.instruction |= count;
9732}
9733
9734static void
9735do_vfp_sp_ldstmia (void)
9736{
9737 vfp_sp_ldstm (VFP_LDSTMIA);
9738}
9739
9740static void
9741do_vfp_sp_ldstmdb (void)
9742{
9743 vfp_sp_ldstm (VFP_LDSTMDB);
9744}
9745
9746static void
9747do_vfp_dp_ldstmia (void)
9748{
9749 vfp_dp_ldstm (VFP_LDSTMIA);
9750}
9751
9752static void
9753do_vfp_dp_ldstmdb (void)
9754{
9755 vfp_dp_ldstm (VFP_LDSTMDB);
9756}
9757
9758static void
9759do_vfp_xp_ldstmia (void)
9760{
9761 vfp_dp_ldstm (VFP_LDSTMIAX);
9762}
9763
9764static void
9765do_vfp_xp_ldstmdb (void)
9766{
9767 vfp_dp_ldstm (VFP_LDSTMDBX);
9768}
9769
9770static void
9771do_vfp_dp_rd_rm (void)
9772{
9773 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9774 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
9775}
9776
9777static void
9778do_vfp_dp_rn_rd (void)
9779{
9780 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
9781 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9782}
9783
9784static void
9785do_vfp_dp_rd_rn (void)
9786{
9787 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9788 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9789}
9790
9791static void
9792do_vfp_dp_rd_rn_rm (void)
9793{
9794 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9795 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9796 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
9797}
9798
9799static void
9800do_vfp_dp_rd (void)
9801{
9802 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9803}
9804
9805static void
9806do_vfp_dp_rm_rd_rn (void)
9807{
9808 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
9809 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9810 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
9811}
9812
9813/* VFPv3 instructions. */
9814static void
9815do_vfp_sp_const (void)
9816{
9817 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9818 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9819 inst.instruction |= (inst.operands[1].imm & 0x0f);
9820}
9821
9822static void
9823do_vfp_dp_const (void)
9824{
9825 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9826 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9827 inst.instruction |= (inst.operands[1].imm & 0x0f);
9828}
9829
9830static void
9831vfp_conv (int srcsize)
9832{
9833 int immbits = srcsize - inst.operands[1].imm;
9834
9835 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9836 {
9837 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9838 i.e. immbits must be in range 0 - 16. */
9839 inst.error = _("immediate value out of range, expected range [0, 16]");
9840 return;
9841 }
9842 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9843 {
9844 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9845 i.e. immbits must be in range 0 - 31. */
9846 inst.error = _("immediate value out of range, expected range [1, 32]");
9847 return;
9848 }
9849
9850 inst.instruction |= (immbits & 1) << 5;
9851 inst.instruction |= (immbits >> 1);
9852}
9853
9854static void
9855do_vfp_sp_conv_16 (void)
9856{
9857 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9858 vfp_conv (16);
9859}
9860
9861static void
9862do_vfp_dp_conv_16 (void)
9863{
9864 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9865 vfp_conv (16);
9866}
9867
9868static void
9869do_vfp_sp_conv_32 (void)
9870{
9871 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9872 vfp_conv (32);
9873}
9874
9875static void
9876do_vfp_dp_conv_32 (void)
9877{
9878 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9879 vfp_conv (32);
9880}
9881\f
9882/* FPA instructions. Also in a logical order. */
9883
9884static void
9885do_fpa_cmp (void)
9886{
9887 inst.instruction |= inst.operands[0].reg << 16;
9888 inst.instruction |= inst.operands[1].reg;
9889}
9890
9891static void
9892do_fpa_ldmstm (void)
9893{
9894 inst.instruction |= inst.operands[0].reg << 12;
9895 switch (inst.operands[1].imm)
9896 {
9897 case 1: inst.instruction |= CP_T_X; break;
9898 case 2: inst.instruction |= CP_T_Y; break;
9899 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9900 case 4: break;
9901 default: abort ();
9902 }
9903
9904 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9905 {
9906 /* The instruction specified "ea" or "fd", so we can only accept
9907 [Rn]{!}. The instruction does not really support stacking or
9908 unstacking, so we have to emulate these by setting appropriate
9909 bits and offsets. */
9910 constraint (inst.reloc.exp.X_op != O_constant
9911 || inst.reloc.exp.X_add_number != 0,
9912 _("this instruction does not support indexing"));
9913
9914 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9915 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9916
9917 if (!(inst.instruction & INDEX_UP))
9918 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9919
9920 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9921 {
9922 inst.operands[2].preind = 0;
9923 inst.operands[2].postind = 1;
9924 }
9925 }
9926
9927 encode_arm_cp_address (2, TRUE, TRUE, 0);
9928}
9929\f
9930/* iWMMXt instructions: strictly in alphabetical order. */
9931
9932static void
9933do_iwmmxt_tandorc (void)
9934{
9935 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9936}
9937
9938static void
9939do_iwmmxt_textrc (void)
9940{
9941 inst.instruction |= inst.operands[0].reg << 12;
9942 inst.instruction |= inst.operands[1].imm;
9943}
9944
9945static void
9946do_iwmmxt_textrm (void)
9947{
9948 inst.instruction |= inst.operands[0].reg << 12;
9949 inst.instruction |= inst.operands[1].reg << 16;
9950 inst.instruction |= inst.operands[2].imm;
9951}
9952
9953static void
9954do_iwmmxt_tinsr (void)
9955{
9956 inst.instruction |= inst.operands[0].reg << 16;
9957 inst.instruction |= inst.operands[1].reg << 12;
9958 inst.instruction |= inst.operands[2].imm;
9959}
9960
9961static void
9962do_iwmmxt_tmia (void)
9963{
9964 inst.instruction |= inst.operands[0].reg << 5;
9965 inst.instruction |= inst.operands[1].reg;
9966 inst.instruction |= inst.operands[2].reg << 12;
9967}
9968
9969static void
9970do_iwmmxt_waligni (void)
9971{
9972 inst.instruction |= inst.operands[0].reg << 12;
9973 inst.instruction |= inst.operands[1].reg << 16;
9974 inst.instruction |= inst.operands[2].reg;
9975 inst.instruction |= inst.operands[3].imm << 20;
9976}
9977
9978static void
9979do_iwmmxt_wmerge (void)
9980{
9981 inst.instruction |= inst.operands[0].reg << 12;
9982 inst.instruction |= inst.operands[1].reg << 16;
9983 inst.instruction |= inst.operands[2].reg;
9984 inst.instruction |= inst.operands[3].imm << 21;
9985}
9986
9987static void
9988do_iwmmxt_wmov (void)
9989{
9990 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9991 inst.instruction |= inst.operands[0].reg << 12;
9992 inst.instruction |= inst.operands[1].reg << 16;
9993 inst.instruction |= inst.operands[1].reg;
9994}
9995
9996static void
9997do_iwmmxt_wldstbh (void)
9998{
9999 int reloc;
10000 inst.instruction |= inst.operands[0].reg << 12;
10001 if (thumb_mode)
10002 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
10003 else
10004 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
10005 encode_arm_cp_address (1, TRUE, FALSE, reloc);
10006}
10007
10008static void
10009do_iwmmxt_wldstw (void)
10010{
10011 /* RIWR_RIWC clears .isreg for a control register. */
10012 if (!inst.operands[0].isreg)
10013 {
10014 constraint (inst.cond != COND_ALWAYS, BAD_COND);
10015 inst.instruction |= 0xf0000000;
10016 }
10017
10018 inst.instruction |= inst.operands[0].reg << 12;
10019 encode_arm_cp_address (1, TRUE, TRUE, 0);
10020}
10021
10022static void
10023do_iwmmxt_wldstd (void)
10024{
10025 inst.instruction |= inst.operands[0].reg << 12;
10026 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
10027 && inst.operands[1].immisreg)
10028 {
10029 inst.instruction &= ~0x1a000ff;
10030 inst.instruction |= (0xfU << 28);
10031 if (inst.operands[1].preind)
10032 inst.instruction |= PRE_INDEX;
10033 if (!inst.operands[1].negative)
10034 inst.instruction |= INDEX_UP;
10035 if (inst.operands[1].writeback)
10036 inst.instruction |= WRITE_BACK;
10037 inst.instruction |= inst.operands[1].reg << 16;
10038 inst.instruction |= inst.reloc.exp.X_add_number << 4;
10039 inst.instruction |= inst.operands[1].imm;
10040 }
10041 else
10042 encode_arm_cp_address (1, TRUE, FALSE, 0);
10043}
10044
10045static void
10046do_iwmmxt_wshufh (void)
10047{
10048 inst.instruction |= inst.operands[0].reg << 12;
10049 inst.instruction |= inst.operands[1].reg << 16;
10050 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
10051 inst.instruction |= (inst.operands[2].imm & 0x0f);
10052}
10053
10054static void
10055do_iwmmxt_wzero (void)
10056{
10057 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10058 inst.instruction |= inst.operands[0].reg;
10059 inst.instruction |= inst.operands[0].reg << 12;
10060 inst.instruction |= inst.operands[0].reg << 16;
10061}
10062
10063static void
10064do_iwmmxt_wrwrwr_or_imm5 (void)
10065{
10066 if (inst.operands[2].isreg)
10067 do_rd_rn_rm ();
10068 else {
10069 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
10070 _("immediate operand requires iWMMXt2"));
10071 do_rd_rn ();
10072 if (inst.operands[2].imm == 0)
10073 {
10074 switch ((inst.instruction >> 20) & 0xf)
10075 {
10076 case 4:
10077 case 5:
10078 case 6:
10079 case 7:
10080 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10081 inst.operands[2].imm = 16;
10082 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
10083 break;
10084 case 8:
10085 case 9:
10086 case 10:
10087 case 11:
10088 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10089 inst.operands[2].imm = 32;
10090 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
10091 break;
10092 case 12:
10093 case 13:
10094 case 14:
10095 case 15:
10096 {
10097 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10098 unsigned long wrn;
10099 wrn = (inst.instruction >> 16) & 0xf;
10100 inst.instruction &= 0xff0fff0f;
10101 inst.instruction |= wrn;
10102 /* Bail out here; the instruction is now assembled. */
10103 return;
10104 }
10105 }
10106 }
10107 /* Map 32 -> 0, etc. */
10108 inst.operands[2].imm &= 0x1f;
10109 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
10110 }
10111}
10112\f
10113/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10114 operations first, then control, shift, and load/store. */
10115
10116/* Insns like "foo X,Y,Z". */
10117
10118static void
10119do_mav_triple (void)
10120{
10121 inst.instruction |= inst.operands[0].reg << 16;
10122 inst.instruction |= inst.operands[1].reg;
10123 inst.instruction |= inst.operands[2].reg << 12;
10124}
10125
10126/* Insns like "foo W,X,Y,Z".
10127 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10128
10129static void
10130do_mav_quad (void)
10131{
10132 inst.instruction |= inst.operands[0].reg << 5;
10133 inst.instruction |= inst.operands[1].reg << 12;
10134 inst.instruction |= inst.operands[2].reg << 16;
10135 inst.instruction |= inst.operands[3].reg;
10136}
10137
10138/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10139static void
10140do_mav_dspsc (void)
10141{
10142 inst.instruction |= inst.operands[1].reg << 12;
10143}
10144
10145/* Maverick shift immediate instructions.
10146 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10147 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10148
10149static void
10150do_mav_shift (void)
10151{
10152 int imm = inst.operands[2].imm;
10153
10154 inst.instruction |= inst.operands[0].reg << 12;
10155 inst.instruction |= inst.operands[1].reg << 16;
10156
10157 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10158 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10159 Bit 4 should be 0. */
10160 imm = (imm & 0xf) | ((imm & 0x70) << 1);
10161
10162 inst.instruction |= imm;
10163}
10164\f
10165/* XScale instructions. Also sorted arithmetic before move. */
10166
10167/* Xscale multiply-accumulate (argument parse)
10168 MIAcc acc0,Rm,Rs
10169 MIAPHcc acc0,Rm,Rs
10170 MIAxycc acc0,Rm,Rs. */
10171
10172static void
10173do_xsc_mia (void)
10174{
10175 inst.instruction |= inst.operands[1].reg;
10176 inst.instruction |= inst.operands[2].reg << 12;
10177}
10178
10179/* Xscale move-accumulator-register (argument parse)
10180
10181 MARcc acc0,RdLo,RdHi. */
10182
10183static void
10184do_xsc_mar (void)
10185{
10186 inst.instruction |= inst.operands[1].reg << 12;
10187 inst.instruction |= inst.operands[2].reg << 16;
10188}
10189
10190/* Xscale move-register-accumulator (argument parse)
10191
10192 MRAcc RdLo,RdHi,acc0. */
10193
10194static void
10195do_xsc_mra (void)
10196{
10197 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
10198 inst.instruction |= inst.operands[0].reg << 12;
10199 inst.instruction |= inst.operands[1].reg << 16;
10200}
10201\f
10202/* Encoding functions relevant only to Thumb. */
10203
10204/* inst.operands[i] is a shifted-register operand; encode
10205 it into inst.instruction in the format used by Thumb32. */
10206
10207static void
10208encode_thumb32_shifted_operand (int i)
10209{
10210 unsigned int value = inst.reloc.exp.X_add_number;
10211 unsigned int shift = inst.operands[i].shift_kind;
10212
10213 constraint (inst.operands[i].immisreg,
10214 _("shift by register not allowed in thumb mode"));
10215 inst.instruction |= inst.operands[i].reg;
10216 if (shift == SHIFT_RRX)
10217 inst.instruction |= SHIFT_ROR << 4;
10218 else
10219 {
10220 constraint (inst.reloc.exp.X_op != O_constant,
10221 _("expression too complex"));
10222
10223 constraint (value > 32
10224 || (value == 32 && (shift == SHIFT_LSL
10225 || shift == SHIFT_ROR)),
10226 _("shift expression is too large"));
10227
10228 if (value == 0)
10229 shift = SHIFT_LSL;
10230 else if (value == 32)
10231 value = 0;
10232
10233 inst.instruction |= shift << 4;
10234 inst.instruction |= (value & 0x1c) << 10;
10235 inst.instruction |= (value & 0x03) << 6;
10236 }
10237}
10238
10239
10240/* inst.operands[i] was set up by parse_address. Encode it into a
10241 Thumb32 format load or store instruction. Reject forms that cannot
10242 be used with such instructions. If is_t is true, reject forms that
10243 cannot be used with a T instruction; if is_d is true, reject forms
10244 that cannot be used with a D instruction. If it is a store insn,
10245 reject PC in Rn. */
10246
10247static void
10248encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
10249{
10250 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
10251
10252 constraint (!inst.operands[i].isreg,
10253 _("Instruction does not support =N addresses"));
10254
10255 inst.instruction |= inst.operands[i].reg << 16;
10256 if (inst.operands[i].immisreg)
10257 {
10258 constraint (is_pc, BAD_PC_ADDRESSING);
10259 constraint (is_t || is_d, _("cannot use register index with this instruction"));
10260 constraint (inst.operands[i].negative,
10261 _("Thumb does not support negative register indexing"));
10262 constraint (inst.operands[i].postind,
10263 _("Thumb does not support register post-indexing"));
10264 constraint (inst.operands[i].writeback,
10265 _("Thumb does not support register indexing with writeback"));
10266 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
10267 _("Thumb supports only LSL in shifted register indexing"));
10268
10269 inst.instruction |= inst.operands[i].imm;
10270 if (inst.operands[i].shifted)
10271 {
10272 constraint (inst.reloc.exp.X_op != O_constant,
10273 _("expression too complex"));
10274 constraint (inst.reloc.exp.X_add_number < 0
10275 || inst.reloc.exp.X_add_number > 3,
10276 _("shift out of range"));
10277 inst.instruction |= inst.reloc.exp.X_add_number << 4;
10278 }
10279 inst.reloc.type = BFD_RELOC_UNUSED;
10280 }
10281 else if (inst.operands[i].preind)
10282 {
10283 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
10284 constraint (is_t && inst.operands[i].writeback,
10285 _("cannot use writeback with this instruction"));
10286 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
10287 BAD_PC_ADDRESSING);
10288
10289 if (is_d)
10290 {
10291 inst.instruction |= 0x01000000;
10292 if (inst.operands[i].writeback)
10293 inst.instruction |= 0x00200000;
10294 }
10295 else
10296 {
10297 inst.instruction |= 0x00000c00;
10298 if (inst.operands[i].writeback)
10299 inst.instruction |= 0x00000100;
10300 }
10301 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10302 }
10303 else if (inst.operands[i].postind)
10304 {
10305 gas_assert (inst.operands[i].writeback);
10306 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
10307 constraint (is_t, _("cannot use post-indexing with this instruction"));
10308
10309 if (is_d)
10310 inst.instruction |= 0x00200000;
10311 else
10312 inst.instruction |= 0x00000900;
10313 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10314 }
10315 else /* unindexed - only for coprocessor */
10316 inst.error = _("instruction does not accept unindexed addressing");
10317}
10318
10319/* Table of Thumb instructions which exist in both 16- and 32-bit
10320 encodings (the latter only in post-V6T2 cores). The index is the
10321 value used in the insns table below. When there is more than one
10322 possible 16-bit encoding for the instruction, this table always
10323 holds variant (1).
10324 Also contains several pseudo-instructions used during relaxation. */
10325#define T16_32_TAB \
10326 X(_adc, 4140, eb400000), \
10327 X(_adcs, 4140, eb500000), \
10328 X(_add, 1c00, eb000000), \
10329 X(_adds, 1c00, eb100000), \
10330 X(_addi, 0000, f1000000), \
10331 X(_addis, 0000, f1100000), \
10332 X(_add_pc,000f, f20f0000), \
10333 X(_add_sp,000d, f10d0000), \
10334 X(_adr, 000f, f20f0000), \
10335 X(_and, 4000, ea000000), \
10336 X(_ands, 4000, ea100000), \
10337 X(_asr, 1000, fa40f000), \
10338 X(_asrs, 1000, fa50f000), \
10339 X(_b, e000, f000b000), \
10340 X(_bcond, d000, f0008000), \
10341 X(_bic, 4380, ea200000), \
10342 X(_bics, 4380, ea300000), \
10343 X(_cmn, 42c0, eb100f00), \
10344 X(_cmp, 2800, ebb00f00), \
10345 X(_cpsie, b660, f3af8400), \
10346 X(_cpsid, b670, f3af8600), \
10347 X(_cpy, 4600, ea4f0000), \
10348 X(_dec_sp,80dd, f1ad0d00), \
10349 X(_eor, 4040, ea800000), \
10350 X(_eors, 4040, ea900000), \
10351 X(_inc_sp,00dd, f10d0d00), \
10352 X(_ldmia, c800, e8900000), \
10353 X(_ldr, 6800, f8500000), \
10354 X(_ldrb, 7800, f8100000), \
10355 X(_ldrh, 8800, f8300000), \
10356 X(_ldrsb, 5600, f9100000), \
10357 X(_ldrsh, 5e00, f9300000), \
10358 X(_ldr_pc,4800, f85f0000), \
10359 X(_ldr_pc2,4800, f85f0000), \
10360 X(_ldr_sp,9800, f85d0000), \
10361 X(_lsl, 0000, fa00f000), \
10362 X(_lsls, 0000, fa10f000), \
10363 X(_lsr, 0800, fa20f000), \
10364 X(_lsrs, 0800, fa30f000), \
10365 X(_mov, 2000, ea4f0000), \
10366 X(_movs, 2000, ea5f0000), \
10367 X(_mul, 4340, fb00f000), \
10368 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10369 X(_mvn, 43c0, ea6f0000), \
10370 X(_mvns, 43c0, ea7f0000), \
10371 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10372 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10373 X(_orr, 4300, ea400000), \
10374 X(_orrs, 4300, ea500000), \
10375 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10376 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10377 X(_rev, ba00, fa90f080), \
10378 X(_rev16, ba40, fa90f090), \
10379 X(_revsh, bac0, fa90f0b0), \
10380 X(_ror, 41c0, fa60f000), \
10381 X(_rors, 41c0, fa70f000), \
10382 X(_sbc, 4180, eb600000), \
10383 X(_sbcs, 4180, eb700000), \
10384 X(_stmia, c000, e8800000), \
10385 X(_str, 6000, f8400000), \
10386 X(_strb, 7000, f8000000), \
10387 X(_strh, 8000, f8200000), \
10388 X(_str_sp,9000, f84d0000), \
10389 X(_sub, 1e00, eba00000), \
10390 X(_subs, 1e00, ebb00000), \
10391 X(_subi, 8000, f1a00000), \
10392 X(_subis, 8000, f1b00000), \
10393 X(_sxtb, b240, fa4ff080), \
10394 X(_sxth, b200, fa0ff080), \
10395 X(_tst, 4200, ea100f00), \
10396 X(_uxtb, b2c0, fa5ff080), \
10397 X(_uxth, b280, fa1ff080), \
10398 X(_nop, bf00, f3af8000), \
10399 X(_yield, bf10, f3af8001), \
10400 X(_wfe, bf20, f3af8002), \
10401 X(_wfi, bf30, f3af8003), \
10402 X(_sev, bf40, f3af8004), \
10403 X(_sevl, bf50, f3af8005), \
10404 X(_udf, de00, f7f0a000)
10405
10406/* To catch errors in encoding functions, the codes are all offset by
10407 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10408 as 16-bit instructions. */
10409#define X(a,b,c) T_MNEM##a
10410enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
10411#undef X
10412
10413#define X(a,b,c) 0x##b
10414static const unsigned short thumb_op16[] = { T16_32_TAB };
10415#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10416#undef X
10417
10418#define X(a,b,c) 0x##c
10419static const unsigned int thumb_op32[] = { T16_32_TAB };
10420#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10421#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10422#undef X
10423#undef T16_32_TAB
10424
10425/* Thumb instruction encoders, in alphabetical order. */
10426
10427/* ADDW or SUBW. */
10428
10429static void
10430do_t_add_sub_w (void)
10431{
10432 int Rd, Rn;
10433
10434 Rd = inst.operands[0].reg;
10435 Rn = inst.operands[1].reg;
10436
10437 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10438 is the SP-{plus,minus}-immediate form of the instruction. */
10439 if (Rn == REG_SP)
10440 constraint (Rd == REG_PC, BAD_PC);
10441 else
10442 reject_bad_reg (Rd);
10443
10444 inst.instruction |= (Rn << 16) | (Rd << 8);
10445 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10446}
10447
10448/* Parse an add or subtract instruction. We get here with inst.instruction
10449 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10450
10451static void
10452do_t_add_sub (void)
10453{
10454 int Rd, Rs, Rn;
10455
10456 Rd = inst.operands[0].reg;
10457 Rs = (inst.operands[1].present
10458 ? inst.operands[1].reg /* Rd, Rs, foo */
10459 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10460
10461 if (Rd == REG_PC)
10462 set_it_insn_type_last ();
10463
10464 if (unified_syntax)
10465 {
10466 bfd_boolean flags;
10467 bfd_boolean narrow;
10468 int opcode;
10469
10470 flags = (inst.instruction == T_MNEM_adds
10471 || inst.instruction == T_MNEM_subs);
10472 if (flags)
10473 narrow = !in_it_block ();
10474 else
10475 narrow = in_it_block ();
10476 if (!inst.operands[2].isreg)
10477 {
10478 int add;
10479
10480 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10481
10482 add = (inst.instruction == T_MNEM_add
10483 || inst.instruction == T_MNEM_adds);
10484 opcode = 0;
10485 if (inst.size_req != 4)
10486 {
10487 /* Attempt to use a narrow opcode, with relaxation if
10488 appropriate. */
10489 if (Rd == REG_SP && Rs == REG_SP && !flags)
10490 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
10491 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
10492 opcode = T_MNEM_add_sp;
10493 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
10494 opcode = T_MNEM_add_pc;
10495 else if (Rd <= 7 && Rs <= 7 && narrow)
10496 {
10497 if (flags)
10498 opcode = add ? T_MNEM_addis : T_MNEM_subis;
10499 else
10500 opcode = add ? T_MNEM_addi : T_MNEM_subi;
10501 }
10502 if (opcode)
10503 {
10504 inst.instruction = THUMB_OP16(opcode);
10505 inst.instruction |= (Rd << 4) | Rs;
10506 if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10507 || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
10508 {
10509 if (inst.size_req == 2)
10510 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10511 else
10512 inst.relax = opcode;
10513 }
10514 }
10515 else
10516 constraint (inst.size_req == 2, BAD_HIREG);
10517 }
10518 if (inst.size_req == 4
10519 || (inst.size_req != 2 && !opcode))
10520 {
10521 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10522 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
10523 THUMB1_RELOC_ONLY);
10524 if (Rd == REG_PC)
10525 {
10526 constraint (add, BAD_PC);
10527 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
10528 _("only SUBS PC, LR, #const allowed"));
10529 constraint (inst.reloc.exp.X_op != O_constant,
10530 _("expression too complex"));
10531 constraint (inst.reloc.exp.X_add_number < 0
10532 || inst.reloc.exp.X_add_number > 0xff,
10533 _("immediate value out of range"));
10534 inst.instruction = T2_SUBS_PC_LR
10535 | inst.reloc.exp.X_add_number;
10536 inst.reloc.type = BFD_RELOC_UNUSED;
10537 return;
10538 }
10539 else if (Rs == REG_PC)
10540 {
10541 /* Always use addw/subw. */
10542 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
10543 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10544 }
10545 else
10546 {
10547 inst.instruction = THUMB_OP32 (inst.instruction);
10548 inst.instruction = (inst.instruction & 0xe1ffffff)
10549 | 0x10000000;
10550 if (flags)
10551 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10552 else
10553 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
10554 }
10555 inst.instruction |= Rd << 8;
10556 inst.instruction |= Rs << 16;
10557 }
10558 }
10559 else
10560 {
10561 unsigned int value = inst.reloc.exp.X_add_number;
10562 unsigned int shift = inst.operands[2].shift_kind;
10563
10564 Rn = inst.operands[2].reg;
10565 /* See if we can do this with a 16-bit instruction. */
10566 if (!inst.operands[2].shifted && inst.size_req != 4)
10567 {
10568 if (Rd > 7 || Rs > 7 || Rn > 7)
10569 narrow = FALSE;
10570
10571 if (narrow)
10572 {
10573 inst.instruction = ((inst.instruction == T_MNEM_adds
10574 || inst.instruction == T_MNEM_add)
10575 ? T_OPCODE_ADD_R3
10576 : T_OPCODE_SUB_R3);
10577 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
10578 return;
10579 }
10580
10581 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
10582 {
10583 /* Thumb-1 cores (except v6-M) require at least one high
10584 register in a narrow non flag setting add. */
10585 if (Rd > 7 || Rn > 7
10586 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
10587 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
10588 {
10589 if (Rd == Rn)
10590 {
10591 Rn = Rs;
10592 Rs = Rd;
10593 }
10594 inst.instruction = T_OPCODE_ADD_HI;
10595 inst.instruction |= (Rd & 8) << 4;
10596 inst.instruction |= (Rd & 7);
10597 inst.instruction |= Rn << 3;
10598 return;
10599 }
10600 }
10601 }
10602
10603 constraint (Rd == REG_PC, BAD_PC);
10604 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10605 constraint (Rs == REG_PC, BAD_PC);
10606 reject_bad_reg (Rn);
10607
10608 /* If we get here, it can't be done in 16 bits. */
10609 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
10610 _("shift must be constant"));
10611 inst.instruction = THUMB_OP32 (inst.instruction);
10612 inst.instruction |= Rd << 8;
10613 inst.instruction |= Rs << 16;
10614 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
10615 _("shift value over 3 not allowed in thumb mode"));
10616 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
10617 _("only LSL shift allowed in thumb mode"));
10618 encode_thumb32_shifted_operand (2);
10619 }
10620 }
10621 else
10622 {
10623 constraint (inst.instruction == T_MNEM_adds
10624 || inst.instruction == T_MNEM_subs,
10625 BAD_THUMB32);
10626
10627 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
10628 {
10629 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
10630 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
10631 BAD_HIREG);
10632
10633 inst.instruction = (inst.instruction == T_MNEM_add
10634 ? 0x0000 : 0x8000);
10635 inst.instruction |= (Rd << 4) | Rs;
10636 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10637 return;
10638 }
10639
10640 Rn = inst.operands[2].reg;
10641 constraint (inst.operands[2].shifted, _("unshifted register required"));
10642
10643 /* We now have Rd, Rs, and Rn set to registers. */
10644 if (Rd > 7 || Rs > 7 || Rn > 7)
10645 {
10646 /* Can't do this for SUB. */
10647 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
10648 inst.instruction = T_OPCODE_ADD_HI;
10649 inst.instruction |= (Rd & 8) << 4;
10650 inst.instruction |= (Rd & 7);
10651 if (Rs == Rd)
10652 inst.instruction |= Rn << 3;
10653 else if (Rn == Rd)
10654 inst.instruction |= Rs << 3;
10655 else
10656 constraint (1, _("dest must overlap one source register"));
10657 }
10658 else
10659 {
10660 inst.instruction = (inst.instruction == T_MNEM_add
10661 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
10662 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
10663 }
10664 }
10665}
10666
10667static void
10668do_t_adr (void)
10669{
10670 unsigned Rd;
10671
10672 Rd = inst.operands[0].reg;
10673 reject_bad_reg (Rd);
10674
10675 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
10676 {
10677 /* Defer to section relaxation. */
10678 inst.relax = inst.instruction;
10679 inst.instruction = THUMB_OP16 (inst.instruction);
10680 inst.instruction |= Rd << 4;
10681 }
10682 else if (unified_syntax && inst.size_req != 2)
10683 {
10684 /* Generate a 32-bit opcode. */
10685 inst.instruction = THUMB_OP32 (inst.instruction);
10686 inst.instruction |= Rd << 8;
10687 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
10688 inst.reloc.pc_rel = 1;
10689 }
10690 else
10691 {
10692 /* Generate a 16-bit opcode. */
10693 inst.instruction = THUMB_OP16 (inst.instruction);
10694 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10695 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
10696 inst.reloc.pc_rel = 1;
10697
10698 inst.instruction |= Rd << 4;
10699 }
10700}
10701
10702/* Arithmetic instructions for which there is just one 16-bit
10703 instruction encoding, and it allows only two low registers.
10704 For maximal compatibility with ARM syntax, we allow three register
10705 operands even when Thumb-32 instructions are not available, as long
10706 as the first two are identical. For instance, both "sbc r0,r1" and
10707 "sbc r0,r0,r1" are allowed. */
10708static void
10709do_t_arit3 (void)
10710{
10711 int Rd, Rs, Rn;
10712
10713 Rd = inst.operands[0].reg;
10714 Rs = (inst.operands[1].present
10715 ? inst.operands[1].reg /* Rd, Rs, foo */
10716 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10717 Rn = inst.operands[2].reg;
10718
10719 reject_bad_reg (Rd);
10720 reject_bad_reg (Rs);
10721 if (inst.operands[2].isreg)
10722 reject_bad_reg (Rn);
10723
10724 if (unified_syntax)
10725 {
10726 if (!inst.operands[2].isreg)
10727 {
10728 /* For an immediate, we always generate a 32-bit opcode;
10729 section relaxation will shrink it later if possible. */
10730 inst.instruction = THUMB_OP32 (inst.instruction);
10731 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10732 inst.instruction |= Rd << 8;
10733 inst.instruction |= Rs << 16;
10734 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10735 }
10736 else
10737 {
10738 bfd_boolean narrow;
10739
10740 /* See if we can do this with a 16-bit instruction. */
10741 if (THUMB_SETS_FLAGS (inst.instruction))
10742 narrow = !in_it_block ();
10743 else
10744 narrow = in_it_block ();
10745
10746 if (Rd > 7 || Rn > 7 || Rs > 7)
10747 narrow = FALSE;
10748 if (inst.operands[2].shifted)
10749 narrow = FALSE;
10750 if (inst.size_req == 4)
10751 narrow = FALSE;
10752
10753 if (narrow
10754 && Rd == Rs)
10755 {
10756 inst.instruction = THUMB_OP16 (inst.instruction);
10757 inst.instruction |= Rd;
10758 inst.instruction |= Rn << 3;
10759 return;
10760 }
10761
10762 /* If we get here, it can't be done in 16 bits. */
10763 constraint (inst.operands[2].shifted
10764 && inst.operands[2].immisreg,
10765 _("shift must be constant"));
10766 inst.instruction = THUMB_OP32 (inst.instruction);
10767 inst.instruction |= Rd << 8;
10768 inst.instruction |= Rs << 16;
10769 encode_thumb32_shifted_operand (2);
10770 }
10771 }
10772 else
10773 {
10774 /* On its face this is a lie - the instruction does set the
10775 flags. However, the only supported mnemonic in this mode
10776 says it doesn't. */
10777 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10778
10779 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10780 _("unshifted register required"));
10781 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10782 constraint (Rd != Rs,
10783 _("dest and source1 must be the same register"));
10784
10785 inst.instruction = THUMB_OP16 (inst.instruction);
10786 inst.instruction |= Rd;
10787 inst.instruction |= Rn << 3;
10788 }
10789}
10790
10791/* Similarly, but for instructions where the arithmetic operation is
10792 commutative, so we can allow either of them to be different from
10793 the destination operand in a 16-bit instruction. For instance, all
10794 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10795 accepted. */
10796static void
10797do_t_arit3c (void)
10798{
10799 int Rd, Rs, Rn;
10800
10801 Rd = inst.operands[0].reg;
10802 Rs = (inst.operands[1].present
10803 ? inst.operands[1].reg /* Rd, Rs, foo */
10804 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10805 Rn = inst.operands[2].reg;
10806
10807 reject_bad_reg (Rd);
10808 reject_bad_reg (Rs);
10809 if (inst.operands[2].isreg)
10810 reject_bad_reg (Rn);
10811
10812 if (unified_syntax)
10813 {
10814 if (!inst.operands[2].isreg)
10815 {
10816 /* For an immediate, we always generate a 32-bit opcode;
10817 section relaxation will shrink it later if possible. */
10818 inst.instruction = THUMB_OP32 (inst.instruction);
10819 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10820 inst.instruction |= Rd << 8;
10821 inst.instruction |= Rs << 16;
10822 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10823 }
10824 else
10825 {
10826 bfd_boolean narrow;
10827
10828 /* See if we can do this with a 16-bit instruction. */
10829 if (THUMB_SETS_FLAGS (inst.instruction))
10830 narrow = !in_it_block ();
10831 else
10832 narrow = in_it_block ();
10833
10834 if (Rd > 7 || Rn > 7 || Rs > 7)
10835 narrow = FALSE;
10836 if (inst.operands[2].shifted)
10837 narrow = FALSE;
10838 if (inst.size_req == 4)
10839 narrow = FALSE;
10840
10841 if (narrow)
10842 {
10843 if (Rd == Rs)
10844 {
10845 inst.instruction = THUMB_OP16 (inst.instruction);
10846 inst.instruction |= Rd;
10847 inst.instruction |= Rn << 3;
10848 return;
10849 }
10850 if (Rd == Rn)
10851 {
10852 inst.instruction = THUMB_OP16 (inst.instruction);
10853 inst.instruction |= Rd;
10854 inst.instruction |= Rs << 3;
10855 return;
10856 }
10857 }
10858
10859 /* If we get here, it can't be done in 16 bits. */
10860 constraint (inst.operands[2].shifted
10861 && inst.operands[2].immisreg,
10862 _("shift must be constant"));
10863 inst.instruction = THUMB_OP32 (inst.instruction);
10864 inst.instruction |= Rd << 8;
10865 inst.instruction |= Rs << 16;
10866 encode_thumb32_shifted_operand (2);
10867 }
10868 }
10869 else
10870 {
10871 /* On its face this is a lie - the instruction does set the
10872 flags. However, the only supported mnemonic in this mode
10873 says it doesn't. */
10874 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10875
10876 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10877 _("unshifted register required"));
10878 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10879
10880 inst.instruction = THUMB_OP16 (inst.instruction);
10881 inst.instruction |= Rd;
10882
10883 if (Rd == Rs)
10884 inst.instruction |= Rn << 3;
10885 else if (Rd == Rn)
10886 inst.instruction |= Rs << 3;
10887 else
10888 constraint (1, _("dest must overlap one source register"));
10889 }
10890}
10891
10892static void
10893do_t_bfc (void)
10894{
10895 unsigned Rd;
10896 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10897 constraint (msb > 32, _("bit-field extends past end of register"));
10898 /* The instruction encoding stores the LSB and MSB,
10899 not the LSB and width. */
10900 Rd = inst.operands[0].reg;
10901 reject_bad_reg (Rd);
10902 inst.instruction |= Rd << 8;
10903 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10904 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10905 inst.instruction |= msb - 1;
10906}
10907
10908static void
10909do_t_bfi (void)
10910{
10911 int Rd, Rn;
10912 unsigned int msb;
10913
10914 Rd = inst.operands[0].reg;
10915 reject_bad_reg (Rd);
10916
10917 /* #0 in second position is alternative syntax for bfc, which is
10918 the same instruction but with REG_PC in the Rm field. */
10919 if (!inst.operands[1].isreg)
10920 Rn = REG_PC;
10921 else
10922 {
10923 Rn = inst.operands[1].reg;
10924 reject_bad_reg (Rn);
10925 }
10926
10927 msb = inst.operands[2].imm + inst.operands[3].imm;
10928 constraint (msb > 32, _("bit-field extends past end of register"));
10929 /* The instruction encoding stores the LSB and MSB,
10930 not the LSB and width. */
10931 inst.instruction |= Rd << 8;
10932 inst.instruction |= Rn << 16;
10933 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10934 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10935 inst.instruction |= msb - 1;
10936}
10937
10938static void
10939do_t_bfx (void)
10940{
10941 unsigned Rd, Rn;
10942
10943 Rd = inst.operands[0].reg;
10944 Rn = inst.operands[1].reg;
10945
10946 reject_bad_reg (Rd);
10947 reject_bad_reg (Rn);
10948
10949 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10950 _("bit-field extends past end of register"));
10951 inst.instruction |= Rd << 8;
10952 inst.instruction |= Rn << 16;
10953 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10954 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10955 inst.instruction |= inst.operands[3].imm - 1;
10956}
10957
10958/* ARM V5 Thumb BLX (argument parse)
10959 BLX <target_addr> which is BLX(1)
10960 BLX <Rm> which is BLX(2)
10961 Unfortunately, there are two different opcodes for this mnemonic.
10962 So, the insns[].value is not used, and the code here zaps values
10963 into inst.instruction.
10964
10965 ??? How to take advantage of the additional two bits of displacement
10966 available in Thumb32 mode? Need new relocation? */
10967
10968static void
10969do_t_blx (void)
10970{
10971 set_it_insn_type_last ();
10972
10973 if (inst.operands[0].isreg)
10974 {
10975 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10976 /* We have a register, so this is BLX(2). */
10977 inst.instruction |= inst.operands[0].reg << 3;
10978 }
10979 else
10980 {
10981 /* No register. This must be BLX(1). */
10982 inst.instruction = 0xf000e800;
10983 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10984 }
10985}
10986
10987static void
10988do_t_branch (void)
10989{
10990 int opcode;
10991 int cond;
10992 bfd_reloc_code_real_type reloc;
10993
10994 cond = inst.cond;
10995 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10996
10997 if (in_it_block ())
10998 {
10999 /* Conditional branches inside IT blocks are encoded as unconditional
11000 branches. */
11001 cond = COND_ALWAYS;
11002 }
11003 else
11004 cond = inst.cond;
11005
11006 if (cond != COND_ALWAYS)
11007 opcode = T_MNEM_bcond;
11008 else
11009 opcode = inst.instruction;
11010
11011 if (unified_syntax
11012 && (inst.size_req == 4
11013 || (inst.size_req != 2
11014 && (inst.operands[0].hasreloc
11015 || inst.reloc.exp.X_op == O_constant))))
11016 {
11017 inst.instruction = THUMB_OP32(opcode);
11018 if (cond == COND_ALWAYS)
11019 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
11020 else
11021 {
11022 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
11023 _("selected architecture does not support "
11024 "wide conditional branch instruction"));
11025
11026 gas_assert (cond != 0xF);
11027 inst.instruction |= cond << 22;
11028 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
11029 }
11030 }
11031 else
11032 {
11033 inst.instruction = THUMB_OP16(opcode);
11034 if (cond == COND_ALWAYS)
11035 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
11036 else
11037 {
11038 inst.instruction |= cond << 8;
11039 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
11040 }
11041 /* Allow section relaxation. */
11042 if (unified_syntax && inst.size_req != 2)
11043 inst.relax = opcode;
11044 }
11045 inst.reloc.type = reloc;
11046 inst.reloc.pc_rel = 1;
11047}
11048
11049/* Actually do the work for Thumb state bkpt and hlt. The only difference
11050 between the two is the maximum immediate allowed - which is passed in
11051 RANGE. */
11052static void
11053do_t_bkpt_hlt1 (int range)
11054{
11055 constraint (inst.cond != COND_ALWAYS,
11056 _("instruction is always unconditional"));
11057 if (inst.operands[0].present)
11058 {
11059 constraint (inst.operands[0].imm > range,
11060 _("immediate value out of range"));
11061 inst.instruction |= inst.operands[0].imm;
11062 }
11063
11064 set_it_insn_type (NEUTRAL_IT_INSN);
11065}
11066
11067static void
11068do_t_hlt (void)
11069{
11070 do_t_bkpt_hlt1 (63);
11071}
11072
11073static void
11074do_t_bkpt (void)
11075{
11076 do_t_bkpt_hlt1 (255);
11077}
11078
11079static void
11080do_t_branch23 (void)
11081{
11082 set_it_insn_type_last ();
11083 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
11084
11085 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11086 this file. We used to simply ignore the PLT reloc type here --
11087 the branch encoding is now needed to deal with TLSCALL relocs.
11088 So if we see a PLT reloc now, put it back to how it used to be to
11089 keep the preexisting behaviour. */
11090 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
11091 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
11092
11093#if defined(OBJ_COFF)
11094 /* If the destination of the branch is a defined symbol which does not have
11095 the THUMB_FUNC attribute, then we must be calling a function which has
11096 the (interfacearm) attribute. We look for the Thumb entry point to that
11097 function and change the branch to refer to that function instead. */
11098 if ( inst.reloc.exp.X_op == O_symbol
11099 && inst.reloc.exp.X_add_symbol != NULL
11100 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
11101 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
11102 inst.reloc.exp.X_add_symbol =
11103 find_real_start (inst.reloc.exp.X_add_symbol);
11104#endif
11105}
11106
11107static void
11108do_t_bx (void)
11109{
11110 set_it_insn_type_last ();
11111 inst.instruction |= inst.operands[0].reg << 3;
11112 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11113 should cause the alignment to be checked once it is known. This is
11114 because BX PC only works if the instruction is word aligned. */
11115}
11116
11117static void
11118do_t_bxj (void)
11119{
11120 int Rm;
11121
11122 set_it_insn_type_last ();
11123 Rm = inst.operands[0].reg;
11124 reject_bad_reg (Rm);
11125 inst.instruction |= Rm << 16;
11126}
11127
11128static void
11129do_t_clz (void)
11130{
11131 unsigned Rd;
11132 unsigned Rm;
11133
11134 Rd = inst.operands[0].reg;
11135 Rm = inst.operands[1].reg;
11136
11137 reject_bad_reg (Rd);
11138 reject_bad_reg (Rm);
11139
11140 inst.instruction |= Rd << 8;
11141 inst.instruction |= Rm << 16;
11142 inst.instruction |= Rm;
11143}
11144
11145static void
11146do_t_cps (void)
11147{
11148 set_it_insn_type (OUTSIDE_IT_INSN);
11149 inst.instruction |= inst.operands[0].imm;
11150}
11151
11152static void
11153do_t_cpsi (void)
11154{
11155 set_it_insn_type (OUTSIDE_IT_INSN);
11156 if (unified_syntax
11157 && (inst.operands[1].present || inst.size_req == 4)
11158 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
11159 {
11160 unsigned int imod = (inst.instruction & 0x0030) >> 4;
11161 inst.instruction = 0xf3af8000;
11162 inst.instruction |= imod << 9;
11163 inst.instruction |= inst.operands[0].imm << 5;
11164 if (inst.operands[1].present)
11165 inst.instruction |= 0x100 | inst.operands[1].imm;
11166 }
11167 else
11168 {
11169 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
11170 && (inst.operands[0].imm & 4),
11171 _("selected processor does not support 'A' form "
11172 "of this instruction"));
11173 constraint (inst.operands[1].present || inst.size_req == 4,
11174 _("Thumb does not support the 2-argument "
11175 "form of this instruction"));
11176 inst.instruction |= inst.operands[0].imm;
11177 }
11178}
11179
11180/* THUMB CPY instruction (argument parse). */
11181
11182static void
11183do_t_cpy (void)
11184{
11185 if (inst.size_req == 4)
11186 {
11187 inst.instruction = THUMB_OP32 (T_MNEM_mov);
11188 inst.instruction |= inst.operands[0].reg << 8;
11189 inst.instruction |= inst.operands[1].reg;
11190 }
11191 else
11192 {
11193 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
11194 inst.instruction |= (inst.operands[0].reg & 0x7);
11195 inst.instruction |= inst.operands[1].reg << 3;
11196 }
11197}
11198
11199static void
11200do_t_cbz (void)
11201{
11202 set_it_insn_type (OUTSIDE_IT_INSN);
11203 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11204 inst.instruction |= inst.operands[0].reg;
11205 inst.reloc.pc_rel = 1;
11206 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
11207}
11208
11209static void
11210do_t_dbg (void)
11211{
11212 inst.instruction |= inst.operands[0].imm;
11213}
11214
11215static void
11216do_t_div (void)
11217{
11218 unsigned Rd, Rn, Rm;
11219
11220 Rd = inst.operands[0].reg;
11221 Rn = (inst.operands[1].present
11222 ? inst.operands[1].reg : Rd);
11223 Rm = inst.operands[2].reg;
11224
11225 reject_bad_reg (Rd);
11226 reject_bad_reg (Rn);
11227 reject_bad_reg (Rm);
11228
11229 inst.instruction |= Rd << 8;
11230 inst.instruction |= Rn << 16;
11231 inst.instruction |= Rm;
11232}
11233
11234static void
11235do_t_hint (void)
11236{
11237 if (unified_syntax && inst.size_req == 4)
11238 inst.instruction = THUMB_OP32 (inst.instruction);
11239 else
11240 inst.instruction = THUMB_OP16 (inst.instruction);
11241}
11242
11243static void
11244do_t_it (void)
11245{
11246 unsigned int cond = inst.operands[0].imm;
11247
11248 set_it_insn_type (IT_INSN);
11249 now_it.mask = (inst.instruction & 0xf) | 0x10;
11250 now_it.cc = cond;
11251 now_it.warn_deprecated = FALSE;
11252
11253 /* If the condition is a negative condition, invert the mask. */
11254 if ((cond & 0x1) == 0x0)
11255 {
11256 unsigned int mask = inst.instruction & 0x000f;
11257
11258 if ((mask & 0x7) == 0)
11259 {
11260 /* No conversion needed. */
11261 now_it.block_length = 1;
11262 }
11263 else if ((mask & 0x3) == 0)
11264 {
11265 mask ^= 0x8;
11266 now_it.block_length = 2;
11267 }
11268 else if ((mask & 0x1) == 0)
11269 {
11270 mask ^= 0xC;
11271 now_it.block_length = 3;
11272 }
11273 else
11274 {
11275 mask ^= 0xE;
11276 now_it.block_length = 4;
11277 }
11278
11279 inst.instruction &= 0xfff0;
11280 inst.instruction |= mask;
11281 }
11282
11283 inst.instruction |= cond << 4;
11284}
11285
11286/* Helper function used for both push/pop and ldm/stm. */
11287static void
11288encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
11289{
11290 bfd_boolean load;
11291
11292 load = (inst.instruction & (1 << 20)) != 0;
11293
11294 if (mask & (1 << 13))
11295 inst.error = _("SP not allowed in register list");
11296
11297 if ((mask & (1 << base)) != 0
11298 && writeback)
11299 inst.error = _("having the base register in the register list when "
11300 "using write back is UNPREDICTABLE");
11301
11302 if (load)
11303 {
11304 if (mask & (1 << 15))
11305 {
11306 if (mask & (1 << 14))
11307 inst.error = _("LR and PC should not both be in register list");
11308 else
11309 set_it_insn_type_last ();
11310 }
11311 }
11312 else
11313 {
11314 if (mask & (1 << 15))
11315 inst.error = _("PC not allowed in register list");
11316 }
11317
11318 if ((mask & (mask - 1)) == 0)
11319 {
11320 /* Single register transfers implemented as str/ldr. */
11321 if (writeback)
11322 {
11323 if (inst.instruction & (1 << 23))
11324 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
11325 else
11326 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
11327 }
11328 else
11329 {
11330 if (inst.instruction & (1 << 23))
11331 inst.instruction = 0x00800000; /* ia -> [base] */
11332 else
11333 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
11334 }
11335
11336 inst.instruction |= 0xf8400000;
11337 if (load)
11338 inst.instruction |= 0x00100000;
11339
11340 mask = ffs (mask) - 1;
11341 mask <<= 12;
11342 }
11343 else if (writeback)
11344 inst.instruction |= WRITE_BACK;
11345
11346 inst.instruction |= mask;
11347 inst.instruction |= base << 16;
11348}
11349
11350static void
11351do_t_ldmstm (void)
11352{
11353 /* This really doesn't seem worth it. */
11354 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11355 _("expression too complex"));
11356 constraint (inst.operands[1].writeback,
11357 _("Thumb load/store multiple does not support {reglist}^"));
11358
11359 if (unified_syntax)
11360 {
11361 bfd_boolean narrow;
11362 unsigned mask;
11363
11364 narrow = FALSE;
11365 /* See if we can use a 16-bit instruction. */
11366 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
11367 && inst.size_req != 4
11368 && !(inst.operands[1].imm & ~0xff))
11369 {
11370 mask = 1 << inst.operands[0].reg;
11371
11372 if (inst.operands[0].reg <= 7)
11373 {
11374 if (inst.instruction == T_MNEM_stmia
11375 ? inst.operands[0].writeback
11376 : (inst.operands[0].writeback
11377 == !(inst.operands[1].imm & mask)))
11378 {
11379 if (inst.instruction == T_MNEM_stmia
11380 && (inst.operands[1].imm & mask)
11381 && (inst.operands[1].imm & (mask - 1)))
11382 as_warn (_("value stored for r%d is UNKNOWN"),
11383 inst.operands[0].reg);
11384
11385 inst.instruction = THUMB_OP16 (inst.instruction);
11386 inst.instruction |= inst.operands[0].reg << 8;
11387 inst.instruction |= inst.operands[1].imm;
11388 narrow = TRUE;
11389 }
11390 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11391 {
11392 /* This means 1 register in reg list one of 3 situations:
11393 1. Instruction is stmia, but without writeback.
11394 2. lmdia without writeback, but with Rn not in
11395 reglist.
11396 3. ldmia with writeback, but with Rn in reglist.
11397 Case 3 is UNPREDICTABLE behaviour, so we handle
11398 case 1 and 2 which can be converted into a 16-bit
11399 str or ldr. The SP cases are handled below. */
11400 unsigned long opcode;
11401 /* First, record an error for Case 3. */
11402 if (inst.operands[1].imm & mask
11403 && inst.operands[0].writeback)
11404 inst.error =
11405 _("having the base register in the register list when "
11406 "using write back is UNPREDICTABLE");
11407
11408 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
11409 : T_MNEM_ldr);
11410 inst.instruction = THUMB_OP16 (opcode);
11411 inst.instruction |= inst.operands[0].reg << 3;
11412 inst.instruction |= (ffs (inst.operands[1].imm)-1);
11413 narrow = TRUE;
11414 }
11415 }
11416 else if (inst.operands[0] .reg == REG_SP)
11417 {
11418 if (inst.operands[0].writeback)
11419 {
11420 inst.instruction =
11421 THUMB_OP16 (inst.instruction == T_MNEM_stmia
11422 ? T_MNEM_push : T_MNEM_pop);
11423 inst.instruction |= inst.operands[1].imm;
11424 narrow = TRUE;
11425 }
11426 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11427 {
11428 inst.instruction =
11429 THUMB_OP16 (inst.instruction == T_MNEM_stmia
11430 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
11431 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
11432 narrow = TRUE;
11433 }
11434 }
11435 }
11436
11437 if (!narrow)
11438 {
11439 if (inst.instruction < 0xffff)
11440 inst.instruction = THUMB_OP32 (inst.instruction);
11441
11442 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
11443 inst.operands[0].writeback);
11444 }
11445 }
11446 else
11447 {
11448 constraint (inst.operands[0].reg > 7
11449 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
11450 constraint (inst.instruction != T_MNEM_ldmia
11451 && inst.instruction != T_MNEM_stmia,
11452 _("Thumb-2 instruction only valid in unified syntax"));
11453 if (inst.instruction == T_MNEM_stmia)
11454 {
11455 if (!inst.operands[0].writeback)
11456 as_warn (_("this instruction will write back the base register"));
11457 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
11458 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
11459 as_warn (_("value stored for r%d is UNKNOWN"),
11460 inst.operands[0].reg);
11461 }
11462 else
11463 {
11464 if (!inst.operands[0].writeback
11465 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
11466 as_warn (_("this instruction will write back the base register"));
11467 else if (inst.operands[0].writeback
11468 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
11469 as_warn (_("this instruction will not write back the base register"));
11470 }
11471
11472 inst.instruction = THUMB_OP16 (inst.instruction);
11473 inst.instruction |= inst.operands[0].reg << 8;
11474 inst.instruction |= inst.operands[1].imm;
11475 }
11476}
11477
11478static void
11479do_t_ldrex (void)
11480{
11481 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
11482 || inst.operands[1].postind || inst.operands[1].writeback
11483 || inst.operands[1].immisreg || inst.operands[1].shifted
11484 || inst.operands[1].negative,
11485 BAD_ADDR_MODE);
11486
11487 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
11488
11489 inst.instruction |= inst.operands[0].reg << 12;
11490 inst.instruction |= inst.operands[1].reg << 16;
11491 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11492}
11493
11494static void
11495do_t_ldrexd (void)
11496{
11497 if (!inst.operands[1].present)
11498 {
11499 constraint (inst.operands[0].reg == REG_LR,
11500 _("r14 not allowed as first register "
11501 "when second register is omitted"));
11502 inst.operands[1].reg = inst.operands[0].reg + 1;
11503 }
11504 constraint (inst.operands[0].reg == inst.operands[1].reg,
11505 BAD_OVERLAP);
11506
11507 inst.instruction |= inst.operands[0].reg << 12;
11508 inst.instruction |= inst.operands[1].reg << 8;
11509 inst.instruction |= inst.operands[2].reg << 16;
11510}
11511
11512static void
11513do_t_ldst (void)
11514{
11515 unsigned long opcode;
11516 int Rn;
11517
11518 if (inst.operands[0].isreg
11519 && !inst.operands[0].preind
11520 && inst.operands[0].reg == REG_PC)
11521 set_it_insn_type_last ();
11522
11523 opcode = inst.instruction;
11524 if (unified_syntax)
11525 {
11526 if (!inst.operands[1].isreg)
11527 {
11528 if (opcode <= 0xffff)
11529 inst.instruction = THUMB_OP32 (opcode);
11530 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
11531 return;
11532 }
11533 if (inst.operands[1].isreg
11534 && !inst.operands[1].writeback
11535 && !inst.operands[1].shifted && !inst.operands[1].postind
11536 && !inst.operands[1].negative && inst.operands[0].reg <= 7
11537 && opcode <= 0xffff
11538 && inst.size_req != 4)
11539 {
11540 /* Insn may have a 16-bit form. */
11541 Rn = inst.operands[1].reg;
11542 if (inst.operands[1].immisreg)
11543 {
11544 inst.instruction = THUMB_OP16 (opcode);
11545 /* [Rn, Rik] */
11546 if (Rn <= 7 && inst.operands[1].imm <= 7)
11547 goto op16;
11548 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
11549 reject_bad_reg (inst.operands[1].imm);
11550 }
11551 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
11552 && opcode != T_MNEM_ldrsb)
11553 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
11554 || (Rn == REG_SP && opcode == T_MNEM_str))
11555 {
11556 /* [Rn, #const] */
11557 if (Rn > 7)
11558 {
11559 if (Rn == REG_PC)
11560 {
11561 if (inst.reloc.pc_rel)
11562 opcode = T_MNEM_ldr_pc2;
11563 else
11564 opcode = T_MNEM_ldr_pc;
11565 }
11566 else
11567 {
11568 if (opcode == T_MNEM_ldr)
11569 opcode = T_MNEM_ldr_sp;
11570 else
11571 opcode = T_MNEM_str_sp;
11572 }
11573 inst.instruction = inst.operands[0].reg << 8;
11574 }
11575 else
11576 {
11577 inst.instruction = inst.operands[0].reg;
11578 inst.instruction |= inst.operands[1].reg << 3;
11579 }
11580 inst.instruction |= THUMB_OP16 (opcode);
11581 if (inst.size_req == 2)
11582 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11583 else
11584 inst.relax = opcode;
11585 return;
11586 }
11587 }
11588 /* Definitely a 32-bit variant. */
11589
11590 /* Warning for Erratum 752419. */
11591 if (opcode == T_MNEM_ldr
11592 && inst.operands[0].reg == REG_SP
11593 && inst.operands[1].writeback == 1
11594 && !inst.operands[1].immisreg)
11595 {
11596 if (no_cpu_selected ()
11597 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
11598 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
11599 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
11600 as_warn (_("This instruction may be unpredictable "
11601 "if executed on M-profile cores "
11602 "with interrupts enabled."));
11603 }
11604
11605 /* Do some validations regarding addressing modes. */
11606 if (inst.operands[1].immisreg)
11607 reject_bad_reg (inst.operands[1].imm);
11608
11609 constraint (inst.operands[1].writeback == 1
11610 && inst.operands[0].reg == inst.operands[1].reg,
11611 BAD_OVERLAP);
11612
11613 inst.instruction = THUMB_OP32 (opcode);
11614 inst.instruction |= inst.operands[0].reg << 12;
11615 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
11616 check_ldr_r15_aligned ();
11617 return;
11618 }
11619
11620 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11621
11622 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
11623 {
11624 /* Only [Rn,Rm] is acceptable. */
11625 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
11626 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
11627 || inst.operands[1].postind || inst.operands[1].shifted
11628 || inst.operands[1].negative,
11629 _("Thumb does not support this addressing mode"));
11630 inst.instruction = THUMB_OP16 (inst.instruction);
11631 goto op16;
11632 }
11633
11634 inst.instruction = THUMB_OP16 (inst.instruction);
11635 if (!inst.operands[1].isreg)
11636 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
11637 return;
11638
11639 constraint (!inst.operands[1].preind
11640 || inst.operands[1].shifted
11641 || inst.operands[1].writeback,
11642 _("Thumb does not support this addressing mode"));
11643 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
11644 {
11645 constraint (inst.instruction & 0x0600,
11646 _("byte or halfword not valid for base register"));
11647 constraint (inst.operands[1].reg == REG_PC
11648 && !(inst.instruction & THUMB_LOAD_BIT),
11649 _("r15 based store not allowed"));
11650 constraint (inst.operands[1].immisreg,
11651 _("invalid base register for register offset"));
11652
11653 if (inst.operands[1].reg == REG_PC)
11654 inst.instruction = T_OPCODE_LDR_PC;
11655 else if (inst.instruction & THUMB_LOAD_BIT)
11656 inst.instruction = T_OPCODE_LDR_SP;
11657 else
11658 inst.instruction = T_OPCODE_STR_SP;
11659
11660 inst.instruction |= inst.operands[0].reg << 8;
11661 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11662 return;
11663 }
11664
11665 constraint (inst.operands[1].reg > 7, BAD_HIREG);
11666 if (!inst.operands[1].immisreg)
11667 {
11668 /* Immediate offset. */
11669 inst.instruction |= inst.operands[0].reg;
11670 inst.instruction |= inst.operands[1].reg << 3;
11671 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11672 return;
11673 }
11674
11675 /* Register offset. */
11676 constraint (inst.operands[1].imm > 7, BAD_HIREG);
11677 constraint (inst.operands[1].negative,
11678 _("Thumb does not support this addressing mode"));
11679
11680 op16:
11681 switch (inst.instruction)
11682 {
11683 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
11684 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
11685 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
11686 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
11687 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
11688 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
11689 case 0x5600 /* ldrsb */:
11690 case 0x5e00 /* ldrsh */: break;
11691 default: abort ();
11692 }
11693
11694 inst.instruction |= inst.operands[0].reg;
11695 inst.instruction |= inst.operands[1].reg << 3;
11696 inst.instruction |= inst.operands[1].imm << 6;
11697}
11698
11699static void
11700do_t_ldstd (void)
11701{
11702 if (!inst.operands[1].present)
11703 {
11704 inst.operands[1].reg = inst.operands[0].reg + 1;
11705 constraint (inst.operands[0].reg == REG_LR,
11706 _("r14 not allowed here"));
11707 constraint (inst.operands[0].reg == REG_R12,
11708 _("r12 not allowed here"));
11709 }
11710
11711 if (inst.operands[2].writeback
11712 && (inst.operands[0].reg == inst.operands[2].reg
11713 || inst.operands[1].reg == inst.operands[2].reg))
11714 as_warn (_("base register written back, and overlaps "
11715 "one of transfer registers"));
11716
11717 inst.instruction |= inst.operands[0].reg << 12;
11718 inst.instruction |= inst.operands[1].reg << 8;
11719 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
11720}
11721
11722static void
11723do_t_ldstt (void)
11724{
11725 inst.instruction |= inst.operands[0].reg << 12;
11726 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
11727}
11728
11729static void
11730do_t_mla (void)
11731{
11732 unsigned Rd, Rn, Rm, Ra;
11733
11734 Rd = inst.operands[0].reg;
11735 Rn = inst.operands[1].reg;
11736 Rm = inst.operands[2].reg;
11737 Ra = inst.operands[3].reg;
11738
11739 reject_bad_reg (Rd);
11740 reject_bad_reg (Rn);
11741 reject_bad_reg (Rm);
11742 reject_bad_reg (Ra);
11743
11744 inst.instruction |= Rd << 8;
11745 inst.instruction |= Rn << 16;
11746 inst.instruction |= Rm;
11747 inst.instruction |= Ra << 12;
11748}
11749
11750static void
11751do_t_mlal (void)
11752{
11753 unsigned RdLo, RdHi, Rn, Rm;
11754
11755 RdLo = inst.operands[0].reg;
11756 RdHi = inst.operands[1].reg;
11757 Rn = inst.operands[2].reg;
11758 Rm = inst.operands[3].reg;
11759
11760 reject_bad_reg (RdLo);
11761 reject_bad_reg (RdHi);
11762 reject_bad_reg (Rn);
11763 reject_bad_reg (Rm);
11764
11765 inst.instruction |= RdLo << 12;
11766 inst.instruction |= RdHi << 8;
11767 inst.instruction |= Rn << 16;
11768 inst.instruction |= Rm;
11769}
11770
11771static void
11772do_t_mov_cmp (void)
11773{
11774 unsigned Rn, Rm;
11775
11776 Rn = inst.operands[0].reg;
11777 Rm = inst.operands[1].reg;
11778
11779 if (Rn == REG_PC)
11780 set_it_insn_type_last ();
11781
11782 if (unified_syntax)
11783 {
11784 int r0off = (inst.instruction == T_MNEM_mov
11785 || inst.instruction == T_MNEM_movs) ? 8 : 16;
11786 unsigned long opcode;
11787 bfd_boolean narrow;
11788 bfd_boolean low_regs;
11789
11790 low_regs = (Rn <= 7 && Rm <= 7);
11791 opcode = inst.instruction;
11792 if (in_it_block ())
11793 narrow = opcode != T_MNEM_movs;
11794 else
11795 narrow = opcode != T_MNEM_movs || low_regs;
11796 if (inst.size_req == 4
11797 || inst.operands[1].shifted)
11798 narrow = FALSE;
11799
11800 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11801 if (opcode == T_MNEM_movs && inst.operands[1].isreg
11802 && !inst.operands[1].shifted
11803 && Rn == REG_PC
11804 && Rm == REG_LR)
11805 {
11806 inst.instruction = T2_SUBS_PC_LR;
11807 return;
11808 }
11809
11810 if (opcode == T_MNEM_cmp)
11811 {
11812 constraint (Rn == REG_PC, BAD_PC);
11813 if (narrow)
11814 {
11815 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11816 but valid. */
11817 warn_deprecated_sp (Rm);
11818 /* R15 was documented as a valid choice for Rm in ARMv6,
11819 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11820 tools reject R15, so we do too. */
11821 constraint (Rm == REG_PC, BAD_PC);
11822 }
11823 else
11824 reject_bad_reg (Rm);
11825 }
11826 else if (opcode == T_MNEM_mov
11827 || opcode == T_MNEM_movs)
11828 {
11829 if (inst.operands[1].isreg)
11830 {
11831 if (opcode == T_MNEM_movs)
11832 {
11833 reject_bad_reg (Rn);
11834 reject_bad_reg (Rm);
11835 }
11836 else if (narrow)
11837 {
11838 /* This is mov.n. */
11839 if ((Rn == REG_SP || Rn == REG_PC)
11840 && (Rm == REG_SP || Rm == REG_PC))
11841 {
11842 as_tsktsk (_("Use of r%u as a source register is "
11843 "deprecated when r%u is the destination "
11844 "register."), Rm, Rn);
11845 }
11846 }
11847 else
11848 {
11849 /* This is mov.w. */
11850 constraint (Rn == REG_PC, BAD_PC);
11851 constraint (Rm == REG_PC, BAD_PC);
11852 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11853 }
11854 }
11855 else
11856 reject_bad_reg (Rn);
11857 }
11858
11859 if (!inst.operands[1].isreg)
11860 {
11861 /* Immediate operand. */
11862 if (!in_it_block () && opcode == T_MNEM_mov)
11863 narrow = 0;
11864 if (low_regs && narrow)
11865 {
11866 inst.instruction = THUMB_OP16 (opcode);
11867 inst.instruction |= Rn << 8;
11868 if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11869 || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
11870 {
11871 if (inst.size_req == 2)
11872 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11873 else
11874 inst.relax = opcode;
11875 }
11876 }
11877 else
11878 {
11879 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11880 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
11881 THUMB1_RELOC_ONLY);
11882
11883 inst.instruction = THUMB_OP32 (inst.instruction);
11884 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11885 inst.instruction |= Rn << r0off;
11886 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11887 }
11888 }
11889 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11890 && (inst.instruction == T_MNEM_mov
11891 || inst.instruction == T_MNEM_movs))
11892 {
11893 /* Register shifts are encoded as separate shift instructions. */
11894 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11895
11896 if (in_it_block ())
11897 narrow = !flags;
11898 else
11899 narrow = flags;
11900
11901 if (inst.size_req == 4)
11902 narrow = FALSE;
11903
11904 if (!low_regs || inst.operands[1].imm > 7)
11905 narrow = FALSE;
11906
11907 if (Rn != Rm)
11908 narrow = FALSE;
11909
11910 switch (inst.operands[1].shift_kind)
11911 {
11912 case SHIFT_LSL:
11913 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11914 break;
11915 case SHIFT_ASR:
11916 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11917 break;
11918 case SHIFT_LSR:
11919 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11920 break;
11921 case SHIFT_ROR:
11922 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11923 break;
11924 default:
11925 abort ();
11926 }
11927
11928 inst.instruction = opcode;
11929 if (narrow)
11930 {
11931 inst.instruction |= Rn;
11932 inst.instruction |= inst.operands[1].imm << 3;
11933 }
11934 else
11935 {
11936 if (flags)
11937 inst.instruction |= CONDS_BIT;
11938
11939 inst.instruction |= Rn << 8;
11940 inst.instruction |= Rm << 16;
11941 inst.instruction |= inst.operands[1].imm;
11942 }
11943 }
11944 else if (!narrow)
11945 {
11946 /* Some mov with immediate shift have narrow variants.
11947 Register shifts are handled above. */
11948 if (low_regs && inst.operands[1].shifted
11949 && (inst.instruction == T_MNEM_mov
11950 || inst.instruction == T_MNEM_movs))
11951 {
11952 if (in_it_block ())
11953 narrow = (inst.instruction == T_MNEM_mov);
11954 else
11955 narrow = (inst.instruction == T_MNEM_movs);
11956 }
11957
11958 if (narrow)
11959 {
11960 switch (inst.operands[1].shift_kind)
11961 {
11962 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11963 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11964 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11965 default: narrow = FALSE; break;
11966 }
11967 }
11968
11969 if (narrow)
11970 {
11971 inst.instruction |= Rn;
11972 inst.instruction |= Rm << 3;
11973 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11974 }
11975 else
11976 {
11977 inst.instruction = THUMB_OP32 (inst.instruction);
11978 inst.instruction |= Rn << r0off;
11979 encode_thumb32_shifted_operand (1);
11980 }
11981 }
11982 else
11983 switch (inst.instruction)
11984 {
11985 case T_MNEM_mov:
11986 /* In v4t or v5t a move of two lowregs produces unpredictable
11987 results. Don't allow this. */
11988 if (low_regs)
11989 {
11990 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11991 "MOV Rd, Rs with two low registers is not "
11992 "permitted on this architecture");
11993 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11994 arm_ext_v6);
11995 }
11996
11997 inst.instruction = T_OPCODE_MOV_HR;
11998 inst.instruction |= (Rn & 0x8) << 4;
11999 inst.instruction |= (Rn & 0x7);
12000 inst.instruction |= Rm << 3;
12001 break;
12002
12003 case T_MNEM_movs:
12004 /* We know we have low registers at this point.
12005 Generate LSLS Rd, Rs, #0. */
12006 inst.instruction = T_OPCODE_LSL_I;
12007 inst.instruction |= Rn;
12008 inst.instruction |= Rm << 3;
12009 break;
12010
12011 case T_MNEM_cmp:
12012 if (low_regs)
12013 {
12014 inst.instruction = T_OPCODE_CMP_LR;
12015 inst.instruction |= Rn;
12016 inst.instruction |= Rm << 3;
12017 }
12018 else
12019 {
12020 inst.instruction = T_OPCODE_CMP_HR;
12021 inst.instruction |= (Rn & 0x8) << 4;
12022 inst.instruction |= (Rn & 0x7);
12023 inst.instruction |= Rm << 3;
12024 }
12025 break;
12026 }
12027 return;
12028 }
12029
12030 inst.instruction = THUMB_OP16 (inst.instruction);
12031
12032 /* PR 10443: Do not silently ignore shifted operands. */
12033 constraint (inst.operands[1].shifted,
12034 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12035
12036 if (inst.operands[1].isreg)
12037 {
12038 if (Rn < 8 && Rm < 8)
12039 {
12040 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12041 since a MOV instruction produces unpredictable results. */
12042 if (inst.instruction == T_OPCODE_MOV_I8)
12043 inst.instruction = T_OPCODE_ADD_I3;
12044 else
12045 inst.instruction = T_OPCODE_CMP_LR;
12046
12047 inst.instruction |= Rn;
12048 inst.instruction |= Rm << 3;
12049 }
12050 else
12051 {
12052 if (inst.instruction == T_OPCODE_MOV_I8)
12053 inst.instruction = T_OPCODE_MOV_HR;
12054 else
12055 inst.instruction = T_OPCODE_CMP_HR;
12056 do_t_cpy ();
12057 }
12058 }
12059 else
12060 {
12061 constraint (Rn > 7,
12062 _("only lo regs allowed with immediate"));
12063 inst.instruction |= Rn << 8;
12064 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
12065 }
12066}
12067
12068static void
12069do_t_mov16 (void)
12070{
12071 unsigned Rd;
12072 bfd_vma imm;
12073 bfd_boolean top;
12074
12075 top = (inst.instruction & 0x00800000) != 0;
12076 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
12077 {
12078 constraint (top, _(":lower16: not allowed this instruction"));
12079 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
12080 }
12081 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
12082 {
12083 constraint (!top, _(":upper16: not allowed this instruction"));
12084 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
12085 }
12086
12087 Rd = inst.operands[0].reg;
12088 reject_bad_reg (Rd);
12089
12090 inst.instruction |= Rd << 8;
12091 if (inst.reloc.type == BFD_RELOC_UNUSED)
12092 {
12093 imm = inst.reloc.exp.X_add_number;
12094 inst.instruction |= (imm & 0xf000) << 4;
12095 inst.instruction |= (imm & 0x0800) << 15;
12096 inst.instruction |= (imm & 0x0700) << 4;
12097 inst.instruction |= (imm & 0x00ff);
12098 }
12099}
12100
12101static void
12102do_t_mvn_tst (void)
12103{
12104 unsigned Rn, Rm;
12105
12106 Rn = inst.operands[0].reg;
12107 Rm = inst.operands[1].reg;
12108
12109 if (inst.instruction == T_MNEM_cmp
12110 || inst.instruction == T_MNEM_cmn)
12111 constraint (Rn == REG_PC, BAD_PC);
12112 else
12113 reject_bad_reg (Rn);
12114 reject_bad_reg (Rm);
12115
12116 if (unified_syntax)
12117 {
12118 int r0off = (inst.instruction == T_MNEM_mvn
12119 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
12120 bfd_boolean narrow;
12121
12122 if (inst.size_req == 4
12123 || inst.instruction > 0xffff
12124 || inst.operands[1].shifted
12125 || Rn > 7 || Rm > 7)
12126 narrow = FALSE;
12127 else if (inst.instruction == T_MNEM_cmn
12128 || inst.instruction == T_MNEM_tst)
12129 narrow = TRUE;
12130 else if (THUMB_SETS_FLAGS (inst.instruction))
12131 narrow = !in_it_block ();
12132 else
12133 narrow = in_it_block ();
12134
12135 if (!inst.operands[1].isreg)
12136 {
12137 /* For an immediate, we always generate a 32-bit opcode;
12138 section relaxation will shrink it later if possible. */
12139 if (inst.instruction < 0xffff)
12140 inst.instruction = THUMB_OP32 (inst.instruction);
12141 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12142 inst.instruction |= Rn << r0off;
12143 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12144 }
12145 else
12146 {
12147 /* See if we can do this with a 16-bit instruction. */
12148 if (narrow)
12149 {
12150 inst.instruction = THUMB_OP16 (inst.instruction);
12151 inst.instruction |= Rn;
12152 inst.instruction |= Rm << 3;
12153 }
12154 else
12155 {
12156 constraint (inst.operands[1].shifted
12157 && inst.operands[1].immisreg,
12158 _("shift must be constant"));
12159 if (inst.instruction < 0xffff)
12160 inst.instruction = THUMB_OP32 (inst.instruction);
12161 inst.instruction |= Rn << r0off;
12162 encode_thumb32_shifted_operand (1);
12163 }
12164 }
12165 }
12166 else
12167 {
12168 constraint (inst.instruction > 0xffff
12169 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
12170 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
12171 _("unshifted register required"));
12172 constraint (Rn > 7 || Rm > 7,
12173 BAD_HIREG);
12174
12175 inst.instruction = THUMB_OP16 (inst.instruction);
12176 inst.instruction |= Rn;
12177 inst.instruction |= Rm << 3;
12178 }
12179}
12180
12181static void
12182do_t_mrs (void)
12183{
12184 unsigned Rd;
12185
12186 if (do_vfp_nsyn_mrs () == SUCCESS)
12187 return;
12188
12189 Rd = inst.operands[0].reg;
12190 reject_bad_reg (Rd);
12191 inst.instruction |= Rd << 8;
12192
12193 if (inst.operands[1].isreg)
12194 {
12195 unsigned br = inst.operands[1].reg;
12196 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
12197 as_bad (_("bad register for mrs"));
12198
12199 inst.instruction |= br & (0xf << 16);
12200 inst.instruction |= (br & 0x300) >> 4;
12201 inst.instruction |= (br & SPSR_BIT) >> 2;
12202 }
12203 else
12204 {
12205 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
12206
12207 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
12208 {
12209 /* PR gas/12698: The constraint is only applied for m_profile.
12210 If the user has specified -march=all, we want to ignore it as
12211 we are building for any CPU type, including non-m variants. */
12212 bfd_boolean m_profile =
12213 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
12214 constraint ((flags != 0) && m_profile, _("selected processor does "
12215 "not support requested special purpose register"));
12216 }
12217 else
12218 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12219 devices). */
12220 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
12221 _("'APSR', 'CPSR' or 'SPSR' expected"));
12222
12223 inst.instruction |= (flags & SPSR_BIT) >> 2;
12224 inst.instruction |= inst.operands[1].imm & 0xff;
12225 inst.instruction |= 0xf0000;
12226 }
12227}
12228
12229static void
12230do_t_msr (void)
12231{
12232 int flags;
12233 unsigned Rn;
12234
12235 if (do_vfp_nsyn_msr () == SUCCESS)
12236 return;
12237
12238 constraint (!inst.operands[1].isreg,
12239 _("Thumb encoding does not support an immediate here"));
12240
12241 if (inst.operands[0].isreg)
12242 flags = (int)(inst.operands[0].reg);
12243 else
12244 flags = inst.operands[0].imm;
12245
12246 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
12247 {
12248 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
12249
12250 /* PR gas/12698: The constraint is only applied for m_profile.
12251 If the user has specified -march=all, we want to ignore it as
12252 we are building for any CPU type, including non-m variants. */
12253 bfd_boolean m_profile =
12254 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
12255 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
12256 && (bits & ~(PSR_s | PSR_f)) != 0)
12257 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
12258 && bits != PSR_f)) && m_profile,
12259 _("selected processor does not support requested special "
12260 "purpose register"));
12261 }
12262 else
12263 constraint ((flags & 0xff) != 0, _("selected processor does not support "
12264 "requested special purpose register"));
12265
12266 Rn = inst.operands[1].reg;
12267 reject_bad_reg (Rn);
12268
12269 inst.instruction |= (flags & SPSR_BIT) >> 2;
12270 inst.instruction |= (flags & 0xf0000) >> 8;
12271 inst.instruction |= (flags & 0x300) >> 4;
12272 inst.instruction |= (flags & 0xff);
12273 inst.instruction |= Rn << 16;
12274}
12275
12276static void
12277do_t_mul (void)
12278{
12279 bfd_boolean narrow;
12280 unsigned Rd, Rn, Rm;
12281
12282 if (!inst.operands[2].present)
12283 inst.operands[2].reg = inst.operands[0].reg;
12284
12285 Rd = inst.operands[0].reg;
12286 Rn = inst.operands[1].reg;
12287 Rm = inst.operands[2].reg;
12288
12289 if (unified_syntax)
12290 {
12291 if (inst.size_req == 4
12292 || (Rd != Rn
12293 && Rd != Rm)
12294 || Rn > 7
12295 || Rm > 7)
12296 narrow = FALSE;
12297 else if (inst.instruction == T_MNEM_muls)
12298 narrow = !in_it_block ();
12299 else
12300 narrow = in_it_block ();
12301 }
12302 else
12303 {
12304 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
12305 constraint (Rn > 7 || Rm > 7,
12306 BAD_HIREG);
12307 narrow = TRUE;
12308 }
12309
12310 if (narrow)
12311 {
12312 /* 16-bit MULS/Conditional MUL. */
12313 inst.instruction = THUMB_OP16 (inst.instruction);
12314 inst.instruction |= Rd;
12315
12316 if (Rd == Rn)
12317 inst.instruction |= Rm << 3;
12318 else if (Rd == Rm)
12319 inst.instruction |= Rn << 3;
12320 else
12321 constraint (1, _("dest must overlap one source register"));
12322 }
12323 else
12324 {
12325 constraint (inst.instruction != T_MNEM_mul,
12326 _("Thumb-2 MUL must not set flags"));
12327 /* 32-bit MUL. */
12328 inst.instruction = THUMB_OP32 (inst.instruction);
12329 inst.instruction |= Rd << 8;
12330 inst.instruction |= Rn << 16;
12331 inst.instruction |= Rm << 0;
12332
12333 reject_bad_reg (Rd);
12334 reject_bad_reg (Rn);
12335 reject_bad_reg (Rm);
12336 }
12337}
12338
12339static void
12340do_t_mull (void)
12341{
12342 unsigned RdLo, RdHi, Rn, Rm;
12343
12344 RdLo = inst.operands[0].reg;
12345 RdHi = inst.operands[1].reg;
12346 Rn = inst.operands[2].reg;
12347 Rm = inst.operands[3].reg;
12348
12349 reject_bad_reg (RdLo);
12350 reject_bad_reg (RdHi);
12351 reject_bad_reg (Rn);
12352 reject_bad_reg (Rm);
12353
12354 inst.instruction |= RdLo << 12;
12355 inst.instruction |= RdHi << 8;
12356 inst.instruction |= Rn << 16;
12357 inst.instruction |= Rm;
12358
12359 if (RdLo == RdHi)
12360 as_tsktsk (_("rdhi and rdlo must be different"));
12361}
12362
12363static void
12364do_t_nop (void)
12365{
12366 set_it_insn_type (NEUTRAL_IT_INSN);
12367
12368 if (unified_syntax)
12369 {
12370 if (inst.size_req == 4 || inst.operands[0].imm > 15)
12371 {
12372 inst.instruction = THUMB_OP32 (inst.instruction);
12373 inst.instruction |= inst.operands[0].imm;
12374 }
12375 else
12376 {
12377 /* PR9722: Check for Thumb2 availability before
12378 generating a thumb2 nop instruction. */
12379 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
12380 {
12381 inst.instruction = THUMB_OP16 (inst.instruction);
12382 inst.instruction |= inst.operands[0].imm << 4;
12383 }
12384 else
12385 inst.instruction = 0x46c0;
12386 }
12387 }
12388 else
12389 {
12390 constraint (inst.operands[0].present,
12391 _("Thumb does not support NOP with hints"));
12392 inst.instruction = 0x46c0;
12393 }
12394}
12395
12396static void
12397do_t_neg (void)
12398{
12399 if (unified_syntax)
12400 {
12401 bfd_boolean narrow;
12402
12403 if (THUMB_SETS_FLAGS (inst.instruction))
12404 narrow = !in_it_block ();
12405 else
12406 narrow = in_it_block ();
12407 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12408 narrow = FALSE;
12409 if (inst.size_req == 4)
12410 narrow = FALSE;
12411
12412 if (!narrow)
12413 {
12414 inst.instruction = THUMB_OP32 (inst.instruction);
12415 inst.instruction |= inst.operands[0].reg << 8;
12416 inst.instruction |= inst.operands[1].reg << 16;
12417 }
12418 else
12419 {
12420 inst.instruction = THUMB_OP16 (inst.instruction);
12421 inst.instruction |= inst.operands[0].reg;
12422 inst.instruction |= inst.operands[1].reg << 3;
12423 }
12424 }
12425 else
12426 {
12427 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
12428 BAD_HIREG);
12429 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12430
12431 inst.instruction = THUMB_OP16 (inst.instruction);
12432 inst.instruction |= inst.operands[0].reg;
12433 inst.instruction |= inst.operands[1].reg << 3;
12434 }
12435}
12436
12437static void
12438do_t_orn (void)
12439{
12440 unsigned Rd, Rn;
12441
12442 Rd = inst.operands[0].reg;
12443 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
12444
12445 reject_bad_reg (Rd);
12446 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12447 reject_bad_reg (Rn);
12448
12449 inst.instruction |= Rd << 8;
12450 inst.instruction |= Rn << 16;
12451
12452 if (!inst.operands[2].isreg)
12453 {
12454 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12455 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12456 }
12457 else
12458 {
12459 unsigned Rm;
12460
12461 Rm = inst.operands[2].reg;
12462 reject_bad_reg (Rm);
12463
12464 constraint (inst.operands[2].shifted
12465 && inst.operands[2].immisreg,
12466 _("shift must be constant"));
12467 encode_thumb32_shifted_operand (2);
12468 }
12469}
12470
12471static void
12472do_t_pkhbt (void)
12473{
12474 unsigned Rd, Rn, Rm;
12475
12476 Rd = inst.operands[0].reg;
12477 Rn = inst.operands[1].reg;
12478 Rm = inst.operands[2].reg;
12479
12480 reject_bad_reg (Rd);
12481 reject_bad_reg (Rn);
12482 reject_bad_reg (Rm);
12483
12484 inst.instruction |= Rd << 8;
12485 inst.instruction |= Rn << 16;
12486 inst.instruction |= Rm;
12487 if (inst.operands[3].present)
12488 {
12489 unsigned int val = inst.reloc.exp.X_add_number;
12490 constraint (inst.reloc.exp.X_op != O_constant,
12491 _("expression too complex"));
12492 inst.instruction |= (val & 0x1c) << 10;
12493 inst.instruction |= (val & 0x03) << 6;
12494 }
12495}
12496
12497static void
12498do_t_pkhtb (void)
12499{
12500 if (!inst.operands[3].present)
12501 {
12502 unsigned Rtmp;
12503
12504 inst.instruction &= ~0x00000020;
12505
12506 /* PR 10168. Swap the Rm and Rn registers. */
12507 Rtmp = inst.operands[1].reg;
12508 inst.operands[1].reg = inst.operands[2].reg;
12509 inst.operands[2].reg = Rtmp;
12510 }
12511 do_t_pkhbt ();
12512}
12513
12514static void
12515do_t_pld (void)
12516{
12517 if (inst.operands[0].immisreg)
12518 reject_bad_reg (inst.operands[0].imm);
12519
12520 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
12521}
12522
12523static void
12524do_t_push_pop (void)
12525{
12526 unsigned mask;
12527
12528 constraint (inst.operands[0].writeback,
12529 _("push/pop do not support {reglist}^"));
12530 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
12531 _("expression too complex"));
12532
12533 mask = inst.operands[0].imm;
12534 if (inst.size_req != 4 && (mask & ~0xff) == 0)
12535 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
12536 else if (inst.size_req != 4
12537 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
12538 ? REG_LR : REG_PC)))
12539 {
12540 inst.instruction = THUMB_OP16 (inst.instruction);
12541 inst.instruction |= THUMB_PP_PC_LR;
12542 inst.instruction |= mask & 0xff;
12543 }
12544 else if (unified_syntax)
12545 {
12546 inst.instruction = THUMB_OP32 (inst.instruction);
12547 encode_thumb2_ldmstm (13, mask, TRUE);
12548 }
12549 else
12550 {
12551 inst.error = _("invalid register list to push/pop instruction");
12552 return;
12553 }
12554}
12555
12556static void
12557do_t_rbit (void)
12558{
12559 unsigned Rd, Rm;
12560
12561 Rd = inst.operands[0].reg;
12562 Rm = inst.operands[1].reg;
12563
12564 reject_bad_reg (Rd);
12565 reject_bad_reg (Rm);
12566
12567 inst.instruction |= Rd << 8;
12568 inst.instruction |= Rm << 16;
12569 inst.instruction |= Rm;
12570}
12571
12572static void
12573do_t_rev (void)
12574{
12575 unsigned Rd, Rm;
12576
12577 Rd = inst.operands[0].reg;
12578 Rm = inst.operands[1].reg;
12579
12580 reject_bad_reg (Rd);
12581 reject_bad_reg (Rm);
12582
12583 if (Rd <= 7 && Rm <= 7
12584 && inst.size_req != 4)
12585 {
12586 inst.instruction = THUMB_OP16 (inst.instruction);
12587 inst.instruction |= Rd;
12588 inst.instruction |= Rm << 3;
12589 }
12590 else if (unified_syntax)
12591 {
12592 inst.instruction = THUMB_OP32 (inst.instruction);
12593 inst.instruction |= Rd << 8;
12594 inst.instruction |= Rm << 16;
12595 inst.instruction |= Rm;
12596 }
12597 else
12598 inst.error = BAD_HIREG;
12599}
12600
12601static void
12602do_t_rrx (void)
12603{
12604 unsigned Rd, Rm;
12605
12606 Rd = inst.operands[0].reg;
12607 Rm = inst.operands[1].reg;
12608
12609 reject_bad_reg (Rd);
12610 reject_bad_reg (Rm);
12611
12612 inst.instruction |= Rd << 8;
12613 inst.instruction |= Rm;
12614}
12615
12616static void
12617do_t_rsb (void)
12618{
12619 unsigned Rd, Rs;
12620
12621 Rd = inst.operands[0].reg;
12622 Rs = (inst.operands[1].present
12623 ? inst.operands[1].reg /* Rd, Rs, foo */
12624 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
12625
12626 reject_bad_reg (Rd);
12627 reject_bad_reg (Rs);
12628 if (inst.operands[2].isreg)
12629 reject_bad_reg (inst.operands[2].reg);
12630
12631 inst.instruction |= Rd << 8;
12632 inst.instruction |= Rs << 16;
12633 if (!inst.operands[2].isreg)
12634 {
12635 bfd_boolean narrow;
12636
12637 if ((inst.instruction & 0x00100000) != 0)
12638 narrow = !in_it_block ();
12639 else
12640 narrow = in_it_block ();
12641
12642 if (Rd > 7 || Rs > 7)
12643 narrow = FALSE;
12644
12645 if (inst.size_req == 4 || !unified_syntax)
12646 narrow = FALSE;
12647
12648 if (inst.reloc.exp.X_op != O_constant
12649 || inst.reloc.exp.X_add_number != 0)
12650 narrow = FALSE;
12651
12652 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12653 relaxation, but it doesn't seem worth the hassle. */
12654 if (narrow)
12655 {
12656 inst.reloc.type = BFD_RELOC_UNUSED;
12657 inst.instruction = THUMB_OP16 (T_MNEM_negs);
12658 inst.instruction |= Rs << 3;
12659 inst.instruction |= Rd;
12660 }
12661 else
12662 {
12663 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12664 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12665 }
12666 }
12667 else
12668 encode_thumb32_shifted_operand (2);
12669}
12670
12671static void
12672do_t_setend (void)
12673{
12674 if (warn_on_deprecated
12675 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12676 as_tsktsk (_("setend use is deprecated for ARMv8"));
12677
12678 set_it_insn_type (OUTSIDE_IT_INSN);
12679 if (inst.operands[0].imm)
12680 inst.instruction |= 0x8;
12681}
12682
12683static void
12684do_t_shift (void)
12685{
12686 if (!inst.operands[1].present)
12687 inst.operands[1].reg = inst.operands[0].reg;
12688
12689 if (unified_syntax)
12690 {
12691 bfd_boolean narrow;
12692 int shift_kind;
12693
12694 switch (inst.instruction)
12695 {
12696 case T_MNEM_asr:
12697 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
12698 case T_MNEM_lsl:
12699 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
12700 case T_MNEM_lsr:
12701 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
12702 case T_MNEM_ror:
12703 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
12704 default: abort ();
12705 }
12706
12707 if (THUMB_SETS_FLAGS (inst.instruction))
12708 narrow = !in_it_block ();
12709 else
12710 narrow = in_it_block ();
12711 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12712 narrow = FALSE;
12713 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
12714 narrow = FALSE;
12715 if (inst.operands[2].isreg
12716 && (inst.operands[1].reg != inst.operands[0].reg
12717 || inst.operands[2].reg > 7))
12718 narrow = FALSE;
12719 if (inst.size_req == 4)
12720 narrow = FALSE;
12721
12722 reject_bad_reg (inst.operands[0].reg);
12723 reject_bad_reg (inst.operands[1].reg);
12724
12725 if (!narrow)
12726 {
12727 if (inst.operands[2].isreg)
12728 {
12729 reject_bad_reg (inst.operands[2].reg);
12730 inst.instruction = THUMB_OP32 (inst.instruction);
12731 inst.instruction |= inst.operands[0].reg << 8;
12732 inst.instruction |= inst.operands[1].reg << 16;
12733 inst.instruction |= inst.operands[2].reg;
12734
12735 /* PR 12854: Error on extraneous shifts. */
12736 constraint (inst.operands[2].shifted,
12737 _("extraneous shift as part of operand to shift insn"));
12738 }
12739 else
12740 {
12741 inst.operands[1].shifted = 1;
12742 inst.operands[1].shift_kind = shift_kind;
12743 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
12744 ? T_MNEM_movs : T_MNEM_mov);
12745 inst.instruction |= inst.operands[0].reg << 8;
12746 encode_thumb32_shifted_operand (1);
12747 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12748 inst.reloc.type = BFD_RELOC_UNUSED;
12749 }
12750 }
12751 else
12752 {
12753 if (inst.operands[2].isreg)
12754 {
12755 switch (shift_kind)
12756 {
12757 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
12758 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
12759 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
12760 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
12761 default: abort ();
12762 }
12763
12764 inst.instruction |= inst.operands[0].reg;
12765 inst.instruction |= inst.operands[2].reg << 3;
12766
12767 /* PR 12854: Error on extraneous shifts. */
12768 constraint (inst.operands[2].shifted,
12769 _("extraneous shift as part of operand to shift insn"));
12770 }
12771 else
12772 {
12773 switch (shift_kind)
12774 {
12775 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12776 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12777 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12778 default: abort ();
12779 }
12780 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12781 inst.instruction |= inst.operands[0].reg;
12782 inst.instruction |= inst.operands[1].reg << 3;
12783 }
12784 }
12785 }
12786 else
12787 {
12788 constraint (inst.operands[0].reg > 7
12789 || inst.operands[1].reg > 7, BAD_HIREG);
12790 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12791
12792 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
12793 {
12794 constraint (inst.operands[2].reg > 7, BAD_HIREG);
12795 constraint (inst.operands[0].reg != inst.operands[1].reg,
12796 _("source1 and dest must be same register"));
12797
12798 switch (inst.instruction)
12799 {
12800 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
12801 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
12802 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
12803 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
12804 default: abort ();
12805 }
12806
12807 inst.instruction |= inst.operands[0].reg;
12808 inst.instruction |= inst.operands[2].reg << 3;
12809
12810 /* PR 12854: Error on extraneous shifts. */
12811 constraint (inst.operands[2].shifted,
12812 _("extraneous shift as part of operand to shift insn"));
12813 }
12814 else
12815 {
12816 switch (inst.instruction)
12817 {
12818 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
12819 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
12820 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
12821 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
12822 default: abort ();
12823 }
12824 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12825 inst.instruction |= inst.operands[0].reg;
12826 inst.instruction |= inst.operands[1].reg << 3;
12827 }
12828 }
12829}
12830
12831static void
12832do_t_simd (void)
12833{
12834 unsigned Rd, Rn, Rm;
12835
12836 Rd = inst.operands[0].reg;
12837 Rn = inst.operands[1].reg;
12838 Rm = inst.operands[2].reg;
12839
12840 reject_bad_reg (Rd);
12841 reject_bad_reg (Rn);
12842 reject_bad_reg (Rm);
12843
12844 inst.instruction |= Rd << 8;
12845 inst.instruction |= Rn << 16;
12846 inst.instruction |= Rm;
12847}
12848
12849static void
12850do_t_simd2 (void)
12851{
12852 unsigned Rd, Rn, Rm;
12853
12854 Rd = inst.operands[0].reg;
12855 Rm = inst.operands[1].reg;
12856 Rn = inst.operands[2].reg;
12857
12858 reject_bad_reg (Rd);
12859 reject_bad_reg (Rn);
12860 reject_bad_reg (Rm);
12861
12862 inst.instruction |= Rd << 8;
12863 inst.instruction |= Rn << 16;
12864 inst.instruction |= Rm;
12865}
12866
12867static void
12868do_t_smc (void)
12869{
12870 unsigned int value = inst.reloc.exp.X_add_number;
12871 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12872 _("SMC is not permitted on this architecture"));
12873 constraint (inst.reloc.exp.X_op != O_constant,
12874 _("expression too complex"));
12875 inst.reloc.type = BFD_RELOC_UNUSED;
12876 inst.instruction |= (value & 0xf000) >> 12;
12877 inst.instruction |= (value & 0x0ff0);
12878 inst.instruction |= (value & 0x000f) << 16;
12879 /* PR gas/15623: SMC instructions must be last in an IT block. */
12880 set_it_insn_type_last ();
12881}
12882
12883static void
12884do_t_hvc (void)
12885{
12886 unsigned int value = inst.reloc.exp.X_add_number;
12887
12888 inst.reloc.type = BFD_RELOC_UNUSED;
12889 inst.instruction |= (value & 0x0fff);
12890 inst.instruction |= (value & 0xf000) << 4;
12891}
12892
12893static void
12894do_t_ssat_usat (int bias)
12895{
12896 unsigned Rd, Rn;
12897
12898 Rd = inst.operands[0].reg;
12899 Rn = inst.operands[2].reg;
12900
12901 reject_bad_reg (Rd);
12902 reject_bad_reg (Rn);
12903
12904 inst.instruction |= Rd << 8;
12905 inst.instruction |= inst.operands[1].imm - bias;
12906 inst.instruction |= Rn << 16;
12907
12908 if (inst.operands[3].present)
12909 {
12910 offsetT shift_amount = inst.reloc.exp.X_add_number;
12911
12912 inst.reloc.type = BFD_RELOC_UNUSED;
12913
12914 constraint (inst.reloc.exp.X_op != O_constant,
12915 _("expression too complex"));
12916
12917 if (shift_amount != 0)
12918 {
12919 constraint (shift_amount > 31,
12920 _("shift expression is too large"));
12921
12922 if (inst.operands[3].shift_kind == SHIFT_ASR)
12923 inst.instruction |= 0x00200000; /* sh bit. */
12924
12925 inst.instruction |= (shift_amount & 0x1c) << 10;
12926 inst.instruction |= (shift_amount & 0x03) << 6;
12927 }
12928 }
12929}
12930
12931static void
12932do_t_ssat (void)
12933{
12934 do_t_ssat_usat (1);
12935}
12936
12937static void
12938do_t_ssat16 (void)
12939{
12940 unsigned Rd, Rn;
12941
12942 Rd = inst.operands[0].reg;
12943 Rn = inst.operands[2].reg;
12944
12945 reject_bad_reg (Rd);
12946 reject_bad_reg (Rn);
12947
12948 inst.instruction |= Rd << 8;
12949 inst.instruction |= inst.operands[1].imm - 1;
12950 inst.instruction |= Rn << 16;
12951}
12952
12953static void
12954do_t_strex (void)
12955{
12956 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12957 || inst.operands[2].postind || inst.operands[2].writeback
12958 || inst.operands[2].immisreg || inst.operands[2].shifted
12959 || inst.operands[2].negative,
12960 BAD_ADDR_MODE);
12961
12962 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12963
12964 inst.instruction |= inst.operands[0].reg << 8;
12965 inst.instruction |= inst.operands[1].reg << 12;
12966 inst.instruction |= inst.operands[2].reg << 16;
12967 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12968}
12969
12970static void
12971do_t_strexd (void)
12972{
12973 if (!inst.operands[2].present)
12974 inst.operands[2].reg = inst.operands[1].reg + 1;
12975
12976 constraint (inst.operands[0].reg == inst.operands[1].reg
12977 || inst.operands[0].reg == inst.operands[2].reg
12978 || inst.operands[0].reg == inst.operands[3].reg,
12979 BAD_OVERLAP);
12980
12981 inst.instruction |= inst.operands[0].reg;
12982 inst.instruction |= inst.operands[1].reg << 12;
12983 inst.instruction |= inst.operands[2].reg << 8;
12984 inst.instruction |= inst.operands[3].reg << 16;
12985}
12986
12987static void
12988do_t_sxtah (void)
12989{
12990 unsigned Rd, Rn, Rm;
12991
12992 Rd = inst.operands[0].reg;
12993 Rn = inst.operands[1].reg;
12994 Rm = inst.operands[2].reg;
12995
12996 reject_bad_reg (Rd);
12997 reject_bad_reg (Rn);
12998 reject_bad_reg (Rm);
12999
13000 inst.instruction |= Rd << 8;
13001 inst.instruction |= Rn << 16;
13002 inst.instruction |= Rm;
13003 inst.instruction |= inst.operands[3].imm << 4;
13004}
13005
13006static void
13007do_t_sxth (void)
13008{
13009 unsigned Rd, Rm;
13010
13011 Rd = inst.operands[0].reg;
13012 Rm = inst.operands[1].reg;
13013
13014 reject_bad_reg (Rd);
13015 reject_bad_reg (Rm);
13016
13017 if (inst.instruction <= 0xffff
13018 && inst.size_req != 4
13019 && Rd <= 7 && Rm <= 7
13020 && (!inst.operands[2].present || inst.operands[2].imm == 0))
13021 {
13022 inst.instruction = THUMB_OP16 (inst.instruction);
13023 inst.instruction |= Rd;
13024 inst.instruction |= Rm << 3;
13025 }
13026 else if (unified_syntax)
13027 {
13028 if (inst.instruction <= 0xffff)
13029 inst.instruction = THUMB_OP32 (inst.instruction);
13030 inst.instruction |= Rd << 8;
13031 inst.instruction |= Rm;
13032 inst.instruction |= inst.operands[2].imm << 4;
13033 }
13034 else
13035 {
13036 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
13037 _("Thumb encoding does not support rotation"));
13038 constraint (1, BAD_HIREG);
13039 }
13040}
13041
13042static void
13043do_t_swi (void)
13044{
13045 /* We have to do the following check manually as ARM_EXT_OS only applies
13046 to ARM_EXT_V6M. */
13047 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
13048 {
13049 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
13050 /* This only applies to the v6m howver, not later architectures. */
13051 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
13052 as_bad (_("SVC is not permitted on this architecture"));
13053 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
13054 }
13055
13056 inst.reloc.type = BFD_RELOC_ARM_SWI;
13057}
13058
13059static void
13060do_t_tb (void)
13061{
13062 unsigned Rn, Rm;
13063 int half;
13064
13065 half = (inst.instruction & 0x10) != 0;
13066 set_it_insn_type_last ();
13067 constraint (inst.operands[0].immisreg,
13068 _("instruction requires register index"));
13069
13070 Rn = inst.operands[0].reg;
13071 Rm = inst.operands[0].imm;
13072
13073 constraint (Rn == REG_SP, BAD_SP);
13074 reject_bad_reg (Rm);
13075
13076 constraint (!half && inst.operands[0].shifted,
13077 _("instruction does not allow shifted index"));
13078 inst.instruction |= (Rn << 16) | Rm;
13079}
13080
13081static void
13082do_t_udf (void)
13083{
13084 if (!inst.operands[0].present)
13085 inst.operands[0].imm = 0;
13086
13087 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
13088 {
13089 constraint (inst.size_req == 2,
13090 _("immediate value out of range"));
13091 inst.instruction = THUMB_OP32 (inst.instruction);
13092 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
13093 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
13094 }
13095 else
13096 {
13097 inst.instruction = THUMB_OP16 (inst.instruction);
13098 inst.instruction |= inst.operands[0].imm;
13099 }
13100
13101 set_it_insn_type (NEUTRAL_IT_INSN);
13102}
13103
13104
13105static void
13106do_t_usat (void)
13107{
13108 do_t_ssat_usat (0);
13109}
13110
13111static void
13112do_t_usat16 (void)
13113{
13114 unsigned Rd, Rn;
13115
13116 Rd = inst.operands[0].reg;
13117 Rn = inst.operands[2].reg;
13118
13119 reject_bad_reg (Rd);
13120 reject_bad_reg (Rn);
13121
13122 inst.instruction |= Rd << 8;
13123 inst.instruction |= inst.operands[1].imm;
13124 inst.instruction |= Rn << 16;
13125}
13126
13127/* Neon instruction encoder helpers. */
13128
13129/* Encodings for the different types for various Neon opcodes. */
13130
13131/* An "invalid" code for the following tables. */
13132#define N_INV -1u
13133
13134struct neon_tab_entry
13135{
13136 unsigned integer;
13137 unsigned float_or_poly;
13138 unsigned scalar_or_imm;
13139};
13140
13141/* Map overloaded Neon opcodes to their respective encodings. */
13142#define NEON_ENC_TAB \
13143 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13144 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13145 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13146 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13147 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13148 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13149 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13150 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13151 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13152 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13153 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13154 /* Register variants of the following two instructions are encoded as
13155 vcge / vcgt with the operands reversed. */ \
13156 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13157 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13158 X(vfma, N_INV, 0x0000c10, N_INV), \
13159 X(vfms, N_INV, 0x0200c10, N_INV), \
13160 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13161 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13162 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13163 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13164 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13165 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13166 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13167 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13168 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13169 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13170 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13171 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13172 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13173 X(vshl, 0x0000400, N_INV, 0x0800510), \
13174 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13175 X(vand, 0x0000110, N_INV, 0x0800030), \
13176 X(vbic, 0x0100110, N_INV, 0x0800030), \
13177 X(veor, 0x1000110, N_INV, N_INV), \
13178 X(vorn, 0x0300110, N_INV, 0x0800010), \
13179 X(vorr, 0x0200110, N_INV, 0x0800010), \
13180 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13181 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13182 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13183 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13184 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13185 X(vst1, 0x0000000, 0x0800000, N_INV), \
13186 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13187 X(vst2, 0x0000100, 0x0800100, N_INV), \
13188 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13189 X(vst3, 0x0000200, 0x0800200, N_INV), \
13190 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13191 X(vst4, 0x0000300, 0x0800300, N_INV), \
13192 X(vmovn, 0x1b20200, N_INV, N_INV), \
13193 X(vtrn, 0x1b20080, N_INV, N_INV), \
13194 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13195 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13196 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13197 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13198 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13199 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13200 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13201 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13202 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13203 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13204 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13205 X(vseleq, 0xe000a00, N_INV, N_INV), \
13206 X(vselvs, 0xe100a00, N_INV, N_INV), \
13207 X(vselge, 0xe200a00, N_INV, N_INV), \
13208 X(vselgt, 0xe300a00, N_INV, N_INV), \
13209 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13210 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13211 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13212 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13213 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13214 X(aes, 0x3b00300, N_INV, N_INV), \
13215 X(sha3op, 0x2000c00, N_INV, N_INV), \
13216 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13217 X(sha2op, 0x3ba0380, N_INV, N_INV)
13218
13219enum neon_opc
13220{
13221#define X(OPC,I,F,S) N_MNEM_##OPC
13222NEON_ENC_TAB
13223#undef X
13224};
13225
13226static const struct neon_tab_entry neon_enc_tab[] =
13227{
13228#define X(OPC,I,F,S) { (I), (F), (S) }
13229NEON_ENC_TAB
13230#undef X
13231};
13232
13233/* Do not use these macros; instead, use NEON_ENCODE defined below. */
13234#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13235#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13236#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13237#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13238#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13239#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13240#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13241#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13242#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13243#define NEON_ENC_SINGLE_(X) \
13244 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13245#define NEON_ENC_DOUBLE_(X) \
13246 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13247#define NEON_ENC_FPV8_(X) \
13248 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13249
13250#define NEON_ENCODE(type, inst) \
13251 do \
13252 { \
13253 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13254 inst.is_neon = 1; \
13255 } \
13256 while (0)
13257
13258#define check_neon_suffixes \
13259 do \
13260 { \
13261 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13262 { \
13263 as_bad (_("invalid neon suffix for non neon instruction")); \
13264 return; \
13265 } \
13266 } \
13267 while (0)
13268
13269/* Define shapes for instruction operands. The following mnemonic characters
13270 are used in this table:
13271
13272 F - VFP S<n> register
13273 D - Neon D<n> register
13274 Q - Neon Q<n> register
13275 I - Immediate
13276 S - Scalar
13277 R - ARM register
13278 L - D<n> register list
13279
13280 This table is used to generate various data:
13281 - enumerations of the form NS_DDR to be used as arguments to
13282 neon_select_shape.
13283 - a table classifying shapes into single, double, quad, mixed.
13284 - a table used to drive neon_select_shape. */
13285
13286#define NEON_SHAPE_DEF \
13287 X(3, (D, D, D), DOUBLE), \
13288 X(3, (Q, Q, Q), QUAD), \
13289 X(3, (D, D, I), DOUBLE), \
13290 X(3, (Q, Q, I), QUAD), \
13291 X(3, (D, D, S), DOUBLE), \
13292 X(3, (Q, Q, S), QUAD), \
13293 X(2, (D, D), DOUBLE), \
13294 X(2, (Q, Q), QUAD), \
13295 X(2, (D, S), DOUBLE), \
13296 X(2, (Q, S), QUAD), \
13297 X(2, (D, R), DOUBLE), \
13298 X(2, (Q, R), QUAD), \
13299 X(2, (D, I), DOUBLE), \
13300 X(2, (Q, I), QUAD), \
13301 X(3, (D, L, D), DOUBLE), \
13302 X(2, (D, Q), MIXED), \
13303 X(2, (Q, D), MIXED), \
13304 X(3, (D, Q, I), MIXED), \
13305 X(3, (Q, D, I), MIXED), \
13306 X(3, (Q, D, D), MIXED), \
13307 X(3, (D, Q, Q), MIXED), \
13308 X(3, (Q, Q, D), MIXED), \
13309 X(3, (Q, D, S), MIXED), \
13310 X(3, (D, Q, S), MIXED), \
13311 X(4, (D, D, D, I), DOUBLE), \
13312 X(4, (Q, Q, Q, I), QUAD), \
13313 X(2, (F, F), SINGLE), \
13314 X(3, (F, F, F), SINGLE), \
13315 X(2, (F, I), SINGLE), \
13316 X(2, (F, D), MIXED), \
13317 X(2, (D, F), MIXED), \
13318 X(3, (F, F, I), MIXED), \
13319 X(4, (R, R, F, F), SINGLE), \
13320 X(4, (F, F, R, R), SINGLE), \
13321 X(3, (D, R, R), DOUBLE), \
13322 X(3, (R, R, D), DOUBLE), \
13323 X(2, (S, R), SINGLE), \
13324 X(2, (R, S), SINGLE), \
13325 X(2, (F, R), SINGLE), \
13326 X(2, (R, F), SINGLE), \
13327/* Half float shape supported so far. */\
13328 X (2, (H, D), MIXED), \
13329 X (2, (D, H), MIXED), \
13330 X (2, (H, F), MIXED), \
13331 X (2, (F, H), MIXED), \
13332 X (2, (H, H), HALF), \
13333 X (2, (H, R), HALF), \
13334 X (2, (R, H), HALF), \
13335 X (2, (H, I), HALF), \
13336 X (3, (H, H, H), HALF), \
13337 X (3, (H, F, I), MIXED), \
13338 X (3, (F, H, I), MIXED)
13339
13340#define S2(A,B) NS_##A##B
13341#define S3(A,B,C) NS_##A##B##C
13342#define S4(A,B,C,D) NS_##A##B##C##D
13343
13344#define X(N, L, C) S##N L
13345
13346enum neon_shape
13347{
13348 NEON_SHAPE_DEF,
13349 NS_NULL
13350};
13351
13352#undef X
13353#undef S2
13354#undef S3
13355#undef S4
13356
13357enum neon_shape_class
13358{
13359 SC_HALF,
13360 SC_SINGLE,
13361 SC_DOUBLE,
13362 SC_QUAD,
13363 SC_MIXED
13364};
13365
13366#define X(N, L, C) SC_##C
13367
13368static enum neon_shape_class neon_shape_class[] =
13369{
13370 NEON_SHAPE_DEF
13371};
13372
13373#undef X
13374
13375enum neon_shape_el
13376{
13377 SE_H,
13378 SE_F,
13379 SE_D,
13380 SE_Q,
13381 SE_I,
13382 SE_S,
13383 SE_R,
13384 SE_L
13385};
13386
13387/* Register widths of above. */
13388static unsigned neon_shape_el_size[] =
13389{
13390 16,
13391 32,
13392 64,
13393 128,
13394 0,
13395 32,
13396 32,
13397 0
13398};
13399
13400struct neon_shape_info
13401{
13402 unsigned els;
13403 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
13404};
13405
13406#define S2(A,B) { SE_##A, SE_##B }
13407#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13408#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13409
13410#define X(N, L, C) { N, S##N L }
13411
13412static struct neon_shape_info neon_shape_tab[] =
13413{
13414 NEON_SHAPE_DEF
13415};
13416
13417#undef X
13418#undef S2
13419#undef S3
13420#undef S4
13421
13422/* Bit masks used in type checking given instructions.
13423 'N_EQK' means the type must be the same as (or based on in some way) the key
13424 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13425 set, various other bits can be set as well in order to modify the meaning of
13426 the type constraint. */
13427
13428enum neon_type_mask
13429{
13430 N_S8 = 0x0000001,
13431 N_S16 = 0x0000002,
13432 N_S32 = 0x0000004,
13433 N_S64 = 0x0000008,
13434 N_U8 = 0x0000010,
13435 N_U16 = 0x0000020,
13436 N_U32 = 0x0000040,
13437 N_U64 = 0x0000080,
13438 N_I8 = 0x0000100,
13439 N_I16 = 0x0000200,
13440 N_I32 = 0x0000400,
13441 N_I64 = 0x0000800,
13442 N_8 = 0x0001000,
13443 N_16 = 0x0002000,
13444 N_32 = 0x0004000,
13445 N_64 = 0x0008000,
13446 N_P8 = 0x0010000,
13447 N_P16 = 0x0020000,
13448 N_F16 = 0x0040000,
13449 N_F32 = 0x0080000,
13450 N_F64 = 0x0100000,
13451 N_P64 = 0x0200000,
13452 N_KEY = 0x1000000, /* Key element (main type specifier). */
13453 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
13454 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
13455 N_UNT = 0x8000000, /* Must be explicitly untyped. */
13456 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
13457 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
13458 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13459 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13460 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13461 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
13462 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13463 N_UTYP = 0,
13464 N_MAX_NONSPECIAL = N_P64
13465};
13466
13467#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13468
13469#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13470#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13471#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13472#define N_S_32 (N_S8 | N_S16 | N_S32)
13473#define N_F_16_32 (N_F16 | N_F32)
13474#define N_SUF_32 (N_SU_32 | N_F_16_32)
13475#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13476#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13477#define N_F_ALL (N_F16 | N_F32 | N_F64)
13478
13479/* Pass this as the first type argument to neon_check_type to ignore types
13480 altogether. */
13481#define N_IGNORE_TYPE (N_KEY | N_EQK)
13482
13483/* Select a "shape" for the current instruction (describing register types or
13484 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13485 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13486 function of operand parsing, so this function doesn't need to be called.
13487 Shapes should be listed in order of decreasing length. */
13488
13489static enum neon_shape
13490neon_select_shape (enum neon_shape shape, ...)
13491{
13492 va_list ap;
13493 enum neon_shape first_shape = shape;
13494
13495 /* Fix missing optional operands. FIXME: we don't know at this point how
13496 many arguments we should have, so this makes the assumption that we have
13497 > 1. This is true of all current Neon opcodes, I think, but may not be
13498 true in the future. */
13499 if (!inst.operands[1].present)
13500 inst.operands[1] = inst.operands[0];
13501
13502 va_start (ap, shape);
13503
13504 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
13505 {
13506 unsigned j;
13507 int matches = 1;
13508
13509 for (j = 0; j < neon_shape_tab[shape].els; j++)
13510 {
13511 if (!inst.operands[j].present)
13512 {
13513 matches = 0;
13514 break;
13515 }
13516
13517 switch (neon_shape_tab[shape].el[j])
13518 {
13519 /* If a .f16, .16, .u16, .s16 type specifier is given over
13520 a VFP single precision register operand, it's essentially
13521 means only half of the register is used.
13522
13523 If the type specifier is given after the mnemonics, the
13524 information is stored in inst.vectype. If the type specifier
13525 is given after register operand, the information is stored
13526 in inst.operands[].vectype.
13527
13528 When there is only one type specifier, and all the register
13529 operands are the same type of hardware register, the type
13530 specifier applies to all register operands.
13531
13532 If no type specifier is given, the shape is inferred from
13533 operand information.
13534
13535 for example:
13536 vadd.f16 s0, s1, s2: NS_HHH
13537 vabs.f16 s0, s1: NS_HH
13538 vmov.f16 s0, r1: NS_HR
13539 vmov.f16 r0, s1: NS_RH
13540 vcvt.f16 r0, s1: NS_RH
13541 vcvt.f16.s32 s2, s2, #29: NS_HFI
13542 vcvt.f16.s32 s2, s2: NS_HF
13543 */
13544 case SE_H:
13545 if (!(inst.operands[j].isreg
13546 && inst.operands[j].isvec
13547 && inst.operands[j].issingle
13548 && !inst.operands[j].isquad
13549 && ((inst.vectype.elems == 1
13550 && inst.vectype.el[0].size == 16)
13551 || (inst.vectype.elems > 1
13552 && inst.vectype.el[j].size == 16)
13553 || (inst.vectype.elems == 0
13554 && inst.operands[j].vectype.type != NT_invtype
13555 && inst.operands[j].vectype.size == 16))))
13556 matches = 0;
13557 break;
13558
13559 case SE_F:
13560 if (!(inst.operands[j].isreg
13561 && inst.operands[j].isvec
13562 && inst.operands[j].issingle
13563 && !inst.operands[j].isquad
13564 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
13565 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
13566 || (inst.vectype.elems == 0
13567 && (inst.operands[j].vectype.size == 32
13568 || inst.operands[j].vectype.type == NT_invtype)))))
13569 matches = 0;
13570 break;
13571
13572 case SE_D:
13573 if (!(inst.operands[j].isreg
13574 && inst.operands[j].isvec
13575 && !inst.operands[j].isquad
13576 && !inst.operands[j].issingle))
13577 matches = 0;
13578 break;
13579
13580 case SE_R:
13581 if (!(inst.operands[j].isreg
13582 && !inst.operands[j].isvec))
13583 matches = 0;
13584 break;
13585
13586 case SE_Q:
13587 if (!(inst.operands[j].isreg
13588 && inst.operands[j].isvec
13589 && inst.operands[j].isquad
13590 && !inst.operands[j].issingle))
13591 matches = 0;
13592 break;
13593
13594 case SE_I:
13595 if (!(!inst.operands[j].isreg
13596 && !inst.operands[j].isscalar))
13597 matches = 0;
13598 break;
13599
13600 case SE_S:
13601 if (!(!inst.operands[j].isreg
13602 && inst.operands[j].isscalar))
13603 matches = 0;
13604 break;
13605
13606 case SE_L:
13607 break;
13608 }
13609 if (!matches)
13610 break;
13611 }
13612 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
13613 /* We've matched all the entries in the shape table, and we don't
13614 have any left over operands which have not been matched. */
13615 break;
13616 }
13617
13618 va_end (ap);
13619
13620 if (shape == NS_NULL && first_shape != NS_NULL)
13621 first_error (_("invalid instruction shape"));
13622
13623 return shape;
13624}
13625
13626/* True if SHAPE is predominantly a quadword operation (most of the time, this
13627 means the Q bit should be set). */
13628
13629static int
13630neon_quad (enum neon_shape shape)
13631{
13632 return neon_shape_class[shape] == SC_QUAD;
13633}
13634
13635static void
13636neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
13637 unsigned *g_size)
13638{
13639 /* Allow modification to be made to types which are constrained to be
13640 based on the key element, based on bits set alongside N_EQK. */
13641 if ((typebits & N_EQK) != 0)
13642 {
13643 if ((typebits & N_HLF) != 0)
13644 *g_size /= 2;
13645 else if ((typebits & N_DBL) != 0)
13646 *g_size *= 2;
13647 if ((typebits & N_SGN) != 0)
13648 *g_type = NT_signed;
13649 else if ((typebits & N_UNS) != 0)
13650 *g_type = NT_unsigned;
13651 else if ((typebits & N_INT) != 0)
13652 *g_type = NT_integer;
13653 else if ((typebits & N_FLT) != 0)
13654 *g_type = NT_float;
13655 else if ((typebits & N_SIZ) != 0)
13656 *g_type = NT_untyped;
13657 }
13658}
13659
13660/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13661 operand type, i.e. the single type specified in a Neon instruction when it
13662 is the only one given. */
13663
13664static struct neon_type_el
13665neon_type_promote (struct neon_type_el *key, unsigned thisarg)
13666{
13667 struct neon_type_el dest = *key;
13668
13669 gas_assert ((thisarg & N_EQK) != 0);
13670
13671 neon_modify_type_size (thisarg, &dest.type, &dest.size);
13672
13673 return dest;
13674}
13675
13676/* Convert Neon type and size into compact bitmask representation. */
13677
13678static enum neon_type_mask
13679type_chk_of_el_type (enum neon_el_type type, unsigned size)
13680{
13681 switch (type)
13682 {
13683 case NT_untyped:
13684 switch (size)
13685 {
13686 case 8: return N_8;
13687 case 16: return N_16;
13688 case 32: return N_32;
13689 case 64: return N_64;
13690 default: ;
13691 }
13692 break;
13693
13694 case NT_integer:
13695 switch (size)
13696 {
13697 case 8: return N_I8;
13698 case 16: return N_I16;
13699 case 32: return N_I32;
13700 case 64: return N_I64;
13701 default: ;
13702 }
13703 break;
13704
13705 case NT_float:
13706 switch (size)
13707 {
13708 case 16: return N_F16;
13709 case 32: return N_F32;
13710 case 64: return N_F64;
13711 default: ;
13712 }
13713 break;
13714
13715 case NT_poly:
13716 switch (size)
13717 {
13718 case 8: return N_P8;
13719 case 16: return N_P16;
13720 case 64: return N_P64;
13721 default: ;
13722 }
13723 break;
13724
13725 case NT_signed:
13726 switch (size)
13727 {
13728 case 8: return N_S8;
13729 case 16: return N_S16;
13730 case 32: return N_S32;
13731 case 64: return N_S64;
13732 default: ;
13733 }
13734 break;
13735
13736 case NT_unsigned:
13737 switch (size)
13738 {
13739 case 8: return N_U8;
13740 case 16: return N_U16;
13741 case 32: return N_U32;
13742 case 64: return N_U64;
13743 default: ;
13744 }
13745 break;
13746
13747 default: ;
13748 }
13749
13750 return N_UTYP;
13751}
13752
13753/* Convert compact Neon bitmask type representation to a type and size. Only
13754 handles the case where a single bit is set in the mask. */
13755
13756static int
13757el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
13758 enum neon_type_mask mask)
13759{
13760 if ((mask & N_EQK) != 0)
13761 return FAIL;
13762
13763 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
13764 *size = 8;
13765 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
13766 *size = 16;
13767 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
13768 *size = 32;
13769 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
13770 *size = 64;
13771 else
13772 return FAIL;
13773
13774 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
13775 *type = NT_signed;
13776 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
13777 *type = NT_unsigned;
13778 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
13779 *type = NT_integer;
13780 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
13781 *type = NT_untyped;
13782 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
13783 *type = NT_poly;
13784 else if ((mask & (N_F_ALL)) != 0)
13785 *type = NT_float;
13786 else
13787 return FAIL;
13788
13789 return SUCCESS;
13790}
13791
13792/* Modify a bitmask of allowed types. This is only needed for type
13793 relaxation. */
13794
13795static unsigned
13796modify_types_allowed (unsigned allowed, unsigned mods)
13797{
13798 unsigned size;
13799 enum neon_el_type type;
13800 unsigned destmask;
13801 int i;
13802
13803 destmask = 0;
13804
13805 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
13806 {
13807 if (el_type_of_type_chk (&type, &size,
13808 (enum neon_type_mask) (allowed & i)) == SUCCESS)
13809 {
13810 neon_modify_type_size (mods, &type, &size);
13811 destmask |= type_chk_of_el_type (type, size);
13812 }
13813 }
13814
13815 return destmask;
13816}
13817
13818/* Check type and return type classification.
13819 The manual states (paraphrase): If one datatype is given, it indicates the
13820 type given in:
13821 - the second operand, if there is one
13822 - the operand, if there is no second operand
13823 - the result, if there are no operands.
13824 This isn't quite good enough though, so we use a concept of a "key" datatype
13825 which is set on a per-instruction basis, which is the one which matters when
13826 only one data type is written.
13827 Note: this function has side-effects (e.g. filling in missing operands). All
13828 Neon instructions should call it before performing bit encoding. */
13829
13830static struct neon_type_el
13831neon_check_type (unsigned els, enum neon_shape ns, ...)
13832{
13833 va_list ap;
13834 unsigned i, pass, key_el = 0;
13835 unsigned types[NEON_MAX_TYPE_ELS];
13836 enum neon_el_type k_type = NT_invtype;
13837 unsigned k_size = -1u;
13838 struct neon_type_el badtype = {NT_invtype, -1};
13839 unsigned key_allowed = 0;
13840
13841 /* Optional registers in Neon instructions are always (not) in operand 1.
13842 Fill in the missing operand here, if it was omitted. */
13843 if (els > 1 && !inst.operands[1].present)
13844 inst.operands[1] = inst.operands[0];
13845
13846 /* Suck up all the varargs. */
13847 va_start (ap, ns);
13848 for (i = 0; i < els; i++)
13849 {
13850 unsigned thisarg = va_arg (ap, unsigned);
13851 if (thisarg == N_IGNORE_TYPE)
13852 {
13853 va_end (ap);
13854 return badtype;
13855 }
13856 types[i] = thisarg;
13857 if ((thisarg & N_KEY) != 0)
13858 key_el = i;
13859 }
13860 va_end (ap);
13861
13862 if (inst.vectype.elems > 0)
13863 for (i = 0; i < els; i++)
13864 if (inst.operands[i].vectype.type != NT_invtype)
13865 {
13866 first_error (_("types specified in both the mnemonic and operands"));
13867 return badtype;
13868 }
13869
13870 /* Duplicate inst.vectype elements here as necessary.
13871 FIXME: No idea if this is exactly the same as the ARM assembler,
13872 particularly when an insn takes one register and one non-register
13873 operand. */
13874 if (inst.vectype.elems == 1 && els > 1)
13875 {
13876 unsigned j;
13877 inst.vectype.elems = els;
13878 inst.vectype.el[key_el] = inst.vectype.el[0];
13879 for (j = 0; j < els; j++)
13880 if (j != key_el)
13881 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
13882 types[j]);
13883 }
13884 else if (inst.vectype.elems == 0 && els > 0)
13885 {
13886 unsigned j;
13887 /* No types were given after the mnemonic, so look for types specified
13888 after each operand. We allow some flexibility here; as long as the
13889 "key" operand has a type, we can infer the others. */
13890 for (j = 0; j < els; j++)
13891 if (inst.operands[j].vectype.type != NT_invtype)
13892 inst.vectype.el[j] = inst.operands[j].vectype;
13893
13894 if (inst.operands[key_el].vectype.type != NT_invtype)
13895 {
13896 for (j = 0; j < els; j++)
13897 if (inst.operands[j].vectype.type == NT_invtype)
13898 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
13899 types[j]);
13900 }
13901 else
13902 {
13903 first_error (_("operand types can't be inferred"));
13904 return badtype;
13905 }
13906 }
13907 else if (inst.vectype.elems != els)
13908 {
13909 first_error (_("type specifier has the wrong number of parts"));
13910 return badtype;
13911 }
13912
13913 for (pass = 0; pass < 2; pass++)
13914 {
13915 for (i = 0; i < els; i++)
13916 {
13917 unsigned thisarg = types[i];
13918 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
13919 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
13920 enum neon_el_type g_type = inst.vectype.el[i].type;
13921 unsigned g_size = inst.vectype.el[i].size;
13922
13923 /* Decay more-specific signed & unsigned types to sign-insensitive
13924 integer types if sign-specific variants are unavailable. */
13925 if ((g_type == NT_signed || g_type == NT_unsigned)
13926 && (types_allowed & N_SU_ALL) == 0)
13927 g_type = NT_integer;
13928
13929 /* If only untyped args are allowed, decay any more specific types to
13930 them. Some instructions only care about signs for some element
13931 sizes, so handle that properly. */
13932 if (((types_allowed & N_UNT) == 0)
13933 && ((g_size == 8 && (types_allowed & N_8) != 0)
13934 || (g_size == 16 && (types_allowed & N_16) != 0)
13935 || (g_size == 32 && (types_allowed & N_32) != 0)
13936 || (g_size == 64 && (types_allowed & N_64) != 0)))
13937 g_type = NT_untyped;
13938
13939 if (pass == 0)
13940 {
13941 if ((thisarg & N_KEY) != 0)
13942 {
13943 k_type = g_type;
13944 k_size = g_size;
13945 key_allowed = thisarg & ~N_KEY;
13946
13947 /* Check architecture constraint on FP16 extension. */
13948 if (k_size == 16
13949 && k_type == NT_float
13950 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
13951 {
13952 inst.error = _(BAD_FP16);
13953 return badtype;
13954 }
13955 }
13956 }
13957 else
13958 {
13959 if ((thisarg & N_VFP) != 0)
13960 {
13961 enum neon_shape_el regshape;
13962 unsigned regwidth, match;
13963
13964 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13965 if (ns == NS_NULL)
13966 {
13967 first_error (_("invalid instruction shape"));
13968 return badtype;
13969 }
13970 regshape = neon_shape_tab[ns].el[i];
13971 regwidth = neon_shape_el_size[regshape];
13972
13973 /* In VFP mode, operands must match register widths. If we
13974 have a key operand, use its width, else use the width of
13975 the current operand. */
13976 if (k_size != -1u)
13977 match = k_size;
13978 else
13979 match = g_size;
13980
13981 /* FP16 will use a single precision register. */
13982 if (regwidth == 32 && match == 16)
13983 {
13984 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
13985 match = regwidth;
13986 else
13987 {
13988 inst.error = _(BAD_FP16);
13989 return badtype;
13990 }
13991 }
13992
13993 if (regwidth != match)
13994 {
13995 first_error (_("operand size must match register width"));
13996 return badtype;
13997 }
13998 }
13999
14000 if ((thisarg & N_EQK) == 0)
14001 {
14002 unsigned given_type = type_chk_of_el_type (g_type, g_size);
14003
14004 if ((given_type & types_allowed) == 0)
14005 {
14006 first_error (_("bad type in Neon instruction"));
14007 return badtype;
14008 }
14009 }
14010 else
14011 {
14012 enum neon_el_type mod_k_type = k_type;
14013 unsigned mod_k_size = k_size;
14014 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
14015 if (g_type != mod_k_type || g_size != mod_k_size)
14016 {
14017 first_error (_("inconsistent types in Neon instruction"));
14018 return badtype;
14019 }
14020 }
14021 }
14022 }
14023 }
14024
14025 return inst.vectype.el[key_el];
14026}
14027
14028/* Neon-style VFP instruction forwarding. */
14029
14030/* Thumb VFP instructions have 0xE in the condition field. */
14031
14032static void
14033do_vfp_cond_or_thumb (void)
14034{
14035 inst.is_neon = 1;
14036
14037 if (thumb_mode)
14038 inst.instruction |= 0xe0000000;
14039 else
14040 inst.instruction |= inst.cond << 28;
14041}
14042
14043/* Look up and encode a simple mnemonic, for use as a helper function for the
14044 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14045 etc. It is assumed that operand parsing has already been done, and that the
14046 operands are in the form expected by the given opcode (this isn't necessarily
14047 the same as the form in which they were parsed, hence some massaging must
14048 take place before this function is called).
14049 Checks current arch version against that in the looked-up opcode. */
14050
14051static void
14052do_vfp_nsyn_opcode (const char *opname)
14053{
14054 const struct asm_opcode *opcode;
14055
14056 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
14057
14058 if (!opcode)
14059 abort ();
14060
14061 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
14062 thumb_mode ? *opcode->tvariant : *opcode->avariant),
14063 _(BAD_FPU));
14064
14065 inst.is_neon = 1;
14066
14067 if (thumb_mode)
14068 {
14069 inst.instruction = opcode->tvalue;
14070 opcode->tencode ();
14071 }
14072 else
14073 {
14074 inst.instruction = (inst.cond << 28) | opcode->avalue;
14075 opcode->aencode ();
14076 }
14077}
14078
14079static void
14080do_vfp_nsyn_add_sub (enum neon_shape rs)
14081{
14082 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
14083
14084 if (rs == NS_FFF || rs == NS_HHH)
14085 {
14086 if (is_add)
14087 do_vfp_nsyn_opcode ("fadds");
14088 else
14089 do_vfp_nsyn_opcode ("fsubs");
14090
14091 /* ARMv8.2 fp16 instruction. */
14092 if (rs == NS_HHH)
14093 do_scalar_fp16_v82_encode ();
14094 }
14095 else
14096 {
14097 if (is_add)
14098 do_vfp_nsyn_opcode ("faddd");
14099 else
14100 do_vfp_nsyn_opcode ("fsubd");
14101 }
14102}
14103
14104/* Check operand types to see if this is a VFP instruction, and if so call
14105 PFN (). */
14106
14107static int
14108try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
14109{
14110 enum neon_shape rs;
14111 struct neon_type_el et;
14112
14113 switch (args)
14114 {
14115 case 2:
14116 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
14117 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
14118 break;
14119
14120 case 3:
14121 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
14122 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14123 N_F_ALL | N_KEY | N_VFP);
14124 break;
14125
14126 default:
14127 abort ();
14128 }
14129
14130 if (et.type != NT_invtype)
14131 {
14132 pfn (rs);
14133 return SUCCESS;
14134 }
14135
14136 inst.error = NULL;
14137 return FAIL;
14138}
14139
14140static void
14141do_vfp_nsyn_mla_mls (enum neon_shape rs)
14142{
14143 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
14144
14145 if (rs == NS_FFF || rs == NS_HHH)
14146 {
14147 if (is_mla)
14148 do_vfp_nsyn_opcode ("fmacs");
14149 else
14150 do_vfp_nsyn_opcode ("fnmacs");
14151
14152 /* ARMv8.2 fp16 instruction. */
14153 if (rs == NS_HHH)
14154 do_scalar_fp16_v82_encode ();
14155 }
14156 else
14157 {
14158 if (is_mla)
14159 do_vfp_nsyn_opcode ("fmacd");
14160 else
14161 do_vfp_nsyn_opcode ("fnmacd");
14162 }
14163}
14164
14165static void
14166do_vfp_nsyn_fma_fms (enum neon_shape rs)
14167{
14168 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
14169
14170 if (rs == NS_FFF || rs == NS_HHH)
14171 {
14172 if (is_fma)
14173 do_vfp_nsyn_opcode ("ffmas");
14174 else
14175 do_vfp_nsyn_opcode ("ffnmas");
14176
14177 /* ARMv8.2 fp16 instruction. */
14178 if (rs == NS_HHH)
14179 do_scalar_fp16_v82_encode ();
14180 }
14181 else
14182 {
14183 if (is_fma)
14184 do_vfp_nsyn_opcode ("ffmad");
14185 else
14186 do_vfp_nsyn_opcode ("ffnmad");
14187 }
14188}
14189
14190static void
14191do_vfp_nsyn_mul (enum neon_shape rs)
14192{
14193 if (rs == NS_FFF || rs == NS_HHH)
14194 {
14195 do_vfp_nsyn_opcode ("fmuls");
14196
14197 /* ARMv8.2 fp16 instruction. */
14198 if (rs == NS_HHH)
14199 do_scalar_fp16_v82_encode ();
14200 }
14201 else
14202 do_vfp_nsyn_opcode ("fmuld");
14203}
14204
14205static void
14206do_vfp_nsyn_abs_neg (enum neon_shape rs)
14207{
14208 int is_neg = (inst.instruction & 0x80) != 0;
14209 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
14210
14211 if (rs == NS_FF || rs == NS_HH)
14212 {
14213 if (is_neg)
14214 do_vfp_nsyn_opcode ("fnegs");
14215 else
14216 do_vfp_nsyn_opcode ("fabss");
14217
14218 /* ARMv8.2 fp16 instruction. */
14219 if (rs == NS_HH)
14220 do_scalar_fp16_v82_encode ();
14221 }
14222 else
14223 {
14224 if (is_neg)
14225 do_vfp_nsyn_opcode ("fnegd");
14226 else
14227 do_vfp_nsyn_opcode ("fabsd");
14228 }
14229}
14230
14231/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14232 insns belong to Neon, and are handled elsewhere. */
14233
14234static void
14235do_vfp_nsyn_ldm_stm (int is_dbmode)
14236{
14237 int is_ldm = (inst.instruction & (1 << 20)) != 0;
14238 if (is_ldm)
14239 {
14240 if (is_dbmode)
14241 do_vfp_nsyn_opcode ("fldmdbs");
14242 else
14243 do_vfp_nsyn_opcode ("fldmias");
14244 }
14245 else
14246 {
14247 if (is_dbmode)
14248 do_vfp_nsyn_opcode ("fstmdbs");
14249 else
14250 do_vfp_nsyn_opcode ("fstmias");
14251 }
14252}
14253
14254static void
14255do_vfp_nsyn_sqrt (void)
14256{
14257 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
14258 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
14259
14260 if (rs == NS_FF || rs == NS_HH)
14261 {
14262 do_vfp_nsyn_opcode ("fsqrts");
14263
14264 /* ARMv8.2 fp16 instruction. */
14265 if (rs == NS_HH)
14266 do_scalar_fp16_v82_encode ();
14267 }
14268 else
14269 do_vfp_nsyn_opcode ("fsqrtd");
14270}
14271
14272static void
14273do_vfp_nsyn_div (void)
14274{
14275 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
14276 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14277 N_F_ALL | N_KEY | N_VFP);
14278
14279 if (rs == NS_FFF || rs == NS_HHH)
14280 {
14281 do_vfp_nsyn_opcode ("fdivs");
14282
14283 /* ARMv8.2 fp16 instruction. */
14284 if (rs == NS_HHH)
14285 do_scalar_fp16_v82_encode ();
14286 }
14287 else
14288 do_vfp_nsyn_opcode ("fdivd");
14289}
14290
14291static void
14292do_vfp_nsyn_nmul (void)
14293{
14294 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
14295 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14296 N_F_ALL | N_KEY | N_VFP);
14297
14298 if (rs == NS_FFF || rs == NS_HHH)
14299 {
14300 NEON_ENCODE (SINGLE, inst);
14301 do_vfp_sp_dyadic ();
14302
14303 /* ARMv8.2 fp16 instruction. */
14304 if (rs == NS_HHH)
14305 do_scalar_fp16_v82_encode ();
14306 }
14307 else
14308 {
14309 NEON_ENCODE (DOUBLE, inst);
14310 do_vfp_dp_rd_rn_rm ();
14311 }
14312 do_vfp_cond_or_thumb ();
14313
14314}
14315
14316static void
14317do_vfp_nsyn_cmp (void)
14318{
14319 enum neon_shape rs;
14320 if (inst.operands[1].isreg)
14321 {
14322 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
14323 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
14324
14325 if (rs == NS_FF || rs == NS_HH)
14326 {
14327 NEON_ENCODE (SINGLE, inst);
14328 do_vfp_sp_monadic ();
14329 }
14330 else
14331 {
14332 NEON_ENCODE (DOUBLE, inst);
14333 do_vfp_dp_rd_rm ();
14334 }
14335 }
14336 else
14337 {
14338 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
14339 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
14340
14341 switch (inst.instruction & 0x0fffffff)
14342 {
14343 case N_MNEM_vcmp:
14344 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
14345 break;
14346 case N_MNEM_vcmpe:
14347 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
14348 break;
14349 default:
14350 abort ();
14351 }
14352
14353 if (rs == NS_FI || rs == NS_HI)
14354 {
14355 NEON_ENCODE (SINGLE, inst);
14356 do_vfp_sp_compare_z ();
14357 }
14358 else
14359 {
14360 NEON_ENCODE (DOUBLE, inst);
14361 do_vfp_dp_rd ();
14362 }
14363 }
14364 do_vfp_cond_or_thumb ();
14365
14366 /* ARMv8.2 fp16 instruction. */
14367 if (rs == NS_HI || rs == NS_HH)
14368 do_scalar_fp16_v82_encode ();
14369}
14370
14371static void
14372nsyn_insert_sp (void)
14373{
14374 inst.operands[1] = inst.operands[0];
14375 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
14376 inst.operands[0].reg = REG_SP;
14377 inst.operands[0].isreg = 1;
14378 inst.operands[0].writeback = 1;
14379 inst.operands[0].present = 1;
14380}
14381
14382static void
14383do_vfp_nsyn_push (void)
14384{
14385 nsyn_insert_sp ();
14386 if (inst.operands[1].issingle)
14387 do_vfp_nsyn_opcode ("fstmdbs");
14388 else
14389 do_vfp_nsyn_opcode ("fstmdbd");
14390}
14391
14392static void
14393do_vfp_nsyn_pop (void)
14394{
14395 nsyn_insert_sp ();
14396 if (inst.operands[1].issingle)
14397 do_vfp_nsyn_opcode ("fldmias");
14398 else
14399 do_vfp_nsyn_opcode ("fldmiad");
14400}
14401
14402/* Fix up Neon data-processing instructions, ORing in the correct bits for
14403 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14404
14405static void
14406neon_dp_fixup (struct arm_it* insn)
14407{
14408 unsigned int i = insn->instruction;
14409 insn->is_neon = 1;
14410
14411 if (thumb_mode)
14412 {
14413 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14414 if (i & (1 << 24))
14415 i |= 1 << 28;
14416
14417 i &= ~(1 << 24);
14418
14419 i |= 0xef000000;
14420 }
14421 else
14422 i |= 0xf2000000;
14423
14424 insn->instruction = i;
14425}
14426
14427/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14428 (0, 1, 2, 3). */
14429
14430static unsigned
14431neon_logbits (unsigned x)
14432{
14433 return ffs (x) - 4;
14434}
14435
14436#define LOW4(R) ((R) & 0xf)
14437#define HI1(R) (((R) >> 4) & 1)
14438
14439/* Encode insns with bit pattern:
14440
14441 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14442 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14443
14444 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14445 different meaning for some instruction. */
14446
14447static void
14448neon_three_same (int isquad, int ubit, int size)
14449{
14450 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14451 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14452 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14453 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14454 inst.instruction |= LOW4 (inst.operands[2].reg);
14455 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14456 inst.instruction |= (isquad != 0) << 6;
14457 inst.instruction |= (ubit != 0) << 24;
14458 if (size != -1)
14459 inst.instruction |= neon_logbits (size) << 20;
14460
14461 neon_dp_fixup (&inst);
14462}
14463
14464/* Encode instructions of the form:
14465
14466 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14467 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14468
14469 Don't write size if SIZE == -1. */
14470
14471static void
14472neon_two_same (int qbit, int ubit, int size)
14473{
14474 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14475 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14476 inst.instruction |= LOW4 (inst.operands[1].reg);
14477 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14478 inst.instruction |= (qbit != 0) << 6;
14479 inst.instruction |= (ubit != 0) << 24;
14480
14481 if (size != -1)
14482 inst.instruction |= neon_logbits (size) << 18;
14483
14484 neon_dp_fixup (&inst);
14485}
14486
14487/* Neon instruction encoders, in approximate order of appearance. */
14488
14489static void
14490do_neon_dyadic_i_su (void)
14491{
14492 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14493 struct neon_type_el et = neon_check_type (3, rs,
14494 N_EQK, N_EQK, N_SU_32 | N_KEY);
14495 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14496}
14497
14498static void
14499do_neon_dyadic_i64_su (void)
14500{
14501 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14502 struct neon_type_el et = neon_check_type (3, rs,
14503 N_EQK, N_EQK, N_SU_ALL | N_KEY);
14504 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14505}
14506
14507static void
14508neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
14509 unsigned immbits)
14510{
14511 unsigned size = et.size >> 3;
14512 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14513 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14514 inst.instruction |= LOW4 (inst.operands[1].reg);
14515 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14516 inst.instruction |= (isquad != 0) << 6;
14517 inst.instruction |= immbits << 16;
14518 inst.instruction |= (size >> 3) << 7;
14519 inst.instruction |= (size & 0x7) << 19;
14520 if (write_ubit)
14521 inst.instruction |= (uval != 0) << 24;
14522
14523 neon_dp_fixup (&inst);
14524}
14525
14526static void
14527do_neon_shl_imm (void)
14528{
14529 if (!inst.operands[2].isreg)
14530 {
14531 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14532 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
14533 int imm = inst.operands[2].imm;
14534
14535 constraint (imm < 0 || (unsigned)imm >= et.size,
14536 _("immediate out of range for shift"));
14537 NEON_ENCODE (IMMED, inst);
14538 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14539 }
14540 else
14541 {
14542 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14543 struct neon_type_el et = neon_check_type (3, rs,
14544 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
14545 unsigned int tmp;
14546
14547 /* VSHL/VQSHL 3-register variants have syntax such as:
14548 vshl.xx Dd, Dm, Dn
14549 whereas other 3-register operations encoded by neon_three_same have
14550 syntax like:
14551 vadd.xx Dd, Dn, Dm
14552 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14553 here. */
14554 tmp = inst.operands[2].reg;
14555 inst.operands[2].reg = inst.operands[1].reg;
14556 inst.operands[1].reg = tmp;
14557 NEON_ENCODE (INTEGER, inst);
14558 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14559 }
14560}
14561
14562static void
14563do_neon_qshl_imm (void)
14564{
14565 if (!inst.operands[2].isreg)
14566 {
14567 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14568 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
14569 int imm = inst.operands[2].imm;
14570
14571 constraint (imm < 0 || (unsigned)imm >= et.size,
14572 _("immediate out of range for shift"));
14573 NEON_ENCODE (IMMED, inst);
14574 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
14575 }
14576 else
14577 {
14578 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14579 struct neon_type_el et = neon_check_type (3, rs,
14580 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
14581 unsigned int tmp;
14582
14583 /* See note in do_neon_shl_imm. */
14584 tmp = inst.operands[2].reg;
14585 inst.operands[2].reg = inst.operands[1].reg;
14586 inst.operands[1].reg = tmp;
14587 NEON_ENCODE (INTEGER, inst);
14588 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14589 }
14590}
14591
14592static void
14593do_neon_rshl (void)
14594{
14595 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14596 struct neon_type_el et = neon_check_type (3, rs,
14597 N_EQK, N_EQK, N_SU_ALL | N_KEY);
14598 unsigned int tmp;
14599
14600 tmp = inst.operands[2].reg;
14601 inst.operands[2].reg = inst.operands[1].reg;
14602 inst.operands[1].reg = tmp;
14603 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14604}
14605
14606static int
14607neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
14608{
14609 /* Handle .I8 pseudo-instructions. */
14610 if (size == 8)
14611 {
14612 /* Unfortunately, this will make everything apart from zero out-of-range.
14613 FIXME is this the intended semantics? There doesn't seem much point in
14614 accepting .I8 if so. */
14615 immediate |= immediate << 8;
14616 size = 16;
14617 }
14618
14619 if (size >= 32)
14620 {
14621 if (immediate == (immediate & 0x000000ff))
14622 {
14623 *immbits = immediate;
14624 return 0x1;
14625 }
14626 else if (immediate == (immediate & 0x0000ff00))
14627 {
14628 *immbits = immediate >> 8;
14629 return 0x3;
14630 }
14631 else if (immediate == (immediate & 0x00ff0000))
14632 {
14633 *immbits = immediate >> 16;
14634 return 0x5;
14635 }
14636 else if (immediate == (immediate & 0xff000000))
14637 {
14638 *immbits = immediate >> 24;
14639 return 0x7;
14640 }
14641 if ((immediate & 0xffff) != (immediate >> 16))
14642 goto bad_immediate;
14643 immediate &= 0xffff;
14644 }
14645
14646 if (immediate == (immediate & 0x000000ff))
14647 {
14648 *immbits = immediate;
14649 return 0x9;
14650 }
14651 else if (immediate == (immediate & 0x0000ff00))
14652 {
14653 *immbits = immediate >> 8;
14654 return 0xb;
14655 }
14656
14657 bad_immediate:
14658 first_error (_("immediate value out of range"));
14659 return FAIL;
14660}
14661
14662static void
14663do_neon_logic (void)
14664{
14665 if (inst.operands[2].present && inst.operands[2].isreg)
14666 {
14667 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14668 neon_check_type (3, rs, N_IGNORE_TYPE);
14669 /* U bit and size field were set as part of the bitmask. */
14670 NEON_ENCODE (INTEGER, inst);
14671 neon_three_same (neon_quad (rs), 0, -1);
14672 }
14673 else
14674 {
14675 const int three_ops_form = (inst.operands[2].present
14676 && !inst.operands[2].isreg);
14677 const int immoperand = (three_ops_form ? 2 : 1);
14678 enum neon_shape rs = (three_ops_form
14679 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
14680 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
14681 struct neon_type_el et = neon_check_type (2, rs,
14682 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14683 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
14684 unsigned immbits;
14685 int cmode;
14686
14687 if (et.type == NT_invtype)
14688 return;
14689
14690 if (three_ops_form)
14691 constraint (inst.operands[0].reg != inst.operands[1].reg,
14692 _("first and second operands shall be the same register"));
14693
14694 NEON_ENCODE (IMMED, inst);
14695
14696 immbits = inst.operands[immoperand].imm;
14697 if (et.size == 64)
14698 {
14699 /* .i64 is a pseudo-op, so the immediate must be a repeating
14700 pattern. */
14701 if (immbits != (inst.operands[immoperand].regisimm ?
14702 inst.operands[immoperand].reg : 0))
14703 {
14704 /* Set immbits to an invalid constant. */
14705 immbits = 0xdeadbeef;
14706 }
14707 }
14708
14709 switch (opcode)
14710 {
14711 case N_MNEM_vbic:
14712 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14713 break;
14714
14715 case N_MNEM_vorr:
14716 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14717 break;
14718
14719 case N_MNEM_vand:
14720 /* Pseudo-instruction for VBIC. */
14721 neon_invert_size (&immbits, 0, et.size);
14722 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14723 break;
14724
14725 case N_MNEM_vorn:
14726 /* Pseudo-instruction for VORR. */
14727 neon_invert_size (&immbits, 0, et.size);
14728 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14729 break;
14730
14731 default:
14732 abort ();
14733 }
14734
14735 if (cmode == FAIL)
14736 return;
14737
14738 inst.instruction |= neon_quad (rs) << 6;
14739 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14740 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14741 inst.instruction |= cmode << 8;
14742 neon_write_immbits (immbits);
14743
14744 neon_dp_fixup (&inst);
14745 }
14746}
14747
14748static void
14749do_neon_bitfield (void)
14750{
14751 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14752 neon_check_type (3, rs, N_IGNORE_TYPE);
14753 neon_three_same (neon_quad (rs), 0, -1);
14754}
14755
14756static void
14757neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
14758 unsigned destbits)
14759{
14760 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14761 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
14762 types | N_KEY);
14763 if (et.type == NT_float)
14764 {
14765 NEON_ENCODE (FLOAT, inst);
14766 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
14767 }
14768 else
14769 {
14770 NEON_ENCODE (INTEGER, inst);
14771 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
14772 }
14773}
14774
14775static void
14776do_neon_dyadic_if_su (void)
14777{
14778 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
14779}
14780
14781static void
14782do_neon_dyadic_if_su_d (void)
14783{
14784 /* This version only allow D registers, but that constraint is enforced during
14785 operand parsing so we don't need to do anything extra here. */
14786 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
14787}
14788
14789static void
14790do_neon_dyadic_if_i_d (void)
14791{
14792 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14793 affected if we specify unsigned args. */
14794 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14795}
14796
14797enum vfp_or_neon_is_neon_bits
14798{
14799 NEON_CHECK_CC = 1,
14800 NEON_CHECK_ARCH = 2,
14801 NEON_CHECK_ARCH8 = 4
14802};
14803
14804/* Call this function if an instruction which may have belonged to the VFP or
14805 Neon instruction sets, but turned out to be a Neon instruction (due to the
14806 operand types involved, etc.). We have to check and/or fix-up a couple of
14807 things:
14808
14809 - Make sure the user hasn't attempted to make a Neon instruction
14810 conditional.
14811 - Alter the value in the condition code field if necessary.
14812 - Make sure that the arch supports Neon instructions.
14813
14814 Which of these operations take place depends on bits from enum
14815 vfp_or_neon_is_neon_bits.
14816
14817 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14818 current instruction's condition is COND_ALWAYS, the condition field is
14819 changed to inst.uncond_value. This is necessary because instructions shared
14820 between VFP and Neon may be conditional for the VFP variants only, and the
14821 unconditional Neon version must have, e.g., 0xF in the condition field. */
14822
14823static int
14824vfp_or_neon_is_neon (unsigned check)
14825{
14826 /* Conditions are always legal in Thumb mode (IT blocks). */
14827 if (!thumb_mode && (check & NEON_CHECK_CC))
14828 {
14829 if (inst.cond != COND_ALWAYS)
14830 {
14831 first_error (_(BAD_COND));
14832 return FAIL;
14833 }
14834 if (inst.uncond_value != -1)
14835 inst.instruction |= inst.uncond_value << 28;
14836 }
14837
14838 if ((check & NEON_CHECK_ARCH)
14839 && !mark_feature_used (&fpu_neon_ext_v1))
14840 {
14841 first_error (_(BAD_FPU));
14842 return FAIL;
14843 }
14844
14845 if ((check & NEON_CHECK_ARCH8)
14846 && !mark_feature_used (&fpu_neon_ext_armv8))
14847 {
14848 first_error (_(BAD_FPU));
14849 return FAIL;
14850 }
14851
14852 return SUCCESS;
14853}
14854
14855static void
14856do_neon_addsub_if_i (void)
14857{
14858 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14859 return;
14860
14861 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14862 return;
14863
14864 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14865 affected if we specify unsigned args. */
14866 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14867}
14868
14869/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14870 result to be:
14871 V<op> A,B (A is operand 0, B is operand 2)
14872 to mean:
14873 V<op> A,B,A
14874 not:
14875 V<op> A,B,B
14876 so handle that case specially. */
14877
14878static void
14879neon_exchange_operands (void)
14880{
14881 if (inst.operands[1].present)
14882 {
14883 void *scratch = xmalloc (sizeof (inst.operands[0]));
14884
14885 /* Swap operands[1] and operands[2]. */
14886 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14887 inst.operands[1] = inst.operands[2];
14888 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14889 free (scratch);
14890 }
14891 else
14892 {
14893 inst.operands[1] = inst.operands[2];
14894 inst.operands[2] = inst.operands[0];
14895 }
14896}
14897
14898static void
14899neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14900{
14901 if (inst.operands[2].isreg)
14902 {
14903 if (invert)
14904 neon_exchange_operands ();
14905 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14906 }
14907 else
14908 {
14909 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14910 struct neon_type_el et = neon_check_type (2, rs,
14911 N_EQK | N_SIZ, immtypes | N_KEY);
14912
14913 NEON_ENCODE (IMMED, inst);
14914 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14915 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14916 inst.instruction |= LOW4 (inst.operands[1].reg);
14917 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14918 inst.instruction |= neon_quad (rs) << 6;
14919 inst.instruction |= (et.type == NT_float) << 10;
14920 inst.instruction |= neon_logbits (et.size) << 18;
14921
14922 neon_dp_fixup (&inst);
14923 }
14924}
14925
14926static void
14927do_neon_cmp (void)
14928{
14929 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
14930}
14931
14932static void
14933do_neon_cmp_inv (void)
14934{
14935 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
14936}
14937
14938static void
14939do_neon_ceq (void)
14940{
14941 neon_compare (N_IF_32, N_IF_32, FALSE);
14942}
14943
14944/* For multiply instructions, we have the possibility of 16-bit or 32-bit
14945 scalars, which are encoded in 5 bits, M : Rm.
14946 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14947 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14948 index in M. */
14949
14950static unsigned
14951neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14952{
14953 unsigned regno = NEON_SCALAR_REG (scalar);
14954 unsigned elno = NEON_SCALAR_INDEX (scalar);
14955
14956 switch (elsize)
14957 {
14958 case 16:
14959 if (regno > 7 || elno > 3)
14960 goto bad_scalar;
14961 return regno | (elno << 3);
14962
14963 case 32:
14964 if (regno > 15 || elno > 1)
14965 goto bad_scalar;
14966 return regno | (elno << 4);
14967
14968 default:
14969 bad_scalar:
14970 first_error (_("scalar out of range for multiply instruction"));
14971 }
14972
14973 return 0;
14974}
14975
14976/* Encode multiply / multiply-accumulate scalar instructions. */
14977
14978static void
14979neon_mul_mac (struct neon_type_el et, int ubit)
14980{
14981 unsigned scalar;
14982
14983 /* Give a more helpful error message if we have an invalid type. */
14984 if (et.type == NT_invtype)
14985 return;
14986
14987 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14988 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14989 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14990 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14991 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14992 inst.instruction |= LOW4 (scalar);
14993 inst.instruction |= HI1 (scalar) << 5;
14994 inst.instruction |= (et.type == NT_float) << 8;
14995 inst.instruction |= neon_logbits (et.size) << 20;
14996 inst.instruction |= (ubit != 0) << 24;
14997
14998 neon_dp_fixup (&inst);
14999}
15000
15001static void
15002do_neon_mac_maybe_scalar (void)
15003{
15004 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
15005 return;
15006
15007 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15008 return;
15009
15010 if (inst.operands[2].isscalar)
15011 {
15012 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
15013 struct neon_type_el et = neon_check_type (3, rs,
15014 N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
15015 NEON_ENCODE (SCALAR, inst);
15016 neon_mul_mac (et, neon_quad (rs));
15017 }
15018 else
15019 {
15020 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15021 affected if we specify unsigned args. */
15022 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
15023 }
15024}
15025
15026static void
15027do_neon_fmac (void)
15028{
15029 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
15030 return;
15031
15032 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15033 return;
15034
15035 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
15036}
15037
15038static void
15039do_neon_tst (void)
15040{
15041 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15042 struct neon_type_el et = neon_check_type (3, rs,
15043 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
15044 neon_three_same (neon_quad (rs), 0, et.size);
15045}
15046
15047/* VMUL with 3 registers allows the P8 type. The scalar version supports the
15048 same types as the MAC equivalents. The polynomial type for this instruction
15049 is encoded the same as the integer type. */
15050
15051static void
15052do_neon_mul (void)
15053{
15054 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
15055 return;
15056
15057 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15058 return;
15059
15060 if (inst.operands[2].isscalar)
15061 do_neon_mac_maybe_scalar ();
15062 else
15063 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
15064}
15065
15066static void
15067do_neon_qdmulh (void)
15068{
15069 if (inst.operands[2].isscalar)
15070 {
15071 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
15072 struct neon_type_el et = neon_check_type (3, rs,
15073 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15074 NEON_ENCODE (SCALAR, inst);
15075 neon_mul_mac (et, neon_quad (rs));
15076 }
15077 else
15078 {
15079 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15080 struct neon_type_el et = neon_check_type (3, rs,
15081 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15082 NEON_ENCODE (INTEGER, inst);
15083 /* The U bit (rounding) comes from bit mask. */
15084 neon_three_same (neon_quad (rs), 0, et.size);
15085 }
15086}
15087
15088static void
15089do_neon_qrdmlah (void)
15090{
15091 /* Check we're on the correct architecture. */
15092 if (!mark_feature_used (&fpu_neon_ext_armv8))
15093 inst.error =
15094 _("instruction form not available on this architecture.");
15095 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
15096 {
15097 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15098 record_feature_use (&fpu_neon_ext_v8_1);
15099 }
15100
15101 if (inst.operands[2].isscalar)
15102 {
15103 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
15104 struct neon_type_el et = neon_check_type (3, rs,
15105 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15106 NEON_ENCODE (SCALAR, inst);
15107 neon_mul_mac (et, neon_quad (rs));
15108 }
15109 else
15110 {
15111 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15112 struct neon_type_el et = neon_check_type (3, rs,
15113 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15114 NEON_ENCODE (INTEGER, inst);
15115 /* The U bit (rounding) comes from bit mask. */
15116 neon_three_same (neon_quad (rs), 0, et.size);
15117 }
15118}
15119
15120static void
15121do_neon_fcmp_absolute (void)
15122{
15123 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15124 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
15125 N_F_16_32 | N_KEY);
15126 /* Size field comes from bit mask. */
15127 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
15128}
15129
15130static void
15131do_neon_fcmp_absolute_inv (void)
15132{
15133 neon_exchange_operands ();
15134 do_neon_fcmp_absolute ();
15135}
15136
15137static void
15138do_neon_step (void)
15139{
15140 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15141 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
15142 N_F_16_32 | N_KEY);
15143 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
15144}
15145
15146static void
15147do_neon_abs_neg (void)
15148{
15149 enum neon_shape rs;
15150 struct neon_type_el et;
15151
15152 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
15153 return;
15154
15155 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15156 return;
15157
15158 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15159 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
15160
15161 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15162 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15163 inst.instruction |= LOW4 (inst.operands[1].reg);
15164 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15165 inst.instruction |= neon_quad (rs) << 6;
15166 inst.instruction |= (et.type == NT_float) << 10;
15167 inst.instruction |= neon_logbits (et.size) << 18;
15168
15169 neon_dp_fixup (&inst);
15170}
15171
15172static void
15173do_neon_sli (void)
15174{
15175 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15176 struct neon_type_el et = neon_check_type (2, rs,
15177 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15178 int imm = inst.operands[2].imm;
15179 constraint (imm < 0 || (unsigned)imm >= et.size,
15180 _("immediate out of range for insert"));
15181 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
15182}
15183
15184static void
15185do_neon_sri (void)
15186{
15187 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15188 struct neon_type_el et = neon_check_type (2, rs,
15189 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15190 int imm = inst.operands[2].imm;
15191 constraint (imm < 1 || (unsigned)imm > et.size,
15192 _("immediate out of range for insert"));
15193 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
15194}
15195
15196static void
15197do_neon_qshlu_imm (void)
15198{
15199 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15200 struct neon_type_el et = neon_check_type (2, rs,
15201 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
15202 int imm = inst.operands[2].imm;
15203 constraint (imm < 0 || (unsigned)imm >= et.size,
15204 _("immediate out of range for shift"));
15205 /* Only encodes the 'U present' variant of the instruction.
15206 In this case, signed types have OP (bit 8) set to 0.
15207 Unsigned types have OP set to 1. */
15208 inst.instruction |= (et.type == NT_unsigned) << 8;
15209 /* The rest of the bits are the same as other immediate shifts. */
15210 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
15211}
15212
15213static void
15214do_neon_qmovn (void)
15215{
15216 struct neon_type_el et = neon_check_type (2, NS_DQ,
15217 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
15218 /* Saturating move where operands can be signed or unsigned, and the
15219 destination has the same signedness. */
15220 NEON_ENCODE (INTEGER, inst);
15221 if (et.type == NT_unsigned)
15222 inst.instruction |= 0xc0;
15223 else
15224 inst.instruction |= 0x80;
15225 neon_two_same (0, 1, et.size / 2);
15226}
15227
15228static void
15229do_neon_qmovun (void)
15230{
15231 struct neon_type_el et = neon_check_type (2, NS_DQ,
15232 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
15233 /* Saturating move with unsigned results. Operands must be signed. */
15234 NEON_ENCODE (INTEGER, inst);
15235 neon_two_same (0, 1, et.size / 2);
15236}
15237
15238static void
15239do_neon_rshift_sat_narrow (void)
15240{
15241 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15242 or unsigned. If operands are unsigned, results must also be unsigned. */
15243 struct neon_type_el et = neon_check_type (2, NS_DQI,
15244 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
15245 int imm = inst.operands[2].imm;
15246 /* This gets the bounds check, size encoding and immediate bits calculation
15247 right. */
15248 et.size /= 2;
15249
15250 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15251 VQMOVN.I<size> <Dd>, <Qm>. */
15252 if (imm == 0)
15253 {
15254 inst.operands[2].present = 0;
15255 inst.instruction = N_MNEM_vqmovn;
15256 do_neon_qmovn ();
15257 return;
15258 }
15259
15260 constraint (imm < 1 || (unsigned)imm > et.size,
15261 _("immediate out of range"));
15262 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
15263}
15264
15265static void
15266do_neon_rshift_sat_narrow_u (void)
15267{
15268 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15269 or unsigned. If operands are unsigned, results must also be unsigned. */
15270 struct neon_type_el et = neon_check_type (2, NS_DQI,
15271 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
15272 int imm = inst.operands[2].imm;
15273 /* This gets the bounds check, size encoding and immediate bits calculation
15274 right. */
15275 et.size /= 2;
15276
15277 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15278 VQMOVUN.I<size> <Dd>, <Qm>. */
15279 if (imm == 0)
15280 {
15281 inst.operands[2].present = 0;
15282 inst.instruction = N_MNEM_vqmovun;
15283 do_neon_qmovun ();
15284 return;
15285 }
15286
15287 constraint (imm < 1 || (unsigned)imm > et.size,
15288 _("immediate out of range"));
15289 /* FIXME: The manual is kind of unclear about what value U should have in
15290 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15291 must be 1. */
15292 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
15293}
15294
15295static void
15296do_neon_movn (void)
15297{
15298 struct neon_type_el et = neon_check_type (2, NS_DQ,
15299 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
15300 NEON_ENCODE (INTEGER, inst);
15301 neon_two_same (0, 1, et.size / 2);
15302}
15303
15304static void
15305do_neon_rshift_narrow (void)
15306{
15307 struct neon_type_el et = neon_check_type (2, NS_DQI,
15308 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
15309 int imm = inst.operands[2].imm;
15310 /* This gets the bounds check, size encoding and immediate bits calculation
15311 right. */
15312 et.size /= 2;
15313
15314 /* If immediate is zero then we are a pseudo-instruction for
15315 VMOVN.I<size> <Dd>, <Qm> */
15316 if (imm == 0)
15317 {
15318 inst.operands[2].present = 0;
15319 inst.instruction = N_MNEM_vmovn;
15320 do_neon_movn ();
15321 return;
15322 }
15323
15324 constraint (imm < 1 || (unsigned)imm > et.size,
15325 _("immediate out of range for narrowing operation"));
15326 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
15327}
15328
15329static void
15330do_neon_shll (void)
15331{
15332 /* FIXME: Type checking when lengthening. */
15333 struct neon_type_el et = neon_check_type (2, NS_QDI,
15334 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
15335 unsigned imm = inst.operands[2].imm;
15336
15337 if (imm == et.size)
15338 {
15339 /* Maximum shift variant. */
15340 NEON_ENCODE (INTEGER, inst);
15341 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15342 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15343 inst.instruction |= LOW4 (inst.operands[1].reg);
15344 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15345 inst.instruction |= neon_logbits (et.size) << 18;
15346
15347 neon_dp_fixup (&inst);
15348 }
15349 else
15350 {
15351 /* A more-specific type check for non-max versions. */
15352 et = neon_check_type (2, NS_QDI,
15353 N_EQK | N_DBL, N_SU_32 | N_KEY);
15354 NEON_ENCODE (IMMED, inst);
15355 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
15356 }
15357}
15358
15359/* Check the various types for the VCVT instruction, and return which version
15360 the current instruction is. */
15361
15362#define CVT_FLAVOUR_VAR \
15363 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15364 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15365 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15366 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15367 /* Half-precision conversions. */ \
15368 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15369 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15370 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15371 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15372 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15373 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15374 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15375 Compared with single/double precision variants, only the co-processor \
15376 field is different, so the encoding flow is reused here. */ \
15377 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15378 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15379 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15380 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15381 /* VFP instructions. */ \
15382 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15383 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15384 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15385 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15386 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15387 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15388 /* VFP instructions with bitshift. */ \
15389 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15390 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15391 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15392 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15393 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15394 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15395 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15396 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15397
15398#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15399 neon_cvt_flavour_##C,
15400
15401/* The different types of conversions we can do. */
15402enum neon_cvt_flavour
15403{
15404 CVT_FLAVOUR_VAR
15405 neon_cvt_flavour_invalid,
15406 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
15407};
15408
15409#undef CVT_VAR
15410
15411static enum neon_cvt_flavour
15412get_neon_cvt_flavour (enum neon_shape rs)
15413{
15414#define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15415 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15416 if (et.type != NT_invtype) \
15417 { \
15418 inst.error = NULL; \
15419 return (neon_cvt_flavour_##C); \
15420 }
15421
15422 struct neon_type_el et;
15423 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
15424 || rs == NS_FF) ? N_VFP : 0;
15425 /* The instruction versions which take an immediate take one register
15426 argument, which is extended to the width of the full register. Thus the
15427 "source" and "destination" registers must have the same width. Hack that
15428 here by making the size equal to the key (wider, in this case) operand. */
15429 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
15430
15431 CVT_FLAVOUR_VAR;
15432
15433 return neon_cvt_flavour_invalid;
15434#undef CVT_VAR
15435}
15436
15437enum neon_cvt_mode
15438{
15439 neon_cvt_mode_a,
15440 neon_cvt_mode_n,
15441 neon_cvt_mode_p,
15442 neon_cvt_mode_m,
15443 neon_cvt_mode_z,
15444 neon_cvt_mode_x,
15445 neon_cvt_mode_r
15446};
15447
15448/* Neon-syntax VFP conversions. */
15449
15450static void
15451do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
15452{
15453 const char *opname = 0;
15454
15455 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
15456 || rs == NS_FHI || rs == NS_HFI)
15457 {
15458 /* Conversions with immediate bitshift. */
15459 const char *enc[] =
15460 {
15461#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15462 CVT_FLAVOUR_VAR
15463 NULL
15464#undef CVT_VAR
15465 };
15466
15467 if (flavour < (int) ARRAY_SIZE (enc))
15468 {
15469 opname = enc[flavour];
15470 constraint (inst.operands[0].reg != inst.operands[1].reg,
15471 _("operands 0 and 1 must be the same register"));
15472 inst.operands[1] = inst.operands[2];
15473 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
15474 }
15475 }
15476 else
15477 {
15478 /* Conversions without bitshift. */
15479 const char *enc[] =
15480 {
15481#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15482 CVT_FLAVOUR_VAR
15483 NULL
15484#undef CVT_VAR
15485 };
15486
15487 if (flavour < (int) ARRAY_SIZE (enc))
15488 opname = enc[flavour];
15489 }
15490
15491 if (opname)
15492 do_vfp_nsyn_opcode (opname);
15493
15494 /* ARMv8.2 fp16 VCVT instruction. */
15495 if (flavour == neon_cvt_flavour_s32_f16
15496 || flavour == neon_cvt_flavour_u32_f16
15497 || flavour == neon_cvt_flavour_f16_u32
15498 || flavour == neon_cvt_flavour_f16_s32)
15499 do_scalar_fp16_v82_encode ();
15500}
15501
15502static void
15503do_vfp_nsyn_cvtz (void)
15504{
15505 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
15506 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
15507 const char *enc[] =
15508 {
15509#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15510 CVT_FLAVOUR_VAR
15511 NULL
15512#undef CVT_VAR
15513 };
15514
15515 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
15516 do_vfp_nsyn_opcode (enc[flavour]);
15517}
15518
15519static void
15520do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
15521 enum neon_cvt_mode mode)
15522{
15523 int sz, op;
15524 int rm;
15525
15526 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15527 D register operands. */
15528 if (flavour == neon_cvt_flavour_s32_f64
15529 || flavour == neon_cvt_flavour_u32_f64)
15530 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15531 _(BAD_FPU));
15532
15533 if (flavour == neon_cvt_flavour_s32_f16
15534 || flavour == neon_cvt_flavour_u32_f16)
15535 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
15536 _(BAD_FP16));
15537
15538 set_it_insn_type (OUTSIDE_IT_INSN);
15539
15540 switch (flavour)
15541 {
15542 case neon_cvt_flavour_s32_f64:
15543 sz = 1;
15544 op = 1;
15545 break;
15546 case neon_cvt_flavour_s32_f32:
15547 sz = 0;
15548 op = 1;
15549 break;
15550 case neon_cvt_flavour_s32_f16:
15551 sz = 0;
15552 op = 1;
15553 break;
15554 case neon_cvt_flavour_u32_f64:
15555 sz = 1;
15556 op = 0;
15557 break;
15558 case neon_cvt_flavour_u32_f32:
15559 sz = 0;
15560 op = 0;
15561 break;
15562 case neon_cvt_flavour_u32_f16:
15563 sz = 0;
15564 op = 0;
15565 break;
15566 default:
15567 first_error (_("invalid instruction shape"));
15568 return;
15569 }
15570
15571 switch (mode)
15572 {
15573 case neon_cvt_mode_a: rm = 0; break;
15574 case neon_cvt_mode_n: rm = 1; break;
15575 case neon_cvt_mode_p: rm = 2; break;
15576 case neon_cvt_mode_m: rm = 3; break;
15577 default: first_error (_("invalid rounding mode")); return;
15578 }
15579
15580 NEON_ENCODE (FPV8, inst);
15581 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
15582 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
15583 inst.instruction |= sz << 8;
15584
15585 /* ARMv8.2 fp16 VCVT instruction. */
15586 if (flavour == neon_cvt_flavour_s32_f16
15587 ||flavour == neon_cvt_flavour_u32_f16)
15588 do_scalar_fp16_v82_encode ();
15589 inst.instruction |= op << 7;
15590 inst.instruction |= rm << 16;
15591 inst.instruction |= 0xf0000000;
15592 inst.is_neon = TRUE;
15593}
15594
15595static void
15596do_neon_cvt_1 (enum neon_cvt_mode mode)
15597{
15598 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
15599 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
15600 NS_FH, NS_HF, NS_FHI, NS_HFI,
15601 NS_NULL);
15602 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
15603
15604 if (flavour == neon_cvt_flavour_invalid)
15605 return;
15606
15607 /* PR11109: Handle round-to-zero for VCVT conversions. */
15608 if (mode == neon_cvt_mode_z
15609 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
15610 && (flavour == neon_cvt_flavour_s16_f16
15611 || flavour == neon_cvt_flavour_u16_f16
15612 || flavour == neon_cvt_flavour_s32_f32
15613 || flavour == neon_cvt_flavour_u32_f32
15614 || flavour == neon_cvt_flavour_s32_f64
15615 || flavour == neon_cvt_flavour_u32_f64)
15616 && (rs == NS_FD || rs == NS_FF))
15617 {
15618 do_vfp_nsyn_cvtz ();
15619 return;
15620 }
15621
15622 /* ARMv8.2 fp16 VCVT conversions. */
15623 if (mode == neon_cvt_mode_z
15624 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
15625 && (flavour == neon_cvt_flavour_s32_f16
15626 || flavour == neon_cvt_flavour_u32_f16)
15627 && (rs == NS_FH))
15628 {
15629 do_vfp_nsyn_cvtz ();
15630 do_scalar_fp16_v82_encode ();
15631 return;
15632 }
15633
15634 /* VFP rather than Neon conversions. */
15635 if (flavour >= neon_cvt_flavour_first_fp)
15636 {
15637 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15638 do_vfp_nsyn_cvt (rs, flavour);
15639 else
15640 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
15641
15642 return;
15643 }
15644
15645 switch (rs)
15646 {
15647 case NS_DDI:
15648 case NS_QQI:
15649 {
15650 unsigned immbits;
15651 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15652 0x0000100, 0x1000100, 0x0, 0x1000000};
15653
15654 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15655 return;
15656
15657 /* Fixed-point conversion with #0 immediate is encoded as an
15658 integer conversion. */
15659 if (inst.operands[2].present && inst.operands[2].imm == 0)
15660 goto int_encode;
15661 NEON_ENCODE (IMMED, inst);
15662 if (flavour != neon_cvt_flavour_invalid)
15663 inst.instruction |= enctab[flavour];
15664 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15665 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15666 inst.instruction |= LOW4 (inst.operands[1].reg);
15667 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15668 inst.instruction |= neon_quad (rs) << 6;
15669 inst.instruction |= 1 << 21;
15670 if (flavour < neon_cvt_flavour_s16_f16)
15671 {
15672 inst.instruction |= 1 << 21;
15673 immbits = 32 - inst.operands[2].imm;
15674 inst.instruction |= immbits << 16;
15675 }
15676 else
15677 {
15678 inst.instruction |= 3 << 20;
15679 immbits = 16 - inst.operands[2].imm;
15680 inst.instruction |= immbits << 16;
15681 inst.instruction &= ~(1 << 9);
15682 }
15683
15684 neon_dp_fixup (&inst);
15685 }
15686 break;
15687
15688 case NS_DD:
15689 case NS_QQ:
15690 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
15691 {
15692 NEON_ENCODE (FLOAT, inst);
15693 set_it_insn_type (OUTSIDE_IT_INSN);
15694
15695 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
15696 return;
15697
15698 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15699 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15700 inst.instruction |= LOW4 (inst.operands[1].reg);
15701 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15702 inst.instruction |= neon_quad (rs) << 6;
15703 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
15704 || flavour == neon_cvt_flavour_u32_f32) << 7;
15705 inst.instruction |= mode << 8;
15706 if (flavour == neon_cvt_flavour_u16_f16
15707 || flavour == neon_cvt_flavour_s16_f16)
15708 /* Mask off the original size bits and reencode them. */
15709 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
15710
15711 if (thumb_mode)
15712 inst.instruction |= 0xfc000000;
15713 else
15714 inst.instruction |= 0xf0000000;
15715 }
15716 else
15717 {
15718 int_encode:
15719 {
15720 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
15721 0x100, 0x180, 0x0, 0x080};
15722
15723 NEON_ENCODE (INTEGER, inst);
15724
15725 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15726 return;
15727
15728 if (flavour != neon_cvt_flavour_invalid)
15729 inst.instruction |= enctab[flavour];
15730
15731 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15732 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15733 inst.instruction |= LOW4 (inst.operands[1].reg);
15734 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15735 inst.instruction |= neon_quad (rs) << 6;
15736 if (flavour >= neon_cvt_flavour_s16_f16
15737 && flavour <= neon_cvt_flavour_f16_u16)
15738 /* Half precision. */
15739 inst.instruction |= 1 << 18;
15740 else
15741 inst.instruction |= 2 << 18;
15742
15743 neon_dp_fixup (&inst);
15744 }
15745 }
15746 break;
15747
15748 /* Half-precision conversions for Advanced SIMD -- neon. */
15749 case NS_QD:
15750 case NS_DQ:
15751
15752 if ((rs == NS_DQ)
15753 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
15754 {
15755 as_bad (_("operand size must match register width"));
15756 break;
15757 }
15758
15759 if ((rs == NS_QD)
15760 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
15761 {
15762 as_bad (_("operand size must match register width"));
15763 break;
15764 }
15765
15766 if (rs == NS_DQ)
15767 inst.instruction = 0x3b60600;
15768 else
15769 inst.instruction = 0x3b60700;
15770
15771 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15772 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15773 inst.instruction |= LOW4 (inst.operands[1].reg);
15774 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15775 neon_dp_fixup (&inst);
15776 break;
15777
15778 default:
15779 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15780 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15781 do_vfp_nsyn_cvt (rs, flavour);
15782 else
15783 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
15784 }
15785}
15786
15787static void
15788do_neon_cvtr (void)
15789{
15790 do_neon_cvt_1 (neon_cvt_mode_x);
15791}
15792
15793static void
15794do_neon_cvt (void)
15795{
15796 do_neon_cvt_1 (neon_cvt_mode_z);
15797}
15798
15799static void
15800do_neon_cvta (void)
15801{
15802 do_neon_cvt_1 (neon_cvt_mode_a);
15803}
15804
15805static void
15806do_neon_cvtn (void)
15807{
15808 do_neon_cvt_1 (neon_cvt_mode_n);
15809}
15810
15811static void
15812do_neon_cvtp (void)
15813{
15814 do_neon_cvt_1 (neon_cvt_mode_p);
15815}
15816
15817static void
15818do_neon_cvtm (void)
15819{
15820 do_neon_cvt_1 (neon_cvt_mode_m);
15821}
15822
15823static void
15824do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
15825{
15826 if (is_double)
15827 mark_feature_used (&fpu_vfp_ext_armv8);
15828
15829 encode_arm_vfp_reg (inst.operands[0].reg,
15830 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
15831 encode_arm_vfp_reg (inst.operands[1].reg,
15832 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
15833 inst.instruction |= to ? 0x10000 : 0;
15834 inst.instruction |= t ? 0x80 : 0;
15835 inst.instruction |= is_double ? 0x100 : 0;
15836 do_vfp_cond_or_thumb ();
15837}
15838
15839static void
15840do_neon_cvttb_1 (bfd_boolean t)
15841{
15842 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
15843 NS_DF, NS_DH, NS_NULL);
15844
15845 if (rs == NS_NULL)
15846 return;
15847 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
15848 {
15849 inst.error = NULL;
15850 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
15851 }
15852 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
15853 {
15854 inst.error = NULL;
15855 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
15856 }
15857 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
15858 {
15859 /* The VCVTB and VCVTT instructions with D-register operands
15860 don't work for SP only targets. */
15861 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15862 _(BAD_FPU));
15863
15864 inst.error = NULL;
15865 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
15866 }
15867 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
15868 {
15869 /* The VCVTB and VCVTT instructions with D-register operands
15870 don't work for SP only targets. */
15871 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15872 _(BAD_FPU));
15873
15874 inst.error = NULL;
15875 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
15876 }
15877 else
15878 return;
15879}
15880
15881static void
15882do_neon_cvtb (void)
15883{
15884 do_neon_cvttb_1 (FALSE);
15885}
15886
15887
15888static void
15889do_neon_cvtt (void)
15890{
15891 do_neon_cvttb_1 (TRUE);
15892}
15893
15894static void
15895neon_move_immediate (void)
15896{
15897 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
15898 struct neon_type_el et = neon_check_type (2, rs,
15899 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
15900 unsigned immlo, immhi = 0, immbits;
15901 int op, cmode, float_p;
15902
15903 constraint (et.type == NT_invtype,
15904 _("operand size must be specified for immediate VMOV"));
15905
15906 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15907 op = (inst.instruction & (1 << 5)) != 0;
15908
15909 immlo = inst.operands[1].imm;
15910 if (inst.operands[1].regisimm)
15911 immhi = inst.operands[1].reg;
15912
15913 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
15914 _("immediate has bits set outside the operand size"));
15915
15916 float_p = inst.operands[1].immisfloat;
15917
15918 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
15919 et.size, et.type)) == FAIL)
15920 {
15921 /* Invert relevant bits only. */
15922 neon_invert_size (&immlo, &immhi, et.size);
15923 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15924 with one or the other; those cases are caught by
15925 neon_cmode_for_move_imm. */
15926 op = !op;
15927 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
15928 &op, et.size, et.type)) == FAIL)
15929 {
15930 first_error (_("immediate out of range"));
15931 return;
15932 }
15933 }
15934
15935 inst.instruction &= ~(1 << 5);
15936 inst.instruction |= op << 5;
15937
15938 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15939 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15940 inst.instruction |= neon_quad (rs) << 6;
15941 inst.instruction |= cmode << 8;
15942
15943 neon_write_immbits (immbits);
15944}
15945
15946static void
15947do_neon_mvn (void)
15948{
15949 if (inst.operands[1].isreg)
15950 {
15951 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15952
15953 NEON_ENCODE (INTEGER, inst);
15954 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15955 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15956 inst.instruction |= LOW4 (inst.operands[1].reg);
15957 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15958 inst.instruction |= neon_quad (rs) << 6;
15959 }
15960 else
15961 {
15962 NEON_ENCODE (IMMED, inst);
15963 neon_move_immediate ();
15964 }
15965
15966 neon_dp_fixup (&inst);
15967}
15968
15969/* Encode instructions of form:
15970
15971 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15972 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15973
15974static void
15975neon_mixed_length (struct neon_type_el et, unsigned size)
15976{
15977 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15978 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15979 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15980 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15981 inst.instruction |= LOW4 (inst.operands[2].reg);
15982 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15983 inst.instruction |= (et.type == NT_unsigned) << 24;
15984 inst.instruction |= neon_logbits (size) << 20;
15985
15986 neon_dp_fixup (&inst);
15987}
15988
15989static void
15990do_neon_dyadic_long (void)
15991{
15992 /* FIXME: Type checking for lengthening op. */
15993 struct neon_type_el et = neon_check_type (3, NS_QDD,
15994 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15995 neon_mixed_length (et, et.size);
15996}
15997
15998static void
15999do_neon_abal (void)
16000{
16001 struct neon_type_el et = neon_check_type (3, NS_QDD,
16002 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
16003 neon_mixed_length (et, et.size);
16004}
16005
16006static void
16007neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
16008{
16009 if (inst.operands[2].isscalar)
16010 {
16011 struct neon_type_el et = neon_check_type (3, NS_QDS,
16012 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
16013 NEON_ENCODE (SCALAR, inst);
16014 neon_mul_mac (et, et.type == NT_unsigned);
16015 }
16016 else
16017 {
16018 struct neon_type_el et = neon_check_type (3, NS_QDD,
16019 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
16020 NEON_ENCODE (INTEGER, inst);
16021 neon_mixed_length (et, et.size);
16022 }
16023}
16024
16025static void
16026do_neon_mac_maybe_scalar_long (void)
16027{
16028 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
16029}
16030
16031static void
16032do_neon_dyadic_wide (void)
16033{
16034 struct neon_type_el et = neon_check_type (3, NS_QQD,
16035 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
16036 neon_mixed_length (et, et.size);
16037}
16038
16039static void
16040do_neon_dyadic_narrow (void)
16041{
16042 struct neon_type_el et = neon_check_type (3, NS_QDD,
16043 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
16044 /* Operand sign is unimportant, and the U bit is part of the opcode,
16045 so force the operand type to integer. */
16046 et.type = NT_integer;
16047 neon_mixed_length (et, et.size / 2);
16048}
16049
16050static void
16051do_neon_mul_sat_scalar_long (void)
16052{
16053 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
16054}
16055
16056static void
16057do_neon_vmull (void)
16058{
16059 if (inst.operands[2].isscalar)
16060 do_neon_mac_maybe_scalar_long ();
16061 else
16062 {
16063 struct neon_type_el et = neon_check_type (3, NS_QDD,
16064 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
16065
16066 if (et.type == NT_poly)
16067 NEON_ENCODE (POLY, inst);
16068 else
16069 NEON_ENCODE (INTEGER, inst);
16070
16071 /* For polynomial encoding the U bit must be zero, and the size must
16072 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16073 obviously, as 0b10). */
16074 if (et.size == 64)
16075 {
16076 /* Check we're on the correct architecture. */
16077 if (!mark_feature_used (&fpu_crypto_ext_armv8))
16078 inst.error =
16079 _("Instruction form not available on this architecture.");
16080
16081 et.size = 32;
16082 }
16083
16084 neon_mixed_length (et, et.size);
16085 }
16086}
16087
16088static void
16089do_neon_ext (void)
16090{
16091 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
16092 struct neon_type_el et = neon_check_type (3, rs,
16093 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
16094 unsigned imm = (inst.operands[3].imm * et.size) / 8;
16095
16096 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
16097 _("shift out of range"));
16098 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16099 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16100 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16101 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16102 inst.instruction |= LOW4 (inst.operands[2].reg);
16103 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16104 inst.instruction |= neon_quad (rs) << 6;
16105 inst.instruction |= imm << 8;
16106
16107 neon_dp_fixup (&inst);
16108}
16109
16110static void
16111do_neon_rev (void)
16112{
16113 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16114 struct neon_type_el et = neon_check_type (2, rs,
16115 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16116 unsigned op = (inst.instruction >> 7) & 3;
16117 /* N (width of reversed regions) is encoded as part of the bitmask. We
16118 extract it here to check the elements to be reversed are smaller.
16119 Otherwise we'd get a reserved instruction. */
16120 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
16121 gas_assert (elsize != 0);
16122 constraint (et.size >= elsize,
16123 _("elements must be smaller than reversal region"));
16124 neon_two_same (neon_quad (rs), 1, et.size);
16125}
16126
16127static void
16128do_neon_dup (void)
16129{
16130 if (inst.operands[1].isscalar)
16131 {
16132 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
16133 struct neon_type_el et = neon_check_type (2, rs,
16134 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16135 unsigned sizebits = et.size >> 3;
16136 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
16137 int logsize = neon_logbits (et.size);
16138 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
16139
16140 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
16141 return;
16142
16143 NEON_ENCODE (SCALAR, inst);
16144 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16145 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16146 inst.instruction |= LOW4 (dm);
16147 inst.instruction |= HI1 (dm) << 5;
16148 inst.instruction |= neon_quad (rs) << 6;
16149 inst.instruction |= x << 17;
16150 inst.instruction |= sizebits << 16;
16151
16152 neon_dp_fixup (&inst);
16153 }
16154 else
16155 {
16156 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
16157 struct neon_type_el et = neon_check_type (2, rs,
16158 N_8 | N_16 | N_32 | N_KEY, N_EQK);
16159 /* Duplicate ARM register to lanes of vector. */
16160 NEON_ENCODE (ARMREG, inst);
16161 switch (et.size)
16162 {
16163 case 8: inst.instruction |= 0x400000; break;
16164 case 16: inst.instruction |= 0x000020; break;
16165 case 32: inst.instruction |= 0x000000; break;
16166 default: break;
16167 }
16168 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
16169 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
16170 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
16171 inst.instruction |= neon_quad (rs) << 21;
16172 /* The encoding for this instruction is identical for the ARM and Thumb
16173 variants, except for the condition field. */
16174 do_vfp_cond_or_thumb ();
16175 }
16176}
16177
16178/* VMOV has particularly many variations. It can be one of:
16179 0. VMOV<c><q> <Qd>, <Qm>
16180 1. VMOV<c><q> <Dd>, <Dm>
16181 (Register operations, which are VORR with Rm = Rn.)
16182 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16183 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16184 (Immediate loads.)
16185 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16186 (ARM register to scalar.)
16187 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16188 (Two ARM registers to vector.)
16189 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16190 (Scalar to ARM register.)
16191 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16192 (Vector to two ARM registers.)
16193 8. VMOV.F32 <Sd>, <Sm>
16194 9. VMOV.F64 <Dd>, <Dm>
16195 (VFP register moves.)
16196 10. VMOV.F32 <Sd>, #imm
16197 11. VMOV.F64 <Dd>, #imm
16198 (VFP float immediate load.)
16199 12. VMOV <Rd>, <Sm>
16200 (VFP single to ARM reg.)
16201 13. VMOV <Sd>, <Rm>
16202 (ARM reg to VFP single.)
16203 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16204 (Two ARM regs to two VFP singles.)
16205 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16206 (Two VFP singles to two ARM regs.)
16207
16208 These cases can be disambiguated using neon_select_shape, except cases 1/9
16209 and 3/11 which depend on the operand type too.
16210
16211 All the encoded bits are hardcoded by this function.
16212
16213 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16214 Cases 5, 7 may be used with VFPv2 and above.
16215
16216 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16217 can specify a type where it doesn't make sense to, and is ignored). */
16218
16219static void
16220do_neon_mov (void)
16221{
16222 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
16223 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR,
16224 NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
16225 NS_HR, NS_RH, NS_HI, NS_NULL);
16226 struct neon_type_el et;
16227 const char *ldconst = 0;
16228
16229 switch (rs)
16230 {
16231 case NS_DD: /* case 1/9. */
16232 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
16233 /* It is not an error here if no type is given. */
16234 inst.error = NULL;
16235 if (et.type == NT_float && et.size == 64)
16236 {
16237 do_vfp_nsyn_opcode ("fcpyd");
16238 break;
16239 }
16240 /* fall through. */
16241
16242 case NS_QQ: /* case 0/1. */
16243 {
16244 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
16245 return;
16246 /* The architecture manual I have doesn't explicitly state which
16247 value the U bit should have for register->register moves, but
16248 the equivalent VORR instruction has U = 0, so do that. */
16249 inst.instruction = 0x0200110;
16250 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16251 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16252 inst.instruction |= LOW4 (inst.operands[1].reg);
16253 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16254 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16255 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16256 inst.instruction |= neon_quad (rs) << 6;
16257
16258 neon_dp_fixup (&inst);
16259 }
16260 break;
16261
16262 case NS_DI: /* case 3/11. */
16263 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
16264 inst.error = NULL;
16265 if (et.type == NT_float && et.size == 64)
16266 {
16267 /* case 11 (fconstd). */
16268 ldconst = "fconstd";
16269 goto encode_fconstd;
16270 }
16271 /* fall through. */
16272
16273 case NS_QI: /* case 2/3. */
16274 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
16275 return;
16276 inst.instruction = 0x0800010;
16277 neon_move_immediate ();
16278 neon_dp_fixup (&inst);
16279 break;
16280
16281 case NS_SR: /* case 4. */
16282 {
16283 unsigned bcdebits = 0;
16284 int logsize;
16285 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
16286 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
16287
16288 /* .<size> is optional here, defaulting to .32. */
16289 if (inst.vectype.elems == 0
16290 && inst.operands[0].vectype.type == NT_invtype
16291 && inst.operands[1].vectype.type == NT_invtype)
16292 {
16293 inst.vectype.el[0].type = NT_untyped;
16294 inst.vectype.el[0].size = 32;
16295 inst.vectype.elems = 1;
16296 }
16297
16298 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
16299 logsize = neon_logbits (et.size);
16300
16301 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
16302 _(BAD_FPU));
16303 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
16304 && et.size != 32, _(BAD_FPU));
16305 constraint (et.type == NT_invtype, _("bad type for scalar"));
16306 constraint (x >= 64 / et.size, _("scalar index out of range"));
16307
16308 switch (et.size)
16309 {
16310 case 8: bcdebits = 0x8; break;
16311 case 16: bcdebits = 0x1; break;
16312 case 32: bcdebits = 0x0; break;
16313 default: ;
16314 }
16315
16316 bcdebits |= x << logsize;
16317
16318 inst.instruction = 0xe000b10;
16319 do_vfp_cond_or_thumb ();
16320 inst.instruction |= LOW4 (dn) << 16;
16321 inst.instruction |= HI1 (dn) << 7;
16322 inst.instruction |= inst.operands[1].reg << 12;
16323 inst.instruction |= (bcdebits & 3) << 5;
16324 inst.instruction |= (bcdebits >> 2) << 21;
16325 }
16326 break;
16327
16328 case NS_DRR: /* case 5 (fmdrr). */
16329 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
16330 _(BAD_FPU));
16331
16332 inst.instruction = 0xc400b10;
16333 do_vfp_cond_or_thumb ();
16334 inst.instruction |= LOW4 (inst.operands[0].reg);
16335 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
16336 inst.instruction |= inst.operands[1].reg << 12;
16337 inst.instruction |= inst.operands[2].reg << 16;
16338 break;
16339
16340 case NS_RS: /* case 6. */
16341 {
16342 unsigned logsize;
16343 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
16344 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
16345 unsigned abcdebits = 0;
16346
16347 /* .<dt> is optional here, defaulting to .32. */
16348 if (inst.vectype.elems == 0
16349 && inst.operands[0].vectype.type == NT_invtype
16350 && inst.operands[1].vectype.type == NT_invtype)
16351 {
16352 inst.vectype.el[0].type = NT_untyped;
16353 inst.vectype.el[0].size = 32;
16354 inst.vectype.elems = 1;
16355 }
16356
16357 et = neon_check_type (2, NS_NULL,
16358 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
16359 logsize = neon_logbits (et.size);
16360
16361 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
16362 _(BAD_FPU));
16363 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
16364 && et.size != 32, _(BAD_FPU));
16365 constraint (et.type == NT_invtype, _("bad type for scalar"));
16366 constraint (x >= 64 / et.size, _("scalar index out of range"));
16367
16368 switch (et.size)
16369 {
16370 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
16371 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
16372 case 32: abcdebits = 0x00; break;
16373 default: ;
16374 }
16375
16376 abcdebits |= x << logsize;
16377 inst.instruction = 0xe100b10;
16378 do_vfp_cond_or_thumb ();
16379 inst.instruction |= LOW4 (dn) << 16;
16380 inst.instruction |= HI1 (dn) << 7;
16381 inst.instruction |= inst.operands[0].reg << 12;
16382 inst.instruction |= (abcdebits & 3) << 5;
16383 inst.instruction |= (abcdebits >> 2) << 21;
16384 }
16385 break;
16386
16387 case NS_RRD: /* case 7 (fmrrd). */
16388 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
16389 _(BAD_FPU));
16390
16391 inst.instruction = 0xc500b10;
16392 do_vfp_cond_or_thumb ();
16393 inst.instruction |= inst.operands[0].reg << 12;
16394 inst.instruction |= inst.operands[1].reg << 16;
16395 inst.instruction |= LOW4 (inst.operands[2].reg);
16396 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16397 break;
16398
16399 case NS_FF: /* case 8 (fcpys). */
16400 do_vfp_nsyn_opcode ("fcpys");
16401 break;
16402
16403 case NS_HI:
16404 case NS_FI: /* case 10 (fconsts). */
16405 ldconst = "fconsts";
16406 encode_fconstd:
16407 if (is_quarter_float (inst.operands[1].imm))
16408 {
16409 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
16410 do_vfp_nsyn_opcode (ldconst);
16411
16412 /* ARMv8.2 fp16 vmov.f16 instruction. */
16413 if (rs == NS_HI)
16414 do_scalar_fp16_v82_encode ();
16415 }
16416 else
16417 first_error (_("immediate out of range"));
16418 break;
16419
16420 case NS_RH:
16421 case NS_RF: /* case 12 (fmrs). */
16422 do_vfp_nsyn_opcode ("fmrs");
16423 /* ARMv8.2 fp16 vmov.f16 instruction. */
16424 if (rs == NS_RH)
16425 do_scalar_fp16_v82_encode ();
16426 break;
16427
16428 case NS_HR:
16429 case NS_FR: /* case 13 (fmsr). */
16430 do_vfp_nsyn_opcode ("fmsr");
16431 /* ARMv8.2 fp16 vmov.f16 instruction. */
16432 if (rs == NS_HR)
16433 do_scalar_fp16_v82_encode ();
16434 break;
16435
16436 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16437 (one of which is a list), but we have parsed four. Do some fiddling to
16438 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16439 expect. */
16440 case NS_RRFF: /* case 14 (fmrrs). */
16441 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
16442 _("VFP registers must be adjacent"));
16443 inst.operands[2].imm = 2;
16444 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
16445 do_vfp_nsyn_opcode ("fmrrs");
16446 break;
16447
16448 case NS_FFRR: /* case 15 (fmsrr). */
16449 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
16450 _("VFP registers must be adjacent"));
16451 inst.operands[1] = inst.operands[2];
16452 inst.operands[2] = inst.operands[3];
16453 inst.operands[0].imm = 2;
16454 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
16455 do_vfp_nsyn_opcode ("fmsrr");
16456 break;
16457
16458 case NS_NULL:
16459 /* neon_select_shape has determined that the instruction
16460 shape is wrong and has already set the error message. */
16461 break;
16462
16463 default:
16464 abort ();
16465 }
16466}
16467
16468static void
16469do_neon_rshift_round_imm (void)
16470{
16471 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16472 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
16473 int imm = inst.operands[2].imm;
16474
16475 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16476 if (imm == 0)
16477 {
16478 inst.operands[2].present = 0;
16479 do_neon_mov ();
16480 return;
16481 }
16482
16483 constraint (imm < 1 || (unsigned)imm > et.size,
16484 _("immediate out of range for shift"));
16485 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
16486 et.size - imm);
16487}
16488
16489static void
16490do_neon_movhf (void)
16491{
16492 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
16493 constraint (rs != NS_HH, _("invalid suffix"));
16494
16495 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16496 _(BAD_FPU));
16497
16498 do_vfp_sp_monadic ();
16499
16500 inst.is_neon = 1;
16501 inst.instruction |= 0xf0000000;
16502}
16503
16504static void
16505do_neon_movl (void)
16506{
16507 struct neon_type_el et = neon_check_type (2, NS_QD,
16508 N_EQK | N_DBL, N_SU_32 | N_KEY);
16509 unsigned sizebits = et.size >> 3;
16510 inst.instruction |= sizebits << 19;
16511 neon_two_same (0, et.type == NT_unsigned, -1);
16512}
16513
16514static void
16515do_neon_trn (void)
16516{
16517 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16518 struct neon_type_el et = neon_check_type (2, rs,
16519 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16520 NEON_ENCODE (INTEGER, inst);
16521 neon_two_same (neon_quad (rs), 1, et.size);
16522}
16523
16524static void
16525do_neon_zip_uzp (void)
16526{
16527 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16528 struct neon_type_el et = neon_check_type (2, rs,
16529 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16530 if (rs == NS_DD && et.size == 32)
16531 {
16532 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16533 inst.instruction = N_MNEM_vtrn;
16534 do_neon_trn ();
16535 return;
16536 }
16537 neon_two_same (neon_quad (rs), 1, et.size);
16538}
16539
16540static void
16541do_neon_sat_abs_neg (void)
16542{
16543 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16544 struct neon_type_el et = neon_check_type (2, rs,
16545 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
16546 neon_two_same (neon_quad (rs), 1, et.size);
16547}
16548
16549static void
16550do_neon_pair_long (void)
16551{
16552 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16553 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
16554 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16555 inst.instruction |= (et.type == NT_unsigned) << 7;
16556 neon_two_same (neon_quad (rs), 1, et.size);
16557}
16558
16559static void
16560do_neon_recip_est (void)
16561{
16562 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16563 struct neon_type_el et = neon_check_type (2, rs,
16564 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
16565 inst.instruction |= (et.type == NT_float) << 8;
16566 neon_two_same (neon_quad (rs), 1, et.size);
16567}
16568
16569static void
16570do_neon_cls (void)
16571{
16572 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16573 struct neon_type_el et = neon_check_type (2, rs,
16574 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
16575 neon_two_same (neon_quad (rs), 1, et.size);
16576}
16577
16578static void
16579do_neon_clz (void)
16580{
16581 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16582 struct neon_type_el et = neon_check_type (2, rs,
16583 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
16584 neon_two_same (neon_quad (rs), 1, et.size);
16585}
16586
16587static void
16588do_neon_cnt (void)
16589{
16590 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16591 struct neon_type_el et = neon_check_type (2, rs,
16592 N_EQK | N_INT, N_8 | N_KEY);
16593 neon_two_same (neon_quad (rs), 1, et.size);
16594}
16595
16596static void
16597do_neon_swp (void)
16598{
16599 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16600 neon_two_same (neon_quad (rs), 1, -1);
16601}
16602
16603static void
16604do_neon_tbl_tbx (void)
16605{
16606 unsigned listlenbits;
16607 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
16608
16609 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
16610 {
16611 first_error (_("bad list length for table lookup"));
16612 return;
16613 }
16614
16615 listlenbits = inst.operands[1].imm - 1;
16616 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16617 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16618 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16619 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16620 inst.instruction |= LOW4 (inst.operands[2].reg);
16621 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16622 inst.instruction |= listlenbits << 8;
16623
16624 neon_dp_fixup (&inst);
16625}
16626
16627static void
16628do_neon_ldm_stm (void)
16629{
16630 /* P, U and L bits are part of bitmask. */
16631 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
16632 unsigned offsetbits = inst.operands[1].imm * 2;
16633
16634 if (inst.operands[1].issingle)
16635 {
16636 do_vfp_nsyn_ldm_stm (is_dbmode);
16637 return;
16638 }
16639
16640 constraint (is_dbmode && !inst.operands[0].writeback,
16641 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16642
16643 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16644 _("register list must contain at least 1 and at most 16 "
16645 "registers"));
16646
16647 inst.instruction |= inst.operands[0].reg << 16;
16648 inst.instruction |= inst.operands[0].writeback << 21;
16649 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
16650 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
16651
16652 inst.instruction |= offsetbits;
16653
16654 do_vfp_cond_or_thumb ();
16655}
16656
16657static void
16658do_neon_ldr_str (void)
16659{
16660 int is_ldr = (inst.instruction & (1 << 20)) != 0;
16661
16662 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16663 And is UNPREDICTABLE in thumb mode. */
16664 if (!is_ldr
16665 && inst.operands[1].reg == REG_PC
16666 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
16667 {
16668 if (thumb_mode)
16669 inst.error = _("Use of PC here is UNPREDICTABLE");
16670 else if (warn_on_deprecated)
16671 as_tsktsk (_("Use of PC here is deprecated"));
16672 }
16673
16674 if (inst.operands[0].issingle)
16675 {
16676 if (is_ldr)
16677 do_vfp_nsyn_opcode ("flds");
16678 else
16679 do_vfp_nsyn_opcode ("fsts");
16680
16681 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16682 if (inst.vectype.el[0].size == 16)
16683 do_scalar_fp16_v82_encode ();
16684 }
16685 else
16686 {
16687 if (is_ldr)
16688 do_vfp_nsyn_opcode ("fldd");
16689 else
16690 do_vfp_nsyn_opcode ("fstd");
16691 }
16692}
16693
16694/* "interleave" version also handles non-interleaving register VLD1/VST1
16695 instructions. */
16696
16697static void
16698do_neon_ld_st_interleave (void)
16699{
16700 struct neon_type_el et = neon_check_type (1, NS_NULL,
16701 N_8 | N_16 | N_32 | N_64);
16702 unsigned alignbits = 0;
16703 unsigned idx;
16704 /* The bits in this table go:
16705 0: register stride of one (0) or two (1)
16706 1,2: register list length, minus one (1, 2, 3, 4).
16707 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16708 We use -1 for invalid entries. */
16709 const int typetable[] =
16710 {
16711 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16712 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16713 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16714 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16715 };
16716 int typebits;
16717
16718 if (et.type == NT_invtype)
16719 return;
16720
16721 if (inst.operands[1].immisalign)
16722 switch (inst.operands[1].imm >> 8)
16723 {
16724 case 64: alignbits = 1; break;
16725 case 128:
16726 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
16727 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
16728 goto bad_alignment;
16729 alignbits = 2;
16730 break;
16731 case 256:
16732 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
16733 goto bad_alignment;
16734 alignbits = 3;
16735 break;
16736 default:
16737 bad_alignment:
16738 first_error (_("bad alignment"));
16739 return;
16740 }
16741
16742 inst.instruction |= alignbits << 4;
16743 inst.instruction |= neon_logbits (et.size) << 6;
16744
16745 /* Bits [4:6] of the immediate in a list specifier encode register stride
16746 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16747 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16748 up the right value for "type" in a table based on this value and the given
16749 list style, then stick it back. */
16750 idx = ((inst.operands[0].imm >> 4) & 7)
16751 | (((inst.instruction >> 8) & 3) << 3);
16752
16753 typebits = typetable[idx];
16754
16755 constraint (typebits == -1, _("bad list type for instruction"));
16756 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
16757 _("bad element type for instruction"));
16758
16759 inst.instruction &= ~0xf00;
16760 inst.instruction |= typebits << 8;
16761}
16762
16763/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16764 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16765 otherwise. The variable arguments are a list of pairs of legal (size, align)
16766 values, terminated with -1. */
16767
16768static int
16769neon_alignment_bit (int size, int align, int *do_alignment, ...)
16770{
16771 va_list ap;
16772 int result = FAIL, thissize, thisalign;
16773
16774 if (!inst.operands[1].immisalign)
16775 {
16776 *do_alignment = 0;
16777 return SUCCESS;
16778 }
16779
16780 va_start (ap, do_alignment);
16781
16782 do
16783 {
16784 thissize = va_arg (ap, int);
16785 if (thissize == -1)
16786 break;
16787 thisalign = va_arg (ap, int);
16788
16789 if (size == thissize && align == thisalign)
16790 result = SUCCESS;
16791 }
16792 while (result != SUCCESS);
16793
16794 va_end (ap);
16795
16796 if (result == SUCCESS)
16797 *do_alignment = 1;
16798 else
16799 first_error (_("unsupported alignment for instruction"));
16800
16801 return result;
16802}
16803
16804static void
16805do_neon_ld_st_lane (void)
16806{
16807 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
16808 int align_good, do_alignment = 0;
16809 int logsize = neon_logbits (et.size);
16810 int align = inst.operands[1].imm >> 8;
16811 int n = (inst.instruction >> 8) & 3;
16812 int max_el = 64 / et.size;
16813
16814 if (et.type == NT_invtype)
16815 return;
16816
16817 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
16818 _("bad list length"));
16819 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
16820 _("scalar index out of range"));
16821 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
16822 && et.size == 8,
16823 _("stride of 2 unavailable when element size is 8"));
16824
16825 switch (n)
16826 {
16827 case 0: /* VLD1 / VST1. */
16828 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
16829 32, 32, -1);
16830 if (align_good == FAIL)
16831 return;
16832 if (do_alignment)
16833 {
16834 unsigned alignbits = 0;
16835 switch (et.size)
16836 {
16837 case 16: alignbits = 0x1; break;
16838 case 32: alignbits = 0x3; break;
16839 default: ;
16840 }
16841 inst.instruction |= alignbits << 4;
16842 }
16843 break;
16844
16845 case 1: /* VLD2 / VST2. */
16846 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
16847 16, 32, 32, 64, -1);
16848 if (align_good == FAIL)
16849 return;
16850 if (do_alignment)
16851 inst.instruction |= 1 << 4;
16852 break;
16853
16854 case 2: /* VLD3 / VST3. */
16855 constraint (inst.operands[1].immisalign,
16856 _("can't use alignment with this instruction"));
16857 break;
16858
16859 case 3: /* VLD4 / VST4. */
16860 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
16861 16, 64, 32, 64, 32, 128, -1);
16862 if (align_good == FAIL)
16863 return;
16864 if (do_alignment)
16865 {
16866 unsigned alignbits = 0;
16867 switch (et.size)
16868 {
16869 case 8: alignbits = 0x1; break;
16870 case 16: alignbits = 0x1; break;
16871 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
16872 default: ;
16873 }
16874 inst.instruction |= alignbits << 4;
16875 }
16876 break;
16877
16878 default: ;
16879 }
16880
16881 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16882 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16883 inst.instruction |= 1 << (4 + logsize);
16884
16885 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
16886 inst.instruction |= logsize << 10;
16887}
16888
16889/* Encode single n-element structure to all lanes VLD<n> instructions. */
16890
16891static void
16892do_neon_ld_dup (void)
16893{
16894 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
16895 int align_good, do_alignment = 0;
16896
16897 if (et.type == NT_invtype)
16898 return;
16899
16900 switch ((inst.instruction >> 8) & 3)
16901 {
16902 case 0: /* VLD1. */
16903 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
16904 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
16905 &do_alignment, 16, 16, 32, 32, -1);
16906 if (align_good == FAIL)
16907 return;
16908 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
16909 {
16910 case 1: break;
16911 case 2: inst.instruction |= 1 << 5; break;
16912 default: first_error (_("bad list length")); return;
16913 }
16914 inst.instruction |= neon_logbits (et.size) << 6;
16915 break;
16916
16917 case 1: /* VLD2. */
16918 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
16919 &do_alignment, 8, 16, 16, 32, 32, 64,
16920 -1);
16921 if (align_good == FAIL)
16922 return;
16923 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
16924 _("bad list length"));
16925 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16926 inst.instruction |= 1 << 5;
16927 inst.instruction |= neon_logbits (et.size) << 6;
16928 break;
16929
16930 case 2: /* VLD3. */
16931 constraint (inst.operands[1].immisalign,
16932 _("can't use alignment with this instruction"));
16933 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
16934 _("bad list length"));
16935 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16936 inst.instruction |= 1 << 5;
16937 inst.instruction |= neon_logbits (et.size) << 6;
16938 break;
16939
16940 case 3: /* VLD4. */
16941 {
16942 int align = inst.operands[1].imm >> 8;
16943 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
16944 16, 64, 32, 64, 32, 128, -1);
16945 if (align_good == FAIL)
16946 return;
16947 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
16948 _("bad list length"));
16949 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16950 inst.instruction |= 1 << 5;
16951 if (et.size == 32 && align == 128)
16952 inst.instruction |= 0x3 << 6;
16953 else
16954 inst.instruction |= neon_logbits (et.size) << 6;
16955 }
16956 break;
16957
16958 default: ;
16959 }
16960
16961 inst.instruction |= do_alignment << 4;
16962}
16963
16964/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16965 apart from bits [11:4]. */
16966
16967static void
16968do_neon_ldx_stx (void)
16969{
16970 if (inst.operands[1].isreg)
16971 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16972
16973 switch (NEON_LANE (inst.operands[0].imm))
16974 {
16975 case NEON_INTERLEAVE_LANES:
16976 NEON_ENCODE (INTERLV, inst);
16977 do_neon_ld_st_interleave ();
16978 break;
16979
16980 case NEON_ALL_LANES:
16981 NEON_ENCODE (DUP, inst);
16982 if (inst.instruction == N_INV)
16983 {
16984 first_error ("only loads support such operands");
16985 break;
16986 }
16987 do_neon_ld_dup ();
16988 break;
16989
16990 default:
16991 NEON_ENCODE (LANE, inst);
16992 do_neon_ld_st_lane ();
16993 }
16994
16995 /* L bit comes from bit mask. */
16996 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16997 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16998 inst.instruction |= inst.operands[1].reg << 16;
16999
17000 if (inst.operands[1].postind)
17001 {
17002 int postreg = inst.operands[1].imm & 0xf;
17003 constraint (!inst.operands[1].immisreg,
17004 _("post-index must be a register"));
17005 constraint (postreg == 0xd || postreg == 0xf,
17006 _("bad register for post-index"));
17007 inst.instruction |= postreg;
17008 }
17009 else
17010 {
17011 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
17012 constraint (inst.reloc.exp.X_op != O_constant
17013 || inst.reloc.exp.X_add_number != 0,
17014 BAD_ADDR_MODE);
17015
17016 if (inst.operands[1].writeback)
17017 {
17018 inst.instruction |= 0xd;
17019 }
17020 else
17021 inst.instruction |= 0xf;
17022 }
17023
17024 if (thumb_mode)
17025 inst.instruction |= 0xf9000000;
17026 else
17027 inst.instruction |= 0xf4000000;
17028}
17029
17030/* FP v8. */
17031static void
17032do_vfp_nsyn_fpv8 (enum neon_shape rs)
17033{
17034 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17035 D register operands. */
17036 if (neon_shape_class[rs] == SC_DOUBLE)
17037 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
17038 _(BAD_FPU));
17039
17040 NEON_ENCODE (FPV8, inst);
17041
17042 if (rs == NS_FFF || rs == NS_HHH)
17043 {
17044 do_vfp_sp_dyadic ();
17045
17046 /* ARMv8.2 fp16 instruction. */
17047 if (rs == NS_HHH)
17048 do_scalar_fp16_v82_encode ();
17049 }
17050 else
17051 do_vfp_dp_rd_rn_rm ();
17052
17053 if (rs == NS_DDD)
17054 inst.instruction |= 0x100;
17055
17056 inst.instruction |= 0xf0000000;
17057}
17058
17059static void
17060do_vsel (void)
17061{
17062 set_it_insn_type (OUTSIDE_IT_INSN);
17063
17064 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
17065 first_error (_("invalid instruction shape"));
17066}
17067
17068static void
17069do_vmaxnm (void)
17070{
17071 set_it_insn_type (OUTSIDE_IT_INSN);
17072
17073 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
17074 return;
17075
17076 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
17077 return;
17078
17079 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
17080}
17081
17082static void
17083do_vrint_1 (enum neon_cvt_mode mode)
17084{
17085 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
17086 struct neon_type_el et;
17087
17088 if (rs == NS_NULL)
17089 return;
17090
17091 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17092 D register operands. */
17093 if (neon_shape_class[rs] == SC_DOUBLE)
17094 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
17095 _(BAD_FPU));
17096
17097 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
17098 | N_VFP);
17099 if (et.type != NT_invtype)
17100 {
17101 /* VFP encodings. */
17102 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
17103 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
17104 set_it_insn_type (OUTSIDE_IT_INSN);
17105
17106 NEON_ENCODE (FPV8, inst);
17107 if (rs == NS_FF || rs == NS_HH)
17108 do_vfp_sp_monadic ();
17109 else
17110 do_vfp_dp_rd_rm ();
17111
17112 switch (mode)
17113 {
17114 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
17115 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
17116 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
17117 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
17118 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
17119 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
17120 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
17121 default: abort ();
17122 }
17123
17124 inst.instruction |= (rs == NS_DD) << 8;
17125 do_vfp_cond_or_thumb ();
17126
17127 /* ARMv8.2 fp16 vrint instruction. */
17128 if (rs == NS_HH)
17129 do_scalar_fp16_v82_encode ();
17130 }
17131 else
17132 {
17133 /* Neon encodings (or something broken...). */
17134 inst.error = NULL;
17135 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
17136
17137 if (et.type == NT_invtype)
17138 return;
17139
17140 set_it_insn_type (OUTSIDE_IT_INSN);
17141 NEON_ENCODE (FLOAT, inst);
17142
17143 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
17144 return;
17145
17146 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17147 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17148 inst.instruction |= LOW4 (inst.operands[1].reg);
17149 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17150 inst.instruction |= neon_quad (rs) << 6;
17151 /* Mask off the original size bits and reencode them. */
17152 inst.instruction = ((inst.instruction & 0xfff3ffff)
17153 | neon_logbits (et.size) << 18);
17154
17155 switch (mode)
17156 {
17157 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
17158 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
17159 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
17160 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
17161 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
17162 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
17163 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
17164 default: abort ();
17165 }
17166
17167 if (thumb_mode)
17168 inst.instruction |= 0xfc000000;
17169 else
17170 inst.instruction |= 0xf0000000;
17171 }
17172}
17173
17174static void
17175do_vrintx (void)
17176{
17177 do_vrint_1 (neon_cvt_mode_x);
17178}
17179
17180static void
17181do_vrintz (void)
17182{
17183 do_vrint_1 (neon_cvt_mode_z);
17184}
17185
17186static void
17187do_vrintr (void)
17188{
17189 do_vrint_1 (neon_cvt_mode_r);
17190}
17191
17192static void
17193do_vrinta (void)
17194{
17195 do_vrint_1 (neon_cvt_mode_a);
17196}
17197
17198static void
17199do_vrintn (void)
17200{
17201 do_vrint_1 (neon_cvt_mode_n);
17202}
17203
17204static void
17205do_vrintp (void)
17206{
17207 do_vrint_1 (neon_cvt_mode_p);
17208}
17209
17210static void
17211do_vrintm (void)
17212{
17213 do_vrint_1 (neon_cvt_mode_m);
17214}
17215
17216/* Crypto v1 instructions. */
17217static void
17218do_crypto_2op_1 (unsigned elttype, int op)
17219{
17220 set_it_insn_type (OUTSIDE_IT_INSN);
17221
17222 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
17223 == NT_invtype)
17224 return;
17225
17226 inst.error = NULL;
17227
17228 NEON_ENCODE (INTEGER, inst);
17229 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17230 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17231 inst.instruction |= LOW4 (inst.operands[1].reg);
17232 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17233 if (op != -1)
17234 inst.instruction |= op << 6;
17235
17236 if (thumb_mode)
17237 inst.instruction |= 0xfc000000;
17238 else
17239 inst.instruction |= 0xf0000000;
17240}
17241
17242static void
17243do_crypto_3op_1 (int u, int op)
17244{
17245 set_it_insn_type (OUTSIDE_IT_INSN);
17246
17247 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
17248 N_32 | N_UNT | N_KEY).type == NT_invtype)
17249 return;
17250
17251 inst.error = NULL;
17252
17253 NEON_ENCODE (INTEGER, inst);
17254 neon_three_same (1, u, 8 << op);
17255}
17256
17257static void
17258do_aese (void)
17259{
17260 do_crypto_2op_1 (N_8, 0);
17261}
17262
17263static void
17264do_aesd (void)
17265{
17266 do_crypto_2op_1 (N_8, 1);
17267}
17268
17269static void
17270do_aesmc (void)
17271{
17272 do_crypto_2op_1 (N_8, 2);
17273}
17274
17275static void
17276do_aesimc (void)
17277{
17278 do_crypto_2op_1 (N_8, 3);
17279}
17280
17281static void
17282do_sha1c (void)
17283{
17284 do_crypto_3op_1 (0, 0);
17285}
17286
17287static void
17288do_sha1p (void)
17289{
17290 do_crypto_3op_1 (0, 1);
17291}
17292
17293static void
17294do_sha1m (void)
17295{
17296 do_crypto_3op_1 (0, 2);
17297}
17298
17299static void
17300do_sha1su0 (void)
17301{
17302 do_crypto_3op_1 (0, 3);
17303}
17304
17305static void
17306do_sha256h (void)
17307{
17308 do_crypto_3op_1 (1, 0);
17309}
17310
17311static void
17312do_sha256h2 (void)
17313{
17314 do_crypto_3op_1 (1, 1);
17315}
17316
17317static void
17318do_sha256su1 (void)
17319{
17320 do_crypto_3op_1 (1, 2);
17321}
17322
17323static void
17324do_sha1h (void)
17325{
17326 do_crypto_2op_1 (N_32, -1);
17327}
17328
17329static void
17330do_sha1su1 (void)
17331{
17332 do_crypto_2op_1 (N_32, 0);
17333}
17334
17335static void
17336do_sha256su0 (void)
17337{
17338 do_crypto_2op_1 (N_32, 1);
17339}
17340
17341static void
17342do_crc32_1 (unsigned int poly, unsigned int sz)
17343{
17344 unsigned int Rd = inst.operands[0].reg;
17345 unsigned int Rn = inst.operands[1].reg;
17346 unsigned int Rm = inst.operands[2].reg;
17347
17348 set_it_insn_type (OUTSIDE_IT_INSN);
17349 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
17350 inst.instruction |= LOW4 (Rn) << 16;
17351 inst.instruction |= LOW4 (Rm);
17352 inst.instruction |= sz << (thumb_mode ? 4 : 21);
17353 inst.instruction |= poly << (thumb_mode ? 20 : 9);
17354
17355 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
17356 as_warn (UNPRED_REG ("r15"));
17357 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
17358 as_warn (UNPRED_REG ("r13"));
17359}
17360
17361static void
17362do_crc32b (void)
17363{
17364 do_crc32_1 (0, 0);
17365}
17366
17367static void
17368do_crc32h (void)
17369{
17370 do_crc32_1 (0, 1);
17371}
17372
17373static void
17374do_crc32w (void)
17375{
17376 do_crc32_1 (0, 2);
17377}
17378
17379static void
17380do_crc32cb (void)
17381{
17382 do_crc32_1 (1, 0);
17383}
17384
17385static void
17386do_crc32ch (void)
17387{
17388 do_crc32_1 (1, 1);
17389}
17390
17391static void
17392do_crc32cw (void)
17393{
17394 do_crc32_1 (1, 2);
17395}
17396
17397\f
17398/* Overall per-instruction processing. */
17399
17400/* We need to be able to fix up arbitrary expressions in some statements.
17401 This is so that we can handle symbols that are an arbitrary distance from
17402 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17403 which returns part of an address in a form which will be valid for
17404 a data instruction. We do this by pushing the expression into a symbol
17405 in the expr_section, and creating a fix for that. */
17406
17407static void
17408fix_new_arm (fragS * frag,
17409 int where,
17410 short int size,
17411 expressionS * exp,
17412 int pc_rel,
17413 int reloc)
17414{
17415 fixS * new_fix;
17416
17417 switch (exp->X_op)
17418 {
17419 case O_constant:
17420 if (pc_rel)
17421 {
17422 /* Create an absolute valued symbol, so we have something to
17423 refer to in the object file. Unfortunately for us, gas's
17424 generic expression parsing will already have folded out
17425 any use of .set foo/.type foo %function that may have
17426 been used to set type information of the target location,
17427 that's being specified symbolically. We have to presume
17428 the user knows what they are doing. */
17429 char name[16 + 8];
17430 symbolS *symbol;
17431
17432 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
17433
17434 symbol = symbol_find_or_make (name);
17435 S_SET_SEGMENT (symbol, absolute_section);
17436 symbol_set_frag (symbol, &zero_address_frag);
17437 S_SET_VALUE (symbol, exp->X_add_number);
17438 exp->X_op = O_symbol;
17439 exp->X_add_symbol = symbol;
17440 exp->X_add_number = 0;
17441 }
17442 /* FALLTHROUGH */
17443 case O_symbol:
17444 case O_add:
17445 case O_subtract:
17446 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
17447 (enum bfd_reloc_code_real) reloc);
17448 break;
17449
17450 default:
17451 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
17452 pc_rel, (enum bfd_reloc_code_real) reloc);
17453 break;
17454 }
17455
17456 /* Mark whether the fix is to a THUMB instruction, or an ARM
17457 instruction. */
17458 new_fix->tc_fix_data = thumb_mode;
17459}
17460
17461/* Create a frg for an instruction requiring relaxation. */
17462static void
17463output_relax_insn (void)
17464{
17465 char * to;
17466 symbolS *sym;
17467 int offset;
17468
17469 /* The size of the instruction is unknown, so tie the debug info to the
17470 start of the instruction. */
17471 dwarf2_emit_insn (0);
17472
17473 switch (inst.reloc.exp.X_op)
17474 {
17475 case O_symbol:
17476 sym = inst.reloc.exp.X_add_symbol;
17477 offset = inst.reloc.exp.X_add_number;
17478 break;
17479 case O_constant:
17480 sym = NULL;
17481 offset = inst.reloc.exp.X_add_number;
17482 break;
17483 default:
17484 sym = make_expr_symbol (&inst.reloc.exp);
17485 offset = 0;
17486 break;
17487 }
17488 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
17489 inst.relax, sym, offset, NULL/*offset, opcode*/);
17490 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
17491}
17492
17493/* Write a 32-bit thumb instruction to buf. */
17494static void
17495put_thumb32_insn (char * buf, unsigned long insn)
17496{
17497 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
17498 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
17499}
17500
17501static void
17502output_inst (const char * str)
17503{
17504 char * to = NULL;
17505
17506 if (inst.error)
17507 {
17508 as_bad ("%s -- `%s'", inst.error, str);
17509 return;
17510 }
17511 if (inst.relax)
17512 {
17513 output_relax_insn ();
17514 return;
17515 }
17516 if (inst.size == 0)
17517 return;
17518
17519 to = frag_more (inst.size);
17520 /* PR 9814: Record the thumb mode into the current frag so that we know
17521 what type of NOP padding to use, if necessary. We override any previous
17522 setting so that if the mode has changed then the NOPS that we use will
17523 match the encoding of the last instruction in the frag. */
17524 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
17525
17526 if (thumb_mode && (inst.size > THUMB_SIZE))
17527 {
17528 gas_assert (inst.size == (2 * THUMB_SIZE));
17529 put_thumb32_insn (to, inst.instruction);
17530 }
17531 else if (inst.size > INSN_SIZE)
17532 {
17533 gas_assert (inst.size == (2 * INSN_SIZE));
17534 md_number_to_chars (to, inst.instruction, INSN_SIZE);
17535 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
17536 }
17537 else
17538 md_number_to_chars (to, inst.instruction, inst.size);
17539
17540 if (inst.reloc.type != BFD_RELOC_UNUSED)
17541 fix_new_arm (frag_now, to - frag_now->fr_literal,
17542 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
17543 inst.reloc.type);
17544
17545 dwarf2_emit_insn (inst.size);
17546}
17547
17548static char *
17549output_it_inst (int cond, int mask, char * to)
17550{
17551 unsigned long instruction = 0xbf00;
17552
17553 mask &= 0xf;
17554 instruction |= mask;
17555 instruction |= cond << 4;
17556
17557 if (to == NULL)
17558 {
17559 to = frag_more (2);
17560#ifdef OBJ_ELF
17561 dwarf2_emit_insn (2);
17562#endif
17563 }
17564
17565 md_number_to_chars (to, instruction, 2);
17566
17567 return to;
17568}
17569
17570/* Tag values used in struct asm_opcode's tag field. */
17571enum opcode_tag
17572{
17573 OT_unconditional, /* Instruction cannot be conditionalized.
17574 The ARM condition field is still 0xE. */
17575 OT_unconditionalF, /* Instruction cannot be conditionalized
17576 and carries 0xF in its ARM condition field. */
17577 OT_csuffix, /* Instruction takes a conditional suffix. */
17578 OT_csuffixF, /* Some forms of the instruction take a conditional
17579 suffix, others place 0xF where the condition field
17580 would be. */
17581 OT_cinfix3, /* Instruction takes a conditional infix,
17582 beginning at character index 3. (In
17583 unified mode, it becomes a suffix.) */
17584 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
17585 tsts, cmps, cmns, and teqs. */
17586 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
17587 character index 3, even in unified mode. Used for
17588 legacy instructions where suffix and infix forms
17589 may be ambiguous. */
17590 OT_csuf_or_in3, /* Instruction takes either a conditional
17591 suffix or an infix at character index 3. */
17592 OT_odd_infix_unc, /* This is the unconditional variant of an
17593 instruction that takes a conditional infix
17594 at an unusual position. In unified mode,
17595 this variant will accept a suffix. */
17596 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
17597 are the conditional variants of instructions that
17598 take conditional infixes in unusual positions.
17599 The infix appears at character index
17600 (tag - OT_odd_infix_0). These are not accepted
17601 in unified mode. */
17602};
17603
17604/* Subroutine of md_assemble, responsible for looking up the primary
17605 opcode from the mnemonic the user wrote. STR points to the
17606 beginning of the mnemonic.
17607
17608 This is not simply a hash table lookup, because of conditional
17609 variants. Most instructions have conditional variants, which are
17610 expressed with a _conditional affix_ to the mnemonic. If we were
17611 to encode each conditional variant as a literal string in the opcode
17612 table, it would have approximately 20,000 entries.
17613
17614 Most mnemonics take this affix as a suffix, and in unified syntax,
17615 'most' is upgraded to 'all'. However, in the divided syntax, some
17616 instructions take the affix as an infix, notably the s-variants of
17617 the arithmetic instructions. Of those instructions, all but six
17618 have the infix appear after the third character of the mnemonic.
17619
17620 Accordingly, the algorithm for looking up primary opcodes given
17621 an identifier is:
17622
17623 1. Look up the identifier in the opcode table.
17624 If we find a match, go to step U.
17625
17626 2. Look up the last two characters of the identifier in the
17627 conditions table. If we find a match, look up the first N-2
17628 characters of the identifier in the opcode table. If we
17629 find a match, go to step CE.
17630
17631 3. Look up the fourth and fifth characters of the identifier in
17632 the conditions table. If we find a match, extract those
17633 characters from the identifier, and look up the remaining
17634 characters in the opcode table. If we find a match, go
17635 to step CM.
17636
17637 4. Fail.
17638
17639 U. Examine the tag field of the opcode structure, in case this is
17640 one of the six instructions with its conditional infix in an
17641 unusual place. If it is, the tag tells us where to find the
17642 infix; look it up in the conditions table and set inst.cond
17643 accordingly. Otherwise, this is an unconditional instruction.
17644 Again set inst.cond accordingly. Return the opcode structure.
17645
17646 CE. Examine the tag field to make sure this is an instruction that
17647 should receive a conditional suffix. If it is not, fail.
17648 Otherwise, set inst.cond from the suffix we already looked up,
17649 and return the opcode structure.
17650
17651 CM. Examine the tag field to make sure this is an instruction that
17652 should receive a conditional infix after the third character.
17653 If it is not, fail. Otherwise, undo the edits to the current
17654 line of input and proceed as for case CE. */
17655
17656static const struct asm_opcode *
17657opcode_lookup (char **str)
17658{
17659 char *end, *base;
17660 char *affix;
17661 const struct asm_opcode *opcode;
17662 const struct asm_cond *cond;
17663 char save[2];
17664
17665 /* Scan up to the end of the mnemonic, which must end in white space,
17666 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17667 for (base = end = *str; *end != '\0'; end++)
17668 if (*end == ' ' || *end == '.')
17669 break;
17670
17671 if (end == base)
17672 return NULL;
17673
17674 /* Handle a possible width suffix and/or Neon type suffix. */
17675 if (end[0] == '.')
17676 {
17677 int offset = 2;
17678
17679 /* The .w and .n suffixes are only valid if the unified syntax is in
17680 use. */
17681 if (unified_syntax && end[1] == 'w')
17682 inst.size_req = 4;
17683 else if (unified_syntax && end[1] == 'n')
17684 inst.size_req = 2;
17685 else
17686 offset = 0;
17687
17688 inst.vectype.elems = 0;
17689
17690 *str = end + offset;
17691
17692 if (end[offset] == '.')
17693 {
17694 /* See if we have a Neon type suffix (possible in either unified or
17695 non-unified ARM syntax mode). */
17696 if (parse_neon_type (&inst.vectype, str) == FAIL)
17697 return NULL;
17698 }
17699 else if (end[offset] != '\0' && end[offset] != ' ')
17700 return NULL;
17701 }
17702 else
17703 *str = end;
17704
17705 /* Look for unaffixed or special-case affixed mnemonic. */
17706 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
17707 end - base);
17708 if (opcode)
17709 {
17710 /* step U */
17711 if (opcode->tag < OT_odd_infix_0)
17712 {
17713 inst.cond = COND_ALWAYS;
17714 return opcode;
17715 }
17716
17717 if (warn_on_deprecated && unified_syntax)
17718 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17719 affix = base + (opcode->tag - OT_odd_infix_0);
17720 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17721 gas_assert (cond);
17722
17723 inst.cond = cond->value;
17724 return opcode;
17725 }
17726
17727 /* Cannot have a conditional suffix on a mnemonic of less than two
17728 characters. */
17729 if (end - base < 3)
17730 return NULL;
17731
17732 /* Look for suffixed mnemonic. */
17733 affix = end - 2;
17734 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17735 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
17736 affix - base);
17737 if (opcode && cond)
17738 {
17739 /* step CE */
17740 switch (opcode->tag)
17741 {
17742 case OT_cinfix3_legacy:
17743 /* Ignore conditional suffixes matched on infix only mnemonics. */
17744 break;
17745
17746 case OT_cinfix3:
17747 case OT_cinfix3_deprecated:
17748 case OT_odd_infix_unc:
17749 if (!unified_syntax)
17750 return 0;
17751 /* else fall through */
17752
17753 case OT_csuffix:
17754 case OT_csuffixF:
17755 case OT_csuf_or_in3:
17756 inst.cond = cond->value;
17757 return opcode;
17758
17759 case OT_unconditional:
17760 case OT_unconditionalF:
17761 if (thumb_mode)
17762 inst.cond = cond->value;
17763 else
17764 {
17765 /* Delayed diagnostic. */
17766 inst.error = BAD_COND;
17767 inst.cond = COND_ALWAYS;
17768 }
17769 return opcode;
17770
17771 default:
17772 return NULL;
17773 }
17774 }
17775
17776 /* Cannot have a usual-position infix on a mnemonic of less than
17777 six characters (five would be a suffix). */
17778 if (end - base < 6)
17779 return NULL;
17780
17781 /* Look for infixed mnemonic in the usual position. */
17782 affix = base + 3;
17783 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17784 if (!cond)
17785 return NULL;
17786
17787 memcpy (save, affix, 2);
17788 memmove (affix, affix + 2, (end - affix) - 2);
17789 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
17790 (end - base) - 2);
17791 memmove (affix + 2, affix, (end - affix) - 2);
17792 memcpy (affix, save, 2);
17793
17794 if (opcode
17795 && (opcode->tag == OT_cinfix3
17796 || opcode->tag == OT_cinfix3_deprecated
17797 || opcode->tag == OT_csuf_or_in3
17798 || opcode->tag == OT_cinfix3_legacy))
17799 {
17800 /* Step CM. */
17801 if (warn_on_deprecated && unified_syntax
17802 && (opcode->tag == OT_cinfix3
17803 || opcode->tag == OT_cinfix3_deprecated))
17804 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17805
17806 inst.cond = cond->value;
17807 return opcode;
17808 }
17809
17810 return NULL;
17811}
17812
17813/* This function generates an initial IT instruction, leaving its block
17814 virtually open for the new instructions. Eventually,
17815 the mask will be updated by now_it_add_mask () each time
17816 a new instruction needs to be included in the IT block.
17817 Finally, the block is closed with close_automatic_it_block ().
17818 The block closure can be requested either from md_assemble (),
17819 a tencode (), or due to a label hook. */
17820
17821static void
17822new_automatic_it_block (int cond)
17823{
17824 now_it.state = AUTOMATIC_IT_BLOCK;
17825 now_it.mask = 0x18;
17826 now_it.cc = cond;
17827 now_it.block_length = 1;
17828 mapping_state (MAP_THUMB);
17829 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
17830 now_it.warn_deprecated = FALSE;
17831 now_it.insn_cond = TRUE;
17832}
17833
17834/* Close an automatic IT block.
17835 See comments in new_automatic_it_block (). */
17836
17837static void
17838close_automatic_it_block (void)
17839{
17840 now_it.mask = 0x10;
17841 now_it.block_length = 0;
17842}
17843
17844/* Update the mask of the current automatically-generated IT
17845 instruction. See comments in new_automatic_it_block (). */
17846
17847static void
17848now_it_add_mask (int cond)
17849{
17850#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17851#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17852 | ((bitvalue) << (nbit)))
17853 const int resulting_bit = (cond & 1);
17854
17855 now_it.mask &= 0xf;
17856 now_it.mask = SET_BIT_VALUE (now_it.mask,
17857 resulting_bit,
17858 (5 - now_it.block_length));
17859 now_it.mask = SET_BIT_VALUE (now_it.mask,
17860 1,
17861 ((5 - now_it.block_length) - 1) );
17862 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
17863
17864#undef CLEAR_BIT
17865#undef SET_BIT_VALUE
17866}
17867
17868/* The IT blocks handling machinery is accessed through the these functions:
17869 it_fsm_pre_encode () from md_assemble ()
17870 set_it_insn_type () optional, from the tencode functions
17871 set_it_insn_type_last () ditto
17872 in_it_block () ditto
17873 it_fsm_post_encode () from md_assemble ()
17874 force_automatic_it_block_close () from label habdling functions
17875
17876 Rationale:
17877 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17878 initializing the IT insn type with a generic initial value depending
17879 on the inst.condition.
17880 2) During the tencode function, two things may happen:
17881 a) The tencode function overrides the IT insn type by
17882 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17883 b) The tencode function queries the IT block state by
17884 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17885
17886 Both set_it_insn_type and in_it_block run the internal FSM state
17887 handling function (handle_it_state), because: a) setting the IT insn
17888 type may incur in an invalid state (exiting the function),
17889 and b) querying the state requires the FSM to be updated.
17890 Specifically we want to avoid creating an IT block for conditional
17891 branches, so it_fsm_pre_encode is actually a guess and we can't
17892 determine whether an IT block is required until the tencode () routine
17893 has decided what type of instruction this actually it.
17894 Because of this, if set_it_insn_type and in_it_block have to be used,
17895 set_it_insn_type has to be called first.
17896
17897 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17898 determines the insn IT type depending on the inst.cond code.
17899 When a tencode () routine encodes an instruction that can be
17900 either outside an IT block, or, in the case of being inside, has to be
17901 the last one, set_it_insn_type_last () will determine the proper
17902 IT instruction type based on the inst.cond code. Otherwise,
17903 set_it_insn_type can be called for overriding that logic or
17904 for covering other cases.
17905
17906 Calling handle_it_state () may not transition the IT block state to
17907 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17908 still queried. Instead, if the FSM determines that the state should
17909 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17910 after the tencode () function: that's what it_fsm_post_encode () does.
17911
17912 Since in_it_block () calls the state handling function to get an
17913 updated state, an error may occur (due to invalid insns combination).
17914 In that case, inst.error is set.
17915 Therefore, inst.error has to be checked after the execution of
17916 the tencode () routine.
17917
17918 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17919 any pending state change (if any) that didn't take place in
17920 handle_it_state () as explained above. */
17921
17922static void
17923it_fsm_pre_encode (void)
17924{
17925 if (inst.cond != COND_ALWAYS)
17926 inst.it_insn_type = INSIDE_IT_INSN;
17927 else
17928 inst.it_insn_type = OUTSIDE_IT_INSN;
17929
17930 now_it.state_handled = 0;
17931}
17932
17933/* IT state FSM handling function. */
17934
17935static int
17936handle_it_state (void)
17937{
17938 now_it.state_handled = 1;
17939 now_it.insn_cond = FALSE;
17940
17941 switch (now_it.state)
17942 {
17943 case OUTSIDE_IT_BLOCK:
17944 switch (inst.it_insn_type)
17945 {
17946 case OUTSIDE_IT_INSN:
17947 break;
17948
17949 case INSIDE_IT_INSN:
17950 case INSIDE_IT_LAST_INSN:
17951 if (thumb_mode == 0)
17952 {
17953 if (unified_syntax
17954 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
17955 as_tsktsk (_("Warning: conditional outside an IT block"\
17956 " for Thumb."));
17957 }
17958 else
17959 {
17960 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
17961 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
17962 {
17963 /* Automatically generate the IT instruction. */
17964 new_automatic_it_block (inst.cond);
17965 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
17966 close_automatic_it_block ();
17967 }
17968 else
17969 {
17970 inst.error = BAD_OUT_IT;
17971 return FAIL;
17972 }
17973 }
17974 break;
17975
17976 case IF_INSIDE_IT_LAST_INSN:
17977 case NEUTRAL_IT_INSN:
17978 break;
17979
17980 case IT_INSN:
17981 now_it.state = MANUAL_IT_BLOCK;
17982 now_it.block_length = 0;
17983 break;
17984 }
17985 break;
17986
17987 case AUTOMATIC_IT_BLOCK:
17988 /* Three things may happen now:
17989 a) We should increment current it block size;
17990 b) We should close current it block (closing insn or 4 insns);
17991 c) We should close current it block and start a new one (due
17992 to incompatible conditions or
17993 4 insns-length block reached). */
17994
17995 switch (inst.it_insn_type)
17996 {
17997 case OUTSIDE_IT_INSN:
17998 /* The closure of the block shall happen immediatelly,
17999 so any in_it_block () call reports the block as closed. */
18000 force_automatic_it_block_close ();
18001 break;
18002
18003 case INSIDE_IT_INSN:
18004 case INSIDE_IT_LAST_INSN:
18005 case IF_INSIDE_IT_LAST_INSN:
18006 now_it.block_length++;
18007
18008 if (now_it.block_length > 4
18009 || !now_it_compatible (inst.cond))
18010 {
18011 force_automatic_it_block_close ();
18012 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
18013 new_automatic_it_block (inst.cond);
18014 }
18015 else
18016 {
18017 now_it.insn_cond = TRUE;
18018 now_it_add_mask (inst.cond);
18019 }
18020
18021 if (now_it.state == AUTOMATIC_IT_BLOCK
18022 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
18023 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
18024 close_automatic_it_block ();
18025 break;
18026
18027 case NEUTRAL_IT_INSN:
18028 now_it.block_length++;
18029 now_it.insn_cond = TRUE;
18030
18031 if (now_it.block_length > 4)
18032 force_automatic_it_block_close ();
18033 else
18034 now_it_add_mask (now_it.cc & 1);
18035 break;
18036
18037 case IT_INSN:
18038 close_automatic_it_block ();
18039 now_it.state = MANUAL_IT_BLOCK;
18040 break;
18041 }
18042 break;
18043
18044 case MANUAL_IT_BLOCK:
18045 {
18046 /* Check conditional suffixes. */
18047 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
18048 int is_last;
18049 now_it.mask <<= 1;
18050 now_it.mask &= 0x1f;
18051 is_last = (now_it.mask == 0x10);
18052 now_it.insn_cond = TRUE;
18053
18054 switch (inst.it_insn_type)
18055 {
18056 case OUTSIDE_IT_INSN:
18057 inst.error = BAD_NOT_IT;
18058 return FAIL;
18059
18060 case INSIDE_IT_INSN:
18061 if (cond != inst.cond)
18062 {
18063 inst.error = BAD_IT_COND;
18064 return FAIL;
18065 }
18066 break;
18067
18068 case INSIDE_IT_LAST_INSN:
18069 case IF_INSIDE_IT_LAST_INSN:
18070 if (cond != inst.cond)
18071 {
18072 inst.error = BAD_IT_COND;
18073 return FAIL;
18074 }
18075 if (!is_last)
18076 {
18077 inst.error = BAD_BRANCH;
18078 return FAIL;
18079 }
18080 break;
18081
18082 case NEUTRAL_IT_INSN:
18083 /* The BKPT instruction is unconditional even in an IT block. */
18084 break;
18085
18086 case IT_INSN:
18087 inst.error = BAD_IT_IT;
18088 return FAIL;
18089 }
18090 }
18091 break;
18092 }
18093
18094 return SUCCESS;
18095}
18096
18097struct depr_insn_mask
18098{
18099 unsigned long pattern;
18100 unsigned long mask;
18101 const char* description;
18102};
18103
18104/* List of 16-bit instruction patterns deprecated in an IT block in
18105 ARMv8. */
18106static const struct depr_insn_mask depr_it_insns[] = {
18107 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18108 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18109 { 0xa000, 0xb800, N_("ADR") },
18110 { 0x4800, 0xf800, N_("Literal loads") },
18111 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18112 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18113 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18114 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18115 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18116 { 0, 0, NULL }
18117};
18118
18119static void
18120it_fsm_post_encode (void)
18121{
18122 int is_last;
18123
18124 if (!now_it.state_handled)
18125 handle_it_state ();
18126
18127 if (now_it.insn_cond
18128 && !now_it.warn_deprecated
18129 && warn_on_deprecated
18130 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
18131 {
18132 if (inst.instruction >= 0x10000)
18133 {
18134 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18135 "deprecated in ARMv8"));
18136 now_it.warn_deprecated = TRUE;
18137 }
18138 else
18139 {
18140 const struct depr_insn_mask *p = depr_it_insns;
18141
18142 while (p->mask != 0)
18143 {
18144 if ((inst.instruction & p->mask) == p->pattern)
18145 {
18146 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18147 "of the following class are deprecated in ARMv8: "
18148 "%s"), p->description);
18149 now_it.warn_deprecated = TRUE;
18150 break;
18151 }
18152
18153 ++p;
18154 }
18155 }
18156
18157 if (now_it.block_length > 1)
18158 {
18159 as_tsktsk (_("IT blocks containing more than one conditional "
18160 "instruction are deprecated in ARMv8"));
18161 now_it.warn_deprecated = TRUE;
18162 }
18163 }
18164
18165 is_last = (now_it.mask == 0x10);
18166 if (is_last)
18167 {
18168 now_it.state = OUTSIDE_IT_BLOCK;
18169 now_it.mask = 0;
18170 }
18171}
18172
18173static void
18174force_automatic_it_block_close (void)
18175{
18176 if (now_it.state == AUTOMATIC_IT_BLOCK)
18177 {
18178 close_automatic_it_block ();
18179 now_it.state = OUTSIDE_IT_BLOCK;
18180 now_it.mask = 0;
18181 }
18182}
18183
18184static int
18185in_it_block (void)
18186{
18187 if (!now_it.state_handled)
18188 handle_it_state ();
18189
18190 return now_it.state != OUTSIDE_IT_BLOCK;
18191}
18192
18193/* Whether OPCODE only has T32 encoding. Since this function is only used by
18194 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18195 here, hence the "known" in the function name. */
18196
18197static bfd_boolean
18198known_t32_only_insn (const struct asm_opcode *opcode)
18199{
18200 /* Original Thumb-1 wide instruction. */
18201 if (opcode->tencode == do_t_blx
18202 || opcode->tencode == do_t_branch23
18203 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
18204 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
18205 return TRUE;
18206
18207 /* Wide-only instruction added to ARMv8-M Baseline. */
18208 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
18209 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
18210 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
18211 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
18212 return TRUE;
18213
18214 return FALSE;
18215}
18216
18217/* Whether wide instruction variant can be used if available for a valid OPCODE
18218 in ARCH. */
18219
18220static bfd_boolean
18221t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
18222{
18223 if (known_t32_only_insn (opcode))
18224 return TRUE;
18225
18226 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18227 of variant T3 of B.W is checked in do_t_branch. */
18228 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
18229 && opcode->tencode == do_t_branch)
18230 return TRUE;
18231
18232 /* Wide instruction variants of all instructions with narrow *and* wide
18233 variants become available with ARMv6t2. Other opcodes are either
18234 narrow-only or wide-only and are thus available if OPCODE is valid. */
18235 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
18236 return TRUE;
18237
18238 /* OPCODE with narrow only instruction variant or wide variant not
18239 available. */
18240 return FALSE;
18241}
18242
18243void
18244md_assemble (char *str)
18245{
18246 char *p = str;
18247 const struct asm_opcode * opcode;
18248
18249 /* Align the previous label if needed. */
18250 if (last_label_seen != NULL)
18251 {
18252 symbol_set_frag (last_label_seen, frag_now);
18253 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
18254 S_SET_SEGMENT (last_label_seen, now_seg);
18255 }
18256
18257 memset (&inst, '\0', sizeof (inst));
18258 inst.reloc.type = BFD_RELOC_UNUSED;
18259
18260 opcode = opcode_lookup (&p);
18261 if (!opcode)
18262 {
18263 /* It wasn't an instruction, but it might be a register alias of
18264 the form alias .req reg, or a Neon .dn/.qn directive. */
18265 if (! create_register_alias (str, p)
18266 && ! create_neon_reg_alias (str, p))
18267 as_bad (_("bad instruction `%s'"), str);
18268
18269 return;
18270 }
18271
18272 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
18273 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18274
18275 /* The value which unconditional instructions should have in place of the
18276 condition field. */
18277 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
18278
18279 if (thumb_mode)
18280 {
18281 arm_feature_set variant;
18282
18283 variant = cpu_variant;
18284 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18285 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
18286 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
18287 /* Check that this instruction is supported for this CPU. */
18288 if (!opcode->tvariant
18289 || (thumb_mode == 1
18290 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
18291 {
18292 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
18293 return;
18294 }
18295 if (inst.cond != COND_ALWAYS && !unified_syntax
18296 && opcode->tencode != do_t_branch)
18297 {
18298 as_bad (_("Thumb does not support conditional execution"));
18299 return;
18300 }
18301
18302 /* Two things are addressed here:
18303 1) Implicit require narrow instructions on Thumb-1.
18304 This avoids relaxation accidentally introducing Thumb-2
18305 instructions.
18306 2) Reject wide instructions in non Thumb-2 cores.
18307
18308 Only instructions with narrow and wide variants need to be handled
18309 but selecting all non wide-only instructions is easier. */
18310 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
18311 && !t32_insn_ok (variant, opcode))
18312 {
18313 if (inst.size_req == 0)
18314 inst.size_req = 2;
18315 else if (inst.size_req == 4)
18316 {
18317 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
18318 as_bad (_("selected processor does not support 32bit wide "
18319 "variant of instruction `%s'"), str);
18320 else
18321 as_bad (_("selected processor does not support `%s' in "
18322 "Thumb-2 mode"), str);
18323 return;
18324 }
18325 }
18326
18327 inst.instruction = opcode->tvalue;
18328
18329 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
18330 {
18331 /* Prepare the it_insn_type for those encodings that don't set
18332 it. */
18333 it_fsm_pre_encode ();
18334
18335 opcode->tencode ();
18336
18337 it_fsm_post_encode ();
18338 }
18339
18340 if (!(inst.error || inst.relax))
18341 {
18342 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
18343 inst.size = (inst.instruction > 0xffff ? 4 : 2);
18344 if (inst.size_req && inst.size_req != inst.size)
18345 {
18346 as_bad (_("cannot honor width suffix -- `%s'"), str);
18347 return;
18348 }
18349 }
18350
18351 /* Something has gone badly wrong if we try to relax a fixed size
18352 instruction. */
18353 gas_assert (inst.size_req == 0 || !inst.relax);
18354
18355 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
18356 *opcode->tvariant);
18357 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18358 set those bits when Thumb-2 32-bit instructions are seen. The impact
18359 of relaxable instructions will be considered later after we finish all
18360 relaxation. */
18361 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
18362 variant = arm_arch_none;
18363 else
18364 variant = cpu_variant;
18365 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
18366 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
18367 arm_ext_v6t2);
18368
18369 check_neon_suffixes;
18370
18371 if (!inst.error)
18372 {
18373 mapping_state (MAP_THUMB);
18374 }
18375 }
18376 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
18377 {
18378 bfd_boolean is_bx;
18379
18380 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18381 is_bx = (opcode->aencode == do_bx);
18382
18383 /* Check that this instruction is supported for this CPU. */
18384 if (!(is_bx && fix_v4bx)
18385 && !(opcode->avariant &&
18386 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
18387 {
18388 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
18389 return;
18390 }
18391 if (inst.size_req)
18392 {
18393 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
18394 return;
18395 }
18396
18397 inst.instruction = opcode->avalue;
18398 if (opcode->tag == OT_unconditionalF)
18399 inst.instruction |= 0xFU << 28;
18400 else
18401 inst.instruction |= inst.cond << 28;
18402 inst.size = INSN_SIZE;
18403 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
18404 {
18405 it_fsm_pre_encode ();
18406 opcode->aencode ();
18407 it_fsm_post_encode ();
18408 }
18409 /* Arm mode bx is marked as both v4T and v5 because it's still required
18410 on a hypothetical non-thumb v5 core. */
18411 if (is_bx)
18412 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
18413 else
18414 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
18415 *opcode->avariant);
18416
18417 check_neon_suffixes;
18418
18419 if (!inst.error)
18420 {
18421 mapping_state (MAP_ARM);
18422 }
18423 }
18424 else
18425 {
18426 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18427 "-- `%s'"), str);
18428 return;
18429 }
18430 output_inst (str);
18431}
18432
18433static void
18434check_it_blocks_finished (void)
18435{
18436#ifdef OBJ_ELF
18437 asection *sect;
18438
18439 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
18440 if (seg_info (sect)->tc_segment_info_data.current_it.state
18441 == MANUAL_IT_BLOCK)
18442 {
18443 as_warn (_("section '%s' finished with an open IT block."),
18444 sect->name);
18445 }
18446#else
18447 if (now_it.state == MANUAL_IT_BLOCK)
18448 as_warn (_("file finished with an open IT block."));
18449#endif
18450}
18451
18452/* Various frobbings of labels and their addresses. */
18453
18454void
18455arm_start_line_hook (void)
18456{
18457 last_label_seen = NULL;
18458}
18459
18460void
18461arm_frob_label (symbolS * sym)
18462{
18463 last_label_seen = sym;
18464
18465 ARM_SET_THUMB (sym, thumb_mode);
18466
18467#if defined OBJ_COFF || defined OBJ_ELF
18468 ARM_SET_INTERWORK (sym, support_interwork);
18469#endif
18470
18471 force_automatic_it_block_close ();
18472
18473 /* Note - do not allow local symbols (.Lxxx) to be labelled
18474 as Thumb functions. This is because these labels, whilst
18475 they exist inside Thumb code, are not the entry points for
18476 possible ARM->Thumb calls. Also, these labels can be used
18477 as part of a computed goto or switch statement. eg gcc
18478 can generate code that looks like this:
18479
18480 ldr r2, [pc, .Laaa]
18481 lsl r3, r3, #2
18482 ldr r2, [r3, r2]
18483 mov pc, r2
18484
18485 .Lbbb: .word .Lxxx
18486 .Lccc: .word .Lyyy
18487 ..etc...
18488 .Laaa: .word Lbbb
18489
18490 The first instruction loads the address of the jump table.
18491 The second instruction converts a table index into a byte offset.
18492 The third instruction gets the jump address out of the table.
18493 The fourth instruction performs the jump.
18494
18495 If the address stored at .Laaa is that of a symbol which has the
18496 Thumb_Func bit set, then the linker will arrange for this address
18497 to have the bottom bit set, which in turn would mean that the
18498 address computation performed by the third instruction would end
18499 up with the bottom bit set. Since the ARM is capable of unaligned
18500 word loads, the instruction would then load the incorrect address
18501 out of the jump table, and chaos would ensue. */
18502 if (label_is_thumb_function_name
18503 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
18504 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
18505 {
18506 /* When the address of a Thumb function is taken the bottom
18507 bit of that address should be set. This will allow
18508 interworking between Arm and Thumb functions to work
18509 correctly. */
18510
18511 THUMB_SET_FUNC (sym, 1);
18512
18513 label_is_thumb_function_name = FALSE;
18514 }
18515
18516 dwarf2_emit_label (sym);
18517}
18518
18519bfd_boolean
18520arm_data_in_code (void)
18521{
18522 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
18523 {
18524 *input_line_pointer = '/';
18525 input_line_pointer += 5;
18526 *input_line_pointer = 0;
18527 return TRUE;
18528 }
18529
18530 return FALSE;
18531}
18532
18533char *
18534arm_canonicalize_symbol_name (char * name)
18535{
18536 int len;
18537
18538 if (thumb_mode && (len = strlen (name)) > 5
18539 && streq (name + len - 5, "/data"))
18540 *(name + len - 5) = 0;
18541
18542 return name;
18543}
18544\f
18545/* Table of all register names defined by default. The user can
18546 define additional names with .req. Note that all register names
18547 should appear in both upper and lowercase variants. Some registers
18548 also have mixed-case names. */
18549
18550#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18551#define REGNUM(p,n,t) REGDEF(p##n, n, t)
18552#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18553#define REGSET(p,t) \
18554 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18555 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18556 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18557 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18558#define REGSETH(p,t) \
18559 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18560 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18561 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18562 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18563#define REGSET2(p,t) \
18564 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18565 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18566 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18567 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18568#define SPLRBANK(base,bank,t) \
18569 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18570 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18571 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18572 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18573 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18574 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18575
18576static const struct reg_entry reg_names[] =
18577{
18578 /* ARM integer registers. */
18579 REGSET(r, RN), REGSET(R, RN),
18580
18581 /* ATPCS synonyms. */
18582 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
18583 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
18584 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
18585
18586 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
18587 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
18588 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
18589
18590 /* Well-known aliases. */
18591 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
18592 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
18593
18594 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
18595 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
18596
18597 /* Coprocessor numbers. */
18598 REGSET(p, CP), REGSET(P, CP),
18599
18600 /* Coprocessor register numbers. The "cr" variants are for backward
18601 compatibility. */
18602 REGSET(c, CN), REGSET(C, CN),
18603 REGSET(cr, CN), REGSET(CR, CN),
18604
18605 /* ARM banked registers. */
18606 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
18607 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
18608 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
18609 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
18610 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
18611 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
18612 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
18613
18614 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
18615 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
18616 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
18617 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
18618 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
18619 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
18620 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
18621 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
18622
18623 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
18624 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
18625 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
18626 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
18627 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
18628 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
18629 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
18630 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
18631 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
18632
18633 /* FPA registers. */
18634 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
18635 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
18636
18637 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
18638 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
18639
18640 /* VFP SP registers. */
18641 REGSET(s,VFS), REGSET(S,VFS),
18642 REGSETH(s,VFS), REGSETH(S,VFS),
18643
18644 /* VFP DP Registers. */
18645 REGSET(d,VFD), REGSET(D,VFD),
18646 /* Extra Neon DP registers. */
18647 REGSETH(d,VFD), REGSETH(D,VFD),
18648
18649 /* Neon QP registers. */
18650 REGSET2(q,NQ), REGSET2(Q,NQ),
18651
18652 /* VFP control registers. */
18653 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
18654 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
18655 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
18656 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
18657 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
18658 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
18659
18660 /* Maverick DSP coprocessor registers. */
18661 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
18662 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
18663
18664 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
18665 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
18666 REGDEF(dspsc,0,DSPSC),
18667
18668 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
18669 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
18670 REGDEF(DSPSC,0,DSPSC),
18671
18672 /* iWMMXt data registers - p0, c0-15. */
18673 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
18674
18675 /* iWMMXt control registers - p1, c0-3. */
18676 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
18677 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
18678 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
18679 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
18680
18681 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18682 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
18683 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
18684 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
18685 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
18686
18687 /* XScale accumulator registers. */
18688 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
18689};
18690#undef REGDEF
18691#undef REGNUM
18692#undef REGSET
18693
18694/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18695 within psr_required_here. */
18696static const struct asm_psr psrs[] =
18697{
18698 /* Backward compatibility notation. Note that "all" is no longer
18699 truly all possible PSR bits. */
18700 {"all", PSR_c | PSR_f},
18701 {"flg", PSR_f},
18702 {"ctl", PSR_c},
18703
18704 /* Individual flags. */
18705 {"f", PSR_f},
18706 {"c", PSR_c},
18707 {"x", PSR_x},
18708 {"s", PSR_s},
18709
18710 /* Combinations of flags. */
18711 {"fs", PSR_f | PSR_s},
18712 {"fx", PSR_f | PSR_x},
18713 {"fc", PSR_f | PSR_c},
18714 {"sf", PSR_s | PSR_f},
18715 {"sx", PSR_s | PSR_x},
18716 {"sc", PSR_s | PSR_c},
18717 {"xf", PSR_x | PSR_f},
18718 {"xs", PSR_x | PSR_s},
18719 {"xc", PSR_x | PSR_c},
18720 {"cf", PSR_c | PSR_f},
18721 {"cs", PSR_c | PSR_s},
18722 {"cx", PSR_c | PSR_x},
18723 {"fsx", PSR_f | PSR_s | PSR_x},
18724 {"fsc", PSR_f | PSR_s | PSR_c},
18725 {"fxs", PSR_f | PSR_x | PSR_s},
18726 {"fxc", PSR_f | PSR_x | PSR_c},
18727 {"fcs", PSR_f | PSR_c | PSR_s},
18728 {"fcx", PSR_f | PSR_c | PSR_x},
18729 {"sfx", PSR_s | PSR_f | PSR_x},
18730 {"sfc", PSR_s | PSR_f | PSR_c},
18731 {"sxf", PSR_s | PSR_x | PSR_f},
18732 {"sxc", PSR_s | PSR_x | PSR_c},
18733 {"scf", PSR_s | PSR_c | PSR_f},
18734 {"scx", PSR_s | PSR_c | PSR_x},
18735 {"xfs", PSR_x | PSR_f | PSR_s},
18736 {"xfc", PSR_x | PSR_f | PSR_c},
18737 {"xsf", PSR_x | PSR_s | PSR_f},
18738 {"xsc", PSR_x | PSR_s | PSR_c},
18739 {"xcf", PSR_x | PSR_c | PSR_f},
18740 {"xcs", PSR_x | PSR_c | PSR_s},
18741 {"cfs", PSR_c | PSR_f | PSR_s},
18742 {"cfx", PSR_c | PSR_f | PSR_x},
18743 {"csf", PSR_c | PSR_s | PSR_f},
18744 {"csx", PSR_c | PSR_s | PSR_x},
18745 {"cxf", PSR_c | PSR_x | PSR_f},
18746 {"cxs", PSR_c | PSR_x | PSR_s},
18747 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
18748 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
18749 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
18750 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
18751 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
18752 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
18753 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
18754 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
18755 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
18756 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
18757 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
18758 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
18759 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
18760 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
18761 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
18762 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
18763 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
18764 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
18765 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
18766 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
18767 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
18768 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
18769 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
18770 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
18771};
18772
18773/* Table of V7M psr names. */
18774static const struct asm_psr v7m_psrs[] =
18775{
18776 {"apsr", 0 }, {"APSR", 0 },
18777 {"iapsr", 1 }, {"IAPSR", 1 },
18778 {"eapsr", 2 }, {"EAPSR", 2 },
18779 {"psr", 3 }, {"PSR", 3 },
18780 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18781 {"ipsr", 5 }, {"IPSR", 5 },
18782 {"epsr", 6 }, {"EPSR", 6 },
18783 {"iepsr", 7 }, {"IEPSR", 7 },
18784 {"msp", 8 }, {"MSP", 8 }, {"msp_s", 8 }, {"MSP_S", 8 },
18785 {"psp", 9 }, {"PSP", 9 }, {"psp_s", 9 }, {"PSP_S", 9 },
18786 {"primask", 16}, {"PRIMASK", 16},
18787 {"basepri", 17}, {"BASEPRI", 17},
18788 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18789 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18790 {"faultmask", 19}, {"FAULTMASK", 19},
18791 {"control", 20}, {"CONTROL", 20},
18792 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18793 {"psp_ns", 0x89}, {"PSP_NS", 0x89}
18794};
18795
18796/* Table of all shift-in-operand names. */
18797static const struct asm_shift_name shift_names [] =
18798{
18799 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
18800 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
18801 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
18802 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
18803 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
18804 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
18805};
18806
18807/* Table of all explicit relocation names. */
18808#ifdef OBJ_ELF
18809static struct reloc_entry reloc_names[] =
18810{
18811 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
18812 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
18813 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
18814 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
18815 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
18816 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
18817 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
18818 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
18819 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
18820 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
18821 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
18822 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
18823 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
18824 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
18825 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
18826 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
18827 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
18828 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
18829};
18830#endif
18831
18832/* Table of all conditional affixes. 0xF is not defined as a condition code. */
18833static const struct asm_cond conds[] =
18834{
18835 {"eq", 0x0},
18836 {"ne", 0x1},
18837 {"cs", 0x2}, {"hs", 0x2},
18838 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18839 {"mi", 0x4},
18840 {"pl", 0x5},
18841 {"vs", 0x6},
18842 {"vc", 0x7},
18843 {"hi", 0x8},
18844 {"ls", 0x9},
18845 {"ge", 0xa},
18846 {"lt", 0xb},
18847 {"gt", 0xc},
18848 {"le", 0xd},
18849 {"al", 0xe}
18850};
18851
18852#define UL_BARRIER(L,U,CODE,FEAT) \
18853 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18854 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18855
18856static struct asm_barrier_opt barrier_opt_names[] =
18857{
18858 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
18859 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
18860 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
18861 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
18862 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
18863 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
18864 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
18865 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
18866 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
18867 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
18868 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
18869 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
18870 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
18871 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
18872 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
18873 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
18874};
18875
18876#undef UL_BARRIER
18877
18878/* Table of ARM-format instructions. */
18879
18880/* Macros for gluing together operand strings. N.B. In all cases
18881 other than OPS0, the trailing OP_stop comes from default
18882 zero-initialization of the unspecified elements of the array. */
18883#define OPS0() { OP_stop, }
18884#define OPS1(a) { OP_##a, }
18885#define OPS2(a,b) { OP_##a,OP_##b, }
18886#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18887#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18888#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18889#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18890
18891/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18892 This is useful when mixing operands for ARM and THUMB, i.e. using the
18893 MIX_ARM_THUMB_OPERANDS macro.
18894 In order to use these macros, prefix the number of operands with _
18895 e.g. _3. */
18896#define OPS_1(a) { a, }
18897#define OPS_2(a,b) { a,b, }
18898#define OPS_3(a,b,c) { a,b,c, }
18899#define OPS_4(a,b,c,d) { a,b,c,d, }
18900#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18901#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18902
18903/* These macros abstract out the exact format of the mnemonic table and
18904 save some repeated characters. */
18905
18906/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18907#define TxCE(mnem, op, top, nops, ops, ae, te) \
18908 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18909 THUMB_VARIANT, do_##ae, do_##te }
18910
18911/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18912 a T_MNEM_xyz enumerator. */
18913#define TCE(mnem, aop, top, nops, ops, ae, te) \
18914 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18915#define tCE(mnem, aop, top, nops, ops, ae, te) \
18916 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18917
18918/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18919 infix after the third character. */
18920#define TxC3(mnem, op, top, nops, ops, ae, te) \
18921 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18922 THUMB_VARIANT, do_##ae, do_##te }
18923#define TxC3w(mnem, op, top, nops, ops, ae, te) \
18924 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18925 THUMB_VARIANT, do_##ae, do_##te }
18926#define TC3(mnem, aop, top, nops, ops, ae, te) \
18927 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18928#define TC3w(mnem, aop, top, nops, ops, ae, te) \
18929 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18930#define tC3(mnem, aop, top, nops, ops, ae, te) \
18931 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18932#define tC3w(mnem, aop, top, nops, ops, ae, te) \
18933 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18934
18935/* Mnemonic that cannot be conditionalized. The ARM condition-code
18936 field is still 0xE. Many of the Thumb variants can be executed
18937 conditionally, so this is checked separately. */
18938#define TUE(mnem, op, top, nops, ops, ae, te) \
18939 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18940 THUMB_VARIANT, do_##ae, do_##te }
18941
18942/* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18943 Used by mnemonics that have very minimal differences in the encoding for
18944 ARM and Thumb variants and can be handled in a common function. */
18945#define TUEc(mnem, op, top, nops, ops, en) \
18946 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18947 THUMB_VARIANT, do_##en, do_##en }
18948
18949/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18950 condition code field. */
18951#define TUF(mnem, op, top, nops, ops, ae, te) \
18952 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18953 THUMB_VARIANT, do_##ae, do_##te }
18954
18955/* ARM-only variants of all the above. */
18956#define CE(mnem, op, nops, ops, ae) \
18957 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18958
18959#define C3(mnem, op, nops, ops, ae) \
18960 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18961
18962/* Legacy mnemonics that always have conditional infix after the third
18963 character. */
18964#define CL(mnem, op, nops, ops, ae) \
18965 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18966 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18967
18968/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18969#define cCE(mnem, op, nops, ops, ae) \
18970 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18971
18972/* Legacy coprocessor instructions where conditional infix and conditional
18973 suffix are ambiguous. For consistency this includes all FPA instructions,
18974 not just the potentially ambiguous ones. */
18975#define cCL(mnem, op, nops, ops, ae) \
18976 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18977 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18978
18979/* Coprocessor, takes either a suffix or a position-3 infix
18980 (for an FPA corner case). */
18981#define C3E(mnem, op, nops, ops, ae) \
18982 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18983 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18984
18985#define xCM_(m1, m2, m3, op, nops, ops, ae) \
18986 { m1 #m2 m3, OPS##nops ops, \
18987 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18988 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18989
18990#define CM(m1, m2, op, nops, ops, ae) \
18991 xCM_ (m1, , m2, op, nops, ops, ae), \
18992 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18993 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18994 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18995 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18996 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18997 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18998 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18999 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19000 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19001 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19002 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19003 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19004 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19005 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19006 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19007 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19008 xCM_ (m1, le, m2, op, nops, ops, ae), \
19009 xCM_ (m1, al, m2, op, nops, ops, ae)
19010
19011#define UE(mnem, op, nops, ops, ae) \
19012 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19013
19014#define UF(mnem, op, nops, ops, ae) \
19015 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19016
19017/* Neon data-processing. ARM versions are unconditional with cond=0xf.
19018 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19019 use the same encoding function for each. */
19020#define NUF(mnem, op, nops, ops, enc) \
19021 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19022 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19023
19024/* Neon data processing, version which indirects through neon_enc_tab for
19025 the various overloaded versions of opcodes. */
19026#define nUF(mnem, op, nops, ops, enc) \
19027 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19028 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19029
19030/* Neon insn with conditional suffix for the ARM version, non-overloaded
19031 version. */
19032#define NCE_tag(mnem, op, nops, ops, enc, tag) \
19033 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19034 THUMB_VARIANT, do_##enc, do_##enc }
19035
19036#define NCE(mnem, op, nops, ops, enc) \
19037 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19038
19039#define NCEF(mnem, op, nops, ops, enc) \
19040 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19041
19042/* Neon insn with conditional suffix for the ARM version, overloaded types. */
19043#define nCE_tag(mnem, op, nops, ops, enc, tag) \
19044 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19045 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19046
19047#define nCE(mnem, op, nops, ops, enc) \
19048 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19049
19050#define nCEF(mnem, op, nops, ops, enc) \
19051 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19052
19053#define do_0 0
19054
19055static const struct asm_opcode insns[] =
19056{
19057#define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19058#define THUMB_VARIANT & arm_ext_v4t
19059 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
19060 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
19061 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
19062 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
19063 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
19064 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
19065 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
19066 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
19067 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
19068 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
19069 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
19070 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
19071 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
19072 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
19073 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
19074 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
19075
19076 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19077 for setting PSR flag bits. They are obsolete in V6 and do not
19078 have Thumb equivalents. */
19079 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
19080 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
19081 CL("tstp", 110f000, 2, (RR, SH), cmp),
19082 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
19083 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
19084 CL("cmpp", 150f000, 2, (RR, SH), cmp),
19085 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
19086 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
19087 CL("cmnp", 170f000, 2, (RR, SH), cmp),
19088
19089 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
19090 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
19091 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
19092 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
19093
19094 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
19095 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
19096 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
19097 OP_RRnpc),
19098 OP_ADDRGLDR),ldst, t_ldst),
19099 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
19100
19101 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19102 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19103 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19104 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19105 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19106 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19107
19108 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
19109 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
19110 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
19111 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
19112
19113 /* Pseudo ops. */
19114 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
19115 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
19116 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
19117 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
19118
19119 /* Thumb-compatibility pseudo ops. */
19120 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
19121 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
19122 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
19123 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
19124 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
19125 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
19126 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
19127 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
19128 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
19129 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
19130 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
19131 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
19132
19133 /* These may simplify to neg. */
19134 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
19135 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
19136
19137#undef THUMB_VARIANT
19138#define THUMB_VARIANT & arm_ext_v6
19139
19140 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
19141
19142 /* V1 instructions with no Thumb analogue prior to V6T2. */
19143#undef THUMB_VARIANT
19144#define THUMB_VARIANT & arm_ext_v6t2
19145
19146 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
19147 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
19148 CL("teqp", 130f000, 2, (RR, SH), cmp),
19149
19150 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
19151 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
19152 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
19153 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
19154
19155 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19156 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19157
19158 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19159 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19160
19161 /* V1 instructions with no Thumb analogue at all. */
19162 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
19163 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
19164
19165 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
19166 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
19167 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
19168 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
19169 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
19170 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
19171 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
19172 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
19173
19174#undef ARM_VARIANT
19175#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19176#undef THUMB_VARIANT
19177#define THUMB_VARIANT & arm_ext_v4t
19178
19179 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
19180 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
19181
19182#undef THUMB_VARIANT
19183#define THUMB_VARIANT & arm_ext_v6t2
19184
19185 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
19186 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
19187
19188 /* Generic coprocessor instructions. */
19189 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
19190 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19191 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19192 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19193 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19194 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
19195 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
19196
19197#undef ARM_VARIANT
19198#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19199
19200 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
19201 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
19202
19203#undef ARM_VARIANT
19204#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19205#undef THUMB_VARIANT
19206#define THUMB_VARIANT & arm_ext_msr
19207
19208 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
19209 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
19210
19211#undef ARM_VARIANT
19212#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19213#undef THUMB_VARIANT
19214#define THUMB_VARIANT & arm_ext_v6t2
19215
19216 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19217 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19218 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19219 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19220 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19221 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19222 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19223 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19224
19225#undef ARM_VARIANT
19226#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19227#undef THUMB_VARIANT
19228#define THUMB_VARIANT & arm_ext_v4t
19229
19230 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19231 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19232 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19233 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19234 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19235 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19236
19237#undef ARM_VARIANT
19238#define ARM_VARIANT & arm_ext_v4t_5
19239
19240 /* ARM Architecture 4T. */
19241 /* Note: bx (and blx) are required on V5, even if the processor does
19242 not support Thumb. */
19243 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
19244
19245#undef ARM_VARIANT
19246#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19247#undef THUMB_VARIANT
19248#define THUMB_VARIANT & arm_ext_v5t
19249
19250 /* Note: blx has 2 variants; the .value coded here is for
19251 BLX(2). Only this variant has conditional execution. */
19252 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
19253 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
19254
19255#undef THUMB_VARIANT
19256#define THUMB_VARIANT & arm_ext_v6t2
19257
19258 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
19259 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19260 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19261 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19262 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19263 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
19264 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
19265 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
19266
19267#undef ARM_VARIANT
19268#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19269#undef THUMB_VARIANT
19270#define THUMB_VARIANT & arm_ext_v5exp
19271
19272 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19273 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19274 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19275 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19276
19277 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19278 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19279
19280 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19281 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19282 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19283 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19284
19285 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19286 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19287 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19288 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19289
19290 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19291 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19292
19293 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19294 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19295 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19296 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19297
19298#undef ARM_VARIANT
19299#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19300#undef THUMB_VARIANT
19301#define THUMB_VARIANT & arm_ext_v6t2
19302
19303 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
19304 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
19305 ldrd, t_ldstd),
19306 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
19307 ADDRGLDRS), ldrd, t_ldstd),
19308
19309 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19310 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19311
19312#undef ARM_VARIANT
19313#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19314
19315 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
19316
19317#undef ARM_VARIANT
19318#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19319#undef THUMB_VARIANT
19320#define THUMB_VARIANT & arm_ext_v6
19321
19322 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
19323 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
19324 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
19325 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
19326 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
19327 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19328 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19329 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19330 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19331 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
19332
19333#undef THUMB_VARIANT
19334#define THUMB_VARIANT & arm_ext_v6t2_v8m
19335
19336 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
19337 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
19338 strex, t_strex),
19339#undef THUMB_VARIANT
19340#define THUMB_VARIANT & arm_ext_v6t2
19341
19342 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19343 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19344
19345 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
19346 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
19347
19348/* ARM V6 not included in V7M. */
19349#undef THUMB_VARIANT
19350#define THUMB_VARIANT & arm_ext_v6_notm
19351 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
19352 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
19353 UF(rfeib, 9900a00, 1, (RRw), rfe),
19354 UF(rfeda, 8100a00, 1, (RRw), rfe),
19355 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
19356 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
19357 UF(rfefa, 8100a00, 1, (RRw), rfe),
19358 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
19359 UF(rfeed, 9900a00, 1, (RRw), rfe),
19360 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
19361 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
19362 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
19363 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
19364 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
19365 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
19366 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
19367 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
19368 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
19369 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
19370
19371/* ARM V6 not included in V7M (eg. integer SIMD). */
19372#undef THUMB_VARIANT
19373#define THUMB_VARIANT & arm_ext_v6_dsp
19374 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
19375 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
19376 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19377 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19378 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19379 /* Old name for QASX. */
19380 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19381 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19382 /* Old name for QSAX. */
19383 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19384 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19385 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19386 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19387 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19388 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19389 /* Old name for SASX. */
19390 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19391 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19392 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19393 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19394 /* Old name for SHASX. */
19395 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19396 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19397 /* Old name for SHSAX. */
19398 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19399 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19400 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19401 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19402 /* Old name for SSAX. */
19403 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19404 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19405 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19406 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19407 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19408 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19409 /* Old name for UASX. */
19410 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19411 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19412 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19413 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19414 /* Old name for UHASX. */
19415 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19416 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19417 /* Old name for UHSAX. */
19418 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19419 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19420 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19421 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19422 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19423 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19424 /* Old name for UQASX. */
19425 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19426 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19427 /* Old name for UQSAX. */
19428 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19429 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19430 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19431 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19432 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19433 /* Old name for USAX. */
19434 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19435 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19436 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19437 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19438 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19439 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19440 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19441 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19442 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19443 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19444 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19445 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19446 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19447 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19448 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19449 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19450 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19451 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19452 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19453 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19454 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19455 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19456 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19457 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19458 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19459 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19460 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19461 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19462 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19463 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
19464 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
19465 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19466 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19467 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
19468
19469#undef ARM_VARIANT
19470#define ARM_VARIANT & arm_ext_v6k
19471#undef THUMB_VARIANT
19472#define THUMB_VARIANT & arm_ext_v6k
19473
19474 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
19475 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
19476 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
19477 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
19478
19479#undef THUMB_VARIANT
19480#define THUMB_VARIANT & arm_ext_v6_notm
19481 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
19482 ldrexd, t_ldrexd),
19483 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
19484 RRnpcb), strexd, t_strexd),
19485
19486#undef THUMB_VARIANT
19487#define THUMB_VARIANT & arm_ext_v6t2_v8m
19488 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
19489 rd_rn, rd_rn),
19490 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
19491 rd_rn, rd_rn),
19492 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
19493 strex, t_strexbh),
19494 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
19495 strex, t_strexbh),
19496 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
19497
19498#undef ARM_VARIANT
19499#define ARM_VARIANT & arm_ext_sec
19500#undef THUMB_VARIANT
19501#define THUMB_VARIANT & arm_ext_sec
19502
19503 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
19504
19505#undef ARM_VARIANT
19506#define ARM_VARIANT & arm_ext_virt
19507#undef THUMB_VARIANT
19508#define THUMB_VARIANT & arm_ext_virt
19509
19510 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
19511 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
19512
19513#undef ARM_VARIANT
19514#define ARM_VARIANT & arm_ext_pan
19515#undef THUMB_VARIANT
19516#define THUMB_VARIANT & arm_ext_pan
19517
19518 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
19519
19520#undef ARM_VARIANT
19521#define ARM_VARIANT & arm_ext_v6t2
19522#undef THUMB_VARIANT
19523#define THUMB_VARIANT & arm_ext_v6t2
19524
19525 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
19526 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
19527 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
19528 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
19529
19530 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
19531 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
19532
19533 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19534 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19535 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19536 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19537
19538#undef THUMB_VARIANT
19539#define THUMB_VARIANT & arm_ext_v6t2_v8m
19540 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
19541 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
19542
19543 /* Thumb-only instructions. */
19544#undef ARM_VARIANT
19545#define ARM_VARIANT NULL
19546 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
19547 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
19548
19549 /* ARM does not really have an IT instruction, so always allow it.
19550 The opcode is copied from Thumb in order to allow warnings in
19551 -mimplicit-it=[never | arm] modes. */
19552#undef ARM_VARIANT
19553#define ARM_VARIANT & arm_ext_v1
19554#undef THUMB_VARIANT
19555#define THUMB_VARIANT & arm_ext_v6t2
19556
19557 TUE("it", bf08, bf08, 1, (COND), it, t_it),
19558 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
19559 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
19560 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
19561 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
19562 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
19563 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
19564 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
19565 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
19566 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
19567 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
19568 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
19569 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
19570 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
19571 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
19572 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19573 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
19574 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
19575
19576 /* Thumb2 only instructions. */
19577#undef ARM_VARIANT
19578#define ARM_VARIANT NULL
19579
19580 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
19581 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
19582 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
19583 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
19584 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
19585 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
19586
19587 /* Hardware division instructions. */
19588#undef ARM_VARIANT
19589#define ARM_VARIANT & arm_ext_adiv
19590#undef THUMB_VARIANT
19591#define THUMB_VARIANT & arm_ext_div
19592
19593 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
19594 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
19595
19596 /* ARM V6M/V7 instructions. */
19597#undef ARM_VARIANT
19598#define ARM_VARIANT & arm_ext_barrier
19599#undef THUMB_VARIANT
19600#define THUMB_VARIANT & arm_ext_barrier
19601
19602 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
19603 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
19604 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
19605
19606 /* ARM V7 instructions. */
19607#undef ARM_VARIANT
19608#define ARM_VARIANT & arm_ext_v7
19609#undef THUMB_VARIANT
19610#define THUMB_VARIANT & arm_ext_v7
19611
19612 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
19613 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
19614
19615#undef ARM_VARIANT
19616#define ARM_VARIANT & arm_ext_mp
19617#undef THUMB_VARIANT
19618#define THUMB_VARIANT & arm_ext_mp
19619
19620 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
19621
19622 /* AArchv8 instructions. */
19623#undef ARM_VARIANT
19624#define ARM_VARIANT & arm_ext_v8
19625
19626/* Instructions shared between armv8-a and armv8-m. */
19627#undef THUMB_VARIANT
19628#define THUMB_VARIANT & arm_ext_atomics
19629
19630 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19631 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19632 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19633 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
19634 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
19635 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
19636 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19637 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
19638 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19639 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
19640 stlex, t_stlex),
19641 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
19642 stlex, t_stlex),
19643 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
19644 stlex, t_stlex),
19645#undef THUMB_VARIANT
19646#define THUMB_VARIANT & arm_ext_v8
19647
19648 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
19649 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
19650 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
19651 ldrexd, t_ldrexd),
19652 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
19653 strexd, t_strexd),
19654 /* ARMv8 T32 only. */
19655#undef ARM_VARIANT
19656#define ARM_VARIANT NULL
19657 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
19658 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
19659 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
19660
19661 /* FP for ARMv8. */
19662#undef ARM_VARIANT
19663#define ARM_VARIANT & fpu_vfp_ext_armv8xd
19664#undef THUMB_VARIANT
19665#define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19666
19667 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
19668 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
19669 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
19670 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
19671 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
19672 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
19673 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
19674 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
19675 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
19676 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
19677 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
19678 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
19679 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
19680 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
19681 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
19682 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
19683 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
19684
19685 /* Crypto v1 extensions. */
19686#undef ARM_VARIANT
19687#define ARM_VARIANT & fpu_crypto_ext_armv8
19688#undef THUMB_VARIANT
19689#define THUMB_VARIANT & fpu_crypto_ext_armv8
19690
19691 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
19692 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
19693 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
19694 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
19695 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
19696 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
19697 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
19698 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
19699 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
19700 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
19701 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
19702 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
19703 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
19704 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
19705
19706#undef ARM_VARIANT
19707#define ARM_VARIANT & crc_ext_armv8
19708#undef THUMB_VARIANT
19709#define THUMB_VARIANT & crc_ext_armv8
19710 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
19711 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
19712 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
19713 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
19714 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
19715 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
19716
19717 /* ARMv8.2 RAS extension. */
19718#undef ARM_VARIANT
19719#define ARM_VARIANT & arm_ext_v8_2
19720#undef THUMB_VARIANT
19721#define THUMB_VARIANT & arm_ext_v8_2
19722 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
19723
19724#undef ARM_VARIANT
19725#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19726#undef THUMB_VARIANT
19727#define THUMB_VARIANT NULL
19728
19729 cCE("wfs", e200110, 1, (RR), rd),
19730 cCE("rfs", e300110, 1, (RR), rd),
19731 cCE("wfc", e400110, 1, (RR), rd),
19732 cCE("rfc", e500110, 1, (RR), rd),
19733
19734 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
19735 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
19736 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
19737 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
19738
19739 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
19740 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
19741 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
19742 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
19743
19744 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
19745 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
19746 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
19747 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
19748 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
19749 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
19750 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
19751 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
19752 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
19753 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
19754 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
19755 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
19756
19757 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
19758 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
19759 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
19760 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
19761 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
19762 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
19763 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
19764 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
19765 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
19766 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
19767 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
19768 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
19769
19770 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
19771 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
19772 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
19773 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
19774 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
19775 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
19776 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
19777 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
19778 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
19779 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
19780 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
19781 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
19782
19783 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
19784 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
19785 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
19786 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
19787 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
19788 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
19789 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
19790 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
19791 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
19792 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
19793 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
19794 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
19795
19796 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
19797 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
19798 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
19799 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
19800 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
19801 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
19802 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
19803 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
19804 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
19805 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
19806 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
19807 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
19808
19809 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
19810 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
19811 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
19812 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
19813 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
19814 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
19815 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
19816 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
19817 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
19818 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
19819 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
19820 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
19821
19822 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
19823 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
19824 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
19825 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
19826 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
19827 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
19828 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
19829 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
19830 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
19831 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
19832 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
19833 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
19834
19835 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
19836 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
19837 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
19838 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
19839 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
19840 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
19841 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
19842 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
19843 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
19844 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
19845 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
19846 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
19847
19848 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
19849 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
19850 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
19851 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
19852 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
19853 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
19854 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
19855 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
19856 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
19857 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
19858 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
19859 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
19860
19861 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
19862 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
19863 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
19864 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
19865 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
19866 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
19867 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
19868 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
19869 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
19870 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
19871 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
19872 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
19873
19874 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
19875 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
19876 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
19877 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
19878 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
19879 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
19880 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
19881 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
19882 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
19883 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
19884 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
19885 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
19886
19887 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
19888 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
19889 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
19890 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
19891 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
19892 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
19893 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
19894 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
19895 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
19896 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
19897 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
19898 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
19899
19900 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
19901 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
19902 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
19903 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
19904 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
19905 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
19906 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
19907 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
19908 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
19909 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
19910 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
19911 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
19912
19913 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
19914 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
19915 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
19916 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
19917 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
19918 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
19919 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
19920 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
19921 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
19922 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
19923 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
19924 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
19925
19926 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
19927 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
19928 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
19929 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
19930 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
19931 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
19932 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
19933 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
19934 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
19935 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
19936 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
19937 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
19938
19939 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
19940 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
19941 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
19942 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
19943 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
19944 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
19945 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
19946 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
19947 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
19948 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
19949 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
19950 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
19951
19952 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
19953 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
19954 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
19955 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
19956 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
19957 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19958 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19959 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19960 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
19961 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
19962 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
19963 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
19964
19965 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
19966 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
19967 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
19968 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
19969 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
19970 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19971 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19972 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19973 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
19974 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
19975 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
19976 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
19977
19978 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
19979 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
19980 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
19981 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
19982 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
19983 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19984 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19985 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19986 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
19987 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
19988 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
19989 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
19990
19991 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
19992 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
19993 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
19994 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
19995 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
19996 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19997 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19998 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19999 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
20000 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
20001 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
20002 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
20003
20004 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
20005 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
20006 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
20007 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
20008 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
20009 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20010 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20011 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20012 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
20013 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
20014 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
20015 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
20016
20017 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
20018 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
20019 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
20020 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
20021 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
20022 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20023 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20024 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20025 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
20026 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
20027 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
20028 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
20029
20030 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
20031 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
20032 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
20033 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
20034 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
20035 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20036 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20037 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20038 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
20039 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
20040 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
20041 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
20042
20043 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
20044 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
20045 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
20046 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
20047 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
20048 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20049 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20050 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20051 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
20052 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
20053 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
20054 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
20055
20056 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
20057 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
20058 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
20059 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
20060 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
20061 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20062 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20063 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20064 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
20065 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
20066 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
20067 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
20068
20069 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
20070 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
20071 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
20072 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
20073 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
20074 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20075 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20076 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20077 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
20078 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
20079 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
20080 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
20081
20082 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
20083 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
20084 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
20085 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
20086 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
20087 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20088 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20089 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20090 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
20091 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
20092 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
20093 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
20094
20095 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
20096 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
20097 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
20098 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
20099 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
20100 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20101 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20102 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20103 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
20104 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
20105 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
20106 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
20107
20108 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
20109 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
20110 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
20111 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
20112 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
20113 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20114 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20115 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20116 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
20117 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
20118 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
20119 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
20120
20121 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
20122 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
20123 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
20124 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
20125
20126 cCL("flts", e000110, 2, (RF, RR), rn_rd),
20127 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
20128 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
20129 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
20130 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
20131 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
20132 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
20133 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
20134 cCL("flte", e080110, 2, (RF, RR), rn_rd),
20135 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
20136 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
20137 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
20138
20139 /* The implementation of the FIX instruction is broken on some
20140 assemblers, in that it accepts a precision specifier as well as a
20141 rounding specifier, despite the fact that this is meaningless.
20142 To be more compatible, we accept it as well, though of course it
20143 does not set any bits. */
20144 cCE("fix", e100110, 2, (RR, RF), rd_rm),
20145 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
20146 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
20147 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
20148 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
20149 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
20150 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
20151 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
20152 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
20153 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
20154 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
20155 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
20156 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
20157
20158 /* Instructions that were new with the real FPA, call them V2. */
20159#undef ARM_VARIANT
20160#define ARM_VARIANT & fpu_fpa_ext_v2
20161
20162 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20163 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20164 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20165 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20166 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20167 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20168
20169#undef ARM_VARIANT
20170#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20171
20172 /* Moves and type conversions. */
20173 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
20174 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
20175 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
20176 cCE("fmstat", ef1fa10, 0, (), noargs),
20177 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
20178 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
20179 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
20180 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
20181 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
20182 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
20183 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
20184 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
20185 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
20186 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
20187
20188 /* Memory operations. */
20189 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
20190 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
20191 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20192 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20193 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20194 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20195 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20196 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20197 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20198 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20199 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20200 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20201 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20202 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20203 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20204 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20205 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20206 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20207
20208 /* Monadic operations. */
20209 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
20210 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
20211 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
20212
20213 /* Dyadic operations. */
20214 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20215 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20216 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20217 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20218 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20219 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20220 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20221 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20222 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20223
20224 /* Comparisons. */
20225 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
20226 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
20227 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
20228 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
20229
20230 /* Double precision load/store are still present on single precision
20231 implementations. */
20232 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
20233 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
20234 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20235 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20236 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20237 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20238 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20239 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20240 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20241 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20242
20243#undef ARM_VARIANT
20244#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20245
20246 /* Moves and type conversions. */
20247 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
20248 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
20249 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
20250 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
20251 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
20252 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
20253 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
20254 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
20255 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
20256 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
20257 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
20258 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
20259 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
20260
20261 /* Monadic operations. */
20262 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
20263 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
20264 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
20265
20266 /* Dyadic operations. */
20267 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20268 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20269 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20270 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20271 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20272 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20273 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20274 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20275 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20276
20277 /* Comparisons. */
20278 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
20279 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
20280 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
20281 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
20282
20283#undef ARM_VARIANT
20284#define ARM_VARIANT & fpu_vfp_ext_v2
20285
20286 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
20287 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
20288 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
20289 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
20290
20291/* Instructions which may belong to either the Neon or VFP instruction sets.
20292 Individual encoder functions perform additional architecture checks. */
20293#undef ARM_VARIANT
20294#define ARM_VARIANT & fpu_vfp_ext_v1xd
20295#undef THUMB_VARIANT
20296#define THUMB_VARIANT & fpu_vfp_ext_v1xd
20297
20298 /* These mnemonics are unique to VFP. */
20299 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
20300 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
20301 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20302 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20303 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20304 nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
20305 nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
20306 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
20307 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
20308 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
20309
20310 /* Mnemonics shared by Neon and VFP. */
20311 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
20312 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
20313 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
20314
20315 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
20316 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
20317
20318 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
20319 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
20320
20321 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20322 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20323 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20324 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20325 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20326 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20327 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
20328 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
20329
20330 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
20331 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
20332 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
20333 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
20334
20335
20336 /* NOTE: All VMOV encoding is special-cased! */
20337 NCE(vmov, 0, 1, (VMOV), neon_mov),
20338 NCE(vmovq, 0, 1, (VMOV), neon_mov),
20339
20340#undef ARM_VARIANT
20341#define ARM_VARIANT & arm_ext_fp16
20342#undef THUMB_VARIANT
20343#define THUMB_VARIANT & arm_ext_fp16
20344 /* New instructions added from v8.2, allowing the extraction and insertion of
20345 the upper 16 bits of a 32-bit vector register. */
20346 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
20347 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
20348
20349#undef THUMB_VARIANT
20350#define THUMB_VARIANT & fpu_neon_ext_v1
20351#undef ARM_VARIANT
20352#define ARM_VARIANT & fpu_neon_ext_v1
20353
20354 /* Data processing with three registers of the same length. */
20355 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20356 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
20357 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
20358 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
20359 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
20360 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
20361 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
20362 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
20363 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
20364 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20365 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
20366 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
20367 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
20368 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
20369 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
20370 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
20371 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
20372 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
20373 /* If not immediate, fall back to neon_dyadic_i64_su.
20374 shl_imm should accept I8 I16 I32 I64,
20375 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20376 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
20377 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
20378 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
20379 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
20380 /* Logic ops, types optional & ignored. */
20381 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20382 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20383 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20384 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20385 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20386 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20387 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20388 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20389 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
20390 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
20391 /* Bitfield ops, untyped. */
20392 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
20393 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
20394 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
20395 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
20396 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
20397 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
20398 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20399 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
20400 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
20401 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
20402 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
20403 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
20404 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
20405 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20406 back to neon_dyadic_if_su. */
20407 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
20408 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
20409 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
20410 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
20411 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
20412 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
20413 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
20414 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
20415 /* Comparison. Type I8 I16 I32 F32. */
20416 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
20417 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
20418 /* As above, D registers only. */
20419 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
20420 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
20421 /* Int and float variants, signedness unimportant. */
20422 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
20423 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
20424 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
20425 /* Add/sub take types I8 I16 I32 I64 F32. */
20426 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
20427 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
20428 /* vtst takes sizes 8, 16, 32. */
20429 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
20430 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
20431 /* VMUL takes I8 I16 I32 F32 P8. */
20432 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
20433 /* VQD{R}MULH takes S16 S32. */
20434 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
20435 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
20436 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
20437 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
20438 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
20439 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
20440 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
20441 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
20442 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
20443 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
20444 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
20445 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
20446 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
20447 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
20448 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
20449 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
20450 /* ARM v8.1 extension. */
20451 nUF (vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
20452 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
20453 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
20454 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
20455
20456 /* Two address, int/float. Types S8 S16 S32 F32. */
20457 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
20458 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
20459
20460 /* Data processing with two registers and a shift amount. */
20461 /* Right shifts, and variants with rounding.
20462 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20463 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
20464 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
20465 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
20466 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
20467 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
20468 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
20469 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
20470 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
20471 /* Shift and insert. Sizes accepted 8 16 32 64. */
20472 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
20473 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
20474 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
20475 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
20476 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20477 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
20478 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
20479 /* Right shift immediate, saturating & narrowing, with rounding variants.
20480 Types accepted S16 S32 S64 U16 U32 U64. */
20481 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
20482 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
20483 /* As above, unsigned. Types accepted S16 S32 S64. */
20484 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
20485 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
20486 /* Right shift narrowing. Types accepted I16 I32 I64. */
20487 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
20488 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
20489 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20490 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
20491 /* CVT with optional immediate for fixed-point variant. */
20492 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
20493
20494 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
20495 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
20496
20497 /* Data processing, three registers of different lengths. */
20498 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20499 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
20500 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
20501 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
20502 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
20503 /* If not scalar, fall back to neon_dyadic_long.
20504 Vector types as above, scalar types S16 S32 U16 U32. */
20505 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
20506 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
20507 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20508 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
20509 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
20510 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20511 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
20512 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
20513 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
20514 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
20515 /* Saturating doubling multiplies. Types S16 S32. */
20516 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
20517 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
20518 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
20519 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20520 S16 S32 U16 U32. */
20521 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
20522
20523 /* Extract. Size 8. */
20524 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
20525 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
20526
20527 /* Two registers, miscellaneous. */
20528 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20529 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
20530 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
20531 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
20532 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
20533 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
20534 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
20535 /* Vector replicate. Sizes 8 16 32. */
20536 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
20537 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
20538 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20539 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
20540 /* VMOVN. Types I16 I32 I64. */
20541 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
20542 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20543 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
20544 /* VQMOVUN. Types S16 S32 S64. */
20545 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
20546 /* VZIP / VUZP. Sizes 8 16 32. */
20547 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
20548 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
20549 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
20550 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
20551 /* VQABS / VQNEG. Types S8 S16 S32. */
20552 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
20553 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
20554 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
20555 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
20556 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20557 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
20558 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
20559 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
20560 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
20561 /* Reciprocal estimates. Types U32 F16 F32. */
20562 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
20563 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
20564 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
20565 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
20566 /* VCLS. Types S8 S16 S32. */
20567 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
20568 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
20569 /* VCLZ. Types I8 I16 I32. */
20570 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
20571 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
20572 /* VCNT. Size 8. */
20573 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
20574 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
20575 /* Two address, untyped. */
20576 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
20577 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
20578 /* VTRN. Sizes 8 16 32. */
20579 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
20580 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
20581
20582 /* Table lookup. Size 8. */
20583 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
20584 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
20585
20586#undef THUMB_VARIANT
20587#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20588#undef ARM_VARIANT
20589#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20590
20591 /* Neon element/structure load/store. */
20592 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
20593 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
20594 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
20595 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
20596 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
20597 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
20598 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
20599 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
20600
20601#undef THUMB_VARIANT
20602#define THUMB_VARIANT & fpu_vfp_ext_v3xd
20603#undef ARM_VARIANT
20604#define ARM_VARIANT & fpu_vfp_ext_v3xd
20605 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
20606 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20607 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20608 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20609 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20610 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20611 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20612 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20613 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20614
20615#undef THUMB_VARIANT
20616#define THUMB_VARIANT & fpu_vfp_ext_v3
20617#undef ARM_VARIANT
20618#define ARM_VARIANT & fpu_vfp_ext_v3
20619
20620 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
20621 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20622 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20623 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20624 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20625 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20626 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20627 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20628 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20629
20630#undef ARM_VARIANT
20631#define ARM_VARIANT & fpu_vfp_ext_fma
20632#undef THUMB_VARIANT
20633#define THUMB_VARIANT & fpu_vfp_ext_fma
20634 /* Mnemonics shared by Neon and VFP. These are included in the
20635 VFP FMA variant; NEON and VFP FMA always includes the NEON
20636 FMA instructions. */
20637 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
20638 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
20639 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20640 the v form should always be used. */
20641 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20642 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20643 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20644 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20645 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20646 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20647
20648#undef THUMB_VARIANT
20649#undef ARM_VARIANT
20650#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20651
20652 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20653 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20654 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20655 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20656 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20657 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20658 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
20659 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
20660
20661#undef ARM_VARIANT
20662#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20663
20664 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
20665 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
20666 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
20667 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
20668 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
20669 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
20670 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
20671 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
20672 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
20673 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
20674 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
20675 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
20676 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
20677 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
20678 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
20679 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
20680 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
20681 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
20682 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
20683 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
20684 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20685 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20686 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20687 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20688 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20689 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20690 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
20691 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
20692 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
20693 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
20694 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
20695 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
20696 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
20697 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
20698 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
20699 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
20700 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
20701 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20702 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20703 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20704 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20705 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20706 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20707 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20708 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20709 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20710 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
20711 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20712 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20713 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20714 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20715 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20716 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20717 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20718 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20719 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20720 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20721 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20722 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20723 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20724 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20725 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20726 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20727 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20728 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20729 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20730 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20731 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20732 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
20733 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
20734 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20735 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20736 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20737 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20738 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20739 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20740 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20741 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20742 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20743 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20744 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20745 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20746 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20747 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20748 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20749 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20750 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20751 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20752 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
20753 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20754 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20755 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20756 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20757 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20758 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20759 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20760 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20761 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20762 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20763 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20764 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20765 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20766 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20767 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20768 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20769 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20770 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20771 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20772 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20773 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20774 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
20775 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20776 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20777 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20778 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20779 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20780 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20781 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20782 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20783 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20784 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20785 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20786 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20787 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20788 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20789 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20790 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20791 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20792 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20793 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20794 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20795 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
20796 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
20797 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20798 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20799 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20800 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20801 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20802 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20803 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20804 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20805 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20806 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
20807 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
20808 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
20809 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
20810 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
20811 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
20812 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20813 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20814 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20815 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
20816 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
20817 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
20818 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
20819 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
20820 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
20821 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20822 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20823 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20824 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20825 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
20826
20827#undef ARM_VARIANT
20828#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20829
20830 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
20831 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
20832 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
20833 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
20834 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
20835 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
20836 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20837 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20838 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20839 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20840 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20841 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20842 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20843 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20844 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20845 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20846 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20847 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20848 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20849 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20850 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
20851 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20852 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20853 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20854 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20855 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20856 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20857 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20858 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20859 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20860 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20861 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20862 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20863 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20864 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20865 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20866 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20867 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20868 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20869 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20870 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20871 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20872 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20873 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20874 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20875 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20876 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20877 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20878 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20879 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20880 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20881 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20882 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20883 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20884 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20885 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20886 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20887
20888#undef ARM_VARIANT
20889#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20890
20891 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
20892 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
20893 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
20894 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
20895 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
20896 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
20897 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
20898 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
20899 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
20900 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
20901 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
20902 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
20903 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
20904 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
20905 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
20906 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
20907 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
20908 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
20909 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
20910 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
20911 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
20912 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
20913 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
20914 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
20915 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
20916 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
20917 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
20918 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
20919 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
20920 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
20921 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
20922 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
20923 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
20924 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
20925 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
20926 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
20927 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
20928 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
20929 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
20930 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
20931 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
20932 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
20933 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
20934 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
20935 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
20936 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
20937 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
20938 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
20939 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
20940 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
20941 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
20942 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
20943 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
20944 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
20945 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
20946 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
20947 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
20948 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
20949 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
20950 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
20951 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
20952 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
20953 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
20954 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
20955 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20956 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20957 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20958 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20959 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20960 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20961 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20962 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20963 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
20964 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
20965 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
20966 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
20967
20968 /* ARMv8-M instructions. */
20969#undef ARM_VARIANT
20970#define ARM_VARIANT NULL
20971#undef THUMB_VARIANT
20972#define THUMB_VARIANT & arm_ext_v8m
20973 TUE("sg", 0, e97fe97f, 0, (), 0, noargs),
20974 TUE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx),
20975 TUE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx),
20976 TUE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
20977 TUE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
20978 TUE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt),
20979 TUE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt),
20980
20981 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
20982 instructions behave as nop if no VFP is present. */
20983#undef THUMB_VARIANT
20984#define THUMB_VARIANT & arm_ext_v8m_main
20985 TUEc("vlldm", 0, ec300a00, 1, (RRnpc), rn),
20986 TUEc("vlstm", 0, ec200a00, 1, (RRnpc), rn),
20987};
20988#undef ARM_VARIANT
20989#undef THUMB_VARIANT
20990#undef TCE
20991#undef TUE
20992#undef TUF
20993#undef TCC
20994#undef cCE
20995#undef cCL
20996#undef C3E
20997#undef CE
20998#undef CM
20999#undef UE
21000#undef UF
21001#undef UT
21002#undef NUF
21003#undef nUF
21004#undef NCE
21005#undef nCE
21006#undef OPS0
21007#undef OPS1
21008#undef OPS2
21009#undef OPS3
21010#undef OPS4
21011#undef OPS5
21012#undef OPS6
21013#undef do_0
21014\f
21015/* MD interface: bits in the object file. */
21016
21017/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21018 for use in the a.out file, and stores them in the array pointed to by buf.
21019 This knows about the endian-ness of the target machine and does
21020 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21021 2 (short) and 4 (long) Floating numbers are put out as a series of
21022 LITTLENUMS (shorts, here at least). */
21023
21024void
21025md_number_to_chars (char * buf, valueT val, int n)
21026{
21027 if (target_big_endian)
21028 number_to_chars_bigendian (buf, val, n);
21029 else
21030 number_to_chars_littleendian (buf, val, n);
21031}
21032
21033static valueT
21034md_chars_to_number (char * buf, int n)
21035{
21036 valueT result = 0;
21037 unsigned char * where = (unsigned char *) buf;
21038
21039 if (target_big_endian)
21040 {
21041 while (n--)
21042 {
21043 result <<= 8;
21044 result |= (*where++ & 255);
21045 }
21046 }
21047 else
21048 {
21049 while (n--)
21050 {
21051 result <<= 8;
21052 result |= (where[n] & 255);
21053 }
21054 }
21055
21056 return result;
21057}
21058
21059/* MD interface: Sections. */
21060
21061/* Calculate the maximum variable size (i.e., excluding fr_fix)
21062 that an rs_machine_dependent frag may reach. */
21063
21064unsigned int
21065arm_frag_max_var (fragS *fragp)
21066{
21067 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21068 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21069
21070 Note that we generate relaxable instructions even for cases that don't
21071 really need it, like an immediate that's a trivial constant. So we're
21072 overestimating the instruction size for some of those cases. Rather
21073 than putting more intelligence here, it would probably be better to
21074 avoid generating a relaxation frag in the first place when it can be
21075 determined up front that a short instruction will suffice. */
21076
21077 gas_assert (fragp->fr_type == rs_machine_dependent);
21078 return INSN_SIZE;
21079}
21080
21081/* Estimate the size of a frag before relaxing. Assume everything fits in
21082 2 bytes. */
21083
21084int
21085md_estimate_size_before_relax (fragS * fragp,
21086 segT segtype ATTRIBUTE_UNUSED)
21087{
21088 fragp->fr_var = 2;
21089 return 2;
21090}
21091
21092/* Convert a machine dependent frag. */
21093
21094void
21095md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
21096{
21097 unsigned long insn;
21098 unsigned long old_op;
21099 char *buf;
21100 expressionS exp;
21101 fixS *fixp;
21102 int reloc_type;
21103 int pc_rel;
21104 int opcode;
21105
21106 buf = fragp->fr_literal + fragp->fr_fix;
21107
21108 old_op = bfd_get_16(abfd, buf);
21109 if (fragp->fr_symbol)
21110 {
21111 exp.X_op = O_symbol;
21112 exp.X_add_symbol = fragp->fr_symbol;
21113 }
21114 else
21115 {
21116 exp.X_op = O_constant;
21117 }
21118 exp.X_add_number = fragp->fr_offset;
21119 opcode = fragp->fr_subtype;
21120 switch (opcode)
21121 {
21122 case T_MNEM_ldr_pc:
21123 case T_MNEM_ldr_pc2:
21124 case T_MNEM_ldr_sp:
21125 case T_MNEM_str_sp:
21126 case T_MNEM_ldr:
21127 case T_MNEM_ldrb:
21128 case T_MNEM_ldrh:
21129 case T_MNEM_str:
21130 case T_MNEM_strb:
21131 case T_MNEM_strh:
21132 if (fragp->fr_var == 4)
21133 {
21134 insn = THUMB_OP32 (opcode);
21135 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
21136 {
21137 insn |= (old_op & 0x700) << 4;
21138 }
21139 else
21140 {
21141 insn |= (old_op & 7) << 12;
21142 insn |= (old_op & 0x38) << 13;
21143 }
21144 insn |= 0x00000c00;
21145 put_thumb32_insn (buf, insn);
21146 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
21147 }
21148 else
21149 {
21150 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
21151 }
21152 pc_rel = (opcode == T_MNEM_ldr_pc2);
21153 break;
21154 case T_MNEM_adr:
21155 if (fragp->fr_var == 4)
21156 {
21157 insn = THUMB_OP32 (opcode);
21158 insn |= (old_op & 0xf0) << 4;
21159 put_thumb32_insn (buf, insn);
21160 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
21161 }
21162 else
21163 {
21164 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
21165 exp.X_add_number -= 4;
21166 }
21167 pc_rel = 1;
21168 break;
21169 case T_MNEM_mov:
21170 case T_MNEM_movs:
21171 case T_MNEM_cmp:
21172 case T_MNEM_cmn:
21173 if (fragp->fr_var == 4)
21174 {
21175 int r0off = (opcode == T_MNEM_mov
21176 || opcode == T_MNEM_movs) ? 0 : 8;
21177 insn = THUMB_OP32 (opcode);
21178 insn = (insn & 0xe1ffffff) | 0x10000000;
21179 insn |= (old_op & 0x700) << r0off;
21180 put_thumb32_insn (buf, insn);
21181 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
21182 }
21183 else
21184 {
21185 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
21186 }
21187 pc_rel = 0;
21188 break;
21189 case T_MNEM_b:
21190 if (fragp->fr_var == 4)
21191 {
21192 insn = THUMB_OP32(opcode);
21193 put_thumb32_insn (buf, insn);
21194 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
21195 }
21196 else
21197 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
21198 pc_rel = 1;
21199 break;
21200 case T_MNEM_bcond:
21201 if (fragp->fr_var == 4)
21202 {
21203 insn = THUMB_OP32(opcode);
21204 insn |= (old_op & 0xf00) << 14;
21205 put_thumb32_insn (buf, insn);
21206 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
21207 }
21208 else
21209 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
21210 pc_rel = 1;
21211 break;
21212 case T_MNEM_add_sp:
21213 case T_MNEM_add_pc:
21214 case T_MNEM_inc_sp:
21215 case T_MNEM_dec_sp:
21216 if (fragp->fr_var == 4)
21217 {
21218 /* ??? Choose between add and addw. */
21219 insn = THUMB_OP32 (opcode);
21220 insn |= (old_op & 0xf0) << 4;
21221 put_thumb32_insn (buf, insn);
21222 if (opcode == T_MNEM_add_pc)
21223 reloc_type = BFD_RELOC_ARM_T32_IMM12;
21224 else
21225 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
21226 }
21227 else
21228 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
21229 pc_rel = 0;
21230 break;
21231
21232 case T_MNEM_addi:
21233 case T_MNEM_addis:
21234 case T_MNEM_subi:
21235 case T_MNEM_subis:
21236 if (fragp->fr_var == 4)
21237 {
21238 insn = THUMB_OP32 (opcode);
21239 insn |= (old_op & 0xf0) << 4;
21240 insn |= (old_op & 0xf) << 16;
21241 put_thumb32_insn (buf, insn);
21242 if (insn & (1 << 20))
21243 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
21244 else
21245 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
21246 }
21247 else
21248 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
21249 pc_rel = 0;
21250 break;
21251 default:
21252 abort ();
21253 }
21254 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21255 (enum bfd_reloc_code_real) reloc_type);
21256 fixp->fx_file = fragp->fr_file;
21257 fixp->fx_line = fragp->fr_line;
21258 fragp->fr_fix += fragp->fr_var;
21259
21260 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21261 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
21262 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
21263 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
21264}
21265
21266/* Return the size of a relaxable immediate operand instruction.
21267 SHIFT and SIZE specify the form of the allowable immediate. */
21268static int
21269relax_immediate (fragS *fragp, int size, int shift)
21270{
21271 offsetT offset;
21272 offsetT mask;
21273 offsetT low;
21274
21275 /* ??? Should be able to do better than this. */
21276 if (fragp->fr_symbol)
21277 return 4;
21278
21279 low = (1 << shift) - 1;
21280 mask = (1 << (shift + size)) - (1 << shift);
21281 offset = fragp->fr_offset;
21282 /* Force misaligned offsets to 32-bit variant. */
21283 if (offset & low)
21284 return 4;
21285 if (offset & ~mask)
21286 return 4;
21287 return 2;
21288}
21289
21290/* Get the address of a symbol during relaxation. */
21291static addressT
21292relaxed_symbol_addr (fragS *fragp, long stretch)
21293{
21294 fragS *sym_frag;
21295 addressT addr;
21296 symbolS *sym;
21297
21298 sym = fragp->fr_symbol;
21299 sym_frag = symbol_get_frag (sym);
21300 know (S_GET_SEGMENT (sym) != absolute_section
21301 || sym_frag == &zero_address_frag);
21302 addr = S_GET_VALUE (sym) + fragp->fr_offset;
21303
21304 /* If frag has yet to be reached on this pass, assume it will
21305 move by STRETCH just as we did. If this is not so, it will
21306 be because some frag between grows, and that will force
21307 another pass. */
21308
21309 if (stretch != 0
21310 && sym_frag->relax_marker != fragp->relax_marker)
21311 {
21312 fragS *f;
21313
21314 /* Adjust stretch for any alignment frag. Note that if have
21315 been expanding the earlier code, the symbol may be
21316 defined in what appears to be an earlier frag. FIXME:
21317 This doesn't handle the fr_subtype field, which specifies
21318 a maximum number of bytes to skip when doing an
21319 alignment. */
21320 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
21321 {
21322 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
21323 {
21324 if (stretch < 0)
21325 stretch = - ((- stretch)
21326 & ~ ((1 << (int) f->fr_offset) - 1));
21327 else
21328 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
21329 if (stretch == 0)
21330 break;
21331 }
21332 }
21333 if (f != NULL)
21334 addr += stretch;
21335 }
21336
21337 return addr;
21338}
21339
21340/* Return the size of a relaxable adr pseudo-instruction or PC-relative
21341 load. */
21342static int
21343relax_adr (fragS *fragp, asection *sec, long stretch)
21344{
21345 addressT addr;
21346 offsetT val;
21347
21348 /* Assume worst case for symbols not known to be in the same section. */
21349 if (fragp->fr_symbol == NULL
21350 || !S_IS_DEFINED (fragp->fr_symbol)
21351 || sec != S_GET_SEGMENT (fragp->fr_symbol)
21352 || S_IS_WEAK (fragp->fr_symbol))
21353 return 4;
21354
21355 val = relaxed_symbol_addr (fragp, stretch);
21356 addr = fragp->fr_address + fragp->fr_fix;
21357 addr = (addr + 4) & ~3;
21358 /* Force misaligned targets to 32-bit variant. */
21359 if (val & 3)
21360 return 4;
21361 val -= addr;
21362 if (val < 0 || val > 1020)
21363 return 4;
21364 return 2;
21365}
21366
21367/* Return the size of a relaxable add/sub immediate instruction. */
21368static int
21369relax_addsub (fragS *fragp, asection *sec)
21370{
21371 char *buf;
21372 int op;
21373
21374 buf = fragp->fr_literal + fragp->fr_fix;
21375 op = bfd_get_16(sec->owner, buf);
21376 if ((op & 0xf) == ((op >> 4) & 0xf))
21377 return relax_immediate (fragp, 8, 0);
21378 else
21379 return relax_immediate (fragp, 3, 0);
21380}
21381
21382/* Return TRUE iff the definition of symbol S could be pre-empted
21383 (overridden) at link or load time. */
21384static bfd_boolean
21385symbol_preemptible (symbolS *s)
21386{
21387 /* Weak symbols can always be pre-empted. */
21388 if (S_IS_WEAK (s))
21389 return TRUE;
21390
21391 /* Non-global symbols cannot be pre-empted. */
21392 if (! S_IS_EXTERNAL (s))
21393 return FALSE;
21394
21395#ifdef OBJ_ELF
21396 /* In ELF, a global symbol can be marked protected, or private. In that
21397 case it can't be pre-empted (other definitions in the same link unit
21398 would violate the ODR). */
21399 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
21400 return FALSE;
21401#endif
21402
21403 /* Other global symbols might be pre-empted. */
21404 return TRUE;
21405}
21406
21407/* Return the size of a relaxable branch instruction. BITS is the
21408 size of the offset field in the narrow instruction. */
21409
21410static int
21411relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
21412{
21413 addressT addr;
21414 offsetT val;
21415 offsetT limit;
21416
21417 /* Assume worst case for symbols not known to be in the same section. */
21418 if (!S_IS_DEFINED (fragp->fr_symbol)
21419 || sec != S_GET_SEGMENT (fragp->fr_symbol)
21420 || S_IS_WEAK (fragp->fr_symbol))
21421 return 4;
21422
21423#ifdef OBJ_ELF
21424 /* A branch to a function in ARM state will require interworking. */
21425 if (S_IS_DEFINED (fragp->fr_symbol)
21426 && ARM_IS_FUNC (fragp->fr_symbol))
21427 return 4;
21428#endif
21429
21430 if (symbol_preemptible (fragp->fr_symbol))
21431 return 4;
21432
21433 val = relaxed_symbol_addr (fragp, stretch);
21434 addr = fragp->fr_address + fragp->fr_fix + 4;
21435 val -= addr;
21436
21437 /* Offset is a signed value *2 */
21438 limit = 1 << bits;
21439 if (val >= limit || val < -limit)
21440 return 4;
21441 return 2;
21442}
21443
21444
21445/* Relax a machine dependent frag. This returns the amount by which
21446 the current size of the frag should change. */
21447
21448int
21449arm_relax_frag (asection *sec, fragS *fragp, long stretch)
21450{
21451 int oldsize;
21452 int newsize;
21453
21454 oldsize = fragp->fr_var;
21455 switch (fragp->fr_subtype)
21456 {
21457 case T_MNEM_ldr_pc2:
21458 newsize = relax_adr (fragp, sec, stretch);
21459 break;
21460 case T_MNEM_ldr_pc:
21461 case T_MNEM_ldr_sp:
21462 case T_MNEM_str_sp:
21463 newsize = relax_immediate (fragp, 8, 2);
21464 break;
21465 case T_MNEM_ldr:
21466 case T_MNEM_str:
21467 newsize = relax_immediate (fragp, 5, 2);
21468 break;
21469 case T_MNEM_ldrh:
21470 case T_MNEM_strh:
21471 newsize = relax_immediate (fragp, 5, 1);
21472 break;
21473 case T_MNEM_ldrb:
21474 case T_MNEM_strb:
21475 newsize = relax_immediate (fragp, 5, 0);
21476 break;
21477 case T_MNEM_adr:
21478 newsize = relax_adr (fragp, sec, stretch);
21479 break;
21480 case T_MNEM_mov:
21481 case T_MNEM_movs:
21482 case T_MNEM_cmp:
21483 case T_MNEM_cmn:
21484 newsize = relax_immediate (fragp, 8, 0);
21485 break;
21486 case T_MNEM_b:
21487 newsize = relax_branch (fragp, sec, 11, stretch);
21488 break;
21489 case T_MNEM_bcond:
21490 newsize = relax_branch (fragp, sec, 8, stretch);
21491 break;
21492 case T_MNEM_add_sp:
21493 case T_MNEM_add_pc:
21494 newsize = relax_immediate (fragp, 8, 2);
21495 break;
21496 case T_MNEM_inc_sp:
21497 case T_MNEM_dec_sp:
21498 newsize = relax_immediate (fragp, 7, 2);
21499 break;
21500 case T_MNEM_addi:
21501 case T_MNEM_addis:
21502 case T_MNEM_subi:
21503 case T_MNEM_subis:
21504 newsize = relax_addsub (fragp, sec);
21505 break;
21506 default:
21507 abort ();
21508 }
21509
21510 fragp->fr_var = newsize;
21511 /* Freeze wide instructions that are at or before the same location as
21512 in the previous pass. This avoids infinite loops.
21513 Don't freeze them unconditionally because targets may be artificially
21514 misaligned by the expansion of preceding frags. */
21515 if (stretch <= 0 && newsize > 2)
21516 {
21517 md_convert_frag (sec->owner, sec, fragp);
21518 frag_wane (fragp);
21519 }
21520
21521 return newsize - oldsize;
21522}
21523
21524/* Round up a section size to the appropriate boundary. */
21525
21526valueT
21527md_section_align (segT segment ATTRIBUTE_UNUSED,
21528 valueT size)
21529{
21530#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21531 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
21532 {
21533 /* For a.out, force the section size to be aligned. If we don't do
21534 this, BFD will align it for us, but it will not write out the
21535 final bytes of the section. This may be a bug in BFD, but it is
21536 easier to fix it here since that is how the other a.out targets
21537 work. */
21538 int align;
21539
21540 align = bfd_get_section_alignment (stdoutput, segment);
21541 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
21542 }
21543#endif
21544
21545 return size;
21546}
21547
21548/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21549 of an rs_align_code fragment. */
21550
21551void
21552arm_handle_align (fragS * fragP)
21553{
21554 static unsigned char const arm_noop[2][2][4] =
21555 {
21556 { /* ARMv1 */
21557 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21558 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21559 },
21560 { /* ARMv6k */
21561 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21562 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21563 },
21564 };
21565 static unsigned char const thumb_noop[2][2][2] =
21566 {
21567 { /* Thumb-1 */
21568 {0xc0, 0x46}, /* LE */
21569 {0x46, 0xc0}, /* BE */
21570 },
21571 { /* Thumb-2 */
21572 {0x00, 0xbf}, /* LE */
21573 {0xbf, 0x00} /* BE */
21574 }
21575 };
21576 static unsigned char const wide_thumb_noop[2][4] =
21577 { /* Wide Thumb-2 */
21578 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21579 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21580 };
21581
21582 unsigned bytes, fix, noop_size;
21583 char * p;
21584 const unsigned char * noop;
21585 const unsigned char *narrow_noop = NULL;
21586#ifdef OBJ_ELF
21587 enum mstate state;
21588#endif
21589
21590 if (fragP->fr_type != rs_align_code)
21591 return;
21592
21593 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
21594 p = fragP->fr_literal + fragP->fr_fix;
21595 fix = 0;
21596
21597 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
21598 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
21599
21600 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
21601
21602 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
21603 {
21604 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
21605 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
21606 {
21607 narrow_noop = thumb_noop[1][target_big_endian];
21608 noop = wide_thumb_noop[target_big_endian];
21609 }
21610 else
21611 noop = thumb_noop[0][target_big_endian];
21612 noop_size = 2;
21613#ifdef OBJ_ELF
21614 state = MAP_THUMB;
21615#endif
21616 }
21617 else
21618 {
21619 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
21620 ? selected_cpu : arm_arch_none,
21621 arm_ext_v6k) != 0]
21622 [target_big_endian];
21623 noop_size = 4;
21624#ifdef OBJ_ELF
21625 state = MAP_ARM;
21626#endif
21627 }
21628
21629 fragP->fr_var = noop_size;
21630
21631 if (bytes & (noop_size - 1))
21632 {
21633 fix = bytes & (noop_size - 1);
21634#ifdef OBJ_ELF
21635 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
21636#endif
21637 memset (p, 0, fix);
21638 p += fix;
21639 bytes -= fix;
21640 }
21641
21642 if (narrow_noop)
21643 {
21644 if (bytes & noop_size)
21645 {
21646 /* Insert a narrow noop. */
21647 memcpy (p, narrow_noop, noop_size);
21648 p += noop_size;
21649 bytes -= noop_size;
21650 fix += noop_size;
21651 }
21652
21653 /* Use wide noops for the remainder */
21654 noop_size = 4;
21655 }
21656
21657 while (bytes >= noop_size)
21658 {
21659 memcpy (p, noop, noop_size);
21660 p += noop_size;
21661 bytes -= noop_size;
21662 fix += noop_size;
21663 }
21664
21665 fragP->fr_fix += fix;
21666}
21667
21668/* Called from md_do_align. Used to create an alignment
21669 frag in a code section. */
21670
21671void
21672arm_frag_align_code (int n, int max)
21673{
21674 char * p;
21675
21676 /* We assume that there will never be a requirement
21677 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21678 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
21679 {
21680 char err_msg[128];
21681
21682 sprintf (err_msg,
21683 _("alignments greater than %d bytes not supported in .text sections."),
21684 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
21685 as_fatal ("%s", err_msg);
21686 }
21687
21688 p = frag_var (rs_align_code,
21689 MAX_MEM_FOR_RS_ALIGN_CODE,
21690 1,
21691 (relax_substateT) max,
21692 (symbolS *) NULL,
21693 (offsetT) n,
21694 (char *) NULL);
21695 *p = 0;
21696}
21697
21698/* Perform target specific initialisation of a frag.
21699 Note - despite the name this initialisation is not done when the frag
21700 is created, but only when its type is assigned. A frag can be created
21701 and used a long time before its type is set, so beware of assuming that
21702 this initialisationis performed first. */
21703
21704#ifndef OBJ_ELF
21705void
21706arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
21707{
21708 /* Record whether this frag is in an ARM or a THUMB area. */
21709 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
21710}
21711
21712#else /* OBJ_ELF is defined. */
21713void
21714arm_init_frag (fragS * fragP, int max_chars)
21715{
21716 int frag_thumb_mode;
21717
21718 /* If the current ARM vs THUMB mode has not already
21719 been recorded into this frag then do so now. */
21720 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
21721 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
21722
21723 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
21724
21725 /* Record a mapping symbol for alignment frags. We will delete this
21726 later if the alignment ends up empty. */
21727 switch (fragP->fr_type)
21728 {
21729 case rs_align:
21730 case rs_align_test:
21731 case rs_fill:
21732 mapping_state_2 (MAP_DATA, max_chars);
21733 break;
21734 case rs_align_code:
21735 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
21736 break;
21737 default:
21738 break;
21739 }
21740}
21741
21742/* When we change sections we need to issue a new mapping symbol. */
21743
21744void
21745arm_elf_change_section (void)
21746{
21747 /* Link an unlinked unwind index table section to the .text section. */
21748 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
21749 && elf_linked_to_section (now_seg) == NULL)
21750 elf_linked_to_section (now_seg) = text_section;
21751}
21752
21753int
21754arm_elf_section_type (const char * str, size_t len)
21755{
21756 if (len == 5 && strncmp (str, "exidx", 5) == 0)
21757 return SHT_ARM_EXIDX;
21758
21759 return -1;
21760}
21761\f
21762/* Code to deal with unwinding tables. */
21763
21764static void add_unwind_adjustsp (offsetT);
21765
21766/* Generate any deferred unwind frame offset. */
21767
21768static void
21769flush_pending_unwind (void)
21770{
21771 offsetT offset;
21772
21773 offset = unwind.pending_offset;
21774 unwind.pending_offset = 0;
21775 if (offset != 0)
21776 add_unwind_adjustsp (offset);
21777}
21778
21779/* Add an opcode to this list for this function. Two-byte opcodes should
21780 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21781 order. */
21782
21783static void
21784add_unwind_opcode (valueT op, int length)
21785{
21786 /* Add any deferred stack adjustment. */
21787 if (unwind.pending_offset)
21788 flush_pending_unwind ();
21789
21790 unwind.sp_restored = 0;
21791
21792 if (unwind.opcode_count + length > unwind.opcode_alloc)
21793 {
21794 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
21795 if (unwind.opcodes)
21796 unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
21797 unwind.opcode_alloc);
21798 else
21799 unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
21800 }
21801 while (length > 0)
21802 {
21803 length--;
21804 unwind.opcodes[unwind.opcode_count] = op & 0xff;
21805 op >>= 8;
21806 unwind.opcode_count++;
21807 }
21808}
21809
21810/* Add unwind opcodes to adjust the stack pointer. */
21811
21812static void
21813add_unwind_adjustsp (offsetT offset)
21814{
21815 valueT op;
21816
21817 if (offset > 0x200)
21818 {
21819 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21820 char bytes[5];
21821 int n;
21822 valueT o;
21823
21824 /* Long form: 0xb2, uleb128. */
21825 /* This might not fit in a word so add the individual bytes,
21826 remembering the list is built in reverse order. */
21827 o = (valueT) ((offset - 0x204) >> 2);
21828 if (o == 0)
21829 add_unwind_opcode (0, 1);
21830
21831 /* Calculate the uleb128 encoding of the offset. */
21832 n = 0;
21833 while (o)
21834 {
21835 bytes[n] = o & 0x7f;
21836 o >>= 7;
21837 if (o)
21838 bytes[n] |= 0x80;
21839 n++;
21840 }
21841 /* Add the insn. */
21842 for (; n; n--)
21843 add_unwind_opcode (bytes[n - 1], 1);
21844 add_unwind_opcode (0xb2, 1);
21845 }
21846 else if (offset > 0x100)
21847 {
21848 /* Two short opcodes. */
21849 add_unwind_opcode (0x3f, 1);
21850 op = (offset - 0x104) >> 2;
21851 add_unwind_opcode (op, 1);
21852 }
21853 else if (offset > 0)
21854 {
21855 /* Short opcode. */
21856 op = (offset - 4) >> 2;
21857 add_unwind_opcode (op, 1);
21858 }
21859 else if (offset < 0)
21860 {
21861 offset = -offset;
21862 while (offset > 0x100)
21863 {
21864 add_unwind_opcode (0x7f, 1);
21865 offset -= 0x100;
21866 }
21867 op = ((offset - 4) >> 2) | 0x40;
21868 add_unwind_opcode (op, 1);
21869 }
21870}
21871
21872/* Finish the list of unwind opcodes for this function. */
21873static void
21874finish_unwind_opcodes (void)
21875{
21876 valueT op;
21877
21878 if (unwind.fp_used)
21879 {
21880 /* Adjust sp as necessary. */
21881 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
21882 flush_pending_unwind ();
21883
21884 /* After restoring sp from the frame pointer. */
21885 op = 0x90 | unwind.fp_reg;
21886 add_unwind_opcode (op, 1);
21887 }
21888 else
21889 flush_pending_unwind ();
21890}
21891
21892
21893/* Start an exception table entry. If idx is nonzero this is an index table
21894 entry. */
21895
21896static void
21897start_unwind_section (const segT text_seg, int idx)
21898{
21899 const char * text_name;
21900 const char * prefix;
21901 const char * prefix_once;
21902 const char * group_name;
21903 size_t prefix_len;
21904 size_t text_len;
21905 char * sec_name;
21906 size_t sec_name_len;
21907 int type;
21908 int flags;
21909 int linkonce;
21910
21911 if (idx)
21912 {
21913 prefix = ELF_STRING_ARM_unwind;
21914 prefix_once = ELF_STRING_ARM_unwind_once;
21915 type = SHT_ARM_EXIDX;
21916 }
21917 else
21918 {
21919 prefix = ELF_STRING_ARM_unwind_info;
21920 prefix_once = ELF_STRING_ARM_unwind_info_once;
21921 type = SHT_PROGBITS;
21922 }
21923
21924 text_name = segment_name (text_seg);
21925 if (streq (text_name, ".text"))
21926 text_name = "";
21927
21928 if (strncmp (text_name, ".gnu.linkonce.t.",
21929 strlen (".gnu.linkonce.t.")) == 0)
21930 {
21931 prefix = prefix_once;
21932 text_name += strlen (".gnu.linkonce.t.");
21933 }
21934
21935 prefix_len = strlen (prefix);
21936 text_len = strlen (text_name);
21937 sec_name_len = prefix_len + text_len;
21938 sec_name = (char *) xmalloc (sec_name_len + 1);
21939 memcpy (sec_name, prefix, prefix_len);
21940 memcpy (sec_name + prefix_len, text_name, text_len);
21941 sec_name[prefix_len + text_len] = '\0';
21942
21943 flags = SHF_ALLOC;
21944 linkonce = 0;
21945 group_name = 0;
21946
21947 /* Handle COMDAT group. */
21948 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
21949 {
21950 group_name = elf_group_name (text_seg);
21951 if (group_name == NULL)
21952 {
21953 as_bad (_("Group section `%s' has no group signature"),
21954 segment_name (text_seg));
21955 ignore_rest_of_line ();
21956 return;
21957 }
21958 flags |= SHF_GROUP;
21959 linkonce = 1;
21960 }
21961
21962 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
21963
21964 /* Set the section link for index tables. */
21965 if (idx)
21966 elf_linked_to_section (now_seg) = text_seg;
21967}
21968
21969
21970/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21971 personality routine data. Returns zero, or the index table value for
21972 an inline entry. */
21973
21974static valueT
21975create_unwind_entry (int have_data)
21976{
21977 int size;
21978 addressT where;
21979 char *ptr;
21980 /* The current word of data. */
21981 valueT data;
21982 /* The number of bytes left in this word. */
21983 int n;
21984
21985 finish_unwind_opcodes ();
21986
21987 /* Remember the current text section. */
21988 unwind.saved_seg = now_seg;
21989 unwind.saved_subseg = now_subseg;
21990
21991 start_unwind_section (now_seg, 0);
21992
21993 if (unwind.personality_routine == NULL)
21994 {
21995 if (unwind.personality_index == -2)
21996 {
21997 if (have_data)
21998 as_bad (_("handlerdata in cantunwind frame"));
21999 return 1; /* EXIDX_CANTUNWIND. */
22000 }
22001
22002 /* Use a default personality routine if none is specified. */
22003 if (unwind.personality_index == -1)
22004 {
22005 if (unwind.opcode_count > 3)
22006 unwind.personality_index = 1;
22007 else
22008 unwind.personality_index = 0;
22009 }
22010
22011 /* Space for the personality routine entry. */
22012 if (unwind.personality_index == 0)
22013 {
22014 if (unwind.opcode_count > 3)
22015 as_bad (_("too many unwind opcodes for personality routine 0"));
22016
22017 if (!have_data)
22018 {
22019 /* All the data is inline in the index table. */
22020 data = 0x80;
22021 n = 3;
22022 while (unwind.opcode_count > 0)
22023 {
22024 unwind.opcode_count--;
22025 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
22026 n--;
22027 }
22028
22029 /* Pad with "finish" opcodes. */
22030 while (n--)
22031 data = (data << 8) | 0xb0;
22032
22033 return data;
22034 }
22035 size = 0;
22036 }
22037 else
22038 /* We get two opcodes "free" in the first word. */
22039 size = unwind.opcode_count - 2;
22040 }
22041 else
22042 {
22043 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22044 if (unwind.personality_index != -1)
22045 {
22046 as_bad (_("attempt to recreate an unwind entry"));
22047 return 1;
22048 }
22049
22050 /* An extra byte is required for the opcode count. */
22051 size = unwind.opcode_count + 1;
22052 }
22053
22054 size = (size + 3) >> 2;
22055 if (size > 0xff)
22056 as_bad (_("too many unwind opcodes"));
22057
22058 frag_align (2, 0, 0);
22059 record_alignment (now_seg, 2);
22060 unwind.table_entry = expr_build_dot ();
22061
22062 /* Allocate the table entry. */
22063 ptr = frag_more ((size << 2) + 4);
22064 /* PR 13449: Zero the table entries in case some of them are not used. */
22065 memset (ptr, 0, (size << 2) + 4);
22066 where = frag_now_fix () - ((size << 2) + 4);
22067
22068 switch (unwind.personality_index)
22069 {
22070 case -1:
22071 /* ??? Should this be a PLT generating relocation? */
22072 /* Custom personality routine. */
22073 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
22074 BFD_RELOC_ARM_PREL31);
22075
22076 where += 4;
22077 ptr += 4;
22078
22079 /* Set the first byte to the number of additional words. */
22080 data = size > 0 ? size - 1 : 0;
22081 n = 3;
22082 break;
22083
22084 /* ABI defined personality routines. */
22085 case 0:
22086 /* Three opcodes bytes are packed into the first word. */
22087 data = 0x80;
22088 n = 3;
22089 break;
22090
22091 case 1:
22092 case 2:
22093 /* The size and first two opcode bytes go in the first word. */
22094 data = ((0x80 + unwind.personality_index) << 8) | size;
22095 n = 2;
22096 break;
22097
22098 default:
22099 /* Should never happen. */
22100 abort ();
22101 }
22102
22103 /* Pack the opcodes into words (MSB first), reversing the list at the same
22104 time. */
22105 while (unwind.opcode_count > 0)
22106 {
22107 if (n == 0)
22108 {
22109 md_number_to_chars (ptr, data, 4);
22110 ptr += 4;
22111 n = 4;
22112 data = 0;
22113 }
22114 unwind.opcode_count--;
22115 n--;
22116 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
22117 }
22118
22119 /* Finish off the last word. */
22120 if (n < 4)
22121 {
22122 /* Pad with "finish" opcodes. */
22123 while (n--)
22124 data = (data << 8) | 0xb0;
22125
22126 md_number_to_chars (ptr, data, 4);
22127 }
22128
22129 if (!have_data)
22130 {
22131 /* Add an empty descriptor if there is no user-specified data. */
22132 ptr = frag_more (4);
22133 md_number_to_chars (ptr, 0, 4);
22134 }
22135
22136 return 0;
22137}
22138
22139
22140/* Initialize the DWARF-2 unwind information for this procedure. */
22141
22142void
22143tc_arm_frame_initial_instructions (void)
22144{
22145 cfi_add_CFA_def_cfa (REG_SP, 0);
22146}
22147#endif /* OBJ_ELF */
22148
22149/* Convert REGNAME to a DWARF-2 register number. */
22150
22151int
22152tc_arm_regname_to_dw2regnum (char *regname)
22153{
22154 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
22155 if (reg != FAIL)
22156 return reg;
22157
22158 /* PR 16694: Allow VFP registers as well. */
22159 reg = arm_reg_parse (&regname, REG_TYPE_VFS);
22160 if (reg != FAIL)
22161 return 64 + reg;
22162
22163 reg = arm_reg_parse (&regname, REG_TYPE_VFD);
22164 if (reg != FAIL)
22165 return reg + 256;
22166
22167 return -1;
22168}
22169
22170#ifdef TE_PE
22171void
22172tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
22173{
22174 expressionS exp;
22175
22176 exp.X_op = O_secrel;
22177 exp.X_add_symbol = symbol;
22178 exp.X_add_number = 0;
22179 emit_expr (&exp, size);
22180}
22181#endif
22182
22183/* MD interface: Symbol and relocation handling. */
22184
22185/* Return the address within the segment that a PC-relative fixup is
22186 relative to. For ARM, PC-relative fixups applied to instructions
22187 are generally relative to the location of the fixup plus 8 bytes.
22188 Thumb branches are offset by 4, and Thumb loads relative to PC
22189 require special handling. */
22190
22191long
22192md_pcrel_from_section (fixS * fixP, segT seg)
22193{
22194 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
22195
22196 /* If this is pc-relative and we are going to emit a relocation
22197 then we just want to put out any pipeline compensation that the linker
22198 will need. Otherwise we want to use the calculated base.
22199 For WinCE we skip the bias for externals as well, since this
22200 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22201 if (fixP->fx_pcrel
22202 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
22203 || (arm_force_relocation (fixP)
22204#ifdef TE_WINCE
22205 && !S_IS_EXTERNAL (fixP->fx_addsy)
22206#endif
22207 )))
22208 base = 0;
22209
22210
22211 switch (fixP->fx_r_type)
22212 {
22213 /* PC relative addressing on the Thumb is slightly odd as the
22214 bottom two bits of the PC are forced to zero for the
22215 calculation. This happens *after* application of the
22216 pipeline offset. However, Thumb adrl already adjusts for
22217 this, so we need not do it again. */
22218 case BFD_RELOC_ARM_THUMB_ADD:
22219 return base & ~3;
22220
22221 case BFD_RELOC_ARM_THUMB_OFFSET:
22222 case BFD_RELOC_ARM_T32_OFFSET_IMM:
22223 case BFD_RELOC_ARM_T32_ADD_PC12:
22224 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22225 return (base + 4) & ~3;
22226
22227 /* Thumb branches are simply offset by +4. */
22228 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22229 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22230 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22231 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22232 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22233 return base + 4;
22234
22235 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22236 if (fixP->fx_addsy
22237 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22238 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22239 && ARM_IS_FUNC (fixP->fx_addsy)
22240 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22241 base = fixP->fx_where + fixP->fx_frag->fr_address;
22242 return base + 4;
22243
22244 /* BLX is like branches above, but forces the low two bits of PC to
22245 zero. */
22246 case BFD_RELOC_THUMB_PCREL_BLX:
22247 if (fixP->fx_addsy
22248 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22249 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22250 && THUMB_IS_FUNC (fixP->fx_addsy)
22251 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22252 base = fixP->fx_where + fixP->fx_frag->fr_address;
22253 return (base + 4) & ~3;
22254
22255 /* ARM mode branches are offset by +8. However, the Windows CE
22256 loader expects the relocation not to take this into account. */
22257 case BFD_RELOC_ARM_PCREL_BLX:
22258 if (fixP->fx_addsy
22259 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22260 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22261 && ARM_IS_FUNC (fixP->fx_addsy)
22262 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22263 base = fixP->fx_where + fixP->fx_frag->fr_address;
22264 return base + 8;
22265
22266 case BFD_RELOC_ARM_PCREL_CALL:
22267 if (fixP->fx_addsy
22268 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22269 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22270 && THUMB_IS_FUNC (fixP->fx_addsy)
22271 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22272 base = fixP->fx_where + fixP->fx_frag->fr_address;
22273 return base + 8;
22274
22275 case BFD_RELOC_ARM_PCREL_BRANCH:
22276 case BFD_RELOC_ARM_PCREL_JUMP:
22277 case BFD_RELOC_ARM_PLT32:
22278#ifdef TE_WINCE
22279 /* When handling fixups immediately, because we have already
22280 discovered the value of a symbol, or the address of the frag involved
22281 we must account for the offset by +8, as the OS loader will never see the reloc.
22282 see fixup_segment() in write.c
22283 The S_IS_EXTERNAL test handles the case of global symbols.
22284 Those need the calculated base, not just the pipe compensation the linker will need. */
22285 if (fixP->fx_pcrel
22286 && fixP->fx_addsy != NULL
22287 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22288 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
22289 return base + 8;
22290 return base;
22291#else
22292 return base + 8;
22293#endif
22294
22295
22296 /* ARM mode loads relative to PC are also offset by +8. Unlike
22297 branches, the Windows CE loader *does* expect the relocation
22298 to take this into account. */
22299 case BFD_RELOC_ARM_OFFSET_IMM:
22300 case BFD_RELOC_ARM_OFFSET_IMM8:
22301 case BFD_RELOC_ARM_HWLITERAL:
22302 case BFD_RELOC_ARM_LITERAL:
22303 case BFD_RELOC_ARM_CP_OFF_IMM:
22304 return base + 8;
22305
22306
22307 /* Other PC-relative relocations are un-offset. */
22308 default:
22309 return base;
22310 }
22311}
22312
22313static bfd_boolean flag_warn_syms = TRUE;
22314
22315bfd_boolean
22316arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
22317{
22318 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22319 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22320 does mean that the resulting code might be very confusing to the reader.
22321 Also this warning can be triggered if the user omits an operand before
22322 an immediate address, eg:
22323
22324 LDR =foo
22325
22326 GAS treats this as an assignment of the value of the symbol foo to a
22327 symbol LDR, and so (without this code) it will not issue any kind of
22328 warning or error message.
22329
22330 Note - ARM instructions are case-insensitive but the strings in the hash
22331 table are all stored in lower case, so we must first ensure that name is
22332 lower case too. */
22333 if (flag_warn_syms && arm_ops_hsh)
22334 {
22335 char * nbuf = strdup (name);
22336 char * p;
22337
22338 for (p = nbuf; *p; p++)
22339 *p = TOLOWER (*p);
22340 if (hash_find (arm_ops_hsh, nbuf) != NULL)
22341 {
22342 static struct hash_control * already_warned = NULL;
22343
22344 if (already_warned == NULL)
22345 already_warned = hash_new ();
22346 /* Only warn about the symbol once. To keep the code
22347 simple we let hash_insert do the lookup for us. */
22348 if (hash_insert (already_warned, name, NULL) == NULL)
22349 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
22350 }
22351 else
22352 free (nbuf);
22353 }
22354
22355 return FALSE;
22356}
22357
22358/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22359 Otherwise we have no need to default values of symbols. */
22360
22361symbolS *
22362md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
22363{
22364#ifdef OBJ_ELF
22365 if (name[0] == '_' && name[1] == 'G'
22366 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
22367 {
22368 if (!GOT_symbol)
22369 {
22370 if (symbol_find (name))
22371 as_bad (_("GOT already in the symbol table"));
22372
22373 GOT_symbol = symbol_new (name, undefined_section,
22374 (valueT) 0, & zero_address_frag);
22375 }
22376
22377 return GOT_symbol;
22378 }
22379#endif
22380
22381 return NULL;
22382}
22383
22384/* Subroutine of md_apply_fix. Check to see if an immediate can be
22385 computed as two separate immediate values, added together. We
22386 already know that this value cannot be computed by just one ARM
22387 instruction. */
22388
22389static unsigned int
22390validate_immediate_twopart (unsigned int val,
22391 unsigned int * highpart)
22392{
22393 unsigned int a;
22394 unsigned int i;
22395
22396 for (i = 0; i < 32; i += 2)
22397 if (((a = rotate_left (val, i)) & 0xff) != 0)
22398 {
22399 if (a & 0xff00)
22400 {
22401 if (a & ~ 0xffff)
22402 continue;
22403 * highpart = (a >> 8) | ((i + 24) << 7);
22404 }
22405 else if (a & 0xff0000)
22406 {
22407 if (a & 0xff000000)
22408 continue;
22409 * highpart = (a >> 16) | ((i + 16) << 7);
22410 }
22411 else
22412 {
22413 gas_assert (a & 0xff000000);
22414 * highpart = (a >> 24) | ((i + 8) << 7);
22415 }
22416
22417 return (a & 0xff) | (i << 7);
22418 }
22419
22420 return FAIL;
22421}
22422
22423static int
22424validate_offset_imm (unsigned int val, int hwse)
22425{
22426 if ((hwse && val > 255) || val > 4095)
22427 return FAIL;
22428 return val;
22429}
22430
22431/* Subroutine of md_apply_fix. Do those data_ops which can take a
22432 negative immediate constant by altering the instruction. A bit of
22433 a hack really.
22434 MOV <-> MVN
22435 AND <-> BIC
22436 ADC <-> SBC
22437 by inverting the second operand, and
22438 ADD <-> SUB
22439 CMP <-> CMN
22440 by negating the second operand. */
22441
22442static int
22443negate_data_op (unsigned long * instruction,
22444 unsigned long value)
22445{
22446 int op, new_inst;
22447 unsigned long negated, inverted;
22448
22449 negated = encode_arm_immediate (-value);
22450 inverted = encode_arm_immediate (~value);
22451
22452 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
22453 switch (op)
22454 {
22455 /* First negates. */
22456 case OPCODE_SUB: /* ADD <-> SUB */
22457 new_inst = OPCODE_ADD;
22458 value = negated;
22459 break;
22460
22461 case OPCODE_ADD:
22462 new_inst = OPCODE_SUB;
22463 value = negated;
22464 break;
22465
22466 case OPCODE_CMP: /* CMP <-> CMN */
22467 new_inst = OPCODE_CMN;
22468 value = negated;
22469 break;
22470
22471 case OPCODE_CMN:
22472 new_inst = OPCODE_CMP;
22473 value = negated;
22474 break;
22475
22476 /* Now Inverted ops. */
22477 case OPCODE_MOV: /* MOV <-> MVN */
22478 new_inst = OPCODE_MVN;
22479 value = inverted;
22480 break;
22481
22482 case OPCODE_MVN:
22483 new_inst = OPCODE_MOV;
22484 value = inverted;
22485 break;
22486
22487 case OPCODE_AND: /* AND <-> BIC */
22488 new_inst = OPCODE_BIC;
22489 value = inverted;
22490 break;
22491
22492 case OPCODE_BIC:
22493 new_inst = OPCODE_AND;
22494 value = inverted;
22495 break;
22496
22497 case OPCODE_ADC: /* ADC <-> SBC */
22498 new_inst = OPCODE_SBC;
22499 value = inverted;
22500 break;
22501
22502 case OPCODE_SBC:
22503 new_inst = OPCODE_ADC;
22504 value = inverted;
22505 break;
22506
22507 /* We cannot do anything. */
22508 default:
22509 return FAIL;
22510 }
22511
22512 if (value == (unsigned) FAIL)
22513 return FAIL;
22514
22515 *instruction &= OPCODE_MASK;
22516 *instruction |= new_inst << DATA_OP_SHIFT;
22517 return value;
22518}
22519
22520/* Like negate_data_op, but for Thumb-2. */
22521
22522static unsigned int
22523thumb32_negate_data_op (offsetT *instruction, unsigned int value)
22524{
22525 int op, new_inst;
22526 int rd;
22527 unsigned int negated, inverted;
22528
22529 negated = encode_thumb32_immediate (-value);
22530 inverted = encode_thumb32_immediate (~value);
22531
22532 rd = (*instruction >> 8) & 0xf;
22533 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
22534 switch (op)
22535 {
22536 /* ADD <-> SUB. Includes CMP <-> CMN. */
22537 case T2_OPCODE_SUB:
22538 new_inst = T2_OPCODE_ADD;
22539 value = negated;
22540 break;
22541
22542 case T2_OPCODE_ADD:
22543 new_inst = T2_OPCODE_SUB;
22544 value = negated;
22545 break;
22546
22547 /* ORR <-> ORN. Includes MOV <-> MVN. */
22548 case T2_OPCODE_ORR:
22549 new_inst = T2_OPCODE_ORN;
22550 value = inverted;
22551 break;
22552
22553 case T2_OPCODE_ORN:
22554 new_inst = T2_OPCODE_ORR;
22555 value = inverted;
22556 break;
22557
22558 /* AND <-> BIC. TST has no inverted equivalent. */
22559 case T2_OPCODE_AND:
22560 new_inst = T2_OPCODE_BIC;
22561 if (rd == 15)
22562 value = FAIL;
22563 else
22564 value = inverted;
22565 break;
22566
22567 case T2_OPCODE_BIC:
22568 new_inst = T2_OPCODE_AND;
22569 value = inverted;
22570 break;
22571
22572 /* ADC <-> SBC */
22573 case T2_OPCODE_ADC:
22574 new_inst = T2_OPCODE_SBC;
22575 value = inverted;
22576 break;
22577
22578 case T2_OPCODE_SBC:
22579 new_inst = T2_OPCODE_ADC;
22580 value = inverted;
22581 break;
22582
22583 /* We cannot do anything. */
22584 default:
22585 return FAIL;
22586 }
22587
22588 if (value == (unsigned int)FAIL)
22589 return FAIL;
22590
22591 *instruction &= T2_OPCODE_MASK;
22592 *instruction |= new_inst << T2_DATA_OP_SHIFT;
22593 return value;
22594}
22595
22596/* Read a 32-bit thumb instruction from buf. */
22597static unsigned long
22598get_thumb32_insn (char * buf)
22599{
22600 unsigned long insn;
22601 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
22602 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22603
22604 return insn;
22605}
22606
22607
22608/* We usually want to set the low bit on the address of thumb function
22609 symbols. In particular .word foo - . should have the low bit set.
22610 Generic code tries to fold the difference of two symbols to
22611 a constant. Prevent this and force a relocation when the first symbols
22612 is a thumb function. */
22613
22614bfd_boolean
22615arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
22616{
22617 if (op == O_subtract
22618 && l->X_op == O_symbol
22619 && r->X_op == O_symbol
22620 && THUMB_IS_FUNC (l->X_add_symbol))
22621 {
22622 l->X_op = O_subtract;
22623 l->X_op_symbol = r->X_add_symbol;
22624 l->X_add_number -= r->X_add_number;
22625 return TRUE;
22626 }
22627
22628 /* Process as normal. */
22629 return FALSE;
22630}
22631
22632/* Encode Thumb2 unconditional branches and calls. The encoding
22633 for the 2 are identical for the immediate values. */
22634
22635static void
22636encode_thumb2_b_bl_offset (char * buf, offsetT value)
22637{
22638#define T2I1I2MASK ((1 << 13) | (1 << 11))
22639 offsetT newval;
22640 offsetT newval2;
22641 addressT S, I1, I2, lo, hi;
22642
22643 S = (value >> 24) & 0x01;
22644 I1 = (value >> 23) & 0x01;
22645 I2 = (value >> 22) & 0x01;
22646 hi = (value >> 12) & 0x3ff;
22647 lo = (value >> 1) & 0x7ff;
22648 newval = md_chars_to_number (buf, THUMB_SIZE);
22649 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22650 newval |= (S << 10) | hi;
22651 newval2 &= ~T2I1I2MASK;
22652 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
22653 md_number_to_chars (buf, newval, THUMB_SIZE);
22654 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22655}
22656
22657void
22658md_apply_fix (fixS * fixP,
22659 valueT * valP,
22660 segT seg)
22661{
22662 offsetT value = * valP;
22663 offsetT newval;
22664 unsigned int newimm;
22665 unsigned long temp;
22666 int sign;
22667 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
22668
22669 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
22670
22671 /* Note whether this will delete the relocation. */
22672
22673 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
22674 fixP->fx_done = 1;
22675
22676 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22677 consistency with the behaviour on 32-bit hosts. Remember value
22678 for emit_reloc. */
22679 value &= 0xffffffff;
22680 value ^= 0x80000000;
22681 value -= 0x80000000;
22682
22683 *valP = value;
22684 fixP->fx_addnumber = value;
22685
22686 /* Same treatment for fixP->fx_offset. */
22687 fixP->fx_offset &= 0xffffffff;
22688 fixP->fx_offset ^= 0x80000000;
22689 fixP->fx_offset -= 0x80000000;
22690
22691 switch (fixP->fx_r_type)
22692 {
22693 case BFD_RELOC_NONE:
22694 /* This will need to go in the object file. */
22695 fixP->fx_done = 0;
22696 break;
22697
22698 case BFD_RELOC_ARM_IMMEDIATE:
22699 /* We claim that this fixup has been processed here,
22700 even if in fact we generate an error because we do
22701 not have a reloc for it, so tc_gen_reloc will reject it. */
22702 fixP->fx_done = 1;
22703
22704 if (fixP->fx_addsy)
22705 {
22706 const char *msg = 0;
22707
22708 if (! S_IS_DEFINED (fixP->fx_addsy))
22709 msg = _("undefined symbol %s used as an immediate value");
22710 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
22711 msg = _("symbol %s is in a different section");
22712 else if (S_IS_WEAK (fixP->fx_addsy))
22713 msg = _("symbol %s is weak and may be overridden later");
22714
22715 if (msg)
22716 {
22717 as_bad_where (fixP->fx_file, fixP->fx_line,
22718 msg, S_GET_NAME (fixP->fx_addsy));
22719 break;
22720 }
22721 }
22722
22723 temp = md_chars_to_number (buf, INSN_SIZE);
22724
22725 /* If the offset is negative, we should use encoding A2 for ADR. */
22726 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
22727 newimm = negate_data_op (&temp, value);
22728 else
22729 {
22730 newimm = encode_arm_immediate (value);
22731
22732 /* If the instruction will fail, see if we can fix things up by
22733 changing the opcode. */
22734 if (newimm == (unsigned int) FAIL)
22735 newimm = negate_data_op (&temp, value);
22736 }
22737
22738 if (newimm == (unsigned int) FAIL)
22739 {
22740 as_bad_where (fixP->fx_file, fixP->fx_line,
22741 _("invalid constant (%lx) after fixup"),
22742 (unsigned long) value);
22743 break;
22744 }
22745
22746 newimm |= (temp & 0xfffff000);
22747 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
22748 break;
22749
22750 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22751 {
22752 unsigned int highpart = 0;
22753 unsigned int newinsn = 0xe1a00000; /* nop. */
22754
22755 if (fixP->fx_addsy)
22756 {
22757 const char *msg = 0;
22758
22759 if (! S_IS_DEFINED (fixP->fx_addsy))
22760 msg = _("undefined symbol %s used as an immediate value");
22761 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
22762 msg = _("symbol %s is in a different section");
22763 else if (S_IS_WEAK (fixP->fx_addsy))
22764 msg = _("symbol %s is weak and may be overridden later");
22765
22766 if (msg)
22767 {
22768 as_bad_where (fixP->fx_file, fixP->fx_line,
22769 msg, S_GET_NAME (fixP->fx_addsy));
22770 break;
22771 }
22772 }
22773
22774 newimm = encode_arm_immediate (value);
22775 temp = md_chars_to_number (buf, INSN_SIZE);
22776
22777 /* If the instruction will fail, see if we can fix things up by
22778 changing the opcode. */
22779 if (newimm == (unsigned int) FAIL
22780 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
22781 {
22782 /* No ? OK - try using two ADD instructions to generate
22783 the value. */
22784 newimm = validate_immediate_twopart (value, & highpart);
22785
22786 /* Yes - then make sure that the second instruction is
22787 also an add. */
22788 if (newimm != (unsigned int) FAIL)
22789 newinsn = temp;
22790 /* Still No ? Try using a negated value. */
22791 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
22792 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
22793 /* Otherwise - give up. */
22794 else
22795 {
22796 as_bad_where (fixP->fx_file, fixP->fx_line,
22797 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22798 (long) value);
22799 break;
22800 }
22801
22802 /* Replace the first operand in the 2nd instruction (which
22803 is the PC) with the destination register. We have
22804 already added in the PC in the first instruction and we
22805 do not want to do it again. */
22806 newinsn &= ~ 0xf0000;
22807 newinsn |= ((newinsn & 0x0f000) << 4);
22808 }
22809
22810 newimm |= (temp & 0xfffff000);
22811 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
22812
22813 highpart |= (newinsn & 0xfffff000);
22814 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
22815 }
22816 break;
22817
22818 case BFD_RELOC_ARM_OFFSET_IMM:
22819 if (!fixP->fx_done && seg->use_rela_p)
22820 value = 0;
22821
22822 case BFD_RELOC_ARM_LITERAL:
22823 sign = value > 0;
22824
22825 if (value < 0)
22826 value = - value;
22827
22828 if (validate_offset_imm (value, 0) == FAIL)
22829 {
22830 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
22831 as_bad_where (fixP->fx_file, fixP->fx_line,
22832 _("invalid literal constant: pool needs to be closer"));
22833 else
22834 as_bad_where (fixP->fx_file, fixP->fx_line,
22835 _("bad immediate value for offset (%ld)"),
22836 (long) value);
22837 break;
22838 }
22839
22840 newval = md_chars_to_number (buf, INSN_SIZE);
22841 if (value == 0)
22842 newval &= 0xfffff000;
22843 else
22844 {
22845 newval &= 0xff7ff000;
22846 newval |= value | (sign ? INDEX_UP : 0);
22847 }
22848 md_number_to_chars (buf, newval, INSN_SIZE);
22849 break;
22850
22851 case BFD_RELOC_ARM_OFFSET_IMM8:
22852 case BFD_RELOC_ARM_HWLITERAL:
22853 sign = value > 0;
22854
22855 if (value < 0)
22856 value = - value;
22857
22858 if (validate_offset_imm (value, 1) == FAIL)
22859 {
22860 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
22861 as_bad_where (fixP->fx_file, fixP->fx_line,
22862 _("invalid literal constant: pool needs to be closer"));
22863 else
22864 as_bad_where (fixP->fx_file, fixP->fx_line,
22865 _("bad immediate value for 8-bit offset (%ld)"),
22866 (long) value);
22867 break;
22868 }
22869
22870 newval = md_chars_to_number (buf, INSN_SIZE);
22871 if (value == 0)
22872 newval &= 0xfffff0f0;
22873 else
22874 {
22875 newval &= 0xff7ff0f0;
22876 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
22877 }
22878 md_number_to_chars (buf, newval, INSN_SIZE);
22879 break;
22880
22881 case BFD_RELOC_ARM_T32_OFFSET_U8:
22882 if (value < 0 || value > 1020 || value % 4 != 0)
22883 as_bad_where (fixP->fx_file, fixP->fx_line,
22884 _("bad immediate value for offset (%ld)"), (long) value);
22885 value /= 4;
22886
22887 newval = md_chars_to_number (buf+2, THUMB_SIZE);
22888 newval |= value;
22889 md_number_to_chars (buf+2, newval, THUMB_SIZE);
22890 break;
22891
22892 case BFD_RELOC_ARM_T32_OFFSET_IMM:
22893 /* This is a complicated relocation used for all varieties of Thumb32
22894 load/store instruction with immediate offset:
22895
22896 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22897 *4, optional writeback(W)
22898 (doubleword load/store)
22899
22900 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22901 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22902 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22903 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22904 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22905
22906 Uppercase letters indicate bits that are already encoded at
22907 this point. Lowercase letters are our problem. For the
22908 second block of instructions, the secondary opcode nybble
22909 (bits 8..11) is present, and bit 23 is zero, even if this is
22910 a PC-relative operation. */
22911 newval = md_chars_to_number (buf, THUMB_SIZE);
22912 newval <<= 16;
22913 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
22914
22915 if ((newval & 0xf0000000) == 0xe0000000)
22916 {
22917 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22918 if (value >= 0)
22919 newval |= (1 << 23);
22920 else
22921 value = -value;
22922 if (value % 4 != 0)
22923 {
22924 as_bad_where (fixP->fx_file, fixP->fx_line,
22925 _("offset not a multiple of 4"));
22926 break;
22927 }
22928 value /= 4;
22929 if (value > 0xff)
22930 {
22931 as_bad_where (fixP->fx_file, fixP->fx_line,
22932 _("offset out of range"));
22933 break;
22934 }
22935 newval &= ~0xff;
22936 }
22937 else if ((newval & 0x000f0000) == 0x000f0000)
22938 {
22939 /* PC-relative, 12-bit offset. */
22940 if (value >= 0)
22941 newval |= (1 << 23);
22942 else
22943 value = -value;
22944 if (value > 0xfff)
22945 {
22946 as_bad_where (fixP->fx_file, fixP->fx_line,
22947 _("offset out of range"));
22948 break;
22949 }
22950 newval &= ~0xfff;
22951 }
22952 else if ((newval & 0x00000100) == 0x00000100)
22953 {
22954 /* Writeback: 8-bit, +/- offset. */
22955 if (value >= 0)
22956 newval |= (1 << 9);
22957 else
22958 value = -value;
22959 if (value > 0xff)
22960 {
22961 as_bad_where (fixP->fx_file, fixP->fx_line,
22962 _("offset out of range"));
22963 break;
22964 }
22965 newval &= ~0xff;
22966 }
22967 else if ((newval & 0x00000f00) == 0x00000e00)
22968 {
22969 /* T-instruction: positive 8-bit offset. */
22970 if (value < 0 || value > 0xff)
22971 {
22972 as_bad_where (fixP->fx_file, fixP->fx_line,
22973 _("offset out of range"));
22974 break;
22975 }
22976 newval &= ~0xff;
22977 newval |= value;
22978 }
22979 else
22980 {
22981 /* Positive 12-bit or negative 8-bit offset. */
22982 int limit;
22983 if (value >= 0)
22984 {
22985 newval |= (1 << 23);
22986 limit = 0xfff;
22987 }
22988 else
22989 {
22990 value = -value;
22991 limit = 0xff;
22992 }
22993 if (value > limit)
22994 {
22995 as_bad_where (fixP->fx_file, fixP->fx_line,
22996 _("offset out of range"));
22997 break;
22998 }
22999 newval &= ~limit;
23000 }
23001
23002 newval |= value;
23003 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
23004 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
23005 break;
23006
23007 case BFD_RELOC_ARM_SHIFT_IMM:
23008 newval = md_chars_to_number (buf, INSN_SIZE);
23009 if (((unsigned long) value) > 32
23010 || (value == 32
23011 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
23012 {
23013 as_bad_where (fixP->fx_file, fixP->fx_line,
23014 _("shift expression is too large"));
23015 break;
23016 }
23017
23018 if (value == 0)
23019 /* Shifts of zero must be done as lsl. */
23020 newval &= ~0x60;
23021 else if (value == 32)
23022 value = 0;
23023 newval &= 0xfffff07f;
23024 newval |= (value & 0x1f) << 7;
23025 md_number_to_chars (buf, newval, INSN_SIZE);
23026 break;
23027
23028 case BFD_RELOC_ARM_T32_IMMEDIATE:
23029 case BFD_RELOC_ARM_T32_ADD_IMM:
23030 case BFD_RELOC_ARM_T32_IMM12:
23031 case BFD_RELOC_ARM_T32_ADD_PC12:
23032 /* We claim that this fixup has been processed here,
23033 even if in fact we generate an error because we do
23034 not have a reloc for it, so tc_gen_reloc will reject it. */
23035 fixP->fx_done = 1;
23036
23037 if (fixP->fx_addsy
23038 && ! S_IS_DEFINED (fixP->fx_addsy))
23039 {
23040 as_bad_where (fixP->fx_file, fixP->fx_line,
23041 _("undefined symbol %s used as an immediate value"),
23042 S_GET_NAME (fixP->fx_addsy));
23043 break;
23044 }
23045
23046 newval = md_chars_to_number (buf, THUMB_SIZE);
23047 newval <<= 16;
23048 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
23049
23050 newimm = FAIL;
23051 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23052 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
23053 {
23054 newimm = encode_thumb32_immediate (value);
23055 if (newimm == (unsigned int) FAIL)
23056 newimm = thumb32_negate_data_op (&newval, value);
23057 }
23058 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
23059 && newimm == (unsigned int) FAIL)
23060 {
23061 /* Turn add/sum into addw/subw. */
23062 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
23063 newval = (newval & 0xfeffffff) | 0x02000000;
23064 /* No flat 12-bit imm encoding for addsw/subsw. */
23065 if ((newval & 0x00100000) == 0)
23066 {
23067 /* 12 bit immediate for addw/subw. */
23068 if (value < 0)
23069 {
23070 value = -value;
23071 newval ^= 0x00a00000;
23072 }
23073 if (value > 0xfff)
23074 newimm = (unsigned int) FAIL;
23075 else
23076 newimm = value;
23077 }
23078 }
23079
23080 if (newimm == (unsigned int)FAIL)
23081 {
23082 as_bad_where (fixP->fx_file, fixP->fx_line,
23083 _("invalid constant (%lx) after fixup"),
23084 (unsigned long) value);
23085 break;
23086 }
23087
23088 newval |= (newimm & 0x800) << 15;
23089 newval |= (newimm & 0x700) << 4;
23090 newval |= (newimm & 0x0ff);
23091
23092 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
23093 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
23094 break;
23095
23096 case BFD_RELOC_ARM_SMC:
23097 if (((unsigned long) value) > 0xffff)
23098 as_bad_where (fixP->fx_file, fixP->fx_line,
23099 _("invalid smc expression"));
23100 newval = md_chars_to_number (buf, INSN_SIZE);
23101 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
23102 md_number_to_chars (buf, newval, INSN_SIZE);
23103 break;
23104
23105 case BFD_RELOC_ARM_HVC:
23106 if (((unsigned long) value) > 0xffff)
23107 as_bad_where (fixP->fx_file, fixP->fx_line,
23108 _("invalid hvc expression"));
23109 newval = md_chars_to_number (buf, INSN_SIZE);
23110 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
23111 md_number_to_chars (buf, newval, INSN_SIZE);
23112 break;
23113
23114 case BFD_RELOC_ARM_SWI:
23115 if (fixP->tc_fix_data != 0)
23116 {
23117 if (((unsigned long) value) > 0xff)
23118 as_bad_where (fixP->fx_file, fixP->fx_line,
23119 _("invalid swi expression"));
23120 newval = md_chars_to_number (buf, THUMB_SIZE);
23121 newval |= value;
23122 md_number_to_chars (buf, newval, THUMB_SIZE);
23123 }
23124 else
23125 {
23126 if (((unsigned long) value) > 0x00ffffff)
23127 as_bad_where (fixP->fx_file, fixP->fx_line,
23128 _("invalid swi expression"));
23129 newval = md_chars_to_number (buf, INSN_SIZE);
23130 newval |= value;
23131 md_number_to_chars (buf, newval, INSN_SIZE);
23132 }
23133 break;
23134
23135 case BFD_RELOC_ARM_MULTI:
23136 if (((unsigned long) value) > 0xffff)
23137 as_bad_where (fixP->fx_file, fixP->fx_line,
23138 _("invalid expression in load/store multiple"));
23139 newval = value | md_chars_to_number (buf, INSN_SIZE);
23140 md_number_to_chars (buf, newval, INSN_SIZE);
23141 break;
23142
23143#ifdef OBJ_ELF
23144 case BFD_RELOC_ARM_PCREL_CALL:
23145
23146 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23147 && fixP->fx_addsy
23148 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23149 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23150 && THUMB_IS_FUNC (fixP->fx_addsy))
23151 /* Flip the bl to blx. This is a simple flip
23152 bit here because we generate PCREL_CALL for
23153 unconditional bls. */
23154 {
23155 newval = md_chars_to_number (buf, INSN_SIZE);
23156 newval = newval | 0x10000000;
23157 md_number_to_chars (buf, newval, INSN_SIZE);
23158 temp = 1;
23159 fixP->fx_done = 1;
23160 }
23161 else
23162 temp = 3;
23163 goto arm_branch_common;
23164
23165 case BFD_RELOC_ARM_PCREL_JUMP:
23166 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23167 && fixP->fx_addsy
23168 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23169 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23170 && THUMB_IS_FUNC (fixP->fx_addsy))
23171 {
23172 /* This would map to a bl<cond>, b<cond>,
23173 b<always> to a Thumb function. We
23174 need to force a relocation for this particular
23175 case. */
23176 newval = md_chars_to_number (buf, INSN_SIZE);
23177 fixP->fx_done = 0;
23178 }
23179
23180 case BFD_RELOC_ARM_PLT32:
23181#endif
23182 case BFD_RELOC_ARM_PCREL_BRANCH:
23183 temp = 3;
23184 goto arm_branch_common;
23185
23186 case BFD_RELOC_ARM_PCREL_BLX:
23187
23188 temp = 1;
23189 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23190 && fixP->fx_addsy
23191 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23192 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23193 && ARM_IS_FUNC (fixP->fx_addsy))
23194 {
23195 /* Flip the blx to a bl and warn. */
23196 const char *name = S_GET_NAME (fixP->fx_addsy);
23197 newval = 0xeb000000;
23198 as_warn_where (fixP->fx_file, fixP->fx_line,
23199 _("blx to '%s' an ARM ISA state function changed to bl"),
23200 name);
23201 md_number_to_chars (buf, newval, INSN_SIZE);
23202 temp = 3;
23203 fixP->fx_done = 1;
23204 }
23205
23206#ifdef OBJ_ELF
23207 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
23208 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
23209#endif
23210
23211 arm_branch_common:
23212 /* We are going to store value (shifted right by two) in the
23213 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23214 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23215 also be be clear. */
23216 if (value & temp)
23217 as_bad_where (fixP->fx_file, fixP->fx_line,
23218 _("misaligned branch destination"));
23219 if ((value & (offsetT)0xfe000000) != (offsetT)0
23220 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
23221 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23222
23223 if (fixP->fx_done || !seg->use_rela_p)
23224 {
23225 newval = md_chars_to_number (buf, INSN_SIZE);
23226 newval |= (value >> 2) & 0x00ffffff;
23227 /* Set the H bit on BLX instructions. */
23228 if (temp == 1)
23229 {
23230 if (value & 2)
23231 newval |= 0x01000000;
23232 else
23233 newval &= ~0x01000000;
23234 }
23235 md_number_to_chars (buf, newval, INSN_SIZE);
23236 }
23237 break;
23238
23239 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
23240 /* CBZ can only branch forward. */
23241
23242 /* Attempts to use CBZ to branch to the next instruction
23243 (which, strictly speaking, are prohibited) will be turned into
23244 no-ops.
23245
23246 FIXME: It may be better to remove the instruction completely and
23247 perform relaxation. */
23248 if (value == -2)
23249 {
23250 newval = md_chars_to_number (buf, THUMB_SIZE);
23251 newval = 0xbf00; /* NOP encoding T1 */
23252 md_number_to_chars (buf, newval, THUMB_SIZE);
23253 }
23254 else
23255 {
23256 if (value & ~0x7e)
23257 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23258
23259 if (fixP->fx_done || !seg->use_rela_p)
23260 {
23261 newval = md_chars_to_number (buf, THUMB_SIZE);
23262 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
23263 md_number_to_chars (buf, newval, THUMB_SIZE);
23264 }
23265 }
23266 break;
23267
23268 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
23269 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
23270 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23271
23272 if (fixP->fx_done || !seg->use_rela_p)
23273 {
23274 newval = md_chars_to_number (buf, THUMB_SIZE);
23275 newval |= (value & 0x1ff) >> 1;
23276 md_number_to_chars (buf, newval, THUMB_SIZE);
23277 }
23278 break;
23279
23280 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
23281 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
23282 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23283
23284 if (fixP->fx_done || !seg->use_rela_p)
23285 {
23286 newval = md_chars_to_number (buf, THUMB_SIZE);
23287 newval |= (value & 0xfff) >> 1;
23288 md_number_to_chars (buf, newval, THUMB_SIZE);
23289 }
23290 break;
23291
23292 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23293 if (fixP->fx_addsy
23294 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23295 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23296 && ARM_IS_FUNC (fixP->fx_addsy)
23297 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
23298 {
23299 /* Force a relocation for a branch 20 bits wide. */
23300 fixP->fx_done = 0;
23301 }
23302 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
23303 as_bad_where (fixP->fx_file, fixP->fx_line,
23304 _("conditional branch out of range"));
23305
23306 if (fixP->fx_done || !seg->use_rela_p)
23307 {
23308 offsetT newval2;
23309 addressT S, J1, J2, lo, hi;
23310
23311 S = (value & 0x00100000) >> 20;
23312 J2 = (value & 0x00080000) >> 19;
23313 J1 = (value & 0x00040000) >> 18;
23314 hi = (value & 0x0003f000) >> 12;
23315 lo = (value & 0x00000ffe) >> 1;
23316
23317 newval = md_chars_to_number (buf, THUMB_SIZE);
23318 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23319 newval |= (S << 10) | hi;
23320 newval2 |= (J1 << 13) | (J2 << 11) | lo;
23321 md_number_to_chars (buf, newval, THUMB_SIZE);
23322 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
23323 }
23324 break;
23325
23326 case BFD_RELOC_THUMB_PCREL_BLX:
23327 /* If there is a blx from a thumb state function to
23328 another thumb function flip this to a bl and warn
23329 about it. */
23330
23331 if (fixP->fx_addsy
23332 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23333 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23334 && THUMB_IS_FUNC (fixP->fx_addsy))
23335 {
23336 const char *name = S_GET_NAME (fixP->fx_addsy);
23337 as_warn_where (fixP->fx_file, fixP->fx_line,
23338 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23339 name);
23340 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23341 newval = newval | 0x1000;
23342 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
23343 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
23344 fixP->fx_done = 1;
23345 }
23346
23347
23348 goto thumb_bl_common;
23349
23350 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23351 /* A bl from Thumb state ISA to an internal ARM state function
23352 is converted to a blx. */
23353 if (fixP->fx_addsy
23354 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23355 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23356 && ARM_IS_FUNC (fixP->fx_addsy)
23357 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
23358 {
23359 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23360 newval = newval & ~0x1000;
23361 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
23362 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
23363 fixP->fx_done = 1;
23364 }
23365
23366 thumb_bl_common:
23367
23368 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
23369 /* For a BLX instruction, make sure that the relocation is rounded up
23370 to a word boundary. This follows the semantics of the instruction
23371 which specifies that bit 1 of the target address will come from bit
23372 1 of the base address. */
23373 value = (value + 3) & ~ 3;
23374
23375#ifdef OBJ_ELF
23376 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
23377 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
23378 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
23379#endif
23380
23381 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
23382 {
23383 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
23384 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23385 else if ((value & ~0x1ffffff)
23386 && ((value & ~0x1ffffff) != ~0x1ffffff))
23387 as_bad_where (fixP->fx_file, fixP->fx_line,
23388 _("Thumb2 branch out of range"));
23389 }
23390
23391 if (fixP->fx_done || !seg->use_rela_p)
23392 encode_thumb2_b_bl_offset (buf, value);
23393
23394 break;
23395
23396 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23397 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
23398 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23399
23400 if (fixP->fx_done || !seg->use_rela_p)
23401 encode_thumb2_b_bl_offset (buf, value);
23402
23403 break;
23404
23405 case BFD_RELOC_8:
23406 if (fixP->fx_done || !seg->use_rela_p)
23407 *buf = value;
23408 break;
23409
23410 case BFD_RELOC_16:
23411 if (fixP->fx_done || !seg->use_rela_p)
23412 md_number_to_chars (buf, value, 2);
23413 break;
23414
23415#ifdef OBJ_ELF
23416 case BFD_RELOC_ARM_TLS_CALL:
23417 case BFD_RELOC_ARM_THM_TLS_CALL:
23418 case BFD_RELOC_ARM_TLS_DESCSEQ:
23419 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
23420 case BFD_RELOC_ARM_TLS_GOTDESC:
23421 case BFD_RELOC_ARM_TLS_GD32:
23422 case BFD_RELOC_ARM_TLS_LE32:
23423 case BFD_RELOC_ARM_TLS_IE32:
23424 case BFD_RELOC_ARM_TLS_LDM32:
23425 case BFD_RELOC_ARM_TLS_LDO32:
23426 S_SET_THREAD_LOCAL (fixP->fx_addsy);
23427 break;
23428
23429 case BFD_RELOC_ARM_GOT32:
23430 case BFD_RELOC_ARM_GOTOFF:
23431 break;
23432
23433 case BFD_RELOC_ARM_GOT_PREL:
23434 if (fixP->fx_done || !seg->use_rela_p)
23435 md_number_to_chars (buf, value, 4);
23436 break;
23437
23438 case BFD_RELOC_ARM_TARGET2:
23439 /* TARGET2 is not partial-inplace, so we need to write the
23440 addend here for REL targets, because it won't be written out
23441 during reloc processing later. */
23442 if (fixP->fx_done || !seg->use_rela_p)
23443 md_number_to_chars (buf, fixP->fx_offset, 4);
23444 break;
23445#endif
23446
23447 case BFD_RELOC_RVA:
23448 case BFD_RELOC_32:
23449 case BFD_RELOC_ARM_TARGET1:
23450 case BFD_RELOC_ARM_ROSEGREL32:
23451 case BFD_RELOC_ARM_SBREL32:
23452 case BFD_RELOC_32_PCREL:
23453#ifdef TE_PE
23454 case BFD_RELOC_32_SECREL:
23455#endif
23456 if (fixP->fx_done || !seg->use_rela_p)
23457#ifdef TE_WINCE
23458 /* For WinCE we only do this for pcrel fixups. */
23459 if (fixP->fx_done || fixP->fx_pcrel)
23460#endif
23461 md_number_to_chars (buf, value, 4);
23462 break;
23463
23464#ifdef OBJ_ELF
23465 case BFD_RELOC_ARM_PREL31:
23466 if (fixP->fx_done || !seg->use_rela_p)
23467 {
23468 newval = md_chars_to_number (buf, 4) & 0x80000000;
23469 if ((value ^ (value >> 1)) & 0x40000000)
23470 {
23471 as_bad_where (fixP->fx_file, fixP->fx_line,
23472 _("rel31 relocation overflow"));
23473 }
23474 newval |= value & 0x7fffffff;
23475 md_number_to_chars (buf, newval, 4);
23476 }
23477 break;
23478#endif
23479
23480 case BFD_RELOC_ARM_CP_OFF_IMM:
23481 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
23482 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
23483 newval = md_chars_to_number (buf, INSN_SIZE);
23484 else
23485 newval = get_thumb32_insn (buf);
23486 if ((newval & 0x0f200f00) == 0x0d000900)
23487 {
23488 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23489 has permitted values that are multiples of 2, in the range 0
23490 to 510. */
23491 if (value < -510 || value > 510 || (value & 1))
23492 as_bad_where (fixP->fx_file, fixP->fx_line,
23493 _("co-processor offset out of range"));
23494 }
23495 else if (value < -1023 || value > 1023 || (value & 3))
23496 as_bad_where (fixP->fx_file, fixP->fx_line,
23497 _("co-processor offset out of range"));
23498 cp_off_common:
23499 sign = value > 0;
23500 if (value < 0)
23501 value = -value;
23502 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23503 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
23504 newval = md_chars_to_number (buf, INSN_SIZE);
23505 else
23506 newval = get_thumb32_insn (buf);
23507 if (value == 0)
23508 newval &= 0xffffff00;
23509 else
23510 {
23511 newval &= 0xff7fff00;
23512 if ((newval & 0x0f200f00) == 0x0d000900)
23513 {
23514 /* This is a fp16 vstr/vldr.
23515
23516 It requires the immediate offset in the instruction is shifted
23517 left by 1 to be a half-word offset.
23518
23519 Here, left shift by 1 first, and later right shift by 2
23520 should get the right offset. */
23521 value <<= 1;
23522 }
23523 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
23524 }
23525 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23526 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
23527 md_number_to_chars (buf, newval, INSN_SIZE);
23528 else
23529 put_thumb32_insn (buf, newval);
23530 break;
23531
23532 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
23533 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
23534 if (value < -255 || value > 255)
23535 as_bad_where (fixP->fx_file, fixP->fx_line,
23536 _("co-processor offset out of range"));
23537 value *= 4;
23538 goto cp_off_common;
23539
23540 case BFD_RELOC_ARM_THUMB_OFFSET:
23541 newval = md_chars_to_number (buf, THUMB_SIZE);
23542 /* Exactly what ranges, and where the offset is inserted depends
23543 on the type of instruction, we can establish this from the
23544 top 4 bits. */
23545 switch (newval >> 12)
23546 {
23547 case 4: /* PC load. */
23548 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23549 forced to zero for these loads; md_pcrel_from has already
23550 compensated for this. */
23551 if (value & 3)
23552 as_bad_where (fixP->fx_file, fixP->fx_line,
23553 _("invalid offset, target not word aligned (0x%08lX)"),
23554 (((unsigned long) fixP->fx_frag->fr_address
23555 + (unsigned long) fixP->fx_where) & ~3)
23556 + (unsigned long) value);
23557
23558 if (value & ~0x3fc)
23559 as_bad_where (fixP->fx_file, fixP->fx_line,
23560 _("invalid offset, value too big (0x%08lX)"),
23561 (long) value);
23562
23563 newval |= value >> 2;
23564 break;
23565
23566 case 9: /* SP load/store. */
23567 if (value & ~0x3fc)
23568 as_bad_where (fixP->fx_file, fixP->fx_line,
23569 _("invalid offset, value too big (0x%08lX)"),
23570 (long) value);
23571 newval |= value >> 2;
23572 break;
23573
23574 case 6: /* Word load/store. */
23575 if (value & ~0x7c)
23576 as_bad_where (fixP->fx_file, fixP->fx_line,
23577 _("invalid offset, value too big (0x%08lX)"),
23578 (long) value);
23579 newval |= value << 4; /* 6 - 2. */
23580 break;
23581
23582 case 7: /* Byte load/store. */
23583 if (value & ~0x1f)
23584 as_bad_where (fixP->fx_file, fixP->fx_line,
23585 _("invalid offset, value too big (0x%08lX)"),
23586 (long) value);
23587 newval |= value << 6;
23588 break;
23589
23590 case 8: /* Halfword load/store. */
23591 if (value & ~0x3e)
23592 as_bad_where (fixP->fx_file, fixP->fx_line,
23593 _("invalid offset, value too big (0x%08lX)"),
23594 (long) value);
23595 newval |= value << 5; /* 6 - 1. */
23596 break;
23597
23598 default:
23599 as_bad_where (fixP->fx_file, fixP->fx_line,
23600 "Unable to process relocation for thumb opcode: %lx",
23601 (unsigned long) newval);
23602 break;
23603 }
23604 md_number_to_chars (buf, newval, THUMB_SIZE);
23605 break;
23606
23607 case BFD_RELOC_ARM_THUMB_ADD:
23608 /* This is a complicated relocation, since we use it for all of
23609 the following immediate relocations:
23610
23611 3bit ADD/SUB
23612 8bit ADD/SUB
23613 9bit ADD/SUB SP word-aligned
23614 10bit ADD PC/SP word-aligned
23615
23616 The type of instruction being processed is encoded in the
23617 instruction field:
23618
23619 0x8000 SUB
23620 0x00F0 Rd
23621 0x000F Rs
23622 */
23623 newval = md_chars_to_number (buf, THUMB_SIZE);
23624 {
23625 int rd = (newval >> 4) & 0xf;
23626 int rs = newval & 0xf;
23627 int subtract = !!(newval & 0x8000);
23628
23629 /* Check for HI regs, only very restricted cases allowed:
23630 Adjusting SP, and using PC or SP to get an address. */
23631 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
23632 || (rs > 7 && rs != REG_SP && rs != REG_PC))
23633 as_bad_where (fixP->fx_file, fixP->fx_line,
23634 _("invalid Hi register with immediate"));
23635
23636 /* If value is negative, choose the opposite instruction. */
23637 if (value < 0)
23638 {
23639 value = -value;
23640 subtract = !subtract;
23641 if (value < 0)
23642 as_bad_where (fixP->fx_file, fixP->fx_line,
23643 _("immediate value out of range"));
23644 }
23645
23646 if (rd == REG_SP)
23647 {
23648 if (value & ~0x1fc)
23649 as_bad_where (fixP->fx_file, fixP->fx_line,
23650 _("invalid immediate for stack address calculation"));
23651 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
23652 newval |= value >> 2;
23653 }
23654 else if (rs == REG_PC || rs == REG_SP)
23655 {
23656 /* PR gas/18541. If the addition is for a defined symbol
23657 within range of an ADR instruction then accept it. */
23658 if (subtract
23659 && value == 4
23660 && fixP->fx_addsy != NULL)
23661 {
23662 subtract = 0;
23663
23664 if (! S_IS_DEFINED (fixP->fx_addsy)
23665 || S_GET_SEGMENT (fixP->fx_addsy) != seg
23666 || S_IS_WEAK (fixP->fx_addsy))
23667 {
23668 as_bad_where (fixP->fx_file, fixP->fx_line,
23669 _("address calculation needs a strongly defined nearby symbol"));
23670 }
23671 else
23672 {
23673 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
23674
23675 /* Round up to the next 4-byte boundary. */
23676 if (v & 3)
23677 v = (v + 3) & ~ 3;
23678 else
23679 v += 4;
23680 v = S_GET_VALUE (fixP->fx_addsy) - v;
23681
23682 if (v & ~0x3fc)
23683 {
23684 as_bad_where (fixP->fx_file, fixP->fx_line,
23685 _("symbol too far away"));
23686 }
23687 else
23688 {
23689 fixP->fx_done = 1;
23690 value = v;
23691 }
23692 }
23693 }
23694
23695 if (subtract || value & ~0x3fc)
23696 as_bad_where (fixP->fx_file, fixP->fx_line,
23697 _("invalid immediate for address calculation (value = 0x%08lX)"),
23698 (unsigned long) (subtract ? - value : value));
23699 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
23700 newval |= rd << 8;
23701 newval |= value >> 2;
23702 }
23703 else if (rs == rd)
23704 {
23705 if (value & ~0xff)
23706 as_bad_where (fixP->fx_file, fixP->fx_line,
23707 _("immediate value out of range"));
23708 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
23709 newval |= (rd << 8) | value;
23710 }
23711 else
23712 {
23713 if (value & ~0x7)
23714 as_bad_where (fixP->fx_file, fixP->fx_line,
23715 _("immediate value out of range"));
23716 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
23717 newval |= rd | (rs << 3) | (value << 6);
23718 }
23719 }
23720 md_number_to_chars (buf, newval, THUMB_SIZE);
23721 break;
23722
23723 case BFD_RELOC_ARM_THUMB_IMM:
23724 newval = md_chars_to_number (buf, THUMB_SIZE);
23725 if (value < 0 || value > 255)
23726 as_bad_where (fixP->fx_file, fixP->fx_line,
23727 _("invalid immediate: %ld is out of range"),
23728 (long) value);
23729 newval |= value;
23730 md_number_to_chars (buf, newval, THUMB_SIZE);
23731 break;
23732
23733 case BFD_RELOC_ARM_THUMB_SHIFT:
23734 /* 5bit shift value (0..32). LSL cannot take 32. */
23735 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
23736 temp = newval & 0xf800;
23737 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
23738 as_bad_where (fixP->fx_file, fixP->fx_line,
23739 _("invalid shift value: %ld"), (long) value);
23740 /* Shifts of zero must be encoded as LSL. */
23741 if (value == 0)
23742 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
23743 /* Shifts of 32 are encoded as zero. */
23744 else if (value == 32)
23745 value = 0;
23746 newval |= value << 6;
23747 md_number_to_chars (buf, newval, THUMB_SIZE);
23748 break;
23749
23750 case BFD_RELOC_VTABLE_INHERIT:
23751 case BFD_RELOC_VTABLE_ENTRY:
23752 fixP->fx_done = 0;
23753 return;
23754
23755 case BFD_RELOC_ARM_MOVW:
23756 case BFD_RELOC_ARM_MOVT:
23757 case BFD_RELOC_ARM_THUMB_MOVW:
23758 case BFD_RELOC_ARM_THUMB_MOVT:
23759 if (fixP->fx_done || !seg->use_rela_p)
23760 {
23761 /* REL format relocations are limited to a 16-bit addend. */
23762 if (!fixP->fx_done)
23763 {
23764 if (value < -0x8000 || value > 0x7fff)
23765 as_bad_where (fixP->fx_file, fixP->fx_line,
23766 _("offset out of range"));
23767 }
23768 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23769 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
23770 {
23771 value >>= 16;
23772 }
23773
23774 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23775 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
23776 {
23777 newval = get_thumb32_insn (buf);
23778 newval &= 0xfbf08f00;
23779 newval |= (value & 0xf000) << 4;
23780 newval |= (value & 0x0800) << 15;
23781 newval |= (value & 0x0700) << 4;
23782 newval |= (value & 0x00ff);
23783 put_thumb32_insn (buf, newval);
23784 }
23785 else
23786 {
23787 newval = md_chars_to_number (buf, 4);
23788 newval &= 0xfff0f000;
23789 newval |= value & 0x0fff;
23790 newval |= (value & 0xf000) << 4;
23791 md_number_to_chars (buf, newval, 4);
23792 }
23793 }
23794 return;
23795
23796 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
23797 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
23798 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
23799 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
23800 gas_assert (!fixP->fx_done);
23801 {
23802 bfd_vma insn;
23803 bfd_boolean is_mov;
23804 bfd_vma encoded_addend = value;
23805
23806 /* Check that addend can be encoded in instruction. */
23807 if (!seg->use_rela_p && (value < 0 || value > 255))
23808 as_bad_where (fixP->fx_file, fixP->fx_line,
23809 _("the offset 0x%08lX is not representable"),
23810 (unsigned long) encoded_addend);
23811
23812 /* Extract the instruction. */
23813 insn = md_chars_to_number (buf, THUMB_SIZE);
23814 is_mov = (insn & 0xf800) == 0x2000;
23815
23816 /* Encode insn. */
23817 if (is_mov)
23818 {
23819 if (!seg->use_rela_p)
23820 insn |= encoded_addend;
23821 }
23822 else
23823 {
23824 int rd, rs;
23825
23826 /* Extract the instruction. */
23827 /* Encoding is the following
23828 0x8000 SUB
23829 0x00F0 Rd
23830 0x000F Rs
23831 */
23832 /* The following conditions must be true :
23833 - ADD
23834 - Rd == Rs
23835 - Rd <= 7
23836 */
23837 rd = (insn >> 4) & 0xf;
23838 rs = insn & 0xf;
23839 if ((insn & 0x8000) || (rd != rs) || rd > 7)
23840 as_bad_where (fixP->fx_file, fixP->fx_line,
23841 _("Unable to process relocation for thumb opcode: %lx"),
23842 (unsigned long) insn);
23843
23844 /* Encode as ADD immediate8 thumb 1 code. */
23845 insn = 0x3000 | (rd << 8);
23846
23847 /* Place the encoded addend into the first 8 bits of the
23848 instruction. */
23849 if (!seg->use_rela_p)
23850 insn |= encoded_addend;
23851 }
23852
23853 /* Update the instruction. */
23854 md_number_to_chars (buf, insn, THUMB_SIZE);
23855 }
23856 break;
23857
23858 case BFD_RELOC_ARM_ALU_PC_G0_NC:
23859 case BFD_RELOC_ARM_ALU_PC_G0:
23860 case BFD_RELOC_ARM_ALU_PC_G1_NC:
23861 case BFD_RELOC_ARM_ALU_PC_G1:
23862 case BFD_RELOC_ARM_ALU_PC_G2:
23863 case BFD_RELOC_ARM_ALU_SB_G0_NC:
23864 case BFD_RELOC_ARM_ALU_SB_G0:
23865 case BFD_RELOC_ARM_ALU_SB_G1_NC:
23866 case BFD_RELOC_ARM_ALU_SB_G1:
23867 case BFD_RELOC_ARM_ALU_SB_G2:
23868 gas_assert (!fixP->fx_done);
23869 if (!seg->use_rela_p)
23870 {
23871 bfd_vma insn;
23872 bfd_vma encoded_addend;
23873 bfd_vma addend_abs = abs (value);
23874
23875 /* Check that the absolute value of the addend can be
23876 expressed as an 8-bit constant plus a rotation. */
23877 encoded_addend = encode_arm_immediate (addend_abs);
23878 if (encoded_addend == (unsigned int) FAIL)
23879 as_bad_where (fixP->fx_file, fixP->fx_line,
23880 _("the offset 0x%08lX is not representable"),
23881 (unsigned long) addend_abs);
23882
23883 /* Extract the instruction. */
23884 insn = md_chars_to_number (buf, INSN_SIZE);
23885
23886 /* If the addend is positive, use an ADD instruction.
23887 Otherwise use a SUB. Take care not to destroy the S bit. */
23888 insn &= 0xff1fffff;
23889 if (value < 0)
23890 insn |= 1 << 22;
23891 else
23892 insn |= 1 << 23;
23893
23894 /* Place the encoded addend into the first 12 bits of the
23895 instruction. */
23896 insn &= 0xfffff000;
23897 insn |= encoded_addend;
23898
23899 /* Update the instruction. */
23900 md_number_to_chars (buf, insn, INSN_SIZE);
23901 }
23902 break;
23903
23904 case BFD_RELOC_ARM_LDR_PC_G0:
23905 case BFD_RELOC_ARM_LDR_PC_G1:
23906 case BFD_RELOC_ARM_LDR_PC_G2:
23907 case BFD_RELOC_ARM_LDR_SB_G0:
23908 case BFD_RELOC_ARM_LDR_SB_G1:
23909 case BFD_RELOC_ARM_LDR_SB_G2:
23910 gas_assert (!fixP->fx_done);
23911 if (!seg->use_rela_p)
23912 {
23913 bfd_vma insn;
23914 bfd_vma addend_abs = abs (value);
23915
23916 /* Check that the absolute value of the addend can be
23917 encoded in 12 bits. */
23918 if (addend_abs >= 0x1000)
23919 as_bad_where (fixP->fx_file, fixP->fx_line,
23920 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23921 (unsigned long) addend_abs);
23922
23923 /* Extract the instruction. */
23924 insn = md_chars_to_number (buf, INSN_SIZE);
23925
23926 /* If the addend is negative, clear bit 23 of the instruction.
23927 Otherwise set it. */
23928 if (value < 0)
23929 insn &= ~(1 << 23);
23930 else
23931 insn |= 1 << 23;
23932
23933 /* Place the absolute value of the addend into the first 12 bits
23934 of the instruction. */
23935 insn &= 0xfffff000;
23936 insn |= addend_abs;
23937
23938 /* Update the instruction. */
23939 md_number_to_chars (buf, insn, INSN_SIZE);
23940 }
23941 break;
23942
23943 case BFD_RELOC_ARM_LDRS_PC_G0:
23944 case BFD_RELOC_ARM_LDRS_PC_G1:
23945 case BFD_RELOC_ARM_LDRS_PC_G2:
23946 case BFD_RELOC_ARM_LDRS_SB_G0:
23947 case BFD_RELOC_ARM_LDRS_SB_G1:
23948 case BFD_RELOC_ARM_LDRS_SB_G2:
23949 gas_assert (!fixP->fx_done);
23950 if (!seg->use_rela_p)
23951 {
23952 bfd_vma insn;
23953 bfd_vma addend_abs = abs (value);
23954
23955 /* Check that the absolute value of the addend can be
23956 encoded in 8 bits. */
23957 if (addend_abs >= 0x100)
23958 as_bad_where (fixP->fx_file, fixP->fx_line,
23959 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23960 (unsigned long) addend_abs);
23961
23962 /* Extract the instruction. */
23963 insn = md_chars_to_number (buf, INSN_SIZE);
23964
23965 /* If the addend is negative, clear bit 23 of the instruction.
23966 Otherwise set it. */
23967 if (value < 0)
23968 insn &= ~(1 << 23);
23969 else
23970 insn |= 1 << 23;
23971
23972 /* Place the first four bits of the absolute value of the addend
23973 into the first 4 bits of the instruction, and the remaining
23974 four into bits 8 .. 11. */
23975 insn &= 0xfffff0f0;
23976 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
23977
23978 /* Update the instruction. */
23979 md_number_to_chars (buf, insn, INSN_SIZE);
23980 }
23981 break;
23982
23983 case BFD_RELOC_ARM_LDC_PC_G0:
23984 case BFD_RELOC_ARM_LDC_PC_G1:
23985 case BFD_RELOC_ARM_LDC_PC_G2:
23986 case BFD_RELOC_ARM_LDC_SB_G0:
23987 case BFD_RELOC_ARM_LDC_SB_G1:
23988 case BFD_RELOC_ARM_LDC_SB_G2:
23989 gas_assert (!fixP->fx_done);
23990 if (!seg->use_rela_p)
23991 {
23992 bfd_vma insn;
23993 bfd_vma addend_abs = abs (value);
23994
23995 /* Check that the absolute value of the addend is a multiple of
23996 four and, when divided by four, fits in 8 bits. */
23997 if (addend_abs & 0x3)
23998 as_bad_where (fixP->fx_file, fixP->fx_line,
23999 _("bad offset 0x%08lX (must be word-aligned)"),
24000 (unsigned long) addend_abs);
24001
24002 if ((addend_abs >> 2) > 0xff)
24003 as_bad_where (fixP->fx_file, fixP->fx_line,
24004 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24005 (unsigned long) addend_abs);
24006
24007 /* Extract the instruction. */
24008 insn = md_chars_to_number (buf, INSN_SIZE);
24009
24010 /* If the addend is negative, clear bit 23 of the instruction.
24011 Otherwise set it. */
24012 if (value < 0)
24013 insn &= ~(1 << 23);
24014 else
24015 insn |= 1 << 23;
24016
24017 /* Place the addend (divided by four) into the first eight
24018 bits of the instruction. */
24019 insn &= 0xfffffff0;
24020 insn |= addend_abs >> 2;
24021
24022 /* Update the instruction. */
24023 md_number_to_chars (buf, insn, INSN_SIZE);
24024 }
24025 break;
24026
24027 case BFD_RELOC_ARM_V4BX:
24028 /* This will need to go in the object file. */
24029 fixP->fx_done = 0;
24030 break;
24031
24032 case BFD_RELOC_UNUSED:
24033 default:
24034 as_bad_where (fixP->fx_file, fixP->fx_line,
24035 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
24036 }
24037}
24038
24039/* Translate internal representation of relocation info to BFD target
24040 format. */
24041
24042arelent *
24043tc_gen_reloc (asection *section, fixS *fixp)
24044{
24045 arelent * reloc;
24046 bfd_reloc_code_real_type code;
24047
24048 reloc = XNEW (arelent);
24049
24050 reloc->sym_ptr_ptr = XNEW (asymbol *);
24051 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
24052 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
24053
24054 if (fixp->fx_pcrel)
24055 {
24056 if (section->use_rela_p)
24057 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
24058 else
24059 fixp->fx_offset = reloc->address;
24060 }
24061 reloc->addend = fixp->fx_offset;
24062
24063 switch (fixp->fx_r_type)
24064 {
24065 case BFD_RELOC_8:
24066 if (fixp->fx_pcrel)
24067 {
24068 code = BFD_RELOC_8_PCREL;
24069 break;
24070 }
24071
24072 case BFD_RELOC_16:
24073 if (fixp->fx_pcrel)
24074 {
24075 code = BFD_RELOC_16_PCREL;
24076 break;
24077 }
24078
24079 case BFD_RELOC_32:
24080 if (fixp->fx_pcrel)
24081 {
24082 code = BFD_RELOC_32_PCREL;
24083 break;
24084 }
24085
24086 case BFD_RELOC_ARM_MOVW:
24087 if (fixp->fx_pcrel)
24088 {
24089 code = BFD_RELOC_ARM_MOVW_PCREL;
24090 break;
24091 }
24092
24093 case BFD_RELOC_ARM_MOVT:
24094 if (fixp->fx_pcrel)
24095 {
24096 code = BFD_RELOC_ARM_MOVT_PCREL;
24097 break;
24098 }
24099
24100 case BFD_RELOC_ARM_THUMB_MOVW:
24101 if (fixp->fx_pcrel)
24102 {
24103 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
24104 break;
24105 }
24106
24107 case BFD_RELOC_ARM_THUMB_MOVT:
24108 if (fixp->fx_pcrel)
24109 {
24110 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
24111 break;
24112 }
24113
24114 case BFD_RELOC_NONE:
24115 case BFD_RELOC_ARM_PCREL_BRANCH:
24116 case BFD_RELOC_ARM_PCREL_BLX:
24117 case BFD_RELOC_RVA:
24118 case BFD_RELOC_THUMB_PCREL_BRANCH7:
24119 case BFD_RELOC_THUMB_PCREL_BRANCH9:
24120 case BFD_RELOC_THUMB_PCREL_BRANCH12:
24121 case BFD_RELOC_THUMB_PCREL_BRANCH20:
24122 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24123 case BFD_RELOC_THUMB_PCREL_BRANCH25:
24124 case BFD_RELOC_VTABLE_ENTRY:
24125 case BFD_RELOC_VTABLE_INHERIT:
24126#ifdef TE_PE
24127 case BFD_RELOC_32_SECREL:
24128#endif
24129 code = fixp->fx_r_type;
24130 break;
24131
24132 case BFD_RELOC_THUMB_PCREL_BLX:
24133#ifdef OBJ_ELF
24134 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
24135 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
24136 else
24137#endif
24138 code = BFD_RELOC_THUMB_PCREL_BLX;
24139 break;
24140
24141 case BFD_RELOC_ARM_LITERAL:
24142 case BFD_RELOC_ARM_HWLITERAL:
24143 /* If this is called then the a literal has
24144 been referenced across a section boundary. */
24145 as_bad_where (fixp->fx_file, fixp->fx_line,
24146 _("literal referenced across section boundary"));
24147 return NULL;
24148
24149#ifdef OBJ_ELF
24150 case BFD_RELOC_ARM_TLS_CALL:
24151 case BFD_RELOC_ARM_THM_TLS_CALL:
24152 case BFD_RELOC_ARM_TLS_DESCSEQ:
24153 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
24154 case BFD_RELOC_ARM_GOT32:
24155 case BFD_RELOC_ARM_GOTOFF:
24156 case BFD_RELOC_ARM_GOT_PREL:
24157 case BFD_RELOC_ARM_PLT32:
24158 case BFD_RELOC_ARM_TARGET1:
24159 case BFD_RELOC_ARM_ROSEGREL32:
24160 case BFD_RELOC_ARM_SBREL32:
24161 case BFD_RELOC_ARM_PREL31:
24162 case BFD_RELOC_ARM_TARGET2:
24163 case BFD_RELOC_ARM_TLS_LDO32:
24164 case BFD_RELOC_ARM_PCREL_CALL:
24165 case BFD_RELOC_ARM_PCREL_JUMP:
24166 case BFD_RELOC_ARM_ALU_PC_G0_NC:
24167 case BFD_RELOC_ARM_ALU_PC_G0:
24168 case BFD_RELOC_ARM_ALU_PC_G1_NC:
24169 case BFD_RELOC_ARM_ALU_PC_G1:
24170 case BFD_RELOC_ARM_ALU_PC_G2:
24171 case BFD_RELOC_ARM_LDR_PC_G0:
24172 case BFD_RELOC_ARM_LDR_PC_G1:
24173 case BFD_RELOC_ARM_LDR_PC_G2:
24174 case BFD_RELOC_ARM_LDRS_PC_G0:
24175 case BFD_RELOC_ARM_LDRS_PC_G1:
24176 case BFD_RELOC_ARM_LDRS_PC_G2:
24177 case BFD_RELOC_ARM_LDC_PC_G0:
24178 case BFD_RELOC_ARM_LDC_PC_G1:
24179 case BFD_RELOC_ARM_LDC_PC_G2:
24180 case BFD_RELOC_ARM_ALU_SB_G0_NC:
24181 case BFD_RELOC_ARM_ALU_SB_G0:
24182 case BFD_RELOC_ARM_ALU_SB_G1_NC:
24183 case BFD_RELOC_ARM_ALU_SB_G1:
24184 case BFD_RELOC_ARM_ALU_SB_G2:
24185 case BFD_RELOC_ARM_LDR_SB_G0:
24186 case BFD_RELOC_ARM_LDR_SB_G1:
24187 case BFD_RELOC_ARM_LDR_SB_G2:
24188 case BFD_RELOC_ARM_LDRS_SB_G0:
24189 case BFD_RELOC_ARM_LDRS_SB_G1:
24190 case BFD_RELOC_ARM_LDRS_SB_G2:
24191 case BFD_RELOC_ARM_LDC_SB_G0:
24192 case BFD_RELOC_ARM_LDC_SB_G1:
24193 case BFD_RELOC_ARM_LDC_SB_G2:
24194 case BFD_RELOC_ARM_V4BX:
24195 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
24196 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
24197 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
24198 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
24199 code = fixp->fx_r_type;
24200 break;
24201
24202 case BFD_RELOC_ARM_TLS_GOTDESC:
24203 case BFD_RELOC_ARM_TLS_GD32:
24204 case BFD_RELOC_ARM_TLS_LE32:
24205 case BFD_RELOC_ARM_TLS_IE32:
24206 case BFD_RELOC_ARM_TLS_LDM32:
24207 /* BFD will include the symbol's address in the addend.
24208 But we don't want that, so subtract it out again here. */
24209 if (!S_IS_COMMON (fixp->fx_addsy))
24210 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
24211 code = fixp->fx_r_type;
24212 break;
24213#endif
24214
24215 case BFD_RELOC_ARM_IMMEDIATE:
24216 as_bad_where (fixp->fx_file, fixp->fx_line,
24217 _("internal relocation (type: IMMEDIATE) not fixed up"));
24218 return NULL;
24219
24220 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
24221 as_bad_where (fixp->fx_file, fixp->fx_line,
24222 _("ADRL used for a symbol not defined in the same file"));
24223 return NULL;
24224
24225 case BFD_RELOC_ARM_OFFSET_IMM:
24226 if (section->use_rela_p)
24227 {
24228 code = fixp->fx_r_type;
24229 break;
24230 }
24231
24232 if (fixp->fx_addsy != NULL
24233 && !S_IS_DEFINED (fixp->fx_addsy)
24234 && S_IS_LOCAL (fixp->fx_addsy))
24235 {
24236 as_bad_where (fixp->fx_file, fixp->fx_line,
24237 _("undefined local label `%s'"),
24238 S_GET_NAME (fixp->fx_addsy));
24239 return NULL;
24240 }
24241
24242 as_bad_where (fixp->fx_file, fixp->fx_line,
24243 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24244 return NULL;
24245
24246 default:
24247 {
24248 const char * type;
24249
24250 switch (fixp->fx_r_type)
24251 {
24252 case BFD_RELOC_NONE: type = "NONE"; break;
24253 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
24254 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
24255 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
24256 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
24257 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
24258 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
24259 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
24260 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
24261 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
24262 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
24263 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
24264 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
24265 default: type = _("<unknown>"); break;
24266 }
24267 as_bad_where (fixp->fx_file, fixp->fx_line,
24268 _("cannot represent %s relocation in this object file format"),
24269 type);
24270 return NULL;
24271 }
24272 }
24273
24274#ifdef OBJ_ELF
24275 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
24276 && GOT_symbol
24277 && fixp->fx_addsy == GOT_symbol)
24278 {
24279 code = BFD_RELOC_ARM_GOTPC;
24280 reloc->addend = fixp->fx_offset = reloc->address;
24281 }
24282#endif
24283
24284 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
24285
24286 if (reloc->howto == NULL)
24287 {
24288 as_bad_where (fixp->fx_file, fixp->fx_line,
24289 _("cannot represent %s relocation in this object file format"),
24290 bfd_get_reloc_code_name (code));
24291 return NULL;
24292 }
24293
24294 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24295 vtable entry to be used in the relocation's section offset. */
24296 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
24297 reloc->address = fixp->fx_offset;
24298
24299 return reloc;
24300}
24301
24302/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24303
24304void
24305cons_fix_new_arm (fragS * frag,
24306 int where,
24307 int size,
24308 expressionS * exp,
24309 bfd_reloc_code_real_type reloc)
24310{
24311 int pcrel = 0;
24312
24313 /* Pick a reloc.
24314 FIXME: @@ Should look at CPU word size. */
24315 switch (size)
24316 {
24317 case 1:
24318 reloc = BFD_RELOC_8;
24319 break;
24320 case 2:
24321 reloc = BFD_RELOC_16;
24322 break;
24323 case 4:
24324 default:
24325 reloc = BFD_RELOC_32;
24326 break;
24327 case 8:
24328 reloc = BFD_RELOC_64;
24329 break;
24330 }
24331
24332#ifdef TE_PE
24333 if (exp->X_op == O_secrel)
24334 {
24335 exp->X_op = O_symbol;
24336 reloc = BFD_RELOC_32_SECREL;
24337 }
24338#endif
24339
24340 fix_new_exp (frag, where, size, exp, pcrel, reloc);
24341}
24342
24343#if defined (OBJ_COFF)
24344void
24345arm_validate_fix (fixS * fixP)
24346{
24347 /* If the destination of the branch is a defined symbol which does not have
24348 the THUMB_FUNC attribute, then we must be calling a function which has
24349 the (interfacearm) attribute. We look for the Thumb entry point to that
24350 function and change the branch to refer to that function instead. */
24351 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
24352 && fixP->fx_addsy != NULL
24353 && S_IS_DEFINED (fixP->fx_addsy)
24354 && ! THUMB_IS_FUNC (fixP->fx_addsy))
24355 {
24356 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
24357 }
24358}
24359#endif
24360
24361
24362int
24363arm_force_relocation (struct fix * fixp)
24364{
24365#if defined (OBJ_COFF) && defined (TE_PE)
24366 if (fixp->fx_r_type == BFD_RELOC_RVA)
24367 return 1;
24368#endif
24369
24370 /* In case we have a call or a branch to a function in ARM ISA mode from
24371 a thumb function or vice-versa force the relocation. These relocations
24372 are cleared off for some cores that might have blx and simple transformations
24373 are possible. */
24374
24375#ifdef OBJ_ELF
24376 switch (fixp->fx_r_type)
24377 {
24378 case BFD_RELOC_ARM_PCREL_JUMP:
24379 case BFD_RELOC_ARM_PCREL_CALL:
24380 case BFD_RELOC_THUMB_PCREL_BLX:
24381 if (THUMB_IS_FUNC (fixp->fx_addsy))
24382 return 1;
24383 break;
24384
24385 case BFD_RELOC_ARM_PCREL_BLX:
24386 case BFD_RELOC_THUMB_PCREL_BRANCH25:
24387 case BFD_RELOC_THUMB_PCREL_BRANCH20:
24388 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24389 if (ARM_IS_FUNC (fixp->fx_addsy))
24390 return 1;
24391 break;
24392
24393 default:
24394 break;
24395 }
24396#endif
24397
24398 /* Resolve these relocations even if the symbol is extern or weak.
24399 Technically this is probably wrong due to symbol preemption.
24400 In practice these relocations do not have enough range to be useful
24401 at dynamic link time, and some code (e.g. in the Linux kernel)
24402 expects these references to be resolved. */
24403 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
24404 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
24405 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
24406 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
24407 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
24408 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
24409 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
24410 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
24411 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
24412 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
24413 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
24414 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
24415 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
24416 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
24417 return 0;
24418
24419 /* Always leave these relocations for the linker. */
24420 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
24421 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
24422 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
24423 return 1;
24424
24425 /* Always generate relocations against function symbols. */
24426 if (fixp->fx_r_type == BFD_RELOC_32
24427 && fixp->fx_addsy
24428 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
24429 return 1;
24430
24431 return generic_force_reloc (fixp);
24432}
24433
24434#if defined (OBJ_ELF) || defined (OBJ_COFF)
24435/* Relocations against function names must be left unadjusted,
24436 so that the linker can use this information to generate interworking
24437 stubs. The MIPS version of this function
24438 also prevents relocations that are mips-16 specific, but I do not
24439 know why it does this.
24440
24441 FIXME:
24442 There is one other problem that ought to be addressed here, but
24443 which currently is not: Taking the address of a label (rather
24444 than a function) and then later jumping to that address. Such
24445 addresses also ought to have their bottom bit set (assuming that
24446 they reside in Thumb code), but at the moment they will not. */
24447
24448bfd_boolean
24449arm_fix_adjustable (fixS * fixP)
24450{
24451 if (fixP->fx_addsy == NULL)
24452 return 1;
24453
24454 /* Preserve relocations against symbols with function type. */
24455 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
24456 return FALSE;
24457
24458 if (THUMB_IS_FUNC (fixP->fx_addsy)
24459 && fixP->fx_subsy == NULL)
24460 return FALSE;
24461
24462 /* We need the symbol name for the VTABLE entries. */
24463 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
24464 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
24465 return FALSE;
24466
24467 /* Don't allow symbols to be discarded on GOT related relocs. */
24468 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
24469 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
24470 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
24471 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
24472 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
24473 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
24474 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
24475 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
24476 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
24477 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
24478 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
24479 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
24480 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
24481 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
24482 return FALSE;
24483
24484 /* Similarly for group relocations. */
24485 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
24486 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
24487 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
24488 return FALSE;
24489
24490 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24491 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
24492 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
24493 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
24494 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
24495 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
24496 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
24497 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
24498 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
24499 return FALSE;
24500
24501 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24502 offsets, so keep these symbols. */
24503 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24504 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
24505 return FALSE;
24506
24507 return TRUE;
24508}
24509#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24510
24511#ifdef OBJ_ELF
24512const char *
24513elf32_arm_target_format (void)
24514{
24515#ifdef TE_SYMBIAN
24516 return (target_big_endian
24517 ? "elf32-bigarm-symbian"
24518 : "elf32-littlearm-symbian");
24519#elif defined (TE_VXWORKS)
24520 return (target_big_endian
24521 ? "elf32-bigarm-vxworks"
24522 : "elf32-littlearm-vxworks");
24523#elif defined (TE_NACL)
24524 return (target_big_endian
24525 ? "elf32-bigarm-nacl"
24526 : "elf32-littlearm-nacl");
24527#else
24528 if (target_big_endian)
24529 return "elf32-bigarm";
24530 else
24531 return "elf32-littlearm";
24532#endif
24533}
24534
24535void
24536armelf_frob_symbol (symbolS * symp,
24537 int * puntp)
24538{
24539 elf_frob_symbol (symp, puntp);
24540}
24541#endif
24542
24543/* MD interface: Finalization. */
24544
24545void
24546arm_cleanup (void)
24547{
24548 literal_pool * pool;
24549
24550 /* Ensure that all the IT blocks are properly closed. */
24551 check_it_blocks_finished ();
24552
24553 for (pool = list_of_pools; pool; pool = pool->next)
24554 {
24555 /* Put it at the end of the relevant section. */
24556 subseg_set (pool->section, pool->sub_section);
24557#ifdef OBJ_ELF
24558 arm_elf_change_section ();
24559#endif
24560 s_ltorg (0);
24561 }
24562}
24563
24564#ifdef OBJ_ELF
24565/* Remove any excess mapping symbols generated for alignment frags in
24566 SEC. We may have created a mapping symbol before a zero byte
24567 alignment; remove it if there's a mapping symbol after the
24568 alignment. */
24569static void
24570check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
24571 void *dummy ATTRIBUTE_UNUSED)
24572{
24573 segment_info_type *seginfo = seg_info (sec);
24574 fragS *fragp;
24575
24576 if (seginfo == NULL || seginfo->frchainP == NULL)
24577 return;
24578
24579 for (fragp = seginfo->frchainP->frch_root;
24580 fragp != NULL;
24581 fragp = fragp->fr_next)
24582 {
24583 symbolS *sym = fragp->tc_frag_data.last_map;
24584 fragS *next = fragp->fr_next;
24585
24586 /* Variable-sized frags have been converted to fixed size by
24587 this point. But if this was variable-sized to start with,
24588 there will be a fixed-size frag after it. So don't handle
24589 next == NULL. */
24590 if (sym == NULL || next == NULL)
24591 continue;
24592
24593 if (S_GET_VALUE (sym) < next->fr_address)
24594 /* Not at the end of this frag. */
24595 continue;
24596 know (S_GET_VALUE (sym) == next->fr_address);
24597
24598 do
24599 {
24600 if (next->tc_frag_data.first_map != NULL)
24601 {
24602 /* Next frag starts with a mapping symbol. Discard this
24603 one. */
24604 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
24605 break;
24606 }
24607
24608 if (next->fr_next == NULL)
24609 {
24610 /* This mapping symbol is at the end of the section. Discard
24611 it. */
24612 know (next->fr_fix == 0 && next->fr_var == 0);
24613 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
24614 break;
24615 }
24616
24617 /* As long as we have empty frags without any mapping symbols,
24618 keep looking. */
24619 /* If the next frag is non-empty and does not start with a
24620 mapping symbol, then this mapping symbol is required. */
24621 if (next->fr_address != next->fr_next->fr_address)
24622 break;
24623
24624 next = next->fr_next;
24625 }
24626 while (next != NULL);
24627 }
24628}
24629#endif
24630
24631/* Adjust the symbol table. This marks Thumb symbols as distinct from
24632 ARM ones. */
24633
24634void
24635arm_adjust_symtab (void)
24636{
24637#ifdef OBJ_COFF
24638 symbolS * sym;
24639
24640 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
24641 {
24642 if (ARM_IS_THUMB (sym))
24643 {
24644 if (THUMB_IS_FUNC (sym))
24645 {
24646 /* Mark the symbol as a Thumb function. */
24647 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
24648 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
24649 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
24650
24651 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
24652 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
24653 else
24654 as_bad (_("%s: unexpected function type: %d"),
24655 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
24656 }
24657 else switch (S_GET_STORAGE_CLASS (sym))
24658 {
24659 case C_EXT:
24660 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
24661 break;
24662 case C_STAT:
24663 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
24664 break;
24665 case C_LABEL:
24666 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
24667 break;
24668 default:
24669 /* Do nothing. */
24670 break;
24671 }
24672 }
24673
24674 if (ARM_IS_INTERWORK (sym))
24675 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
24676 }
24677#endif
24678#ifdef OBJ_ELF
24679 symbolS * sym;
24680 char bind;
24681
24682 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
24683 {
24684 if (ARM_IS_THUMB (sym))
24685 {
24686 elf_symbol_type * elf_sym;
24687
24688 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
24689 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
24690
24691 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
24692 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
24693 {
24694 /* If it's a .thumb_func, declare it as so,
24695 otherwise tag label as .code 16. */
24696 if (THUMB_IS_FUNC (sym))
24697 ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
24698 ST_BRANCH_TO_THUMB);
24699 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24700 elf_sym->internal_elf_sym.st_info =
24701 ELF_ST_INFO (bind, STT_ARM_16BIT);
24702 }
24703 }
24704 }
24705
24706 /* Remove any overlapping mapping symbols generated by alignment frags. */
24707 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
24708 /* Now do generic ELF adjustments. */
24709 elf_adjust_symtab ();
24710#endif
24711}
24712
24713/* MD interface: Initialization. */
24714
24715static void
24716set_constant_flonums (void)
24717{
24718 int i;
24719
24720 for (i = 0; i < NUM_FLOAT_VALS; i++)
24721 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
24722 abort ();
24723}
24724
24725/* Auto-select Thumb mode if it's the only available instruction set for the
24726 given architecture. */
24727
24728static void
24729autoselect_thumb_from_cpu_variant (void)
24730{
24731 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
24732 opcode_select (16);
24733}
24734
24735void
24736md_begin (void)
24737{
24738 unsigned mach;
24739 unsigned int i;
24740
24741 if ( (arm_ops_hsh = hash_new ()) == NULL
24742 || (arm_cond_hsh = hash_new ()) == NULL
24743 || (arm_shift_hsh = hash_new ()) == NULL
24744 || (arm_psr_hsh = hash_new ()) == NULL
24745 || (arm_v7m_psr_hsh = hash_new ()) == NULL
24746 || (arm_reg_hsh = hash_new ()) == NULL
24747 || (arm_reloc_hsh = hash_new ()) == NULL
24748 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
24749 as_fatal (_("virtual memory exhausted"));
24750
24751 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
24752 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
24753 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
24754 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
24755 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
24756 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
24757 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
24758 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
24759 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
24760 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
24761 (void *) (v7m_psrs + i));
24762 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
24763 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
24764 for (i = 0;
24765 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
24766 i++)
24767 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
24768 (void *) (barrier_opt_names + i));
24769#ifdef OBJ_ELF
24770 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
24771 {
24772 struct reloc_entry * entry = reloc_names + i;
24773
24774 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
24775 /* This makes encode_branch() use the EABI versions of this relocation. */
24776 entry->reloc = BFD_RELOC_UNUSED;
24777
24778 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
24779 }
24780#endif
24781
24782 set_constant_flonums ();
24783
24784 /* Set the cpu variant based on the command-line options. We prefer
24785 -mcpu= over -march= if both are set (as for GCC); and we prefer
24786 -mfpu= over any other way of setting the floating point unit.
24787 Use of legacy options with new options are faulted. */
24788 if (legacy_cpu)
24789 {
24790 if (mcpu_cpu_opt || march_cpu_opt)
24791 as_bad (_("use of old and new-style options to set CPU type"));
24792
24793 mcpu_cpu_opt = legacy_cpu;
24794 }
24795 else if (!mcpu_cpu_opt)
24796 mcpu_cpu_opt = march_cpu_opt;
24797
24798 if (legacy_fpu)
24799 {
24800 if (mfpu_opt)
24801 as_bad (_("use of old and new-style options to set FPU type"));
24802
24803 mfpu_opt = legacy_fpu;
24804 }
24805 else if (!mfpu_opt)
24806 {
24807#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24808 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24809 /* Some environments specify a default FPU. If they don't, infer it
24810 from the processor. */
24811 if (mcpu_fpu_opt)
24812 mfpu_opt = mcpu_fpu_opt;
24813 else
24814 mfpu_opt = march_fpu_opt;
24815#else
24816 mfpu_opt = &fpu_default;
24817#endif
24818 }
24819
24820 if (!mfpu_opt)
24821 {
24822 if (mcpu_cpu_opt != NULL)
24823 mfpu_opt = &fpu_default;
24824 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
24825 mfpu_opt = &fpu_arch_vfp_v2;
24826 else
24827 mfpu_opt = &fpu_arch_fpa;
24828 }
24829
24830#ifdef CPU_DEFAULT
24831 if (!mcpu_cpu_opt)
24832 {
24833 mcpu_cpu_opt = &cpu_default;
24834 selected_cpu = cpu_default;
24835 }
24836 else if (no_cpu_selected ())
24837 selected_cpu = cpu_default;
24838#else
24839 if (mcpu_cpu_opt)
24840 selected_cpu = *mcpu_cpu_opt;
24841 else
24842 mcpu_cpu_opt = &arm_arch_any;
24843#endif
24844
24845 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24846
24847 autoselect_thumb_from_cpu_variant ();
24848
24849 arm_arch_used = thumb_arch_used = arm_arch_none;
24850
24851#if defined OBJ_COFF || defined OBJ_ELF
24852 {
24853 unsigned int flags = 0;
24854
24855#if defined OBJ_ELF
24856 flags = meabi_flags;
24857
24858 switch (meabi_flags)
24859 {
24860 case EF_ARM_EABI_UNKNOWN:
24861#endif
24862 /* Set the flags in the private structure. */
24863 if (uses_apcs_26) flags |= F_APCS26;
24864 if (support_interwork) flags |= F_INTERWORK;
24865 if (uses_apcs_float) flags |= F_APCS_FLOAT;
24866 if (pic_code) flags |= F_PIC;
24867 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
24868 flags |= F_SOFT_FLOAT;
24869
24870 switch (mfloat_abi_opt)
24871 {
24872 case ARM_FLOAT_ABI_SOFT:
24873 case ARM_FLOAT_ABI_SOFTFP:
24874 flags |= F_SOFT_FLOAT;
24875 break;
24876
24877 case ARM_FLOAT_ABI_HARD:
24878 if (flags & F_SOFT_FLOAT)
24879 as_bad (_("hard-float conflicts with specified fpu"));
24880 break;
24881 }
24882
24883 /* Using pure-endian doubles (even if soft-float). */
24884 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
24885 flags |= F_VFP_FLOAT;
24886
24887#if defined OBJ_ELF
24888 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
24889 flags |= EF_ARM_MAVERICK_FLOAT;
24890 break;
24891
24892 case EF_ARM_EABI_VER4:
24893 case EF_ARM_EABI_VER5:
24894 /* No additional flags to set. */
24895 break;
24896
24897 default:
24898 abort ();
24899 }
24900#endif
24901 bfd_set_private_flags (stdoutput, flags);
24902
24903 /* We have run out flags in the COFF header to encode the
24904 status of ATPCS support, so instead we create a dummy,
24905 empty, debug section called .arm.atpcs. */
24906 if (atpcs)
24907 {
24908 asection * sec;
24909
24910 sec = bfd_make_section (stdoutput, ".arm.atpcs");
24911
24912 if (sec != NULL)
24913 {
24914 bfd_set_section_flags
24915 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
24916 bfd_set_section_size (stdoutput, sec, 0);
24917 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
24918 }
24919 }
24920 }
24921#endif
24922
24923 /* Record the CPU type as well. */
24924 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
24925 mach = bfd_mach_arm_iWMMXt2;
24926 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
24927 mach = bfd_mach_arm_iWMMXt;
24928 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
24929 mach = bfd_mach_arm_XScale;
24930 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
24931 mach = bfd_mach_arm_ep9312;
24932 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
24933 mach = bfd_mach_arm_5TE;
24934 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
24935 {
24936 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
24937 mach = bfd_mach_arm_5T;
24938 else
24939 mach = bfd_mach_arm_5;
24940 }
24941 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
24942 {
24943 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
24944 mach = bfd_mach_arm_4T;
24945 else
24946 mach = bfd_mach_arm_4;
24947 }
24948 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
24949 mach = bfd_mach_arm_3M;
24950 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
24951 mach = bfd_mach_arm_3;
24952 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
24953 mach = bfd_mach_arm_2a;
24954 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
24955 mach = bfd_mach_arm_2;
24956 else
24957 mach = bfd_mach_arm_unknown;
24958
24959 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
24960}
24961
24962/* Command line processing. */
24963
24964/* md_parse_option
24965 Invocation line includes a switch not recognized by the base assembler.
24966 See if it's a processor-specific option.
24967
24968 This routine is somewhat complicated by the need for backwards
24969 compatibility (since older releases of gcc can't be changed).
24970 The new options try to make the interface as compatible as
24971 possible with GCC.
24972
24973 New options (supported) are:
24974
24975 -mcpu=<cpu name> Assemble for selected processor
24976 -march=<architecture name> Assemble for selected architecture
24977 -mfpu=<fpu architecture> Assemble for selected FPU.
24978 -EB/-mbig-endian Big-endian
24979 -EL/-mlittle-endian Little-endian
24980 -k Generate PIC code
24981 -mthumb Start in Thumb mode
24982 -mthumb-interwork Code supports ARM/Thumb interworking
24983
24984 -m[no-]warn-deprecated Warn about deprecated features
24985 -m[no-]warn-syms Warn when symbols match instructions
24986
24987 For now we will also provide support for:
24988
24989 -mapcs-32 32-bit Program counter
24990 -mapcs-26 26-bit Program counter
24991 -macps-float Floats passed in FP registers
24992 -mapcs-reentrant Reentrant code
24993 -matpcs
24994 (sometime these will probably be replaced with -mapcs=<list of options>
24995 and -matpcs=<list of options>)
24996
24997 The remaining options are only supported for back-wards compatibility.
24998 Cpu variants, the arm part is optional:
24999 -m[arm]1 Currently not supported.
25000 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25001 -m[arm]3 Arm 3 processor
25002 -m[arm]6[xx], Arm 6 processors
25003 -m[arm]7[xx][t][[d]m] Arm 7 processors
25004 -m[arm]8[10] Arm 8 processors
25005 -m[arm]9[20][tdmi] Arm 9 processors
25006 -mstrongarm[110[0]] StrongARM processors
25007 -mxscale XScale processors
25008 -m[arm]v[2345[t[e]]] Arm architectures
25009 -mall All (except the ARM1)
25010 FP variants:
25011 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25012 -mfpe-old (No float load/store multiples)
25013 -mvfpxd VFP Single precision
25014 -mvfp All VFP
25015 -mno-fpu Disable all floating point instructions
25016
25017 The following CPU names are recognized:
25018 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25019 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25020 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25021 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25022 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25023 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25024 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25025
25026 */
25027
25028const char * md_shortopts = "m:k";
25029
25030#ifdef ARM_BI_ENDIAN
25031#define OPTION_EB (OPTION_MD_BASE + 0)
25032#define OPTION_EL (OPTION_MD_BASE + 1)
25033#else
25034#if TARGET_BYTES_BIG_ENDIAN
25035#define OPTION_EB (OPTION_MD_BASE + 0)
25036#else
25037#define OPTION_EL (OPTION_MD_BASE + 1)
25038#endif
25039#endif
25040#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25041
25042struct option md_longopts[] =
25043{
25044#ifdef OPTION_EB
25045 {"EB", no_argument, NULL, OPTION_EB},
25046#endif
25047#ifdef OPTION_EL
25048 {"EL", no_argument, NULL, OPTION_EL},
25049#endif
25050 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
25051 {NULL, no_argument, NULL, 0}
25052};
25053
25054
25055size_t md_longopts_size = sizeof (md_longopts);
25056
25057struct arm_option_table
25058{
25059 const char *option; /* Option name to match. */
25060 const char *help; /* Help information. */
25061 int *var; /* Variable to change. */
25062 int value; /* What to change it to. */
25063 const char *deprecated; /* If non-null, print this message. */
25064};
25065
25066struct arm_option_table arm_opts[] =
25067{
25068 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
25069 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
25070 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25071 &support_interwork, 1, NULL},
25072 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
25073 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
25074 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
25075 1, NULL},
25076 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
25077 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
25078 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
25079 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
25080 NULL},
25081
25082 /* These are recognized by the assembler, but have no affect on code. */
25083 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
25084 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
25085
25086 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
25087 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25088 &warn_on_deprecated, 0, NULL},
25089 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
25090 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
25091 {NULL, NULL, NULL, 0, NULL}
25092};
25093
25094struct arm_legacy_option_table
25095{
25096 const char *option; /* Option name to match. */
25097 const arm_feature_set **var; /* Variable to change. */
25098 const arm_feature_set value; /* What to change it to. */
25099 const char *deprecated; /* If non-null, print this message. */
25100};
25101
25102const struct arm_legacy_option_table arm_legacy_opts[] =
25103{
25104 /* DON'T add any new processors to this list -- we want the whole list
25105 to go away... Add them to the processors table instead. */
25106 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
25107 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
25108 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
25109 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
25110 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
25111 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
25112 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
25113 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
25114 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
25115 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
25116 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
25117 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
25118 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
25119 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
25120 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
25121 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
25122 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
25123 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
25124 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
25125 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
25126 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
25127 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
25128 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
25129 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
25130 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
25131 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
25132 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
25133 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
25134 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
25135 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
25136 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
25137 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
25138 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
25139 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
25140 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
25141 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
25142 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
25143 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
25144 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
25145 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
25146 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
25147 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
25148 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
25149 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
25150 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
25151 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
25152 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25153 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25154 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25155 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25156 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
25157 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
25158 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
25159 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
25160 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
25161 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
25162 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
25163 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
25164 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
25165 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
25166 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
25167 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
25168 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
25169 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
25170 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
25171 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
25172 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
25173 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
25174 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
25175 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
25176 N_("use -mcpu=strongarm110")},
25177 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
25178 N_("use -mcpu=strongarm1100")},
25179 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
25180 N_("use -mcpu=strongarm1110")},
25181 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
25182 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
25183 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
25184
25185 /* Architecture variants -- don't add any more to this list either. */
25186 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
25187 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
25188 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
25189 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
25190 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
25191 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
25192 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
25193 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
25194 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
25195 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
25196 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
25197 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
25198 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
25199 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
25200 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
25201 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
25202 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
25203 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
25204
25205 /* Floating point variants -- don't add any more to this list either. */
25206 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
25207 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
25208 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
25209 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
25210 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25211
25212 {NULL, NULL, ARM_ARCH_NONE, NULL}
25213};
25214
25215struct arm_cpu_option_table
25216{
25217 const char *name;
25218 size_t name_len;
25219 const arm_feature_set value;
25220 /* For some CPUs we assume an FPU unless the user explicitly sets
25221 -mfpu=... */
25222 const arm_feature_set default_fpu;
25223 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25224 case. */
25225 const char *canonical_name;
25226};
25227
25228/* This list should, at a minimum, contain all the cpu names
25229 recognized by GCC. */
25230#define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25231static const struct arm_cpu_option_table arm_cpus[] =
25232{
25233 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
25234 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
25235 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
25236 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
25237 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
25238 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25239 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25240 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25241 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25242 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25243 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25244 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
25245 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25246 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
25247 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25248 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
25249 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25250 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25251 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25252 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25253 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25254 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25255 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25256 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25257 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25258 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25259 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25260 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25261 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25262 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25263 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25264 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25265 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25266 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25267 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25268 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25269 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25270 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25271 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25272 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
25273 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25274 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25275 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25276 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25277 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25278 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25279 /* For V5 or later processors we default to using VFP; but the user
25280 should really set the FPU type explicitly. */
25281 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
25282 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25283 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
25284 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
25285 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
25286 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
25287 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
25288 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25289 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
25290 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
25291 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25292 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25293 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
25294 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
25295 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25296 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
25297 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
25298 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25299 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25300 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
25301 "ARM1026EJ-S"),
25302 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
25303 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25304 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25305 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25306 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25307 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25308 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
25309 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
25310 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
25311 "ARM1136JF-S"),
25312 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
25313 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
25314 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
25315 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
25316 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
25317 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ, FPU_NONE, NULL),
25318 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ, FPU_ARCH_VFP_V2, NULL),
25319 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
25320 FPU_NONE, "Cortex-A5"),
25321 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
25322 "Cortex-A7"),
25323 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
25324 ARM_FEATURE_COPROC (FPU_VFP_V3
25325 | FPU_NEON_EXT_V1),
25326 "Cortex-A8"),
25327 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
25328 ARM_FEATURE_COPROC (FPU_VFP_V3
25329 | FPU_NEON_EXT_V1),
25330 "Cortex-A9"),
25331 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
25332 "Cortex-A12"),
25333 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
25334 "Cortex-A15"),
25335 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
25336 "Cortex-A17"),
25337 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25338 "Cortex-A32"),
25339 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25340 "Cortex-A35"),
25341 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25342 "Cortex-A53"),
25343 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25344 "Cortex-A57"),
25345 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25346 "Cortex-A72"),
25347 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
25348 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
25349 "Cortex-R4F"),
25350 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
25351 FPU_NONE, "Cortex-R5"),
25352 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
25353 FPU_ARCH_VFP_V3D16,
25354 "Cortex-R7"),
25355 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV,
25356 FPU_ARCH_VFP_V3D16,
25357 "Cortex-R8"),
25358 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M7"),
25359 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
25360 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
25361 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
25362 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
25363 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
25364 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25365 "Samsung " \
25366 "Exynos M1"),
25367 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25368 "Qualcomm "
25369 "QDF24XX"),
25370
25371 /* ??? XSCALE is really an architecture. */
25372 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
25373 /* ??? iwmmxt is not a processor. */
25374 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
25375 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
25376 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
25377 /* Maverick */
25378 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
25379 FPU_ARCH_MAVERICK, "ARM920T"),
25380 /* Marvell processors. */
25381 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP
25382 | ARM_EXT_SEC,
25383 ARM_EXT2_V6T2_V8M),
25384 FPU_ARCH_VFP_V3D16, NULL),
25385 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP
25386 | ARM_EXT_SEC,
25387 ARM_EXT2_V6T2_V8M),
25388 FPU_ARCH_NEON_VFP_V4, NULL),
25389 /* APM X-Gene family. */
25390 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25391 "APM X-Gene 1"),
25392 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25393 "APM X-Gene 2"),
25394
25395 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
25396};
25397#undef ARM_CPU_OPT
25398
25399struct arm_arch_option_table
25400{
25401 const char *name;
25402 size_t name_len;
25403 const arm_feature_set value;
25404 const arm_feature_set default_fpu;
25405};
25406
25407/* This list should, at a minimum, contain all the architecture names
25408 recognized by GCC. */
25409#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25410static const struct arm_arch_option_table arm_archs[] =
25411{
25412 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
25413 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
25414 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
25415 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
25416 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
25417 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
25418 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
25419 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
25420 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
25421 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
25422 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
25423 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
25424 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
25425 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
25426 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
25427 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
25428 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
25429 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
25430 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
25431 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
25432 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
25433 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25434 kept to preserve existing behaviour. */
25435 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP),
25436 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP),
25437 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
25438 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
25439 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
25440 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25441 kept to preserve existing behaviour. */
25442 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP),
25443 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP),
25444 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
25445 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
25446 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
25447 /* The official spelling of the ARMv7 profile variants is the dashed form.
25448 Accept the non-dashed form for compatibility with old toolchains. */
25449 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
25450 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP),
25451 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
25452 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
25453 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
25454 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
25455 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
25456 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
25457 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
25458 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP),
25459 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
25460 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP),
25461 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP),
25462 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
25463 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
25464 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
25465 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
25466};
25467#undef ARM_ARCH_OPT
25468
25469/* ISA extensions in the co-processor and main instruction set space. */
25470struct arm_option_extension_value_table
25471{
25472 const char *name;
25473 size_t name_len;
25474 const arm_feature_set merge_value;
25475 const arm_feature_set clear_value;
25476 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25477 indicates that an extension is available for all architectures while
25478 ARM_ANY marks an empty entry. */
25479 const arm_feature_set allowed_archs[2];
25480};
25481
25482/* The following table must be in alphabetical order with a NULL last entry.
25483 */
25484#define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25485#define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25486static const struct arm_option_extension_value_table arm_extensions[] =
25487{
25488 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
25489 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25490 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25491 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
25492 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25493 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
25494 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
25495 ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
25496 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
25497 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25498 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
25499 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
25500 ARM_ARCH_V8_2A),
25501 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
25502 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
25503 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
25504 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
25505 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
25506 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
25507 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
25508 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
25509 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
25510 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
25511 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
25512 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
25513 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
25514 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
25515 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
25516 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
25517 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
25518 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
25519 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
25520 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25521 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
25522 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
25523 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25524 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
25525 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
25526 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
25527 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
25528 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
25529 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
25530 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25531 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
25532 | ARM_EXT_DIV),
25533 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
25534 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
25535 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
25536 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
25537 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
25538};
25539#undef ARM_EXT_OPT
25540
25541/* ISA floating-point and Advanced SIMD extensions. */
25542struct arm_option_fpu_value_table
25543{
25544 const char *name;
25545 const arm_feature_set value;
25546};
25547
25548/* This list should, at a minimum, contain all the fpu names
25549 recognized by GCC. */
25550static const struct arm_option_fpu_value_table arm_fpus[] =
25551{
25552 {"softfpa", FPU_NONE},
25553 {"fpe", FPU_ARCH_FPE},
25554 {"fpe2", FPU_ARCH_FPE},
25555 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
25556 {"fpa", FPU_ARCH_FPA},
25557 {"fpa10", FPU_ARCH_FPA},
25558 {"fpa11", FPU_ARCH_FPA},
25559 {"arm7500fe", FPU_ARCH_FPA},
25560 {"softvfp", FPU_ARCH_VFP},
25561 {"softvfp+vfp", FPU_ARCH_VFP_V2},
25562 {"vfp", FPU_ARCH_VFP_V2},
25563 {"vfp9", FPU_ARCH_VFP_V2},
25564 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
25565 {"vfp10", FPU_ARCH_VFP_V2},
25566 {"vfp10-r0", FPU_ARCH_VFP_V1},
25567 {"vfpxd", FPU_ARCH_VFP_V1xD},
25568 {"vfpv2", FPU_ARCH_VFP_V2},
25569 {"vfpv3", FPU_ARCH_VFP_V3},
25570 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
25571 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
25572 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
25573 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
25574 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
25575 {"arm1020t", FPU_ARCH_VFP_V1},
25576 {"arm1020e", FPU_ARCH_VFP_V2},
25577 {"arm1136jfs", FPU_ARCH_VFP_V2},
25578 {"arm1136jf-s", FPU_ARCH_VFP_V2},
25579 {"maverick", FPU_ARCH_MAVERICK},
25580 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
25581 {"neon-fp16", FPU_ARCH_NEON_FP16},
25582 {"vfpv4", FPU_ARCH_VFP_V4},
25583 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
25584 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
25585 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
25586 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
25587 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
25588 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
25589 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
25590 {"crypto-neon-fp-armv8",
25591 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
25592 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
25593 {"crypto-neon-fp-armv8.1",
25594 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
25595 {NULL, ARM_ARCH_NONE}
25596};
25597
25598struct arm_option_value_table
25599{
25600 const char *name;
25601 long value;
25602};
25603
25604static const struct arm_option_value_table arm_float_abis[] =
25605{
25606 {"hard", ARM_FLOAT_ABI_HARD},
25607 {"softfp", ARM_FLOAT_ABI_SOFTFP},
25608 {"soft", ARM_FLOAT_ABI_SOFT},
25609 {NULL, 0}
25610};
25611
25612#ifdef OBJ_ELF
25613/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25614static const struct arm_option_value_table arm_eabis[] =
25615{
25616 {"gnu", EF_ARM_EABI_UNKNOWN},
25617 {"4", EF_ARM_EABI_VER4},
25618 {"5", EF_ARM_EABI_VER5},
25619 {NULL, 0}
25620};
25621#endif
25622
25623struct arm_long_option_table
25624{
25625 const char * option; /* Substring to match. */
25626 const char * help; /* Help information. */
25627 int (* func) (const char * subopt); /* Function to decode sub-option. */
25628 const char * deprecated; /* If non-null, print this message. */
25629};
25630
25631static bfd_boolean
25632arm_parse_extension (const char *str, const arm_feature_set **opt_p)
25633{
25634 arm_feature_set *ext_set = XNEW (arm_feature_set);
25635
25636 /* We insist on extensions being specified in alphabetical order, and with
25637 extensions being added before being removed. We achieve this by having
25638 the global ARM_EXTENSIONS table in alphabetical order, and using the
25639 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25640 or removing it (0) and only allowing it to change in the order
25641 -1 -> 1 -> 0. */
25642 const struct arm_option_extension_value_table * opt = NULL;
25643 const arm_feature_set arm_any = ARM_ANY;
25644 int adding_value = -1;
25645
25646 /* Copy the feature set, so that we can modify it. */
25647 *ext_set = **opt_p;
25648 *opt_p = ext_set;
25649
25650 while (str != NULL && *str != 0)
25651 {
25652 const char *ext;
25653 size_t len;
25654
25655 if (*str != '+')
25656 {
25657 as_bad (_("invalid architectural extension"));
25658 return FALSE;
25659 }
25660
25661 str++;
25662 ext = strchr (str, '+');
25663
25664 if (ext != NULL)
25665 len = ext - str;
25666 else
25667 len = strlen (str);
25668
25669 if (len >= 2 && strncmp (str, "no", 2) == 0)
25670 {
25671 if (adding_value != 0)
25672 {
25673 adding_value = 0;
25674 opt = arm_extensions;
25675 }
25676
25677 len -= 2;
25678 str += 2;
25679 }
25680 else if (len > 0)
25681 {
25682 if (adding_value == -1)
25683 {
25684 adding_value = 1;
25685 opt = arm_extensions;
25686 }
25687 else if (adding_value != 1)
25688 {
25689 as_bad (_("must specify extensions to add before specifying "
25690 "those to remove"));
25691 return FALSE;
25692 }
25693 }
25694
25695 if (len == 0)
25696 {
25697 as_bad (_("missing architectural extension"));
25698 return FALSE;
25699 }
25700
25701 gas_assert (adding_value != -1);
25702 gas_assert (opt != NULL);
25703
25704 /* Scan over the options table trying to find an exact match. */
25705 for (; opt->name != NULL; opt++)
25706 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25707 {
25708 int i, nb_allowed_archs =
25709 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
25710 /* Check we can apply the extension to this architecture. */
25711 for (i = 0; i < nb_allowed_archs; i++)
25712 {
25713 /* Empty entry. */
25714 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
25715 continue;
25716 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *ext_set))
25717 break;
25718 }
25719 if (i == nb_allowed_archs)
25720 {
25721 as_bad (_("extension does not apply to the base architecture"));
25722 return FALSE;
25723 }
25724
25725 /* Add or remove the extension. */
25726 if (adding_value)
25727 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
25728 else
25729 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
25730
25731 break;
25732 }
25733
25734 if (opt->name == NULL)
25735 {
25736 /* Did we fail to find an extension because it wasn't specified in
25737 alphabetical order, or because it does not exist? */
25738
25739 for (opt = arm_extensions; opt->name != NULL; opt++)
25740 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25741 break;
25742
25743 if (opt->name == NULL)
25744 as_bad (_("unknown architectural extension `%s'"), str);
25745 else
25746 as_bad (_("architectural extensions must be specified in "
25747 "alphabetical order"));
25748
25749 return FALSE;
25750 }
25751 else
25752 {
25753 /* We should skip the extension we've just matched the next time
25754 round. */
25755 opt++;
25756 }
25757
25758 str = ext;
25759 };
25760
25761 return TRUE;
25762}
25763
25764static bfd_boolean
25765arm_parse_cpu (const char *str)
25766{
25767 const struct arm_cpu_option_table *opt;
25768 const char *ext = strchr (str, '+');
25769 size_t len;
25770
25771 if (ext != NULL)
25772 len = ext - str;
25773 else
25774 len = strlen (str);
25775
25776 if (len == 0)
25777 {
25778 as_bad (_("missing cpu name `%s'"), str);
25779 return FALSE;
25780 }
25781
25782 for (opt = arm_cpus; opt->name != NULL; opt++)
25783 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25784 {
25785 mcpu_cpu_opt = &opt->value;
25786 mcpu_fpu_opt = &opt->default_fpu;
25787 if (opt->canonical_name)
25788 {
25789 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
25790 strcpy (selected_cpu_name, opt->canonical_name);
25791 }
25792 else
25793 {
25794 size_t i;
25795
25796 if (len >= sizeof selected_cpu_name)
25797 len = (sizeof selected_cpu_name) - 1;
25798
25799 for (i = 0; i < len; i++)
25800 selected_cpu_name[i] = TOUPPER (opt->name[i]);
25801 selected_cpu_name[i] = 0;
25802 }
25803
25804 if (ext != NULL)
25805 return arm_parse_extension (ext, &mcpu_cpu_opt);
25806
25807 return TRUE;
25808 }
25809
25810 as_bad (_("unknown cpu `%s'"), str);
25811 return FALSE;
25812}
25813
25814static bfd_boolean
25815arm_parse_arch (const char *str)
25816{
25817 const struct arm_arch_option_table *opt;
25818 const char *ext = strchr (str, '+');
25819 size_t len;
25820
25821 if (ext != NULL)
25822 len = ext - str;
25823 else
25824 len = strlen (str);
25825
25826 if (len == 0)
25827 {
25828 as_bad (_("missing architecture name `%s'"), str);
25829 return FALSE;
25830 }
25831
25832 for (opt = arm_archs; opt->name != NULL; opt++)
25833 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25834 {
25835 march_cpu_opt = &opt->value;
25836 march_fpu_opt = &opt->default_fpu;
25837 strcpy (selected_cpu_name, opt->name);
25838
25839 if (ext != NULL)
25840 return arm_parse_extension (ext, &march_cpu_opt);
25841
25842 return TRUE;
25843 }
25844
25845 as_bad (_("unknown architecture `%s'\n"), str);
25846 return FALSE;
25847}
25848
25849static bfd_boolean
25850arm_parse_fpu (const char * str)
25851{
25852 const struct arm_option_fpu_value_table * opt;
25853
25854 for (opt = arm_fpus; opt->name != NULL; opt++)
25855 if (streq (opt->name, str))
25856 {
25857 mfpu_opt = &opt->value;
25858 return TRUE;
25859 }
25860
25861 as_bad (_("unknown floating point format `%s'\n"), str);
25862 return FALSE;
25863}
25864
25865static bfd_boolean
25866arm_parse_float_abi (const char * str)
25867{
25868 const struct arm_option_value_table * opt;
25869
25870 for (opt = arm_float_abis; opt->name != NULL; opt++)
25871 if (streq (opt->name, str))
25872 {
25873 mfloat_abi_opt = opt->value;
25874 return TRUE;
25875 }
25876
25877 as_bad (_("unknown floating point abi `%s'\n"), str);
25878 return FALSE;
25879}
25880
25881#ifdef OBJ_ELF
25882static bfd_boolean
25883arm_parse_eabi (const char * str)
25884{
25885 const struct arm_option_value_table *opt;
25886
25887 for (opt = arm_eabis; opt->name != NULL; opt++)
25888 if (streq (opt->name, str))
25889 {
25890 meabi_flags = opt->value;
25891 return TRUE;
25892 }
25893 as_bad (_("unknown EABI `%s'\n"), str);
25894 return FALSE;
25895}
25896#endif
25897
25898static bfd_boolean
25899arm_parse_it_mode (const char * str)
25900{
25901 bfd_boolean ret = TRUE;
25902
25903 if (streq ("arm", str))
25904 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
25905 else if (streq ("thumb", str))
25906 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
25907 else if (streq ("always", str))
25908 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
25909 else if (streq ("never", str))
25910 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
25911 else
25912 {
25913 as_bad (_("unknown implicit IT mode `%s', should be "\
25914 "arm, thumb, always, or never."), str);
25915 ret = FALSE;
25916 }
25917
25918 return ret;
25919}
25920
25921static bfd_boolean
25922arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
25923{
25924 codecomposer_syntax = TRUE;
25925 arm_comment_chars[0] = ';';
25926 arm_line_separator_chars[0] = 0;
25927 return TRUE;
25928}
25929
25930struct arm_long_option_table arm_long_opts[] =
25931{
25932 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25933 arm_parse_cpu, NULL},
25934 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25935 arm_parse_arch, NULL},
25936 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25937 arm_parse_fpu, NULL},
25938 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25939 arm_parse_float_abi, NULL},
25940#ifdef OBJ_ELF
25941 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25942 arm_parse_eabi, NULL},
25943#endif
25944 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25945 arm_parse_it_mode, NULL},
25946 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25947 arm_ccs_mode, NULL},
25948 {NULL, NULL, 0, NULL}
25949};
25950
25951int
25952md_parse_option (int c, const char * arg)
25953{
25954 struct arm_option_table *opt;
25955 const struct arm_legacy_option_table *fopt;
25956 struct arm_long_option_table *lopt;
25957
25958 switch (c)
25959 {
25960#ifdef OPTION_EB
25961 case OPTION_EB:
25962 target_big_endian = 1;
25963 break;
25964#endif
25965
25966#ifdef OPTION_EL
25967 case OPTION_EL:
25968 target_big_endian = 0;
25969 break;
25970#endif
25971
25972 case OPTION_FIX_V4BX:
25973 fix_v4bx = TRUE;
25974 break;
25975
25976 case 'a':
25977 /* Listing option. Just ignore these, we don't support additional
25978 ones. */
25979 return 0;
25980
25981 default:
25982 for (opt = arm_opts; opt->option != NULL; opt++)
25983 {
25984 if (c == opt->option[0]
25985 && ((arg == NULL && opt->option[1] == 0)
25986 || streq (arg, opt->option + 1)))
25987 {
25988 /* If the option is deprecated, tell the user. */
25989 if (warn_on_deprecated && opt->deprecated != NULL)
25990 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
25991 arg ? arg : "", _(opt->deprecated));
25992
25993 if (opt->var != NULL)
25994 *opt->var = opt->value;
25995
25996 return 1;
25997 }
25998 }
25999
26000 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
26001 {
26002 if (c == fopt->option[0]
26003 && ((arg == NULL && fopt->option[1] == 0)
26004 || streq (arg, fopt->option + 1)))
26005 {
26006 /* If the option is deprecated, tell the user. */
26007 if (warn_on_deprecated && fopt->deprecated != NULL)
26008 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
26009 arg ? arg : "", _(fopt->deprecated));
26010
26011 if (fopt->var != NULL)
26012 *fopt->var = &fopt->value;
26013
26014 return 1;
26015 }
26016 }
26017
26018 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
26019 {
26020 /* These options are expected to have an argument. */
26021 if (c == lopt->option[0]
26022 && arg != NULL
26023 && strncmp (arg, lopt->option + 1,
26024 strlen (lopt->option + 1)) == 0)
26025 {
26026 /* If the option is deprecated, tell the user. */
26027 if (warn_on_deprecated && lopt->deprecated != NULL)
26028 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
26029 _(lopt->deprecated));
26030
26031 /* Call the sup-option parser. */
26032 return lopt->func (arg + strlen (lopt->option) - 1);
26033 }
26034 }
26035
26036 return 0;
26037 }
26038
26039 return 1;
26040}
26041
26042void
26043md_show_usage (FILE * fp)
26044{
26045 struct arm_option_table *opt;
26046 struct arm_long_option_table *lopt;
26047
26048 fprintf (fp, _(" ARM-specific assembler options:\n"));
26049
26050 for (opt = arm_opts; opt->option != NULL; opt++)
26051 if (opt->help != NULL)
26052 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
26053
26054 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
26055 if (lopt->help != NULL)
26056 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
26057
26058#ifdef OPTION_EB
26059 fprintf (fp, _("\
26060 -EB assemble code for a big-endian cpu\n"));
26061#endif
26062
26063#ifdef OPTION_EL
26064 fprintf (fp, _("\
26065 -EL assemble code for a little-endian cpu\n"));
26066#endif
26067
26068 fprintf (fp, _("\
26069 --fix-v4bx Allow BX in ARMv4 code\n"));
26070}
26071
26072
26073#ifdef OBJ_ELF
26074typedef struct
26075{
26076 int val;
26077 arm_feature_set flags;
26078} cpu_arch_ver_table;
26079
26080/* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26081 must be sorted least features first but some reordering is needed, eg. for
26082 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26083static const cpu_arch_ver_table cpu_arch_ver[] =
26084{
26085 {1, ARM_ARCH_V4},
26086 {2, ARM_ARCH_V4T},
26087 {3, ARM_ARCH_V5},
26088 {3, ARM_ARCH_V5T},
26089 {4, ARM_ARCH_V5TE},
26090 {5, ARM_ARCH_V5TEJ},
26091 {6, ARM_ARCH_V6},
26092 {9, ARM_ARCH_V6K},
26093 {7, ARM_ARCH_V6Z},
26094 {11, ARM_ARCH_V6M},
26095 {12, ARM_ARCH_V6SM},
26096 {8, ARM_ARCH_V6T2},
26097 {10, ARM_ARCH_V7VE},
26098 {10, ARM_ARCH_V7R},
26099 {10, ARM_ARCH_V7M},
26100 {14, ARM_ARCH_V8A},
26101 {16, ARM_ARCH_V8M_BASE},
26102 {17, ARM_ARCH_V8M_MAIN},
26103 {0, ARM_ARCH_NONE}
26104};
26105
26106/* Set an attribute if it has not already been set by the user. */
26107static void
26108aeabi_set_attribute_int (int tag, int value)
26109{
26110 if (tag < 1
26111 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
26112 || !attributes_set_explicitly[tag])
26113 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
26114}
26115
26116static void
26117aeabi_set_attribute_string (int tag, const char *value)
26118{
26119 if (tag < 1
26120 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
26121 || !attributes_set_explicitly[tag])
26122 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
26123}
26124
26125/* Set the public EABI object attributes. */
26126void
26127aeabi_set_public_attributes (void)
26128{
26129 int arch;
26130 char profile;
26131 int virt_sec = 0;
26132 int fp16_optional = 0;
26133 arm_feature_set arm_arch = ARM_ARCH_NONE;
26134 arm_feature_set flags;
26135 arm_feature_set tmp;
26136 arm_feature_set arm_arch_v8m_base = ARM_ARCH_V8M_BASE;
26137 const cpu_arch_ver_table *p;
26138
26139 /* Choose the architecture based on the capabilities of the requested cpu
26140 (if any) and/or the instructions actually used. */
26141 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
26142 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
26143 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
26144
26145 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
26146 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
26147
26148 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
26149 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
26150
26151 selected_cpu = flags;
26152
26153 /* Allow the user to override the reported architecture. */
26154 if (object_arch)
26155 {
26156 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
26157 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
26158 }
26159
26160 /* We need to make sure that the attributes do not identify us as v6S-M
26161 when the only v6S-M feature in use is the Operating System Extensions. */
26162 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
26163 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
26164 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
26165
26166 tmp = flags;
26167 arch = 0;
26168 for (p = cpu_arch_ver; p->val; p++)
26169 {
26170 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
26171 {
26172 arch = p->val;
26173 arm_arch = p->flags;
26174 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
26175 }
26176 }
26177
26178 /* The table lookup above finds the last architecture to contribute
26179 a new feature. Unfortunately, Tag13 is a subset of the union of
26180 v6T2 and v7-M, so it is never seen as contributing a new feature.
26181 We can not search for the last entry which is entirely used,
26182 because if no CPU is specified we build up only those flags
26183 actually used. Perhaps we should separate out the specified
26184 and implicit cases. Avoid taking this path for -march=all by
26185 checking for contradictory v7-A / v7-M features. */
26186 if (arch == TAG_CPU_ARCH_V7
26187 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
26188 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
26189 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
26190 {
26191 arch = TAG_CPU_ARCH_V7E_M;
26192 arm_arch = (arm_feature_set) ARM_ARCH_V7EM;
26193 }
26194
26195 ARM_CLEAR_FEATURE (tmp, flags, arm_arch_v8m_base);
26196 if (arch == TAG_CPU_ARCH_V8M_BASE && ARM_CPU_HAS_FEATURE (tmp, arm_arch_any))
26197 {
26198 arch = TAG_CPU_ARCH_V8M_MAIN;
26199 arm_arch = (arm_feature_set) ARM_ARCH_V8M_MAIN;
26200 }
26201
26202 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26203 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26204 ARMv8-M, -march=all must be detected as ARMv8-A. */
26205 if (arch == TAG_CPU_ARCH_V8M_MAIN
26206 && ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
26207 {
26208 arch = TAG_CPU_ARCH_V8;
26209 arm_arch = (arm_feature_set) ARM_ARCH_V8A;
26210 }
26211
26212 /* Tag_CPU_name. */
26213 if (selected_cpu_name[0])
26214 {
26215 char *q;
26216
26217 q = selected_cpu_name;
26218 if (strncmp (q, "armv", 4) == 0)
26219 {
26220 int i;
26221
26222 q += 4;
26223 for (i = 0; q[i]; i++)
26224 q[i] = TOUPPER (q[i]);
26225 }
26226 aeabi_set_attribute_string (Tag_CPU_name, q);
26227 }
26228
26229 /* Tag_CPU_arch. */
26230 aeabi_set_attribute_int (Tag_CPU_arch, arch);
26231
26232 /* Tag_CPU_arch_profile. */
26233 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
26234 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
26235 || (ARM_CPU_HAS_FEATURE (flags, arm_ext_atomics)
26236 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only)))
26237 profile = 'A';
26238 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
26239 profile = 'R';
26240 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
26241 profile = 'M';
26242 else
26243 profile = '\0';
26244
26245 if (profile != '\0')
26246 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
26247
26248 /* Tag_DSP_extension. */
26249 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_dsp))
26250 {
26251 arm_feature_set ext;
26252
26253 /* DSP instructions not in architecture. */
26254 ARM_CLEAR_FEATURE (ext, flags, arm_arch);
26255 if (ARM_CPU_HAS_FEATURE (ext, arm_ext_dsp))
26256 aeabi_set_attribute_int (Tag_DSP_extension, 1);
26257 }
26258
26259 /* Tag_ARM_ISA_use. */
26260 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
26261 || arch == 0)
26262 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
26263
26264 /* Tag_THUMB_ISA_use. */
26265 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
26266 || arch == 0)
26267 {
26268 int thumb_isa_use;
26269
26270 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
26271 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
26272 thumb_isa_use = 3;
26273 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
26274 thumb_isa_use = 2;
26275 else
26276 thumb_isa_use = 1;
26277 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
26278 }
26279
26280 /* Tag_VFP_arch. */
26281 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
26282 aeabi_set_attribute_int (Tag_VFP_arch,
26283 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
26284 ? 7 : 8);
26285 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
26286 aeabi_set_attribute_int (Tag_VFP_arch,
26287 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
26288 ? 5 : 6);
26289 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
26290 {
26291 fp16_optional = 1;
26292 aeabi_set_attribute_int (Tag_VFP_arch, 3);
26293 }
26294 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
26295 {
26296 aeabi_set_attribute_int (Tag_VFP_arch, 4);
26297 fp16_optional = 1;
26298 }
26299 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
26300 aeabi_set_attribute_int (Tag_VFP_arch, 2);
26301 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
26302 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
26303 aeabi_set_attribute_int (Tag_VFP_arch, 1);
26304
26305 /* Tag_ABI_HardFP_use. */
26306 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
26307 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
26308 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
26309
26310 /* Tag_WMMX_arch. */
26311 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
26312 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
26313 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
26314 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
26315
26316 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26317 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
26318 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
26319 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
26320 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
26321 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
26322 {
26323 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
26324 {
26325 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
26326 }
26327 else
26328 {
26329 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
26330 fp16_optional = 1;
26331 }
26332 }
26333
26334 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26335 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
26336 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
26337
26338 /* Tag_DIV_use.
26339
26340 We set Tag_DIV_use to two when integer divide instructions have been used
26341 in ARM state, or when Thumb integer divide instructions have been used,
26342 but we have no architecture profile set, nor have we any ARM instructions.
26343
26344 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26345 by the base architecture.
26346
26347 For new architectures we will have to check these tests. */
26348 gas_assert (arch <= TAG_CPU_ARCH_V8
26349 || (arch >= TAG_CPU_ARCH_V8M_BASE
26350 && arch <= TAG_CPU_ARCH_V8M_MAIN));
26351 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
26352 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
26353 aeabi_set_attribute_int (Tag_DIV_use, 0);
26354 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
26355 || (profile == '\0'
26356 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
26357 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
26358 aeabi_set_attribute_int (Tag_DIV_use, 2);
26359
26360 /* Tag_MP_extension_use. */
26361 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
26362 aeabi_set_attribute_int (Tag_MPextension_use, 1);
26363
26364 /* Tag Virtualization_use. */
26365 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
26366 virt_sec |= 1;
26367 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
26368 virt_sec |= 2;
26369 if (virt_sec != 0)
26370 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
26371}
26372
26373/* Add the default contents for the .ARM.attributes section. */
26374void
26375arm_md_end (void)
26376{
26377 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
26378 return;
26379
26380 aeabi_set_public_attributes ();
26381}
26382#endif /* OBJ_ELF */
26383
26384
26385/* Parse a .cpu directive. */
26386
26387static void
26388s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
26389{
26390 const struct arm_cpu_option_table *opt;
26391 char *name;
26392 char saved_char;
26393
26394 name = input_line_pointer;
26395 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
26396 input_line_pointer++;
26397 saved_char = *input_line_pointer;
26398 *input_line_pointer = 0;
26399
26400 /* Skip the first "all" entry. */
26401 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
26402 if (streq (opt->name, name))
26403 {
26404 mcpu_cpu_opt = &opt->value;
26405 selected_cpu = opt->value;
26406 if (opt->canonical_name)
26407 strcpy (selected_cpu_name, opt->canonical_name);
26408 else
26409 {
26410 int i;
26411 for (i = 0; opt->name[i]; i++)
26412 selected_cpu_name[i] = TOUPPER (opt->name[i]);
26413
26414 selected_cpu_name[i] = 0;
26415 }
26416 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
26417 *input_line_pointer = saved_char;
26418 demand_empty_rest_of_line ();
26419 return;
26420 }
26421 as_bad (_("unknown cpu `%s'"), name);
26422 *input_line_pointer = saved_char;
26423 ignore_rest_of_line ();
26424}
26425
26426
26427/* Parse a .arch directive. */
26428
26429static void
26430s_arm_arch (int ignored ATTRIBUTE_UNUSED)
26431{
26432 const struct arm_arch_option_table *opt;
26433 char saved_char;
26434 char *name;
26435
26436 name = input_line_pointer;
26437 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
26438 input_line_pointer++;
26439 saved_char = *input_line_pointer;
26440 *input_line_pointer = 0;
26441
26442 /* Skip the first "all" entry. */
26443 for (opt = arm_archs + 1; opt->name != NULL; opt++)
26444 if (streq (opt->name, name))
26445 {
26446 mcpu_cpu_opt = &opt->value;
26447 selected_cpu = opt->value;
26448 strcpy (selected_cpu_name, opt->name);
26449 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
26450 *input_line_pointer = saved_char;
26451 demand_empty_rest_of_line ();
26452 return;
26453 }
26454
26455 as_bad (_("unknown architecture `%s'\n"), name);
26456 *input_line_pointer = saved_char;
26457 ignore_rest_of_line ();
26458}
26459
26460
26461/* Parse a .object_arch directive. */
26462
26463static void
26464s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
26465{
26466 const struct arm_arch_option_table *opt;
26467 char saved_char;
26468 char *name;
26469
26470 name = input_line_pointer;
26471 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
26472 input_line_pointer++;
26473 saved_char = *input_line_pointer;
26474 *input_line_pointer = 0;
26475
26476 /* Skip the first "all" entry. */
26477 for (opt = arm_archs + 1; opt->name != NULL; opt++)
26478 if (streq (opt->name, name))
26479 {
26480 object_arch = &opt->value;
26481 *input_line_pointer = saved_char;
26482 demand_empty_rest_of_line ();
26483 return;
26484 }
26485
26486 as_bad (_("unknown architecture `%s'\n"), name);
26487 *input_line_pointer = saved_char;
26488 ignore_rest_of_line ();
26489}
26490
26491/* Parse a .arch_extension directive. */
26492
26493static void
26494s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
26495{
26496 const struct arm_option_extension_value_table *opt;
26497 const arm_feature_set arm_any = ARM_ANY;
26498 char saved_char;
26499 char *name;
26500 int adding_value = 1;
26501
26502 name = input_line_pointer;
26503 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
26504 input_line_pointer++;
26505 saved_char = *input_line_pointer;
26506 *input_line_pointer = 0;
26507
26508 if (strlen (name) >= 2
26509 && strncmp (name, "no", 2) == 0)
26510 {
26511 adding_value = 0;
26512 name += 2;
26513 }
26514
26515 for (opt = arm_extensions; opt->name != NULL; opt++)
26516 if (streq (opt->name, name))
26517 {
26518 int i, nb_allowed_archs =
26519 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
26520 for (i = 0; i < nb_allowed_archs; i++)
26521 {
26522 /* Empty entry. */
26523 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
26524 continue;
26525 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *mcpu_cpu_opt))
26526 break;
26527 }
26528
26529 if (i == nb_allowed_archs)
26530 {
26531 as_bad (_("architectural extension `%s' is not allowed for the "
26532 "current base architecture"), name);
26533 break;
26534 }
26535
26536 if (adding_value)
26537 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu,
26538 opt->merge_value);
26539 else
26540 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value);
26541
26542 mcpu_cpu_opt = &selected_cpu;
26543 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
26544 *input_line_pointer = saved_char;
26545 demand_empty_rest_of_line ();
26546 return;
26547 }
26548
26549 if (opt->name == NULL)
26550 as_bad (_("unknown architecture extension `%s'\n"), name);
26551
26552 *input_line_pointer = saved_char;
26553 ignore_rest_of_line ();
26554}
26555
26556/* Parse a .fpu directive. */
26557
26558static void
26559s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
26560{
26561 const struct arm_option_fpu_value_table *opt;
26562 char saved_char;
26563 char *name;
26564
26565 name = input_line_pointer;
26566 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
26567 input_line_pointer++;
26568 saved_char = *input_line_pointer;
26569 *input_line_pointer = 0;
26570
26571 for (opt = arm_fpus; opt->name != NULL; opt++)
26572 if (streq (opt->name, name))
26573 {
26574 mfpu_opt = &opt->value;
26575 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
26576 *input_line_pointer = saved_char;
26577 demand_empty_rest_of_line ();
26578 return;
26579 }
26580
26581 as_bad (_("unknown floating point format `%s'\n"), name);
26582 *input_line_pointer = saved_char;
26583 ignore_rest_of_line ();
26584}
26585
26586/* Copy symbol information. */
26587
26588void
26589arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
26590{
26591 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
26592}
26593
26594#ifdef OBJ_ELF
26595/* Given a symbolic attribute NAME, return the proper integer value.
26596 Returns -1 if the attribute is not known. */
26597
26598int
26599arm_convert_symbolic_attribute (const char *name)
26600{
26601 static const struct
26602 {
26603 const char * name;
26604 const int tag;
26605 }
26606 attribute_table[] =
26607 {
26608 /* When you modify this table you should
26609 also modify the list in doc/c-arm.texi. */
26610#define T(tag) {#tag, tag}
26611 T (Tag_CPU_raw_name),
26612 T (Tag_CPU_name),
26613 T (Tag_CPU_arch),
26614 T (Tag_CPU_arch_profile),
26615 T (Tag_ARM_ISA_use),
26616 T (Tag_THUMB_ISA_use),
26617 T (Tag_FP_arch),
26618 T (Tag_VFP_arch),
26619 T (Tag_WMMX_arch),
26620 T (Tag_Advanced_SIMD_arch),
26621 T (Tag_PCS_config),
26622 T (Tag_ABI_PCS_R9_use),
26623 T (Tag_ABI_PCS_RW_data),
26624 T (Tag_ABI_PCS_RO_data),
26625 T (Tag_ABI_PCS_GOT_use),
26626 T (Tag_ABI_PCS_wchar_t),
26627 T (Tag_ABI_FP_rounding),
26628 T (Tag_ABI_FP_denormal),
26629 T (Tag_ABI_FP_exceptions),
26630 T (Tag_ABI_FP_user_exceptions),
26631 T (Tag_ABI_FP_number_model),
26632 T (Tag_ABI_align_needed),
26633 T (Tag_ABI_align8_needed),
26634 T (Tag_ABI_align_preserved),
26635 T (Tag_ABI_align8_preserved),
26636 T (Tag_ABI_enum_size),
26637 T (Tag_ABI_HardFP_use),
26638 T (Tag_ABI_VFP_args),
26639 T (Tag_ABI_WMMX_args),
26640 T (Tag_ABI_optimization_goals),
26641 T (Tag_ABI_FP_optimization_goals),
26642 T (Tag_compatibility),
26643 T (Tag_CPU_unaligned_access),
26644 T (Tag_FP_HP_extension),
26645 T (Tag_VFP_HP_extension),
26646 T (Tag_ABI_FP_16bit_format),
26647 T (Tag_MPextension_use),
26648 T (Tag_DIV_use),
26649 T (Tag_nodefaults),
26650 T (Tag_also_compatible_with),
26651 T (Tag_conformance),
26652 T (Tag_T2EE_use),
26653 T (Tag_Virtualization_use),
26654 T (Tag_DSP_extension),
26655 /* We deliberately do not include Tag_MPextension_use_legacy. */
26656#undef T
26657 };
26658 unsigned int i;
26659
26660 if (name == NULL)
26661 return -1;
26662
26663 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
26664 if (streq (name, attribute_table[i].name))
26665 return attribute_table[i].tag;
26666
26667 return -1;
26668}
26669
26670
26671/* Apply sym value for relocations only in the case that they are for
26672 local symbols in the same segment as the fixup and you have the
26673 respective architectural feature for blx and simple switches. */
26674int
26675arm_apply_sym_value (struct fix * fixP, segT this_seg)
26676{
26677 if (fixP->fx_addsy
26678 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
26679 /* PR 17444: If the local symbol is in a different section then a reloc
26680 will always be generated for it, so applying the symbol value now
26681 will result in a double offset being stored in the relocation. */
26682 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
26683 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
26684 {
26685 switch (fixP->fx_r_type)
26686 {
26687 case BFD_RELOC_ARM_PCREL_BLX:
26688 case BFD_RELOC_THUMB_PCREL_BRANCH23:
26689 if (ARM_IS_FUNC (fixP->fx_addsy))
26690 return 1;
26691 break;
26692
26693 case BFD_RELOC_ARM_PCREL_CALL:
26694 case BFD_RELOC_THUMB_PCREL_BLX:
26695 if (THUMB_IS_FUNC (fixP->fx_addsy))
26696 return 1;
26697 break;
26698
26699 default:
26700 break;
26701 }
26702
26703 }
26704 return 0;
26705}
26706#endif /* OBJ_ELF */
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