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sim: split sim-signal.h include out
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1/* This must come before any other includes. */
2#include "defs.h"
3
4#include <inttypes.h>
5#include <signal.h>
6#include "bfd.h"
7#include "sim/callback.h"
8#include "sim/sim.h"
9
10#include "sim-main.h"
11#include "sim-options.h"
12#include "sim-signal.h"
13
14#include "gdb/sim-d10v.h"
15#include "gdb/signals.h"
16
17#include <string.h>
18#include <stdlib.h>
19#include <assert.h>
20
21enum _leftright { LEFT_FIRST, RIGHT_FIRST };
22
23struct _state State;
24
25int d10v_debug;
26
27/* Set this to true to get the previous segment layout. */
28
29int old_segment_mapping;
30
31unsigned long ins_type_counters[ (int)INS_MAX ];
32
33uint16 OP[4];
34
35static long hash (long insn, int format);
36static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32 ins, int size);
37static void get_operands (struct simops *s, uint32 ins);
38static void do_long (SIM_DESC, SIM_CPU *, uint32 ins);
39static void do_2_short (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2, enum _leftright leftright);
40static void do_parallel (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2);
41static char *add_commas (char *buf, int sizeof_buf, unsigned long value);
42static INLINE uint8 *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
43
44#define MAX_HASH 63
45struct hash_entry
46{
47 struct hash_entry *next;
48 uint32 opcode;
49 uint32 mask;
50 int size;
51 struct simops *ops;
52};
53
54struct hash_entry hash_table[MAX_HASH+1];
55
56INLINE static long
57hash (long insn, int format)
58{
59 if (format & LONG_OPCODE)
60 return ((insn & 0x3F000000) >> 24);
61 else
62 return((insn & 0x7E00) >> 9);
63}
64
65INLINE static struct hash_entry *
66lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32 ins, int size)
67{
68 struct hash_entry *h;
69
70 if (size)
71 h = &hash_table[(ins & 0x3F000000) >> 24];
72 else
73 h = &hash_table[(ins & 0x7E00) >> 9];
74
75 while ((ins & h->mask) != h->opcode || h->size != size)
76 {
77 if (h->next == NULL)
78 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGILL);
79 h = h->next;
80 }
81 return (h);
82}
83
84INLINE static void
85get_operands (struct simops *s, uint32 ins)
86{
87 int i, shift, bits, flags;
88 uint32 mask;
89 for (i=0; i < s->numops; i++)
90 {
91 shift = s->operands[3*i];
92 bits = s->operands[3*i+1];
93 flags = s->operands[3*i+2];
94 mask = 0x7FFFFFFF >> (31 - bits);
95 OP[i] = (ins >> shift) & mask;
96 }
97 /* FIXME: for tracing, update values that need to be updated each
98 instruction decode cycle */
99 State.trace.psw = PSW;
100}
101
102static void
103do_long (SIM_DESC sd, SIM_CPU *cpu, uint32 ins)
104{
105 struct hash_entry *h;
106#ifdef DEBUG
107 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
108 sim_io_printf (sd, "do_long 0x%x\n", ins);
109#endif
110 h = lookup_hash (sd, cpu, ins, 1);
111 if (h == NULL)
112 return;
113 get_operands (h->ops, ins);
114 State.ins_type = INS_LONG;
115 ins_type_counters[ (int)State.ins_type ]++;
116 (h->ops->func) (sd, cpu);
117}
118
119static void
120do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2, enum _leftright leftright)
121{
122 struct hash_entry *h;
123 enum _ins_type first, second;
124
125#ifdef DEBUG
126 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
127 sim_io_printf (sd, "do_2_short 0x%x (%s) -> 0x%x\n", ins1,
128 leftright ? "left" : "right", ins2);
129#endif
130
131 if (leftright == LEFT_FIRST)
132 {
133 first = INS_LEFT;
134 second = INS_RIGHT;
135 ins_type_counters[ (int)INS_LEFTRIGHT ]++;
136 }
137 else
138 {
139 first = INS_RIGHT;
140 second = INS_LEFT;
141 ins_type_counters[ (int)INS_RIGHTLEFT ]++;
142 }
143
144 /* Issue the first instruction */
145 h = lookup_hash (sd, cpu, ins1, 0);
146 if (h == NULL)
147 return;
148 get_operands (h->ops, ins1);
149 State.ins_type = first;
150 ins_type_counters[ (int)State.ins_type ]++;
151 (h->ops->func) (sd, cpu);
152
153 /* Issue the second instruction (if the PC hasn't changed) */
154 if (!State.pc_changed)
155 {
156 /* finish any existing instructions */
157 SLOT_FLUSH ();
158 h = lookup_hash (sd, cpu, ins2, 0);
159 if (h == NULL)
160 return;
161 get_operands (h->ops, ins2);
162 State.ins_type = second;
163 ins_type_counters[ (int)State.ins_type ]++;
164 ins_type_counters[ (int)INS_CYCLES ]++;
165 (h->ops->func) (sd, cpu);
166 }
167 else
168 ins_type_counters[ (int)INS_COND_JUMP ]++;
169}
170
171static void
172do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2)
173{
174 struct hash_entry *h1, *h2;
175#ifdef DEBUG
176 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
177 sim_io_printf (sd, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
178#endif
179 ins_type_counters[ (int)INS_PARALLEL ]++;
180 h1 = lookup_hash (sd, cpu, ins1, 0);
181 if (h1 == NULL)
182 return;
183 h2 = lookup_hash (sd, cpu, ins2, 0);
184 if (h2 == NULL)
185 return;
186
187 if (h1->ops->exec_type == PARONLY)
188 {
189 get_operands (h1->ops, ins1);
190 State.ins_type = INS_LEFT_COND_TEST;
191 ins_type_counters[ (int)State.ins_type ]++;
192 (h1->ops->func) (sd, cpu);
193 if (State.exe)
194 {
195 ins_type_counters[ (int)INS_COND_TRUE ]++;
196 get_operands (h2->ops, ins2);
197 State.ins_type = INS_RIGHT_COND_EXE;
198 ins_type_counters[ (int)State.ins_type ]++;
199 (h2->ops->func) (sd, cpu);
200 }
201 else
202 ins_type_counters[ (int)INS_COND_FALSE ]++;
203 }
204 else if (h2->ops->exec_type == PARONLY)
205 {
206 get_operands (h2->ops, ins2);
207 State.ins_type = INS_RIGHT_COND_TEST;
208 ins_type_counters[ (int)State.ins_type ]++;
209 (h2->ops->func) (sd, cpu);
210 if (State.exe)
211 {
212 ins_type_counters[ (int)INS_COND_TRUE ]++;
213 get_operands (h1->ops, ins1);
214 State.ins_type = INS_LEFT_COND_EXE;
215 ins_type_counters[ (int)State.ins_type ]++;
216 (h1->ops->func) (sd, cpu);
217 }
218 else
219 ins_type_counters[ (int)INS_COND_FALSE ]++;
220 }
221 else
222 {
223 get_operands (h1->ops, ins1);
224 State.ins_type = INS_LEFT_PARALLEL;
225 ins_type_counters[ (int)State.ins_type ]++;
226 (h1->ops->func) (sd, cpu);
227 get_operands (h2->ops, ins2);
228 State.ins_type = INS_RIGHT_PARALLEL;
229 ins_type_counters[ (int)State.ins_type ]++;
230 (h2->ops->func) (sd, cpu);
231 }
232}
233
234static char *
235add_commas (char *buf, int sizeof_buf, unsigned long value)
236{
237 int comma = 3;
238 char *endbuf = buf + sizeof_buf - 1;
239
240 *--endbuf = '\0';
241 do {
242 if (comma-- == 0)
243 {
244 *--endbuf = ',';
245 comma = 2;
246 }
247
248 *--endbuf = (value % 10) + '0';
249 } while ((value /= 10) != 0);
250
251 return endbuf;
252}
253
254static void
255sim_size (int power)
256{
257 int i;
258 for (i = 0; i < IMEM_SEGMENTS; i++)
259 {
260 if (State.mem.insn[i])
261 free (State.mem.insn[i]);
262 }
263 for (i = 0; i < DMEM_SEGMENTS; i++)
264 {
265 if (State.mem.data[i])
266 free (State.mem.data[i]);
267 }
268 for (i = 0; i < UMEM_SEGMENTS; i++)
269 {
270 if (State.mem.unif[i])
271 free (State.mem.unif[i]);
272 }
273 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
274 registers. */
275 State.mem.data[0] = calloc (1, SEGMENT_SIZE);
276}
277
278/* For tracing - leave info on last access around. */
279static char *last_segname = "invalid";
280static char *last_from = "invalid";
281static char *last_to = "invalid";
282
283enum
284 {
285 IMAP0_OFFSET = 0xff00,
286 DMAP0_OFFSET = 0xff08,
287 DMAP2_SHADDOW = 0xff04,
288 DMAP2_OFFSET = 0xff0c
289 };
290
291static void
292set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value)
293{
294 uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
295 + DMAP0_OFFSET + 2 * reg_nr);
296 WRITE_16 (raw, value);
297#ifdef DEBUG
298 if ((d10v_debug & DEBUG_MEMORY))
299 {
300 sim_io_printf (sd, "mem: dmap%d=0x%04lx\n", reg_nr, value);
301 }
302#endif
303}
304
305static unsigned long
306dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
307{
308 uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
309 + DMAP0_OFFSET + 2 * reg_nr);
310 return READ_16 (raw);
311}
312
313static void
314set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value)
315{
316 uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
317 + IMAP0_OFFSET + 2 * reg_nr);
318 WRITE_16 (raw, value);
319#ifdef DEBUG
320 if ((d10v_debug & DEBUG_MEMORY))
321 {
322 sim_io_printf (sd, "mem: imap%d=0x%04lx\n", reg_nr, value);
323 }
324#endif
325}
326
327static unsigned long
328imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
329{
330 uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
331 + IMAP0_OFFSET + 2 * reg_nr);
332 return READ_16 (raw);
333}
334
335enum
336 {
337 HELD_SPI_IDX = 0,
338 HELD_SPU_IDX = 1
339 };
340
341static unsigned long
342spu_register (void)
343{
344 if (PSW_SM)
345 return GPR (SP_IDX);
346 else
347 return HELD_SP (HELD_SPU_IDX);
348}
349
350static unsigned long
351spi_register (void)
352{
353 if (!PSW_SM)
354 return GPR (SP_IDX);
355 else
356 return HELD_SP (HELD_SPI_IDX);
357}
358
359static void
360set_spi_register (unsigned long value)
361{
362 if (!PSW_SM)
363 SET_GPR (SP_IDX, value);
364 SET_HELD_SP (HELD_SPI_IDX, value);
365}
366
367static void
368set_spu_register (unsigned long value)
369{
370 if (PSW_SM)
371 SET_GPR (SP_IDX, value);
372 SET_HELD_SP (HELD_SPU_IDX, value);
373}
374
375/* Given a virtual address in the DMAP address space, translate it
376 into a physical address. */
377
378static unsigned long
379sim_d10v_translate_dmap_addr (SIM_DESC sd,
380 SIM_CPU *cpu,
381 unsigned long offset,
382 int nr_bytes,
383 unsigned long *phys,
384 void *regcache,
385 unsigned long (*dmap_register) (SIM_DESC,
386 SIM_CPU *,
387 void *regcache,
388 int reg_nr))
389{
390 short map;
391 int regno;
392 last_from = "logical-data";
393 if (offset >= DMAP_BLOCK_SIZE * SIM_D10V_NR_DMAP_REGS)
394 {
395 /* Logical address out side of data segments, not supported */
396 return 0;
397 }
398 regno = (offset / DMAP_BLOCK_SIZE);
399 offset = (offset % DMAP_BLOCK_SIZE);
400 if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE)
401 {
402 /* Don't cross a BLOCK boundary */
403 nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
404 }
405 map = dmap_register (sd, cpu, regcache, regno);
406 if (regno == 3)
407 {
408 /* Always maps to data memory */
409 int iospi = (offset / 0x1000) % 4;
410 int iosp = (map >> (4 * (3 - iospi))) % 0x10;
411 last_to = "io-space";
412 *phys = (SIM_D10V_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset);
413 }
414 else
415 {
416 int sp = ((map & 0x3000) >> 12);
417 int segno = (map & 0x3ff);
418 switch (sp)
419 {
420 case 0: /* 00: Unified memory */
421 *phys = SIM_D10V_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
422 last_to = "unified";
423 break;
424 case 1: /* 01: Instruction Memory */
425 *phys = SIM_D10V_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
426 last_to = "chip-insn";
427 break;
428 case 2: /* 10: Internal data memory */
429 *phys = SIM_D10V_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
430 last_to = "chip-data";
431 break;
432 case 3: /* 11: Reserved */
433 return 0;
434 }
435 }
436 return nr_bytes;
437}
438
439/* Given a virtual address in the IMAP address space, translate it
440 into a physical address. */
441
442static unsigned long
443sim_d10v_translate_imap_addr (SIM_DESC sd,
444 SIM_CPU *cpu,
445 unsigned long offset,
446 int nr_bytes,
447 unsigned long *phys,
448 void *regcache,
449 unsigned long (*imap_register) (SIM_DESC,
450 SIM_CPU *,
451 void *regcache,
452 int reg_nr))
453{
454 short map;
455 int regno;
456 int sp;
457 int segno;
458 last_from = "logical-insn";
459 if (offset >= (IMAP_BLOCK_SIZE * SIM_D10V_NR_IMAP_REGS))
460 {
461 /* Logical address outside of IMAP segments, not supported */
462 return 0;
463 }
464 regno = (offset / IMAP_BLOCK_SIZE);
465 offset = (offset % IMAP_BLOCK_SIZE);
466 if (offset + nr_bytes > IMAP_BLOCK_SIZE)
467 {
468 /* Don't cross a BLOCK boundary */
469 nr_bytes = IMAP_BLOCK_SIZE - offset;
470 }
471 map = imap_register (sd, cpu, regcache, regno);
472 sp = (map & 0x3000) >> 12;
473 segno = (map & 0x007f);
474 switch (sp)
475 {
476 case 0: /* 00: unified memory */
477 *phys = SIM_D10V_MEMORY_UNIFIED + (segno << 17) + offset;
478 last_to = "unified";
479 break;
480 case 1: /* 01: instruction memory */
481 *phys = SIM_D10V_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset;
482 last_to = "chip-insn";
483 break;
484 case 2: /*10*/
485 /* Reserved. */
486 return 0;
487 case 3: /* 11: for testing - instruction memory */
488 offset = (offset % 0x800);
489 *phys = SIM_D10V_MEMORY_INSN + offset;
490 if (offset + nr_bytes > 0x800)
491 /* don't cross VM boundary */
492 nr_bytes = 0x800 - offset;
493 last_to = "test-insn";
494 break;
495 }
496 return nr_bytes;
497}
498
499static unsigned long
500sim_d10v_translate_addr (SIM_DESC sd,
501 SIM_CPU *cpu,
502 unsigned long memaddr,
503 int nr_bytes,
504 unsigned long *targ_addr,
505 void *regcache,
506 unsigned long (*dmap_register) (SIM_DESC,
507 SIM_CPU *,
508 void *regcache,
509 int reg_nr),
510 unsigned long (*imap_register) (SIM_DESC,
511 SIM_CPU *,
512 void *regcache,
513 int reg_nr))
514{
515 unsigned long phys;
516 unsigned long seg;
517 unsigned long off;
518
519 last_from = "unknown";
520 last_to = "unknown";
521
522 seg = (memaddr >> 24);
523 off = (memaddr & 0xffffffL);
524
525 /* However, if we've asked to use the previous generation of segment
526 mapping, rearrange the segments as follows. */
527
528 if (old_segment_mapping)
529 {
530 switch (seg)
531 {
532 case 0x00: /* DMAP translated memory */
533 seg = 0x10;
534 break;
535 case 0x01: /* IMAP translated memory */
536 seg = 0x11;
537 break;
538 case 0x10: /* On-chip data memory */
539 seg = 0x02;
540 break;
541 case 0x11: /* On-chip insn memory */
542 seg = 0x01;
543 break;
544 case 0x12: /* Unified memory */
545 seg = 0x00;
546 break;
547 }
548 }
549
550 switch (seg)
551 {
552 case 0x00: /* Physical unified memory */
553 last_from = "phys-unified";
554 last_to = "unified";
555 phys = SIM_D10V_MEMORY_UNIFIED + off;
556 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
557 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
558 break;
559
560 case 0x01: /* Physical instruction memory */
561 last_from = "phys-insn";
562 last_to = "chip-insn";
563 phys = SIM_D10V_MEMORY_INSN + off;
564 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
565 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
566 break;
567
568 case 0x02: /* Physical data memory segment */
569 last_from = "phys-data";
570 last_to = "chip-data";
571 phys = SIM_D10V_MEMORY_DATA + off;
572 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
573 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
574 break;
575
576 case 0x10: /* in logical data address segment */
577 nr_bytes = sim_d10v_translate_dmap_addr (sd, cpu, off, nr_bytes, &phys,
578 regcache, dmap_register);
579 break;
580
581 case 0x11: /* in logical instruction address segment */
582 nr_bytes = sim_d10v_translate_imap_addr (sd, cpu, off, nr_bytes, &phys,
583 regcache, imap_register);
584 break;
585
586 default:
587 return 0;
588 }
589
590 *targ_addr = phys;
591 return nr_bytes;
592}
593
594/* Return a pointer into the raw buffer designated by phys_addr. It
595 is assumed that the client has already ensured that the access
596 isn't going to cross a segment boundary. */
597
598uint8 *
599map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr)
600{
601 uint8 **memory;
602 uint8 *raw;
603 unsigned offset;
604 int segment = ((phys_addr >> 24) & 0xff);
605
606 switch (segment)
607 {
608
609 case 0x00: /* Unified memory */
610 {
611 memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
612 last_segname = "umem";
613 break;
614 }
615
616 case 0x01: /* On-chip insn memory */
617 {
618 memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
619 last_segname = "imem";
620 break;
621 }
622
623 case 0x02: /* On-chip data memory */
624 {
625 if ((phys_addr & 0xff00) == 0xff00)
626 {
627 phys_addr = (phys_addr & 0xffff);
628 if (phys_addr == DMAP2_SHADDOW)
629 {
630 phys_addr = DMAP2_OFFSET;
631 last_segname = "dmap";
632 }
633 else
634 last_segname = "reg";
635 }
636 else
637 last_segname = "dmem";
638 memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
639 break;
640 }
641
642 default:
643 /* OOPS! */
644 last_segname = "scrap";
645 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS);
646 }
647
648 if (*memory == NULL)
649 *memory = xcalloc (1, SEGMENT_SIZE);
650
651 offset = (phys_addr % SEGMENT_SIZE);
652 raw = *memory + offset;
653 return raw;
654}
655
656/* Transfer data to/from simulated memory. Since a bug in either the
657 simulated program or in gdb or the simulator itself may cause a
658 bogus address to be passed in, we need to do some sanity checking
659 on addresses to make sure they are within bounds. When an address
660 fails the bounds check, treat it as a zero length read/write rather
661 than aborting the entire run. */
662
663static int
664xfer_mem (SIM_DESC sd,
665 SIM_ADDR virt,
666 unsigned char *buffer,
667 int size,
668 int write_p)
669{
670 uint8 *memory;
671 unsigned long phys;
672 int phys_size;
673 phys_size = sim_d10v_translate_addr (sd, NULL, virt, size, &phys, NULL,
674 dmap_register, imap_register);
675 if (phys_size == 0)
676 return 0;
677
678 memory = map_memory (sd, NULL, phys);
679
680#ifdef DEBUG
681 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
682 {
683 sim_io_printf
684 (sd,
685 "sim_%s %d bytes: 0x%08" PRIxTA " (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
686 write_p ? "write" : "read",
687 phys_size, virt, last_from,
688 phys, last_to,
689 (long) memory, last_segname);
690 }
691#endif
692
693 if (write_p)
694 {
695 memcpy (memory, buffer, phys_size);
696 }
697 else
698 {
699 memcpy (buffer, memory, phys_size);
700 }
701
702 return phys_size;
703}
704
705
706int
707sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
708{
709 /* FIXME: this should be performing a virtual transfer */
710 /* FIXME: We cast the const away, but it's safe because xfer_mem only reads
711 when write_p==1. This is still ugly. */
712 return xfer_mem (sd, addr, (void *) buffer, size, 1);
713}
714
715int
716sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
717{
718 /* FIXME: this should be performing a virtual transfer */
719 return xfer_mem (sd, addr, buffer, size, 0);
720}
721
722static sim_cia
723d10v_pc_get (sim_cpu *cpu)
724{
725 return PC;
726}
727
728static void
729d10v_pc_set (sim_cpu *cpu, sim_cia pc)
730{
731 SIM_DESC sd = CPU_STATE (cpu);
732 SET_PC (pc);
733}
734
735static void
736free_state (SIM_DESC sd)
737{
738 if (STATE_MODULES (sd) != NULL)
739 sim_module_uninstall (sd);
740 sim_cpu_free_all (sd);
741 sim_state_free (sd);
742}
743
744static int d10v_reg_fetch (SIM_CPU *, int, unsigned char *, int);
745static int d10v_reg_store (SIM_CPU *, int, unsigned char *, int);
746
747SIM_DESC
748sim_open (SIM_OPEN_KIND kind, host_callback *cb,
749 struct bfd *abfd, char * const *argv)
750{
751 struct simops *s;
752 struct hash_entry *h;
753 static int init_p = 0;
754 char * const *p;
755 int i;
756 SIM_DESC sd = sim_state_alloc (kind, cb);
757 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
758
759 /* Set default options before parsing user options. */
760 current_alignment = STRICT_ALIGNMENT;
761
762 /* The cpu data is kept in a separately allocated chunk of memory. */
763 if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
764 {
765 free_state (sd);
766 return 0;
767 }
768
769 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
770 {
771 free_state (sd);
772 return 0;
773 }
774
775 /* The parser will print an error message for us, so we silently return. */
776 if (sim_parse_args (sd, argv) != SIM_RC_OK)
777 {
778 free_state (sd);
779 return 0;
780 }
781
782 /* Check for/establish the a reference program image. */
783 if (sim_analyze_program (sd,
784 (STATE_PROG_ARGV (sd) != NULL
785 ? *STATE_PROG_ARGV (sd)
786 : NULL), abfd) != SIM_RC_OK)
787 {
788 free_state (sd);
789 return 0;
790 }
791
792 /* Configure/verify the target byte order and other runtime
793 configuration options. */
794 if (sim_config (sd) != SIM_RC_OK)
795 {
796 sim_module_uninstall (sd);
797 return 0;
798 }
799
800 if (sim_post_argv_init (sd) != SIM_RC_OK)
801 {
802 /* Uninstall the modules to avoid memory leaks,
803 file descriptor leaks, etc. */
804 sim_module_uninstall (sd);
805 return 0;
806 }
807
808 /* CPU specific initialization. */
809 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
810 {
811 SIM_CPU *cpu = STATE_CPU (sd, i);
812
813 CPU_REG_FETCH (cpu) = d10v_reg_fetch;
814 CPU_REG_STORE (cpu) = d10v_reg_store;
815 CPU_PC_FETCH (cpu) = d10v_pc_get;
816 CPU_PC_STORE (cpu) = d10v_pc_set;
817 }
818
819 old_segment_mapping = 0;
820
821 /* NOTE: This argument parsing is only effective when this function
822 is called by GDB. Standalone argument parsing is handled by
823 sim/common/run.c. */
824 for (p = argv + 1; *p; ++p)
825 {
826 if (strcmp (*p, "-oldseg") == 0)
827 old_segment_mapping = 1;
828#ifdef DEBUG
829 else if (strcmp (*p, "-t") == 0)
830 d10v_debug = DEBUG;
831 else if (strncmp (*p, "-t", 2) == 0)
832 d10v_debug = atoi (*p + 2);
833#endif
834 }
835
836 /* put all the opcodes in the hash table */
837 if (!init_p++)
838 {
839 for (s = Simops; s->func; s++)
840 {
841 h = &hash_table[hash(s->opcode,s->format)];
842
843 /* go to the last entry in the chain */
844 while (h->next)
845 h = h->next;
846
847 if (h->ops)
848 {
849 h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
850 if (!h->next)
851 perror ("malloc failure");
852
853 h = h->next;
854 }
855 h->ops = s;
856 h->mask = s->mask;
857 h->opcode = s->opcode;
858 h->size = s->is_long;
859 }
860 }
861
862 /* reset the processor state */
863 if (!State.mem.data[0])
864 sim_size (1);
865
866 return sd;
867}
868
869uint8 *
870dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16 offset)
871{
872 unsigned long phys;
873 uint8 *mem;
874 int phys_size;
875
876 /* Note: DMEM address range is 0..0x10000. Calling code can compute
877 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
878 is uint16 this is modulo'ed onto 0x0e5d. */
879
880 phys_size = sim_d10v_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL,
881 dmap_register);
882 if (phys_size == 0)
883 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS);
884 mem = map_memory (sd, cpu, phys);
885#ifdef DEBUG
886 if ((d10v_debug & DEBUG_MEMORY))
887 {
888 sim_io_printf
889 (sd,
890 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
891 offset, last_from,
892 phys, phys_size, last_to,
893 (long) mem, last_segname);
894 }
895#endif
896 return mem;
897}
898
899uint8 *
900imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
901{
902 unsigned long phys;
903 uint8 *mem;
904 int phys_size = sim_d10v_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL,
905 imap_register);
906 if (phys_size == 0)
907 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS);
908 mem = map_memory (sd, cpu, phys);
909#ifdef DEBUG
910 if ((d10v_debug & DEBUG_MEMORY))
911 {
912 sim_io_printf
913 (sd,
914 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
915 offset, last_from,
916 phys, phys_size, last_to,
917 (long) mem, last_segname);
918 }
919#endif
920 return mem;
921}
922
923static void
924step_once (SIM_DESC sd, SIM_CPU *cpu)
925{
926 uint32 inst;
927 uint8 *iaddr;
928
929 /* TODO: Unindent this block. */
930 {
931 iaddr = imem_addr (sd, cpu, (uint32)PC << 2);
932
933 inst = get_longword( iaddr );
934
935 State.pc_changed = 0;
936 ins_type_counters[ (int)INS_CYCLES ]++;
937
938 switch (inst & 0xC0000000)
939 {
940 case 0xC0000000:
941 /* long instruction */
942 do_long (sd, cpu, inst & 0x3FFFFFFF);
943 break;
944 case 0x80000000:
945 /* R -> L */
946 do_2_short (sd, cpu, inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, RIGHT_FIRST);
947 break;
948 case 0x40000000:
949 /* L -> R */
950 do_2_short (sd, cpu, (inst & 0x3FFF8000) >> 15, inst & 0x7FFF, LEFT_FIRST);
951 break;
952 case 0:
953 do_parallel (sd, cpu, (inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
954 break;
955 }
956
957 /* If the PC of the current instruction matches RPT_E then
958 schedule a branch to the loop start. If one of those
959 instructions happens to be a branch, than that instruction
960 will be ignored */
961 if (!State.pc_changed)
962 {
963 if (PSW_RP && PC == RPT_E)
964 {
965 /* Note: The behavour of a branch instruction at RPT_E
966 is implementation dependant, this simulator takes the
967 branch. Branching to RPT_E is valid, the instruction
968 must be executed before the loop is taken. */
969 if (RPT_C == 1)
970 {
971 SET_PSW_RP (0);
972 SET_RPT_C (0);
973 SET_PC (PC + 1);
974 }
975 else
976 {
977 SET_RPT_C (RPT_C - 1);
978 SET_PC (RPT_S);
979 }
980 }
981 else
982 SET_PC (PC + 1);
983 }
984
985 /* Check for a breakpoint trap on this instruction. This
986 overrides any pending branches or loops */
987 if (PSW_DB && PC == IBA)
988 {
989 SET_BPC (PC);
990 SET_BPSW (PSW);
991 SET_PSW (PSW & PSW_SM_BIT);
992 SET_PC (SDBT_VECTOR_START);
993 }
994
995 /* Writeback all the DATA / PC changes */
996 SLOT_FLUSH ();
997 }
998}
999
1000void
1001sim_engine_run (SIM_DESC sd,
1002 int next_cpu_nr, /* ignore */
1003 int nr_cpus, /* ignore */
1004 int siggnal)
1005{
1006 sim_cpu *cpu;
1007
1008 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1009
1010 cpu = STATE_CPU (sd, 0);
1011
1012 switch (siggnal)
1013 {
1014 case 0:
1015 break;
1016 case GDB_SIGNAL_BUS:
1017 SET_BPC (PC);
1018 SET_BPSW (PSW);
1019 SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1020 JMP (AE_VECTOR_START);
1021 SLOT_FLUSH ();
1022 break;
1023 case GDB_SIGNAL_ILL:
1024 SET_BPC (PC);
1025 SET_BPSW (PSW);
1026 SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1027 JMP (RIE_VECTOR_START);
1028 SLOT_FLUSH ();
1029 break;
1030 default:
1031 /* just ignore it */
1032 break;
1033 }
1034
1035 while (1)
1036 {
1037 step_once (sd, cpu);
1038 if (sim_events_tick (sd))
1039 sim_events_process (sd);
1040 }
1041}
1042
1043void
1044sim_info (SIM_DESC sd, int verbose)
1045{
1046 char buf1[40];
1047 char buf2[40];
1048 char buf3[40];
1049 char buf4[40];
1050 char buf5[40];
1051 unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
1052 unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ];
1053 unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ];
1054 unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ];
1055 unsigned long left_total = left + left_parallel + left_cond + left_nops;
1056
1057 unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
1058 unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ];
1059 unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
1060 unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
1061 unsigned long right_total = right + right_parallel + right_cond + right_nops;
1062
1063 unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ];
1064 unsigned long ins_long = ins_type_counters[ (int)INS_LONG ];
1065 unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ];
1066 unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ];
1067 unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ];
1068 unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ];
1069 unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ];
1070 unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ];
1071 unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ];
1072 unsigned long total = (unknown + left_total + right_total + ins_long);
1073
1074 int size = strlen (add_commas (buf1, sizeof (buf1), total));
1075 int parallel_size = strlen (add_commas (buf1, sizeof (buf1),
1076 (left_parallel > right_parallel) ? left_parallel : right_parallel));
1077 int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
1078 int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
1079 int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
1080
1081 sim_io_printf (sd,
1082 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1083 size, add_commas (buf1, sizeof (buf1), left_total),
1084 normal_size, add_commas (buf2, sizeof (buf2), left),
1085 parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
1086 cond_size, add_commas (buf4, sizeof (buf4), left_cond),
1087 nop_size, add_commas (buf5, sizeof (buf5), left_nops));
1088
1089 sim_io_printf (sd,
1090 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1091 size, add_commas (buf1, sizeof (buf1), right_total),
1092 normal_size, add_commas (buf2, sizeof (buf2), right),
1093 parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
1094 cond_size, add_commas (buf4, sizeof (buf4), right_cond),
1095 nop_size, add_commas (buf5, sizeof (buf5), right_nops));
1096
1097 if (ins_long)
1098 sim_io_printf (sd,
1099 "executed %*s long instruction(s)\n",
1100 size, add_commas (buf1, sizeof (buf1), ins_long));
1101
1102 if (parallel)
1103 sim_io_printf (sd,
1104 "executed %*s parallel instruction(s)\n",
1105 size, add_commas (buf1, sizeof (buf1), parallel));
1106
1107 if (leftright)
1108 sim_io_printf (sd,
1109 "executed %*s instruction(s) encoded L->R\n",
1110 size, add_commas (buf1, sizeof (buf1), leftright));
1111
1112 if (rightleft)
1113 sim_io_printf (sd,
1114 "executed %*s instruction(s) encoded R->L\n",
1115 size, add_commas (buf1, sizeof (buf1), rightleft));
1116
1117 if (unknown)
1118 sim_io_printf (sd,
1119 "executed %*s unknown instruction(s)\n",
1120 size, add_commas (buf1, sizeof (buf1), unknown));
1121
1122 if (cond_true)
1123 sim_io_printf (sd,
1124 "executed %*s instruction(s) due to EXExxx condition being true\n",
1125 size, add_commas (buf1, sizeof (buf1), cond_true));
1126
1127 if (cond_false)
1128 sim_io_printf (sd,
1129 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1130 size, add_commas (buf1, sizeof (buf1), cond_false));
1131
1132 if (cond_jump)
1133 sim_io_printf (sd,
1134 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1135 size, add_commas (buf1, sizeof (buf1), cond_jump));
1136
1137 sim_io_printf (sd,
1138 "executed %*s cycle(s)\n",
1139 size, add_commas (buf1, sizeof (buf1), cycles));
1140
1141 sim_io_printf (sd,
1142 "executed %*s total instructions\n",
1143 size, add_commas (buf1, sizeof (buf1), total));
1144}
1145
1146SIM_RC
1147sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
1148 char * const *argv, char * const *env)
1149{
1150 bfd_vma start_address;
1151
1152 /* Make sure we have the right structure for the following memset. */
1153 static_assert (offsetof (struct _state, regs) == 0,
1154 "State.regs is not at offset 0");
1155
1156 /* Reset state from the regs field until the mem field. */
1157 memset (&State, 0, (uintptr_t) &State.mem - (uintptr_t) &State.regs);
1158
1159 /* There was a hack here to copy the values of argc and argv into r0
1160 and r1. The values were also saved into some high memory that
1161 won't be overwritten by the stack (0x7C00). The reason for doing
1162 this was to allow the 'run' program to accept arguments. Without
1163 the hack, this is not possible anymore. If the simulator is run
1164 from the debugger, arguments cannot be passed in, so this makes
1165 no difference. */
1166
1167 /* set PC */
1168 if (abfd != NULL)
1169 start_address = bfd_get_start_address (abfd);
1170 else
1171 start_address = 0xffc0 << 2;
1172#ifdef DEBUG
1173 if (d10v_debug)
1174 sim_io_printf (sd, "sim_create_inferior: PC=0x%" BFD_VMA_FMT "x\n",
1175 start_address);
1176#endif
1177 {
1178 SIM_CPU *cpu = STATE_CPU (sd, 0);
1179 SET_CREG (PC_CR, start_address >> 2);
1180 }
1181
1182 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
1183 initializes imap0 and imap1 to 0x1000 as part of its ROM
1184 initialization. */
1185 if (old_segment_mapping)
1186 {
1187 /* External memory startup. This is the HARD reset state. */
1188 set_imap_register (sd, 0, 0x0000);
1189 set_imap_register (sd, 1, 0x007f);
1190 set_dmap_register (sd, 0, 0x2000);
1191 set_dmap_register (sd, 1, 0x2000);
1192 set_dmap_register (sd, 2, 0x0000); /* Old DMAP */
1193 set_dmap_register (sd, 3, 0x0000);
1194 }
1195 else
1196 {
1197 /* Internal memory startup. This is the ROM intialized state. */
1198 set_imap_register (sd, 0, 0x1000);
1199 set_imap_register (sd, 1, 0x1000);
1200 set_dmap_register (sd, 0, 0x2000);
1201 set_dmap_register (sd, 1, 0x2000);
1202 set_dmap_register (sd, 2, 0x2000); /* DMAP2 initial internal value is
1203 0x2000 on the new board. */
1204 set_dmap_register (sd, 3, 0x0000);
1205 }
1206
1207 SLOT_FLUSH ();
1208 return SIM_RC_OK;
1209}
1210
1211static int
1212d10v_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
1213{
1214 SIM_DESC sd = CPU_STATE (cpu);
1215 int size;
1216 switch ((enum sim_d10v_regs) rn)
1217 {
1218 case SIM_D10V_R0_REGNUM:
1219 case SIM_D10V_R1_REGNUM:
1220 case SIM_D10V_R2_REGNUM:
1221 case SIM_D10V_R3_REGNUM:
1222 case SIM_D10V_R4_REGNUM:
1223 case SIM_D10V_R5_REGNUM:
1224 case SIM_D10V_R6_REGNUM:
1225 case SIM_D10V_R7_REGNUM:
1226 case SIM_D10V_R8_REGNUM:
1227 case SIM_D10V_R9_REGNUM:
1228 case SIM_D10V_R10_REGNUM:
1229 case SIM_D10V_R11_REGNUM:
1230 case SIM_D10V_R12_REGNUM:
1231 case SIM_D10V_R13_REGNUM:
1232 case SIM_D10V_R14_REGNUM:
1233 case SIM_D10V_R15_REGNUM:
1234 WRITE_16 (memory, GPR (rn - SIM_D10V_R0_REGNUM));
1235 size = 2;
1236 break;
1237 case SIM_D10V_CR0_REGNUM:
1238 case SIM_D10V_CR1_REGNUM:
1239 case SIM_D10V_CR2_REGNUM:
1240 case SIM_D10V_CR3_REGNUM:
1241 case SIM_D10V_CR4_REGNUM:
1242 case SIM_D10V_CR5_REGNUM:
1243 case SIM_D10V_CR6_REGNUM:
1244 case SIM_D10V_CR7_REGNUM:
1245 case SIM_D10V_CR8_REGNUM:
1246 case SIM_D10V_CR9_REGNUM:
1247 case SIM_D10V_CR10_REGNUM:
1248 case SIM_D10V_CR11_REGNUM:
1249 case SIM_D10V_CR12_REGNUM:
1250 case SIM_D10V_CR13_REGNUM:
1251 case SIM_D10V_CR14_REGNUM:
1252 case SIM_D10V_CR15_REGNUM:
1253 WRITE_16 (memory, CREG (rn - SIM_D10V_CR0_REGNUM));
1254 size = 2;
1255 break;
1256 case SIM_D10V_A0_REGNUM:
1257 case SIM_D10V_A1_REGNUM:
1258 WRITE_64 (memory, ACC (rn - SIM_D10V_A0_REGNUM));
1259 size = 8;
1260 break;
1261 case SIM_D10V_SPI_REGNUM:
1262 /* PSW_SM indicates that the current SP is the USER
1263 stack-pointer. */
1264 WRITE_16 (memory, spi_register ());
1265 size = 2;
1266 break;
1267 case SIM_D10V_SPU_REGNUM:
1268 /* PSW_SM indicates that the current SP is the USER
1269 stack-pointer. */
1270 WRITE_16 (memory, spu_register ());
1271 size = 2;
1272 break;
1273 case SIM_D10V_IMAP0_REGNUM:
1274 case SIM_D10V_IMAP1_REGNUM:
1275 WRITE_16 (memory, imap_register (sd, cpu, NULL, rn - SIM_D10V_IMAP0_REGNUM));
1276 size = 2;
1277 break;
1278 case SIM_D10V_DMAP0_REGNUM:
1279 case SIM_D10V_DMAP1_REGNUM:
1280 case SIM_D10V_DMAP2_REGNUM:
1281 case SIM_D10V_DMAP3_REGNUM:
1282 WRITE_16 (memory, dmap_register (sd, cpu, NULL, rn - SIM_D10V_DMAP0_REGNUM));
1283 size = 2;
1284 break;
1285 case SIM_D10V_TS2_DMAP_REGNUM:
1286 size = 0;
1287 break;
1288 default:
1289 size = 0;
1290 break;
1291 }
1292 return size;
1293}
1294
1295static int
1296d10v_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
1297{
1298 SIM_DESC sd = CPU_STATE (cpu);
1299 int size;
1300 switch ((enum sim_d10v_regs) rn)
1301 {
1302 case SIM_D10V_R0_REGNUM:
1303 case SIM_D10V_R1_REGNUM:
1304 case SIM_D10V_R2_REGNUM:
1305 case SIM_D10V_R3_REGNUM:
1306 case SIM_D10V_R4_REGNUM:
1307 case SIM_D10V_R5_REGNUM:
1308 case SIM_D10V_R6_REGNUM:
1309 case SIM_D10V_R7_REGNUM:
1310 case SIM_D10V_R8_REGNUM:
1311 case SIM_D10V_R9_REGNUM:
1312 case SIM_D10V_R10_REGNUM:
1313 case SIM_D10V_R11_REGNUM:
1314 case SIM_D10V_R12_REGNUM:
1315 case SIM_D10V_R13_REGNUM:
1316 case SIM_D10V_R14_REGNUM:
1317 case SIM_D10V_R15_REGNUM:
1318 SET_GPR (rn - SIM_D10V_R0_REGNUM, READ_16 (memory));
1319 size = 2;
1320 break;
1321 case SIM_D10V_CR0_REGNUM:
1322 case SIM_D10V_CR1_REGNUM:
1323 case SIM_D10V_CR2_REGNUM:
1324 case SIM_D10V_CR3_REGNUM:
1325 case SIM_D10V_CR4_REGNUM:
1326 case SIM_D10V_CR5_REGNUM:
1327 case SIM_D10V_CR6_REGNUM:
1328 case SIM_D10V_CR7_REGNUM:
1329 case SIM_D10V_CR8_REGNUM:
1330 case SIM_D10V_CR9_REGNUM:
1331 case SIM_D10V_CR10_REGNUM:
1332 case SIM_D10V_CR11_REGNUM:
1333 case SIM_D10V_CR12_REGNUM:
1334 case SIM_D10V_CR13_REGNUM:
1335 case SIM_D10V_CR14_REGNUM:
1336 case SIM_D10V_CR15_REGNUM:
1337 SET_CREG (rn - SIM_D10V_CR0_REGNUM, READ_16 (memory));
1338 size = 2;
1339 break;
1340 case SIM_D10V_A0_REGNUM:
1341 case SIM_D10V_A1_REGNUM:
1342 SET_ACC (rn - SIM_D10V_A0_REGNUM, READ_64 (memory) & MASK40);
1343 size = 8;
1344 break;
1345 case SIM_D10V_SPI_REGNUM:
1346 /* PSW_SM indicates that the current SP is the USER
1347 stack-pointer. */
1348 set_spi_register (READ_16 (memory));
1349 size = 2;
1350 break;
1351 case SIM_D10V_SPU_REGNUM:
1352 set_spu_register (READ_16 (memory));
1353 size = 2;
1354 break;
1355 case SIM_D10V_IMAP0_REGNUM:
1356 case SIM_D10V_IMAP1_REGNUM:
1357 set_imap_register (sd, rn - SIM_D10V_IMAP0_REGNUM, READ_16(memory));
1358 size = 2;
1359 break;
1360 case SIM_D10V_DMAP0_REGNUM:
1361 case SIM_D10V_DMAP1_REGNUM:
1362 case SIM_D10V_DMAP2_REGNUM:
1363 case SIM_D10V_DMAP3_REGNUM:
1364 set_dmap_register (sd, rn - SIM_D10V_DMAP0_REGNUM, READ_16(memory));
1365 size = 2;
1366 break;
1367 case SIM_D10V_TS2_DMAP_REGNUM:
1368 size = 0;
1369 break;
1370 default:
1371 size = 0;
1372 break;
1373 }
1374 SLOT_FLUSH ();
1375 return size;
1376}
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