MIPS: Add Octeon 3 support

[thirdparty/binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 0e9f716916eed7c4aa2953dcc58399381083851d..6e0299e25cebcefcfd63b6a181ebc7fc9fea6fa5 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -316,9 +316,10 @@ decode_mips_operand (const char *p)
 #define N5     (INSN_5400 | INSN_5500)
 #define N54    INSN_5400
 #define N55    INSN_5500
-#define IOCT   (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
-#define IOCTP  (INSN_OCTEONP | INSN_OCTEON2)
-#define IOCT2  INSN_OCTEON2
+#define IOCT   (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCTP  (INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCT2  (INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCT3  INSN_OCTEON3
 #define XLR     INSN_XLR
 #define IVIRT  ASE_VIRT
 #define IVIRT64        ASE_VIRT64
@@ -1496,11 +1497,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtlhx",              "s",            0x00000053, 0xfc1fffff, RD_1|MOD_HILO,          0,              0,              SMT,    0 },
 {"mtcr",               "t,s",          0x70000019, 0xfc00ffff, RD_1|RD_2,              0,              XLR,            0,      0 },
 {"mtm0",               "s",            0x70000008, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtm0",               "s,t",          0x70000008, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtm1",               "s",            0x7000000c, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtm1",               "s,t",          0x7000000c, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtm2",               "s",            0x7000000d, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtm2",               "s,t",          0x7000000d, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtp0",               "s",            0x70000009, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtp0",               "s,t",          0x70000009, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtp1",               "s",            0x7000000a, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtp1",               "s,t",          0x7000000a, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtp2",               "s",            0x7000000b, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtp2",               "s,t",          0x7000000b, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtsa",               "s",            0x00000029, 0xfc1fffff, RD_1,                   0,              EE,             0,      0 },
 {"mtsab",              "s,j",          0x04180000, 0xfc1f0000, RD_1,                   0,              EE,             0,      0 },
 {"mtsah",              "s,j",          0x04190000, 0xfc1f0000, RD_1,                   0,              EE,             0,      0 },