/* collection of junk waiting time to sort out
- Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1996-2024 Free Software Foundation, Inc.
Contributed by Cygnus Support.
-This file is part of the GNU Simulators.
+ This file is part of GDB, the GNU debugger.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef M32R_SIM_H
#define M32R_SIM_H
-/* gdb register numbers */
+#include "symcat.h"
+
+/* GDB register numbers. */
#define PSW_REGNUM 16
#define CBR_REGNUM 17
#define SPI_REGNUM 18
#define ACC1H_REGNUM 25
#define BBPSW_REGNUM 26
#define BBPC_REGNUM 27
+#define EVB_REGNUM 28
extern int m32r_decode_gdb_ctrl_regnum (int);
+/* The other cpu cores reuse m32rbf funcs to avoid duplication, but they don't
+ provide externs to access, and we can't e.g. include decode.h in decodex.h
+ because of all the redefinitions of cgen macros. */
+
+extern void m32rbf_model_insn_before (SIM_CPU *, int);
+extern void m32rbf_model_insn_after (SIM_CPU *, int, int);
+extern CPUREG_FETCH_FN m32rbf_fetch_register;
+extern CPUREG_STORE_FN m32rbf_store_register;
+extern UQI m32rbf_h_psw_get (SIM_CPU *);
+extern void m32rbf_h_psw_set (SIM_CPU *, UQI);
+extern UQI m32r2f_h_psw_get (SIM_CPU *);
+extern void m32r2f_h_psw_set (SIM_CPU *, UQI);
+extern UQI m32rxf_h_psw_get (SIM_CPU *);
+extern void m32rxf_h_psw_set (SIM_CPU *, UQI);
+extern void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
+extern void m32r2f_h_bpsw_set (SIM_CPU *, UQI);
+extern void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
+extern SI m32rbf_h_gr_get (SIM_CPU *, UINT);
+extern void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
+extern USI m32rbf_h_cr_get (SIM_CPU *, UINT);
+extern void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
+
/* Cover macros for hardware accesses.
FIXME: Eventually move to cgen. */
#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
-extern SI a_m32r_h_gr_get (SIM_CPU *, UINT);
-extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
-extern USI a_m32r_h_cr_get (SIM_CPU *, UINT);
-extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
-
-extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
+extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
+extern USI m32r2f_h_cr_get_handler (SIM_CPU *, UINT);
+extern void m32r2f_h_cr_set_handler (SIM_CPU *, UINT, USI);
+extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT);
+extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI);
+
+#ifndef GET_H_CR
+#define GET_H_CR(regno) \
+ XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
+#define SET_H_CR(regno, val) \
+ XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
+#endif
-extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
+extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
+extern UQI m32r2f_h_psw_get_handler (SIM_CPU *);
+extern void m32r2f_h_psw_set_handler (SIM_CPU *, UQI);
+extern UQI m32rxf_h_psw_get_handler (SIM_CPU *);
+extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI);
+
+#ifndef GET_H_PSW
+#define GET_H_PSW() \
+ XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
+#define SET_H_PSW(val) \
+ XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
+#endif
-extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
-extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
+/* FIXME: These prototypes are necessary because the cgen generated
+ cpu.h, cpux.h and cpu2.h headers do not provide them, and functions
+ which take or return parameters that are larger than an int must be
+ prototyed in order for them to work correctly.
+ The correct solution is to fix the code in cgen/sim.scm to generate
+ prototypes for each of the functions it generates. */
+extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
+extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
+extern DI m32r2f_h_accum_get_handler (SIM_CPU *);
+extern void m32r2f_h_accum_set_handler (SIM_CPU *, DI);
+extern DI m32rxf_h_accum_get_handler (SIM_CPU *);
+extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI);
+
+extern DI m32r2f_h_accums_get_handler (SIM_CPU *, UINT);
+extern void m32r2f_h_accums_set_handler (SIM_CPU *, UINT, DI);
+extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT);
+extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI);
+
+#ifndef GET_H_ACCUM
+#define GET_H_ACCUM() \
+ XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
+#define SET_H_ACCUM(val) \
+ XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
+#endif
\f
/* Misc. profile data. */
#define TRAP_SYSCALL 0
#define TRAP_BREAKPOINT 1
-/* Support for the MSPR register (Cache Purge Control Register)
- and the MCCR register (Cache Control Register) are needed in order for
- overlays to work correctly with the scache.
- MSPR no longer exists but is supported for upward compatibility with
- early overlay support. */
-
-/* Cache Purge Control (only exists on early versions of chips) */
-#define MSPR_ADDR 0xfffffff7
-#define MSPR_PURGE 1
-
-/* Lock Control Register (not supported) */
-#define MLCR_ADDR 0xfffffff7
-#define MLCR_LM 1
-
-/* Power Management Control Register (not supported) */
-#define MPMR_ADDR 0xfffffffb
-
-/* Cache Control Register */
-#define MCCR_ADDR 0xffffffff
-#define MCCR_CP 0x80
-/* not supported */
-#define MCCR_CM0 2
-#define MCCR_CM1 1
-
-/* Serial device addresses. */
-#ifdef M32R_EVA /* orig eva board, no longer supported */
-#define UART_INCHAR_ADDR 0xff102013
-#define UART_OUTCHAR_ADDR 0xff10200f
-#define UART_STATUS_ADDR 0xff102006
-/* Indicate ready bit is inverted. */
-#define UART_INPUT_READY0
-#else
-/* These are the values for the MSA2000 board.
- ??? Will eventually need to move this to a config file. */
-#define UART_INCHAR_ADDR 0xff004009
-#define UART_OUTCHAR_ADDR 0xff004007
-#define UART_STATUS_ADDR 0xff004002
-#endif
-
-#define UART_INPUT_READY 0x4
-#define UART_OUTPUT_READY 0x1
-
-/* Start address and length of all device support. */
-#define M32R_DEVICE_ADDR 0xff000000
-#define M32R_DEVICE_LEN 0x01000000
-
-/* sim_core_attach device argument. */
-extern device m32r_devices;
-
-/* FIXME: Temporary, until device support ready. */
-struct _device { int foo; };
-
/* Handle the trap insn. */
USI m32r_trap (SIM_CPU *, PCADDR, int);
+\f
+struct m32r_sim_cpu {
+ M32R_MISC_PROFILE m32r_misc_profile;
+#define CPU_M32R_MISC_PROFILE(cpu) (& M32R_SIM_CPU (cpu)->m32r_misc_profile)
+
+ /* CPU specific parts go here.
+ Note that in files that don't need to access these pieces WANT_CPU_FOO
+ won't be defined and thus these parts won't appear. This is ok in the
+ sense that things work. It is a source of bugs though.
+ One has to of course be careful to not take the size of this
+ struct and no structure members accessed in non-cpu specific files can
+ go after here. Oh for a better language. */
+#if defined (WANT_CPU_M32RBF)
+ M32RBF_CPU_DATA cpu_data;
+#endif
+#if defined (WANT_CPU_M32RXF)
+ M32RXF_CPU_DATA cpu_data;
+#elif defined (WANT_CPU_M32R2F)
+ M32R2F_CPU_DATA cpu_data;
+#endif
+};
+#define M32R_SIM_CPU(cpu) ((struct m32r_sim_cpu *) CPU_ARCH_DATA (cpu))
#endif /* M32R_SIM_H */
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