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Arm64: correct address index operands for LD1RO{H,W,D}
authorJan Beulich <jbeulich@suse.com>
Fri, 3 Jan 2020 09:16:44 +0000 (10:16 +0100)
committerJan Beulich <jbeulich@suse.com>
Fri, 3 Jan 2020 09:16:44 +0000 (10:16 +0100)
commit5437a02abc9fe106054965828787e8f232692935
tree4723e3eddeef436e20d15d44c109b0f1529db3batree | snapshot
parent567dfba2bed4bce68a13b0c8963dec9605dea6c8commit | diff
Arm64: correct address index operands for LD1RO{H,W,D}

Just like their LD1RQ{H,W,D} counterparts, as per the specification the
index registers get scaled by element size.
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