aarch64: Fix SVE2 register/immediate distinction

aarch64: Fix SVE2 register/immediate distinction

GAS refuses to interpret register names like x0 as unadorned
immediates, due to the obvious potential for confusion with
register operands.  (An explicit #x0 is OK.)

For compatibility reasons, we can't extend the set of registers
that GAS rejects for existing instructions.  For example:

   mov x0, z0

was valid code before SVE was added, so it needs to stay valid
code even when SVE is enabled.  But we can make GAS reject newer
registers in newer instructions.  The SVE instruction:

   and z0.s, z0.s, z0.h

is therefore invalid, rather than z0.h being an immediate.

This patch extends the SVE behaviour to SVE2.  The old call
to AARCH64_CPU_HAS_FEATURE was technically the wrong way around,
although it didn't matter in practice for base SVE instructions
since their avariants only set SVE.