[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallba...

[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch

This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX,
BFCSEL). These are the first instructions in ARM that have more than one
relocations in them.

This is the first infrastructure patch that adds a new bfd_reloc_code_real enum
for the fallback branch offset.
This is common for all such instructions and needs to be resolvable by the
assembler.

ChangeLog entries are as follows :
*** bfd/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

*** gas/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (md_pcrel_from_section): New switch case
	for BFD_RELOC_THUMB_PCREL_BRANCH5.
	(v8_1_branch_value_check): New function to check branch
	offsets.
	(md_appdy_fix): New switch case for
	BFD_RELOC_THUMB_PCREL_BRANCH5.
	(tc_gen_reloc): Likewise.

*** opcodes/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.