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(parent: ceae703) | patch
Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.
authorJim Wilson <jim.wilson@linaro.org>
Sun, 19 Feb 2017 21:16:56 +0000 (13:16 -0800)
committerJim Wilson <jim.wilson@linaro.org>
Sun, 19 Feb 2017 21:16:56 +0000 (13:16 -0800)
commit2e7e5e28909bcffe2267b417f9cff0441b576fba
treec2aac362b90239464de9622e1cbdecc7e58851f1tree | snapshot
parentceae703d41819c1f03e3250b6e6df64dc6e7d3ffcommit | diff
Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.

sim/aarch64/
* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
with type set to input type size.
(do_vec_xtl): Change bias from 3 to 4 for byte case.

sim/testsuite/sim/aarch64/
* bit.s: Change cmp immediates to account for addv bug fix.
* cmtst.s, ldn_single.s, stn_single.s: Likewise.
* xtl.s: New.
sim/aarch64/ChangeLog diff | blob | blame | history
sim/aarch64/simulator.c diff | blob | blame | history
sim/testsuite/sim/aarch64/ChangeLog diff | blob | blame | history
sim/testsuite/sim/aarch64/bit.s diff | blob | blame | history
sim/testsuite/sim/aarch64/cmtst.s diff | blob | blame | history
sim/testsuite/sim/aarch64/ldn_single.s diff | blob | blame | history
sim/testsuite/sim/aarch64/stn_single.s diff | blob | blame | history
sim/testsuite/sim/aarch64/xtl.s [new file with mode: 0644] blob
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