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author	Andrew Cagney <cagney@redhat.com>
	Mon, 8 Dec 1997 03:22:58 +0000 (03:22 +0000)
committer	Andrew Cagney <cagney@redhat.com>
	Mon, 8 Dec 1997 03:22:58 +0000 (03:22 +0000)
commit	bc6df23d1457c9c5e9616f737659d68d7fef6e50
tree	939e443924f25f220bb46be291d4b15852230d73	tree \| snapshot
parent	0a5875fc63c256f0daa9db6ed9a35257ab3db247	commit \| diff

For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping
through an exception may not work correctly.
For GDB reads/writes to the control registers, ensure the cpu state is
updated correctly.

sim/d10v/ChangeLog		diff \| blob \| blame \| history
sim/d10v/d10v_sim.h		diff \| blob \| blame \| history
sim/d10v/simops.c		diff \| blob \| blame \| history
sim/testsuite/d10v-elf/ChangeLog		diff \| blob \| blame \| history

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