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author	Mike Frysinger <vapier@gentoo.org>
	Fri, 12 Aug 2016 14:12:41 +0000 (22:12 +0800)
committer	Mike Frysinger <vapier@gentoo.org>
	Mon, 12 Apr 2021 04:14:32 +0000 (00:14 -0400)
commit	d5a71b1131778cf2a023855966831eb2457d50d6
tree	77243d6b326ca6dfa0ebb60446a9bc518b11617e	tree \| snapshot
parent	32d715691aa037f2838b41fa257c2e239d67c134	commit \| diff

sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code

Every arch handles this the same way, so move it to the common code.
This will also make unifying the sim_cpu structure easier.

57 files changed:

sim/aarch64/ChangeLog		diff \| blob \| blame \| history
sim/aarch64/interp.c		diff \| blob \| blame \| history
sim/arm/ChangeLog		diff \| blob \| blame \| history
sim/arm/wrapper.c		diff \| blob \| blame \| history
sim/avr/ChangeLog		diff \| blob \| blame \| history
sim/avr/interp.c		diff \| blob \| blame \| history
sim/bfin/ChangeLog		diff \| blob \| blame \| history
sim/bfin/interp.c		diff \| blob \| blame \| history
sim/bpf/ChangeLog		diff \| blob \| blame \| history
sim/bpf/sim-if.c		diff \| blob \| blame \| history
sim/common/ChangeLog		diff \| blob \| blame \| history
sim/common/sim-cpu.c		diff \| blob \| blame \| history
sim/common/sim-cpu.h		diff \| blob \| blame \| history
sim/cr16/ChangeLog		diff \| blob \| blame \| history
sim/cr16/interp.c		diff \| blob \| blame \| history
sim/cris/ChangeLog		diff \| blob \| blame \| history
sim/cris/sim-if.c		diff \| blob \| blame \| history
sim/d10v/ChangeLog		diff \| blob \| blame \| history
sim/d10v/interp.c		diff \| blob \| blame \| history
sim/example-synacor/ChangeLog		diff \| blob \| blame \| history
sim/example-synacor/interp.c		diff \| blob \| blame \| history
sim/frv/ChangeLog		diff \| blob \| blame \| history
sim/frv/sim-if.c		diff \| blob \| blame \| history
sim/ft32/ChangeLog		diff \| blob \| blame \| history
sim/ft32/interp.c		diff \| blob \| blame \| history
sim/h8300/ChangeLog		diff \| blob \| blame \| history
sim/h8300/compile.c		diff \| blob \| blame \| history
sim/iq2000/ChangeLog		diff \| blob \| blame \| history
sim/iq2000/sim-if.c		diff \| blob \| blame \| history
sim/lm32/ChangeLog		diff \| blob \| blame \| history
sim/lm32/sim-if.c		diff \| blob \| blame \| history
sim/m32r/ChangeLog		diff \| blob \| blame \| history
sim/m32r/sim-if.c		diff \| blob \| blame \| history
sim/m68hc11/ChangeLog		diff \| blob \| blame \| history
sim/m68hc11/interp.c		diff \| blob \| blame \| history
sim/mcore/ChangeLog		diff \| blob \| blame \| history
sim/mcore/interp.c		diff \| blob \| blame \| history
sim/microblaze/ChangeLog		diff \| blob \| blame \| history
sim/microblaze/interp.c		diff \| blob \| blame \| history
sim/mips/ChangeLog		diff \| blob \| blame \| history
sim/mips/interp.c		diff \| blob \| blame \| history
sim/mn10300/ChangeLog		diff \| blob \| blame \| history
sim/mn10300/interp.c		diff \| blob \| blame \| history
sim/moxie/ChangeLog		diff \| blob \| blame \| history
sim/moxie/interp.c		diff \| blob \| blame \| history
sim/msp430/ChangeLog		diff \| blob \| blame \| history
sim/msp430/msp430-sim.c		diff \| blob \| blame \| history
sim/or1k/ChangeLog		diff \| blob \| blame \| history
sim/or1k/sim-if.c		diff \| blob \| blame \| history
sim/pru/ChangeLog		diff \| blob \| blame \| history
sim/pru/interp.c		diff \| blob \| blame \| history
sim/riscv/ChangeLog		diff \| blob \| blame \| history
sim/riscv/interp.c		diff \| blob \| blame \| history
sim/sh/ChangeLog		diff \| blob \| blame \| history
sim/sh/interp.c		diff \| blob \| blame \| history
sim/v850/ChangeLog		diff \| blob \| blame \| history
sim/v850/interp.c		diff \| blob \| blame \| history

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