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(parent: fbd9e35) | patch
Fix right shifts in mcore simulator on 64 bit hosts.
authorJeff Law <jeffreyalaw@gmail.com>
Fri, 1 Dec 2023 14:19:50 +0000 (07:19 -0700)
committerJeff Law <jeffreyalaw@gmail.com>
Fri, 1 Dec 2023 14:19:50 +0000 (07:19 -0700)
commit37d6ee9350c68c1f9688eeb030e3585b548fec81
treed8d13ae34a82808e783fb42df6b80a08e476a066tree | snapshot
parentfbd9e35c5436108732575e82e78cc42be5ba52f5commit | diff
Fix right shifts in mcore simulator on 64 bit hosts.

If the value to be shifted has the sign bit set, the sign
bit would get copied into bits 32..63 of the temporary.  Those
would then be right shifted into the final value giving an
incorrect final result.

This was observed with upcoming GCC improvements which eliminate
unnecessary extensions.
sim/mcore/interp.c diff | blob | blame | history
sim/testsuite/mcore/lsr.s [new file with mode: 0644] blob
sim/testsuite/mcore/lsri.s [new file with mode: 0644] blob
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