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sim/riscv: Complete tidying up with SBREAK
authorTsukasa OI <research_trasio@irq.a4lg.com>
Sun, 4 Sep 2022 07:45:06 +0000 (07:45 +0000)
committerAndrew Burgess <aburgess@redhat.com>
Mon, 5 Sep 2022 08:42:06 +0000 (09:42 +0100)
commitb9593cb70533f28d276ab8d582dfe622aa4591d5
treee3222ab019a57858835bc10e4aa07d5fcf3d0573tree | snapshot
parent06c00d5feaf78869b42c28f9b5519c922a6dc765commit | diff
sim/riscv: Complete tidying up with SBREAK

This commit removes SBREAK-related references on the simulator as it's
renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1).

sim/ChangeLog:

* riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak".
sim/riscv/sim-main.c diff | blob | blame | history
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