Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and
handle the exclusion for any ISA levels properly in `opcode_is_member'.
Flatten the structure of the `if' statements there. No functional
change for the existing opcode tables.
include/
* opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA
exclusion.
(opcode_is_member): Handle ISA level exclusion.
MIPS/opcodes: Factor out ISA matching against flags
In preparation for the next change factor out code for ISA matching
against instruction flags used in MIPS opcode tables, similarly to how
CPU matching is already done. No functional change, though for clarity
split the single `if' statement into multiple ones and use temporaries
rather than repeated expressions.
include/
* opcode/mips.h (isa_is_member): New inline function, factored
out from...
(opcode_is_member): ... here.
MIPS/opcodes: Add legacy CP1 control register names
The two CP1 control registers defined by legacy ISAs used to be referred
to by various names, such as FCR0, FCR31, FSR, however their documented
full names have always been the Implementation and Revision, and Control
and Status respectively, so the FIR and FCSR acronyms coming from modern
ISA revisions will be just as unambiguous while improving the clarity of
disassembly. Do not update the TX39 though as it did not have an FPU.
opcodes/
* mips-dis.c (mips_cp1_names_mips): New variable.
(mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
"r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
"r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
"r12000", "r14000", "r16000", "mips5", "loongson2e", and
"loongson2f".
gas/
* testsuite/gas/mips/cp1-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
* testsuite/gas/mips/branch-misc-3.d: Update disassembly
according to changes to opcodes.
* testsuite/gas/mips/cp1-names-r3000.d: Likewise.
* testsuite/gas/mips/cp1-names-r4000.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips1.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips2.d: Likewise.
* testsuite/gas/mips/trunc.d: Likewise.
MIPS/GAS/testsuite: Add tests for coprocessor access instructions
Cover basic CP0, CP2, CP3 move, load and store instructions across the
relevant ISA levels. Omit CP0 move and CP1 instructions as they are
covered elsewhere.
gas/
* testsuite/gas/mips/cp0c.d: New test.
* testsuite/gas/mips/cp0m.d: New test.
* testsuite/gas/mips/r3900@cp0m.d: New test.
* testsuite/gas/mips/cp2.d: New test.
* testsuite/gas/mips/micromips@cp2.d: New test.
* testsuite/gas/mips/cp2m.d: New test.
* testsuite/gas/mips/mipsr6@cp2m.d: New test.
* testsuite/gas/mips/micromips@cp2m.d: New test.
* testsuite/gas/mips/cp2d.d: New test.
* testsuite/gas/mips/mipsr6@cp2d.d: New test.
* testsuite/gas/mips/micromips@cp2d.d: New test.
* testsuite/gas/mips/cp2-64.d: New test.
* testsuite/gas/mips/micromips@cp2-64.d: New test.
* testsuite/gas/mips/cp3.d: New test.
* testsuite/gas/mips/cp3m.d: New test.
* testsuite/gas/mips/cp3d.d: New test.
* testsuite/gas/mips/cp0c.s: New test source.
* testsuite/gas/mips/cp0m.s: New test source.
* testsuite/gas/mips/cp2.s: New test source.
* testsuite/gas/mips/cp2m.s: New test source.
* testsuite/gas/mips/cp2d.s: New test source.
* testsuite/gas/mips/cp2-64.s: New test source.
* testsuite/gas/mips/cp3.s: New test source.
* testsuite/gas/mips/cp3m.s: New test source.
* testsuite/gas/mips/cp3d.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/opcodes: Do not use CP0 register names for control registers
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
MIPS/binutils/testsuite: Fix XPA and Virtualization ASE cases
Fix commit 9785fc2a4d22 ("MIPS: Fix XPA base and Virtualization ASE
instruction handling") and explicitly use the `mips:3000' machine for
disassembly across the XPA base and XPA Virtualization ASE test cases,
providing actual coverage for the `virt' and `xpa' disassembler options
and removing failures for targets that default to those ASEs enabled:
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
This is because the test cases rely on these ASEs being disabled for
disassembly by default and expect instructions belonging to these ASEs
not to be shown unless explicitly enabled. The `mips-xpa-virt-4' test
case passes regardless, but we want it to verify the explicit options do
work, so use the `mips:3000' machine to set the defaults there as well.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Use `mips:3000'
machine for disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: Likewise.
In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154ba ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.
Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.
Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
and "mtthc2" to using the `G' rather than `g' operand code for
the coprocessor control register referred.
include/
* opcode/mips.h: Complement change made to opcodes and remove
references to the `g' regular MIPS ISA operand code.
microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1
The DMTC1 instruction operates on a floating-point general register as
its second operand, however in the disassembly of the microMIPS encoding
a floating-point control register is shown instead. This is due to an
incorrect ordering of the two "dmtc1" entries in the opcode table, which
gives precedence to one using the `G' aka coprocessor format over one
using the `S' or floating-point register format.
The coprocessor format, or OP_REG_COPRO, is used so that GAS supports
referring to FPRs by their numbers in assembly, such as $0, $1, etc.
however in the case of CP1/FPU it is also used by the disassembler to
decode those numbers to the names of corresponding control registers.
This in turn causes nonsensical disassembly such as:
dmtc1 a1,c1_fir
in a reference to $f0. It has been like this ever since microMIPS ISA
support has been added.
Correct the ordering of the two entries then by swapping them with each
other, making disassembly output consistent with the regular MIPS DMTC1
instruction as well all the remaining CP1 move instructions. Adjust all
the test cases affected accordingly.
opcodes/
* micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
entries with each other.
gas/
* testsuite/gas/mips/micromips.d: Update disassembly according
to "dmtc1" entry fix with opcodes.
* testsuite/gas/mips/micromips-compact.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
Fix an issue caused by commit f9419b056fe2 ("MIPS gas: code cleanup"),
<https://sourceware.org/ml/binutils/2002-05/msg00192.html>, and replace
the incorrect use of RA with the CFC1 and CTC1 instructions with FCSR.
While the register referred by its number is $31 in both cases, these
instructions operate on the floating-point control register file rather
than general-purpose registers.
gas/
* config/tc-mips.c (FCSR): New macro.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
H.J. Lu [Fri, 28 May 2021 16:34:10 +0000 (09:34 -0700)]
x86: Restore PC16 relocation overflow check
The x86-64 psABI has
---
A program or object file using R_X86_64_8, R_X86_64_16, R_X86_64_PC16
or R_X86_64_PC8 relocations is not conformant to this ABI, these
relocations are only added for documentation purposes.
---
Since x86 PC16 relocations have been used for 16-bit programs in an ELF32
or ELF64 container, PC16 relocation should wrap-around in 16-bit address
space. Revert
Simon Marchi [Thu, 27 May 2021 19:18:49 +0000 (15:18 -0400)]
gdb: fix tab after space indentation issues
I spotted some indentation issues where we had some spaces followed by
tabs at beginning of line, that I wanted to fix. So while at it, I did
a quick grep to find and fix all I could find.
gdb/ChangeLog:
* Fix tab after space indentation issues throughout.
Simon Marchi [Thu, 27 May 2021 19:01:28 +0000 (15:01 -0400)]
gdb: fix some indentation issues
I wrote a small script to spot a pattern of indentation mistakes I saw
happened in breakpoint.c. And while at it I ran it on all files and
fixed what I found. No behavior changes intended, just indentation and
addition / removal of curly braces.
Simon Marchi [Thu, 27 May 2021 18:58:37 +0000 (14:58 -0400)]
gdb: remove iterate_over_breakpoints function
Now that we have range functions that let us use ranged for loops, we
can remove iterate_over_breakpoints in favor of those, which are easier
to read and write. This requires exposing the declaration of
all_breakpoints and all_breakpoints_safe in breakpoint.h, as well as the
supporting types.
Change some users of iterate_over_breakpoints to use all_breakpoints,
when they don't need to delete the breakpoint, and all_breakpoints_safe
otherwise.
gdb/ChangeLog:
* breakpoint.h (iterate_over_breakpoints): Remove. Update
callers to use all_breakpoints or all_breakpoints_safe.
(breakpoint_range, all_breakpoints, breakpoint_safe_range,
all_breakpoints_safe): Move here.
* breakpoint.c (all_breakpoints, all_breakpoints_safe): Make
non-static.
(iterate_over_breakpoints): Remove.
* python/py-finishbreakpoint.c (bpfinishpy_detect_out_scope_cb):
Return void.
* python/py-breakpoint.c (build_bp_list): Add comment, reverse
return value logic.
* guile/scm-breakpoint.c (bpscm_build_bp_list): Return void.
for (bp_location *loc : all_bp_locations_at_addr (address))
{
// use loc
}
The all_bp_locations_at_addr returns a bp_locations_at_addr_range
object, which is really just a wrapper around two std::vector iterators
representing the beginning and end of the interesting range. These
iterators are found when constructing the bp_locations_at_addr_range
object using std::equal_range, which seems a perfect fit for this use
case.
One thing I noticed about the current ALL_BP_LOCATIONS_AT_ADDR is that
if you call it with a NULL start variable, that variable gets filled in
and can be re-used for subsequent iterations. This avoids the cost of
finding the start of the interesting range again for the subsequent
iterations. This happens in build_target_command_list, for example.
The same effect can be achieved by storing the range in a local
variable, it can be iterated on multiple times.
Note that the original comment over ALL_BP_LOCATIONS_AT_ADDR says:
Iterates through locations with address ADDRESS for the currently
selected program space.
I don't see anything restricting the iteration to a given program space,
as we iterate over all bp_locations, which as far as I know contains all
breakpoint locations, regardless of the program space. So I just
dropped that part of the comment.
gdb/ChangeLog:
* breakpoint.c (get_first_locp_gte_addr): Remove.
(ALL_BP_LOCATIONS_AT_ADDR): Remove. Replace all uses with
all_bp_locations_at_addr.
(struct bp_locations_at_addr_range): New.
(all_bp_locations_at_addr): New.
(bp_locations_compare_addrs): New.
Simon Marchi [Thu, 27 May 2021 18:58:37 +0000 (14:58 -0400)]
gdb: add all_bp_locations function
Add the all_bp_locations function to replace the ALL_BP_LOCATIONS macro.
For simplicity, all_bp_locations simply returns a const reference to the
bp_locations vector. But the callers just treat it as a range to
iterate on, so if we ever change the breakpoint location storage, we can
change the all_bp_locations function to return some other range type,
and the callers won't need to be changed.
gdb/ChangeLog:
* breakpoint.c (ALL_BP_LOCATIONS): Remove, update users to use
all_bp_locations.
(all_bp_locations): New.
Simon Marchi [Thu, 27 May 2021 18:58:37 +0000 (14:58 -0400)]
gdb: make bp_locations an std::vector
Change the type of the global location list, bp_locations, to be an
std::vector.
Adjust the users to deal with that, mostly in an obvious way by using
.data() and .size(). The user where it's slightly less obvious is
update_global_location_list. There, we std::move the old location list
out of the global vector into a local variable. The code to fill the
new location list gets simpler, as it's now simply using .push_back(),
no need to count the locations beforehand.
In the rest of update_global_location_list, the code is adjusted to work
with indices instead of `bp_location **`, to iterate on the location
list. I believe it's a bit easier to understand this way. But more
importantly, when we build with _GLIBCXX_DEBUG, the operator[] of the
vector does bound checking, so we will know if we ever access past a
vector size (which we won't if we access by raw pointer). I think that
work can further be done to make that function easier to understand,
notably find better names than "loc" and "loc2" for variables, but
that's work for later.
gdb/ChangeLog:
* breakpoint.c (bp_locations): Change to std::vector, update all
users.
(bp_locations_count): Remove.
(update_global_location_list): Change to work with indices
rather than bp_location**.
Simon Marchi [Thu, 27 May 2021 18:58:36 +0000 (14:58 -0400)]
gdb: add all_tracepoints function
Same idea as the previous patches, but to replace the ALL_TRACEPOINTS
macro. Define a new filtered_iterator that only keeps the breakpoints
for which is_tracepoint returns true (just like the macro did).
I would have like to make it so tracepoint_range yields some
`tracepoint *` instead of some `breakpoint *`, that would help simplify
the callers, who wouldn't have to do the cast themselves. But I didn't
find an obvious way to do it. It can always be added later.
It turns out there is already an all_tracepoints function, which returns
a vector containing all the breakpoints that are tracepoint. Remove it,
most users will just work seamlessly with the new function. The
exception is start_tracing, which iterated multiple times on the vector.
Adapt this one so it iterates multiple times on the returned range.
Since the existing users of all_tracepoints are outside of breakpoint.c,
this requires defining all_tracepoints and a few supporting types in
breakpoint.h. So, move breakpoint_iterator from breakpoint.c to
breakpoint.h.
Simon Marchi [Thu, 27 May 2021 18:58:36 +0000 (14:58 -0400)]
gdb: add all_breakpoints_safe function
Same as the previous patch, but intended to replace the
ALL_BREAKPOINTS_SAFE macro, which allows deleting the current breakpoint
while iterating. The new range type simply wraps the range added by the
previous patch with basic_safe_range.
I didn't remove the ALL_BREAKPOINTS_SAFE macro, because there is one
spot where it's more tricky to remove, in the
check_longjmp_breakpoint_for_call_dummy function. More thought it
needed for this one.
gdb/ChangeLog:
* breakpoint.c (breakpoint_safe_range): New.
(all_breakpoints_safe): New. Use instead of
ALL_BREAKPOINTS_SAFE where possible.
Simon Marchi [Thu, 27 May 2021 18:58:36 +0000 (14:58 -0400)]
gdb: add all_breakpoints function
Introduce the all_breakpoints function, which returns a range that can
be used to iterate on breakpoints. Replace all uses of the
ALL_BREAKPOINTS macro with this.
In one instance, I could replace the breakpoint iteration with a call to
get_breakpoint.
gdb/ChangeLog:
* breakpoint.c (ALL_BREAKPOINTS): Remove, replace all uses with
all_breakpoints.
(breakpoint_iterator): New.
(breakpoint_range): New.
(all_breakpoints): New.
Hannes Domani [Sun, 22 Nov 2020 15:51:30 +0000 (16:51 +0100)]
Add optional full_window argument to TuiWindow.write
To prevent flickering when first calling erase, then write, this new
argument indicates that the passed string contains the full contents of
the window. This fills every unused cell of the window with a space, so
it's not necessary to call erase beforehand.
Simon Marchi [Thu, 27 May 2021 17:59:01 +0000 (13:59 -0400)]
gdb: add option to reverse order of _initialize function calls
An earlier patch in this series fixed a dependency problem between two
_initialize functions. That problem was uncovered by reversing the
order of the initialize function calls.
In short, symtab.c tried to add the alias "maintenance
flush-symbol-cache" for the command "maintenance flush symbol-cache".
Because the "maintenance flush" prefix command was not yet created (it
happens in maint.c, initialized later in this reversed order), the
add_alias_cmd function returned NULL. That result was passed to
deprecate_cmd, which didn't expected that value, and that caused a
segfault. This was fixed by changing alias creation functions to take
the target command as a cmd_list_element, instead of by name.
This patch adds a runtime option to reverse the order of the initialize
calls at will. I chose to use an environment variable for this, over a
parameter (even a "maintenance" one), because:
- The init functions are called before the early init commands are
executed, so we could use -iex to turn this mode on early enough.
This is obvious when you remember that commands / parameters are
created by initialize funcitions :).
- This is not something anybody would want to tweak after startup
anyway.
gdb/ChangeLog:
* make-init-c: Add option to reverse function calls.
Simon Marchi [Thu, 27 May 2021 17:59:01 +0000 (13:59 -0400)]
gdb: add make-init-c script
I would like to modify how the init.c file is generated (its content).
But as it is, a shell script with multiple sed invocations in a Makefile
target, it's not very maintainable. Replace that with a shell script
that does the same, but in a more readable way.
The Makefile rule uses the "-" prefix in front of the for loop, I
presume to ignore any error coming from the fact that xml-builtin.c and
cp-name-parser.c are not found in the srcdir (they are generated source
files). I prefer not to blindly ignore errors, so filter these files
out of INIT_FILES instead (we already filter out other files).
There are no expected meaningful changes to the generated init.c file.
Just the _initialize_all_file declaration that is moved down and "void"
in parenthesis that is removed.
The new regular expression is a bit tighter than the existing one, it
requires the init function to be followed by exactly ` ()`. Update
bpf-tdep.c accordingly.
gdb/ChangeLog:
* Makefile.in (INIT_FILES_FILTER_OUT): New.
(INIT_FILES): Use INIT_FILES_FILTER_OUT.
(stamp-init): Use make-init-c.
* bpf-tdep.c (_initialize_bpf_tdep): Remove "void".
* silent-rules.mk (ECHO_INIT_C): Change.
* make-init-c: New file.
Simon Marchi [Thu, 27 May 2021 17:59:01 +0000 (13:59 -0400)]
gdb: remove add_alias_cmd overload that accepts a string
Same idea as previous patch, but for add_alias_cmd. Remove the overload
that accepts the target command as a string (the target command name),
leaving only the one that takes the cmd_list_element.
gdb/ChangeLog:
* command.h (add_alias_cmd): Accept target as
cmd_list_element. Update callers.
Simon Marchi [Thu, 27 May 2021 17:59:01 +0000 (13:59 -0400)]
gdb: make add_com_alias accept target as a cmd_list_element
The alias creation functions currently accept a name to specify the
target command. They pass this to add_alias_cmd, which needs to lookup
the target command by name.
Given that:
- We don't support creating an alias for a command before that command
exists.
- We always use add_info_alias just after creating that target command,
and therefore have access to the target command's cmd_list_element.
... change add_com_alias to accept the target command as a
cmd_list_element (other functions are done in subsequent patches). This
ensures we don't create the alias before the target command, because you
need to get the cmd_list_element from somewhere when you call the alias
creation function. And it avoids an unecessary command lookup. So it
seems better to me in every aspect.
gdb/ChangeLog:
* command.h (add_com_alias): Accept target as
cmd_list_element. Update callers.
Simon Marchi [Thu, 27 May 2021 17:59:00 +0000 (13:59 -0400)]
gdb/python: use return values of add_setshow functions in add_setshow_generic
In add_setshow_generic, we create set/show commands using add_setshow_*
functions, then look up the commands by name to set the context pointer.
It would be simpler and more efficient to use the return values of the
add_setshow_* functions, do that.
gdb/ChangeLog:
* python/py-param.c (add_setshow_generic): Use return values of
add_setshow functions.
Simon Marchi [Thu, 27 May 2021 17:59:00 +0000 (13:59 -0400)]
gdb: make add_setshow commands return set_show_commands
Some add_set_show commands return a single cmd_list_element, the one for
the "set" command. A subsequent patch will need to access the show
command's cmd_list_element as well. Change these functions to return a
new structure type that holds both pointers.
I initially only modified add_setshow_boolean_cmd (the one I needed),
but I think it's better to change the whole chain to keep everything in
sync.
Tom de Vries [Thu, 27 May 2021 13:22:38 +0000 (15:22 +0200)]
[gdb/symtab] Fix segfault in process_psymtab_comp_unit
When running test-case gdb.dwarf2/dw2-dummy-cu.exp without -readnow, we run
into:
...
(gdb) file outputs/gdb.dwarf2/dw2-dummy-cu/dw2-dummy-cu^M
Reading symbols from outputs/gdb.dwarf2/dw2-dummy-cu/dw2-dummy-cu...^M
ERROR: Couldn't load dw2-dummy-cu into GDB (eof).
...
The problem is that we're running into a segfault:
...
Thread 1 "gdb" received signal SIGSEGV, Segmentation fault.
process_psymtab_comp_unit (this_cu=0x2141090, per_objfile=0x1aa4140,
want_partial_unit=false, pretend_language=language_minimal)
at /home/vries/gdb_versions/devel/src/gdb/dwarf2/read.c:7023
7023 switch (reader.comp_unit_die->tag)
...
due to reader.comp_unit_die == nullptr:
...
(gdb) p reader.comp_unit_die
$1 = (die_info *) 0x0
...
Indeed, there's no CU DIE in the test-case:
...
$ readelf -wi outputs/gdb.dwarf2/dw2-dummy-cu/dw2-dummy-cu
Contents of the .debug_info section:
Tom de Vries [Thu, 27 May 2021 13:22:38 +0000 (15:22 +0200)]
[gdb/testsuite] Prevent proc override in gdb-index.exp
When running these two test-cases in this specific order we get:
...
$ make check 'RUNTESTFLAGS=gdb.dwarf2/gdb-index.exp \
gdb.dwarf2/gdb-add-index-symlink.exp'
...
Running gdb.dwarf2/gdb-index.exp ...
Running gdb.dwarf2/gdb-add-index-symlink.exp ...
FAIL: gdb.dwarf2/gdb-add-index-symlink.exp: gdb-index file created
FAIL: gdb.dwarf2/gdb-add-index-symlink.exp: Unable to call \
gdb-add-index with a symlink to a symfile
...
The problem is that gdb-index.exp introduces a proc add_gdb_index which
overrides the one in lib/gdb.exp and stays active after the test is done.
Consequently it's used in gdb-add-index-symlink.exp, which should use the one
from lib/gdb.exp.
Fix this by renaming proc add_gdb_index in gdb-index.exp.
Tom de Vries [Thu, 27 May 2021 13:22:38 +0000 (15:22 +0200)]
[gdb/symtab] Fix Dwarf Error: cannot find DIE
When loading the debug info package
libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug from openSUSE Leap 15.2, we
run into a dwarf error:
...
$ gdb -q -batch libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug
Dwarf Error: Cannot not find DIE at 0x18a936e7 \
[from module libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug]
...
The DIE @ 0x18a936e7 does in fact exist, and is part of a CU @ 0x18a23e52.
No error message is printed when using -readnow.
What happens is the following:
- a dwarf2_per_cu_data P is created for the CU.
- a dwarf2_cu A is created for the same CU.
- another dwarf2_cu B is created for the same CU.
- the dwarf2_cu B is set in per_objfile->m_dwarf2_cus, such that
per_objfile->get_cu (P) returns B.
- P->load_all_dies is set to 1.
- all dies are read into the A->partial_dies htab
- dwarf2_cu A is destroyed.
- we try to find the partial_die for the DIE @ 0x18a936e7 in B->partial_dies.
We can't find it, but do not try to load all dies, because P->load_all_dies
is already set to 1.
- an error message is generated.
The question is why we're creating dwarf2_cu A and B for the same CU.
The dwarf2_cu A is created here:
...
(gdb) bt
#0 dwarf2_cu::dwarf2_cu (this=0x79a9660, per_cu=0x23c0b30,
per_objfile=0x1ad01b0) at dwarf2/cu.c:38
#1 0x0000000000675799 in cutu_reader::cutu_reader (this=0x7fffffffd040,
this_cu=0x23c0b30, per_objfile=0x1ad01b0, abbrev_table=0x0,
existing_cu=0x0, skip_partial=false) at dwarf2/read.c:6487
#2 0x0000000000676eb3 in process_psymtab_comp_unit (this_cu=0x23c0b30,
per_objfile=0x1ad01b0, want_partial_unit=false,
pretend_language=language_minimal) at dwarf2/read.c:7028
...
And the dwarf2_cu B is created here:
...
(gdb) bt
#0 dwarf2_cu::dwarf2_cu (this=0x885e8c0, per_cu=0x23c0b30,
per_objfile=0x1ad01b0) at dwarf2/cu.c:38
#1 0x0000000000675799 in cutu_reader::cutu_reader (this=0x7fffffffcc50,
this_cu=0x23c0b30, per_objfile=0x1ad01b0, abbrev_table=0x0,
existing_cu=0x0, skip_partial=false) at dwarf2/read.c:6487
#2 0x0000000000678118 in load_partial_comp_unit (this_cu=0x23c0b30,
per_objfile=0x1ad01b0, existing_cu=0x0) at dwarf2/read.c:7436
#3 0x000000000069721d in find_partial_die (sect_off=(unknown: 0x18a55054),
offset_in_dwz=0, cu=0x0) at dwarf2/read.c:19391
#4 0x000000000069755b in partial_die_info::fixup (this=0x9096900,
cu=0xa6a85f0) at dwarf2/read.c:19512
#5 0x0000000000697586 in partial_die_info::fixup (this=0x8629bb0,
cu=0xa6a85f0) at dwarf2/read.c:19516
#6 0x00000000006787b1 in scan_partial_symbols (first_die=0x8629b40,
lowpc=0x7fffffffcf58, highpc=0x7fffffffcf50, set_addrmap=0, cu=0x79a9660)
at dwarf2/read.c:7563
#7 0x0000000000678878 in scan_partial_symbols (first_die=0x796ebf0,
lowpc=0x7fffffffcf58, highpc=0x7fffffffcf50, set_addrmap=0, cu=0x79a9660)
at dwarf2/read.c:7580
#8 0x0000000000676b82 in process_psymtab_comp_unit_reader
(reader=0x7fffffffd040, info_ptr=0x7fffc1b3f29b, comp_unit_die=0x6ea90f0,
pretend_language=language_minimal) at dwarf2/read.c:6954
#9 0x0000000000676ffd in process_psymtab_comp_unit (this_cu=0x23c0b30,
per_objfile=0x1ad01b0, want_partial_unit=false,
pretend_language=language_minimal) at dwarf2/read.c:7057
...
So in frame #9, a cutu_reader is created with dwarf2_cu A. Then a fixup takes
us to the following CU @ 0x18aa33d6, in frame #5. And a similar fixup in
frame #4 takes us back to CU @ 0x18a23e52. At that point, there's no
information available that we're already trying to read that CU, and we end up
creating another cutu_reader with dwarf2_cu B.
It seems that there are two related problems:
- creating two dwarf2_cu's is not optimal
- the unoptimal case is not handled correctly
This patch addresses the last problem, by moving the load_all_dies flag from
dwarf2_per_cu_data to dwarf2_cu, such that it is paired with the partial_dies
field, which ensures that the two can be kept in sync.
Simon Marchi [Thu, 27 May 2021 03:31:29 +0000 (23:31 -0400)]
Revert "gdb: change dwarf_die_debug to bool"
This was wrong: dwarf_die_debug is used as an integer, for example where
it is passed to dump_die. It is documented in the command's help, which
I missed the first time.
to indicate that 16-bit mode instructions are used in the object to
allow linker to properly perform relocation overflow check for 16-bit
PC-relative relocations in 16-bit mode instructions.
1. Update x86 assembler to always generate the GNU property note with
GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object.
2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if
input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16.
bfd/
PR ld/27905
* elf32-i386.c: Include "libiberty.h".
(elf_howto_table): Add 16-bit R_386_PC16 entry.
(elf_i386_rtype_to_howto): Add a BFD argument. Use 16-bit
R_386_PC16 if input has 16-bit mode instructions.
(elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto
call.
(elf_i386_tls_transition): Likewise.
(elf_i386_relocate_section): Likewise.
* elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit
R_X86_64_PC16 entry.
(elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input
has 16-bit mode instructions.
* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set
elf_x86_has_code16 if relocatable input is marked with
GNU_PROPERTY_X86_FEATURE_2_CODE16.
* elfxx-x86.h (elf_x86_obj_tdata): Add has_code16.
(elf_x86_has_code16): New.
binutils/
PR ld/27905
* readelf.c (decode_x86_feature_2): Support
GNU_PROPERTY_X86_FEATURE_2_CODE16.
gas/
PR ld/27905
* config/tc-i386.c (set_code_flag): Update x86_feature_2_used
with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF
object.
(set_16bit_gcc_code_flag): Likewise.
(x86_cleanup): Always generate the GNU property note if
x86_feature_2_used isn't 0.
* testsuite/gas/i386/code16-2.d: New file.
* testsuite/gas/i386/code16-2.s: Likewise.
* testsuite/gas/i386/x86-64-code16-2.d: Likewise.
* testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2.
Simon Marchi [Wed, 26 May 2021 13:27:54 +0000 (09:27 -0400)]
gdb: don't zero-initialize reg_buffer contents
The reg_buffer constructor zero-initializes (value-initializes, in C++
speak) the gdb_bytes of the m_registers array. This is not necessary,
as these bytes are only meaningful if the corresponding register_status
is REG_VALID. If the corresponding register_status is REG_VALID, then
they will have been overwritten with the actual register data when
reading the registers from the system into the reg_buffer.
Fix that by removing the empty parenthesis following the new expression,
meaning that the bytes will now be default-initialized, meaning they'll
be left uninitialized. For reference, this is explained here:
These new expressions were added in 835dcf92618e ("Use std::unique_ptr
in reg_buffer"). As mentioned in that commit message, the use of
value-initialisation was done on purpose to keep existing behavior, but
now there is some data that suggest it would be beneficial not to do it,
which is why I suggest changing it.
This doesn't make a big difference on typical architectures where the
register buffer is not that big. However, on ROCm (AMD GPU), the
register buffer is about 65000 bytes big, so the reg_buffer constructor
shows up in profiling. If you want to make some tests and profile it on
a standard system, it's always possible to change:
- m_registers.reset (new gdb_byte[m_descr->sizeof_raw_registers] ());
+ m_registers.reset (new gdb_byte[65000] ());
and run a program that constantly hits a breakpoint with a false
condition. For example, by doing this change and running the following
program:
static void break_here () {}
int main ()
{
for (int i = 0; i < 100000; i++)
break_here ();
}
with the following GDB incantation:
/usr/bin/time ./gdb -nx --data-directory=data-directory -q test -ex "b break_here if 0" -ex r -batch
Tom Tromey [Wed, 26 May 2021 13:02:51 +0000 (07:02 -0600)]
Introduce htab_delete_entry
In a bigger series I'm working on, it is convenient to have a
libiberty hash table that manages objects allocated with 'new'. To
make this simpler, I wrote a small template function to serve as a
concise wrapper. Then I realized that this could be reused in a few
other places.
gdb/ChangeLog
2021-05-26 Tom Tromey <tom@tromey.com>
* dwarf2/read.c (allocate_type_unit_groups_table)
(handle_DW_AT_stmt_list, allocate_dwo_file_hash_table): Use
htab_delete_entry.
(free_line_header_voidp): Remove.
* completer.c
(completion_tracker::completion_hash_entry::deleter): Remove.
(completion_tracker::discard_completions): Use htab_delete_entry.
* utils.h (htab_delete_entry): New template function.
Nelson Chu [Wed, 26 May 2021 02:34:13 +0000 (10:34 +0800)]
RISC-V: Allow to link the objects with unknown prefixed extensions.
Since the policies of GNU and llvm toolchain are different for now,
current binutils mainline cannot accept any draft extensions, including
rvv, zfh, .... The Clang/LLVM allows these draft stuff on mainline,
but the GNU ld might be used with them, so this causes the link time
problems.
The patch allows ld to link the objects with unknown prefixed extensions,
which are probably generated by LLVM or customized toolchains.
bfd/
* elfxx-riscv.h (check_unknown_prefixed_ext): New bool.
* elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the
prefixed extension name if check_unknown_prefixed_ext is false.
* elfnn-riscv.c (riscv_merge_arch_attr_info): Set
check_unknown_prefixed_ext to false for linker.
gas/
* config/tc-riscv.c (riscv_set_arch): Set
check_unknown_prefixed_ext to true for assembler.
Tamar Christina [Tue, 25 May 2021 15:04:04 +0000 (16:04 +0100)]
Arm: Fix forward thumb references [PR gas/25235]
When assembling a forward reference the symbol will be unknown and so during
do_t_adr we cannot set the thumb bit. The bit it set so early to prevent
relaxations that are invalid. i.e. relaxing a Thumb2 to Thumb1 insn when the
symbol is Thumb.
But because it's done so early we miss the case for forward references.
This patch changes it so that we additionally check the thumb bit during the
internal relocation processing.
In principle we should be able to only set the bit during reloc processing but
that would require changes to the other relocations that the instruction could
be relaxed to.
This approach still allows early relaxations (which means that we have less
iteration of internal reloc processing) while still fixing the forward reference
case.
gas/ChangeLog:
2021-05-24 Tamar Christina <tamar.christina@arm.com>
PR gas/25235
* config/tc-arm.c (md_convert_frag): Set LSB when Thumb symbol.
(relax_adr): Thumb symbols 4 bytes.
* testsuite/gas/arm/pr25235.d: New test.
* testsuite/gas/arm/pr25235.s: New test.
Alan Modra [Tue, 25 May 2021 05:36:49 +0000 (15:06 +0930)]
[GOLD] PR27815, gold fails to build with latest GCC
Don't use nullptr, it requires -std=c++11 on versions of gcc prior to
6.1. It would be possible to arrange to pass -std=c++11 automatically
when required (top level configure does that for gcc builds) but that
seems overkill and since we're not up-to-date on the top level config
files would mean someone would need to sync those over.
PR gold/27815
* gc.h (gc_process_relocs): Use cast in Section_id constructor.
I exposed a problem with the change in commit 574ec1084d to the outer
loop of _bfd_elf_parse_attributes. "p_end - p >= 4" is better than
"p < p_end - 4" as far as pointer UB is concerned if the size of the
attritbute section is say, 3 bytes. However you do need to ensure p
never exceeds p_end, and that length remaining is kept consistent with
the pointer.
* elf-attrs.c (elf_attr_strdup): New function.
(_bfd_elf_attr_strdup): Use it here.
(elf_add_obj_attr_string): New function, extracted from..
(bfd_elf_add_obj_attr_string): ..here.
(elf_add_obj_attr_int_string): New function, extracted from..
(bfd_elf_add_obj_attr_int_string): ..here.
(_bfd_elf_parse_attributes): Don't allocate an extra byte for a
string terminator. Instead ensure parsing doesn't go past
end of sub-section. Use size_t variables for lengths.
Mike Frysinger [Wed, 19 May 2021 01:54:36 +0000 (21:54 -0400)]
opcodes: cris: move desc & opc files from sim/
All other cgen ports keep their generated desc & opc files under
opcodes/, so move the cris files over too. The cris-opc.c file,
while not generated, is already here to complement.
MAINTAINERS: Update path to readline config.{sub,guess} files
Complement commit 6999161a2a3b ("Move readline to the readline/readline
subdirectory") and update the path to readline config.{sub,guess} files
documented in MAINTAINERS.
* MAINTAINERS: Update path to readline config.{sub,guess} files.
Update config.sub and config.guess for MIPS R3 and R5 ISA support
Complement commit ae52f4830604 ("Add MIPS r3 and r5 support.") and get
changes for config.sub to recognize MIPS CPU patterns for the R3 and R5
ISA levels, used by GAS to set defaults in gas/configure.ac. Oddly, R6
ISA support has been correctly added already.
/
* config.guess: Import from upstream.
* config.sub: Likewise.
readline/
* readline/support/config.guess: Import from upstream.
* readline/support/config.sub: Likewise.
Andrew Burgess [Fri, 21 May 2021 15:26:40 +0000 (16:26 +0100)]
gdb/doc: add '@:' after 'e.g.' to help texinfo
Add '@:' after 'e.g.' to let texinfo know that this is not the end of
a sentence. This is only needed when there's a space immediately
after the last '.'.
gdb/doc/ChangeLog:
* gdb.texi (Initialization Files): Add '@:' after 'e.g.'.
(Source Path): Likewise.
(GDB/MI Development and Front Ends): Likewise.
(ARM Features): Likewise.
(gdb man): Likewise.
Nelson Chu [Fri, 21 May 2021 07:40:33 +0000 (15:40 +0800)]
RISC-V: PR25212, Report errors for invalid march and mabi combinations.
This patch clarify the following invalid combinations of march and mabi,
* ilp32f/lp64f abi without f extension.
* ilp32d/lp64d abi without d extension.
* ilp32q/lp64q abi without q extension.
* e extension with any abi except ilp32e
GNU assembler reports errors when finding the above invalid combinations.
But LLVM-MC reports warnings and ignores these invalid cases. It help to
set the correct ilp32/lp64/ilp32e abi according to rv32/rv64/rve. This
looks good and convenient, so perhaps we can do the same things. However,
if you don't set the mabi, GNU assembler also try to set the suitable
ABI according to march/elf-attribute. Compared to LLVM-MC, we will choose
double/quad abi if d/f extension is set.
gas/
PR 25212
* config/tc-riscv.c (riscv_set_abi_by_arch): If -mabi isn't set, we
will choose ilp32e abi for rv32e. Besides, report errors for the
invalid march and mabi combinations.
* testsuite/gas/riscv/mabi-attr-rv32e.s: New testcase. Only accept
ilp32e abi for rve extension.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64f.d: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.d: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
Renamed all mabi testcases to their march-mabi settings.
Mike Frysinger [Mon, 24 May 2021 03:27:40 +0000 (23:27 -0400)]
sim: cris: fix memory setup typos
The cleanup to use BFD_VMA_FMT also adjusted this line, but used the
incorrect format: while BFD_VMA_FMT needs an explicit "x", PRIx32 does
not, so the spurious "x" here confused the parser and broke execution.
Mike Frysinger [Mon, 24 May 2021 02:15:01 +0000 (22:15 -0400)]
sim: bfin: fix the otp fix
I misread the code and thought data0/... were bu64 when they were
actually bu32. Fix the call to assemble the 2 64-bit values instead
of passing the 2 halves of the first 64-bit value.
Mike Frysinger [Mon, 24 May 2021 01:35:32 +0000 (21:35 -0400)]
sim: bfin: fix build warnings w/newer gcc
The bfin_otp_write_page_val func wants a pointer to an bu64[2] array,
but this code passes it a pointer to a single bu64. It's in a struct
with a known compatible layout:
bu64 data0, data1, data2, data3;
But gcc doesn't allow these kinds of tricks anymore. Use the more
verbose form to make the compiler happy since this is not performance
sensitive code.
Tom de Vries [Sun, 23 May 2021 08:08:45 +0000 (10:08 +0200)]
[gdb/tdep] Use pid to choose process 64/32-bitness
In a linux kernel mailing list discussion, it was mentioned that "gdb has
this odd thing where it takes the 64-bit vs 32-bit data for the whole process
from one thread, and picks the worst possible thread to do it (ie explicitly
not even the main thread, ...)" [1].
The picking of the thread is done here in
x86_linux_nat_target::read_description:
...
/* GNU/Linux LWP ID's are process ID's. */
tid = inferior_ptid.lwp ();
if (tid == 0)
tid = inferior_ptid.pid (); /* Not a threaded program. */
...
To understand what this code does, let's investigate a scenario in which
inferior_ptid.lwp () != inferior_ptid.pid ().
Say we start exec jit-attach-pie, identified with pid x. The main thread
starts another thread that sleeps, and then the main thread waits for the
sleeping thread. So we have two threads, identified with LWP IDs x and x+1:
...
PID LWP CMD
x x ./jit-attach-pie
x x+1 ./jit-attach-pie
...
[ The thread with LWP x is known as the thread group leader. ]
When attaching to this exec using the pid, gdb does a stop_all_threads which
iterates over all the threads, first LWP x, and then LWP x+1.
So the state we arrive with at x86_linux_nat_target::read_description is:
...
(gdb) p inferior_ptid
$1 = {m_pid = x, m_lwp = x+1, m_tid = 0}
...
and consequently we probe 64/32-bitness from thread LWP x+1.
[ Note that this is different from when gdb doesn't attach but instead
launches the exec itself, in which case there's just one thread to begin with,
and consequently the probed thread is LWP x. ]
According to aforementioned remark, a better choice would have been the main
thread, that is, LWP x.
This patch implement that choice, by simply doing:
...
tid = inferior_ptid.pid ();
...
The fact that gdb makes a per-process permanent choice for 64/32-bitness is a
problem in itself: each thread can be in either 64 or 32 bit mode, and change
forth and back. That is a problem that this patch doesn't fix.
Now finally: why does this matter in the context of the linux kernel
discussion? The discussion was related to a patch that exposed io_uring
threads to user-space. This made it possible that one of those threads would
be picked out to select 64/32-bitness. Given that such threads are atypical
user-space threads in the sense that they don't return to user-space and don't
have a userspace register state, reading their registers returns garbage, and
so it could f.i. occur that in a 64-bit process with all normal user-space
threads in 64-bit mode, the probing would return 32-bit.
It may be that this is worked-around on the kernel side by providing userspace
register state in those threads such that current gdb is happy. Nevertheless,
it seems prudent to fix this on the gdb size as well.
Chenghua Xu [Sun, 23 May 2021 02:16:36 +0000 (10:16 +0800)]
elf: Use official name LoongArch for EM_LOONGARCH.
The official name for Loongson Architecture is LoongArch, it is better
to use LoongArch instead of Loongson Loongarch for EM_LOONGARCH to avoid
confusion and keep consistent with the various of software in the future.
The official documentation in Chinese:
http://www.loongson.cn/uploadfile/cpu/LoongArch.pdf
The translated version in English:
https://loongson.github.io/LoongArch-Documentation/
binutils/
* readelf.c (get_machine_name): Change Loongson Loongarch to
LoongArch.
include/
* elf/common.h (EM_LOONGARCH): Change Loongson Loongarch to
LoongArch.
Alan Modra [Fri, 21 May 2021 13:04:34 +0000 (22:34 +0930)]
bfd dwarf2 sanity checking
This patch is aimed at the many places in dwarf2.c that blindly
increment a data pointer after calling functions that are meant to
read a fixed number of bytes. The problem with that is with damaged
dwarf we might increment a data pointer past the end of data, which is
UB and complicates (ie. bugs likely) any further use of that data
pointer. To fix those problems, I've moved incrementing of the data
pointer into the functions that do the reads. _bfd_safe_read_leb128
gets the same treatment for consistency.
* libbfd.c (_bfd_safe_read_leb128): Remove length_return parameter.
Replace data pointer with pointer to pointer. Increment pointer
over bytes read.
* libbfd-in.h (_bfd_safe_read_leb128): Update prototype.
* elf-attrs.c (_bfd_elf_parse_attributes): Adjust to suit. Be
careful not to increment data pointer past end. Remove now
redundant pr17512 check.
* wasm-module.c (READ_LEB128): Adjust to suit changes to
_bfd_safe_read_leb128.
* dwarf2.c (read_n_bytes): New inline function, old one renamed to..
(read_blk): ..this. Allocate and return block. Increment bfd_byte**
arg.
(read_3_bytes): New function.
(read_1_byte, read_1_signed_byte, read_2_bytes, read_4_bytes),
(read_8_bytes, read_string, read_indirect_string),
(read_indirect_line_string, read_alt_indirect_string): Take a
byte_byte** arg which is incremented over bytes read. Remove any
bytes_read return. Rewrite limit checks to compare lengths
rather than pointers.
(read_abbrevs, read_attribute_value, read_formatted_entries),
(decode_line_info, find_abstract_instance, read_ranges),
(read_rnglists, scan_unit_for_symbols, parse_comp_unit),
(stash_comp_unit): Adjust to suit. Rewrite limit checks to
compare lengths rather than pointers.
* libbfd.h: Regenerate.
Alan Modra [Wed, 19 May 2021 22:49:00 +0000 (08:19 +0930)]
[GOLD] PR27815, gold fails to build with latest GCC
...gold/gc.h:250:37: error: ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second: [-Werror]
250 | (*secvec).push_back(Section_id(NULL, 0));
| ^~~~~~~~~~~~~~~~~~~
PR gold/27815
* gc.h (gc_process_relocs): Use nullptr in Section_id constructor.
sim: mips: Add shadow mappings for 32-bit memory address space
32-bit MIPS programs run on the 64-bit simulator model in 64-bit
sign-extended space. The mapping from 64-bit sign-extended addresses to
32-bit addresses was removed by commit 26f8bf63bf36f9062a5cc1afacf71462a4abe0c8, breaking the 64-bit simulator
model. Add shadow mappings from 64-bit sign extended address space to
32-bit address spaces, in lieu of the AddressTranslation function.
sim: mips: Only truncate sign extension bits for 32-bit target models
64-bit BFD for MIPS applies a standard sign extension on all addresses
assuming 64-bit target. These bits are required for 64-bit and can only
be safely truncated for 32-bit target models. This partially reverts commit b36d953bced0a4fecdde1823abac70ed7038ee95
The sign-extension logic modeled by BFD is an integral part of the
MIPS64 architecture spec. It appears in the virtual address map, where
sign extension allows for 32-bit compatibility segments [1] with 64-bit
addressing. Truncating these addresses prematurely (commit
models (-DWITH_TARGET_WORD_BITSIZE=64).
In the ISA itself, direct addressing (Load-Upper-Immediate) and indirect
addressing (Load-Word) both automatically sign-extend their results. These
instructions regenerate the sign-extended addresses even if we don't start
with one (see pr gdb/19447).
Moreover, some instructions like ADD*/SUB* have unpredictable behaviour when
an operand is not correctly sign extended [3]. This affects PC-relative
addressing in particular, so arithmetic on the link-address generated in the
return address register by a jump-and-link is no longer possible, neither is
the use of the PC-relative addressing instructions provided by MIPSR6.
[1] "MIPS64 Architecture for Programmers Volume III: The MIPS64
Privileged Resource Architecture", Document Number: MD00091,
Revision 6.02, December 10, 2015, Section 4.3 "Virtual Address
Spaces", pp. 29-31
https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00091-2B-MIPS64PRA-AFP-06.03.pdf
[2] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Document Number: MD00087,
Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical
List of Instructions", pp. 321
https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf
[3] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Document Number: MD00087,
Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical
List of Instructions", pp. 56
https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf
John Baldwin [Sat, 22 May 2021 00:26:24 +0000 (17:26 -0700)]
sim/d10v: Use offsetof in a static assertion about structure layout.
clang 11 fails to compile the static assertion as it cannot compute
the pointer value at a compile time:
gdb/sim/d10v/interp.c:1149:37: error: static_assert expression is not an integral constant expression
static_assert ((uintptr_t) &State == (uintptr_t) &State.regs,
~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
Instead, assert that the offset of State.regs is 0.
sim/d10v/ChangeLog:
* interp.c (sim_create_inferior): Use offsetof in static
assertion.
testsuite/gdb.dwarf2: avoid dead code in dw2-inline-with-lexical-scope.c
The test in gdb.dwarf2/dw2-inline-with-lexical-scope.c fails with icc.
The reason is, icc did not emit code for a dead statement, which in
turn caused some labels to be collapsed. Fix this by replacing the
dead code with assignment to a global value. The statement itself
does not change the test scenario.
Also fix a whitespacing problem around an assignment operator.
gdb/testsuite/ChangeLog:
2021-05-21 Tankut Baris Aktemur <tankut.baris.aktemur@intel.com>
* gdb.dwarf2/dw2-inline-with-lexical-scope.c (func): Replace
a dead code with an assignment to a global var. Fix a
whitespacing problem around an assignment operator.
Tom de Vries [Fri, 21 May 2021 13:09:14 +0000 (15:09 +0200)]
[gdb/breakpoint] Fix assert in jit_event_handler
Consider a minimal test-case test.c:
...
int main (void) { return 0; }
...
which we can compile into llvm byte code using clang:
...
$ clang -g -S -emit-llvm --target=x86_64-unknown-unknown-elf test.c
...
and then run using lli, which uses the llvm jit:
...
$ lli test.ll
...
If we run this under gdb, we run into an assert:
...
$ gdb -q -batch -ex run --args /usr/bin/lli test.ll
Dwarf Error: Cannot not find DIE at 0x18a936e7 \
[from module libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug]
When running jit_breakpoint_re_set_internal, we first handle
libLLVM.so.10.debug, and set a jit breakpoint.
Next we handle libLLVM.so.10:
...
(gdb) p the_objfile.original_name
$42 = 0x2494170 "libLLVM.so.10"
...
but the minimal symbols we find are from libLLVM.so.10.debug:
...
(gdb) p reg_symbol.objfile.original_name
$43 = 0x38e7c50 "libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug"
(gdb) p desc_symbol.objfile.original_name
$44 = 0x38e7c50 "libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug"
...
and consequently, the objf_data is the one from libLLVM.so.10.debug:
...
jiter_objfile_data *objf_data
= get_jiter_objfile_data (reg_symbol.objfile);
...
and so we hit this:
...
if (objf_data->cached_code_address == addr)
continue;
...
and no second jit breakpoint is inserted.
Subsequently, the jit breakpoint is triggered and handled, but when finding
the symbol for the breakpoint address we get:
...
(gdb) p jit_bp_sym.objfile.original_name
$52 = 0x2494170 "libLLVM.so.10"
...
The assert 'jiter->jiter_data != nullptr' triggers because it checks
libLLVM.so.10 while the one with jiter_data setup is libLLVM.so.10.debug.
This fixes the assert:
...
jiter_objfile_data *objf_data
- = get_jiter_objfile_data (reg_symbol.objfile);
- = get_jiter_objfile_data (the_objfile);
...
but consequently we'll have two jit breakpoints, so we also make sure we don't
set a jit breakpoint on separate debug objects like libLLVM.so.10.debug.
Tested on x86_64-linux.
gdb/ChangeLog:
2021-05-21 Tom de Vries <tdevries@suse.de>
PR breakpoint/27889
* jit.c (jit_breakpoint_re_set_internal): Skip separate debug
objects. Call get_jiter_objfile_data with the_objfile.
cli-script: use unique_ptr to not leak next struct
In cli/cli-script.c, process_next_line() allocates memory
which will eventually end up being assigned to the 'next'
field in struct command_line. However, in a case
recurse_read_control_structure returns 'invalid_control'
this memory is leaked. This commit uses std::unique_ptr
as appropriate to prevent this leakage.
This issue was found by coverity scanning.
gdb/ChangeLog:
* cli/cli-script.h (command_line_up): New unique_ptr typedef.
* cli/cli-script.c (multi_line_command_p): Use unique_ptr
command_line_up instead of struct command_line.
(build_command_line): Likewise.
(get_command_line): Update the cmd function call parameter.
(process_next_line): Use unique_ptr command_line_up instead
of struct command_line.
(recurse_read_control_structure): Change the the type of
next to command_line_up.
(read_command_lines_1): Change type of `next' to be
command_line_up and update all references of `next'
accordingly.
Sergey Belyashov [Thu, 20 May 2021 15:14:10 +0000 (16:14 +0100)]
Fix overflow detection in the Z80 assembler.
* config/tc-z80.c (emit_data_val): Warn on constant overflow.
(signed_overflow): New function.
(unsigned_overflow): New function.
(is_overflow): Use new functions.
(md_apply_fix): Use signed_overflow.
* testsuite/gas/z80/ez80_adl_suf.d: Fix test.
* testsuite/gas/z80/ez80_isuf.s: Likewise.
* testsuite/gas/z80/ez80_z80_suf.d: Likewise.
Andrew Burgess [Thu, 20 May 2021 08:16:41 +0000 (09:16 +0100)]
gdb/bfd: avoid crash when architecture is forced to csky or riscv
I built GDB with `--enable-targets=all`, then started GDB passing it
an x86-64 executable, finally I ran 'maint selftest', and observed GDB
crash like this:
We end up in here because during the selftests GDB forces the
architecture to be csky, but the BFD being accessed is still of type
x86-64. As a result obj_attrs_section returns NULL, which means we
end up passing NULL to bfd_get_section_by_name. If we follow the
function calls from bfd_get_section_by_name we eventually end up in
bfd_hash_hash, which asserts that the string (i.e. the name) is not
NULL.
The same crash can be reproduced in GDB without using the selftests,
for example:
(gdb) file x86_64.elf
(gdb) start
(gdb) set architecture csky
(gdb) disassemble main
Dump of assembler code for function main:
BFD: BFD (GNU Binutils) 2.36.50.20210519 assertion fail ../../src/bfd/hash.c:438
Aborted (core dumped)
The fix I propose here is to have bfd_get_section_by_name return NULL
if name is ever NULL. For consistency I updated
bfd_get_section_by_name_if in the same way, even though I'm not
hitting any problems along that code path right now.
I looked through the source tree and removed two NULL checks in
bfd/dwarf2.c which are no longer needed, its possible that there are
additional NULL checks that could be removed, I just didn't find them.
bfd/ChangeLog:
* section.c (bfd_get_section_by_name): Return NULL if name is
NULL.
(bfd_get_section_by_name_if): Likewise.
* dwarf2.c (read_section): Remove unneeded NULL check.
(find_debug_info): Likewise.
Tom de Vries [Thu, 20 May 2021 11:58:35 +0000 (13:58 +0200)]
sim: ppc: fix Wpointer-sign warning
When compiling with --enable-werror and CFLAGS="-O0 -g -Wall", we run into:
...
src/sim/ppc/hw_memory.c: In function 'hw_memory_init_address':
src/sim/ppc/hw_memory.c:194:75: error: pointer targets in passing \
argument 4 of 'device_find_integer_array_property' differ in signedness \
[-Werror=pointer-sign]
int nr_cells
= device_find_integer_array_property(me, "available", 0, &dummy);
^
...
Will Schmidt [Thu, 20 May 2021 01:11:57 +0000 (20:11 -0500)]
[PATCH]rs6000,testsuite Add a powerpc64-prologue testcase.
Add a powerpc64-prologue testcase, this is based on the existing
powerpc-prologue test, but updated for the powerpc64 (le) target.
YYYY-MM-DD Will Schmidt <will_schmidt@vnet.ibm.com>
gcc/testsuite/ChangeLog
* gdb.arch/powerpc64-prologue.c: New test to exercise prologues
for the powerpc64 LE target.
* gdb.arch/powerpc-prologue.exp: Test Harness.
projects / thirdparty / binutils-gdb.git / log
