Tom Tromey [Tue, 1 Jun 2021 14:11:30 +0000 (08:11 -0600)]
Always build 'all' in gdb/testsuite
gdb's Makefile currently excludes testsuite from the subdirectories to
build. I don't think there's a good reason for this, so this patch
adds testsuite to the SUBDIRS list and removes a special case from
'all'.
gdb/ChangeLog
2021-06-01 Tom Tromey <tromey@adacore.com>
Tom Tromey [Tue, 1 Jun 2021 14:11:30 +0000 (08:11 -0600)]
Remove gdb/testsuite/configure
I didn't see a strong reason to have a separate configure script in
gdb/testsuite, so this patch removes it. The few relevant configury
bits are moved into gdb's configure script. Some of the old
testsuite/configure script (e.g., the header check) is dead code.
This also adds a Makefile rule to rebuild lib/pdtrace. This was
missing from the old code.
'read1' is now a dependency of check-read1, rather than extra code at
configure time.
Finally, the old "ENABLE_LIBCTF" subst in gdb/configure was not used;
nor was the variable defined, so this was always empty. However, the
lower-case variant was used by the testsuite, so this patch renames
the subst.
gdb/ChangeLog
2021-06-01 Tom Tromey <tromey@adacore.com>
* configure.ac: Copy some code from testsuite/configure.ac.
(enable_libctf): Subst this, not ENABLE_LIBCTF.
* configure: Rebuild.
gdb/testsuite/ChangeLog
2021-06-01 Tom Tromey <tromey@adacore.com>
* aclocal.m4, configure.ac, configure: Remove.
* Makefile.in (EXTRA_RULES): Remove.
($(abs_builddir)/site.exp site.exp): Don't depend on
config.status.
(distclean maintainer-clean realclean, Makefile): Update.
(config.status): Remove target.
(lib/pdtrace): New target.
(all): Don't depend on EXTRA_RULES.
(check-read1): Depend on read1.so, expect-read1.
Tom de Vries [Tue, 1 Jun 2021 13:25:51 +0000 (15:25 +0200)]
[gdb/symtab] Ignore cold clones
Consider the test-case contained in this patch, compiled for c using gcc-10:
...
$ gcc-10 -x c src/gdb/testsuite/gdb.cp/cold-clone.cc -O2 -g -Wall -Wextra
...
When setting a breakpoint on foo, we get one breakpoint location:
...
$ gdb -q -batch a.out -ex "b foo"
Breakpoint 1 at 0x400560: file cold-clone.cc, line 28.
...
However, when we compile for c++ instead, we get two breakpoint locations:
...
$ gdb -q -batch a.out -ex "b foo" -ex "info break"
Breakpoint 1 at 0x400430: foo. (2 locations)
Num Type Disp Enb Address What
1 breakpoint keep y <MULTIPLE>
1.1 y 0x0000000000400430 in foo() at cold-clone.cc:30
1.2 y 0x0000000000400560 in foo() at cold-clone.cc:28
...
The additional breakpoint location at 0x400430 corresponds to the cold clone:
...
$ nm a.out | grep foo 0000000000400560 t _ZL3foov 0000000000400430 t _ZL3foov.cold
...
which demangled looks like this:
...
$ nm -C a.out | grep foo 0000000000400560 t foo() 0000000000400430 t foo() [clone .cold]
...
[ Or, in the case of the cc1 mentioned in PR23710:
...
$ nm cc1 | grep do_rpo_vn.*cold 000000000058659d t \
_ZL9do_rpo_vnP8functionP8edge_defP11bitmap_headbb.cold.138
$ nm -C cc1 | grep do_rpo_vn.*cold 000000000058659d t \
do_rpo_vn(function*, edge_def*, bitmap_head*, bool, bool) [clone .cold.138]
... ]
The cold clone is a part of the function that is split off from the rest of
the function because it's considered cold (not frequently executed). So while
the symbol points to code that is part of a function, it doesn't point to a
function entry, so the desirable behaviour for "break foo" is to ignore this
symbol.
When compiling for c, the symbol "foo.cold" is entered as minimal symbol
with the search name "foo.cold", and the lookup using "foo" fails to find that
symbol.
But when compiling for c++, the symbol "foo.cold" is entered as minimal symbol
with both the mangled and demangled name, and for the demangled name
"foo() [clone .cold]" we get the search name "foo" (because
cp_search_name_hash stops hashing at '('), and the lookup using "foo" succeeds.
Fix this by recognizing the cold clone suffix and returning false for such a
minimal symbol in msymbol_is_function.
Tested on x86_64-linux.
gdb/ChangeLog:
2021-06-01 Tom de Vries <tdevries@suse.de>
PR symtab/26096
* minsyms.c (msymbol_is_cold_clone): New function.
(msymbol_is_function): Use msymbol_is_cold_clone.
gdb/testsuite/ChangeLog:
2021-06-01 Tom de Vries <tdevries@suse.de>
PR symtab/26096
* gdb.cp/cold-clone.cc: New test.
* gdb.cp/cold-clone.exp: New file.
Andrew Burgess [Thu, 20 May 2021 13:09:22 +0000 (14:09 +0100)]
gdb: run 'maint selftest' with an executable loaded
I spotted that 'maint selftest' with an executable loaded into GDB,
would (when GDB was compiled for all targets) crash GDB. I fixed this
with a commit to bfd:
gdb/bfd: avoid crash when architecture is forced to csky or riscv
However, this issue was not spotted as we currently only run 'maint
selftest' without an executable loaded.
This commit extends the testsuite to run 'maint selftest' both with
and without an executable loaded into GDB.
Currently, when no executable is loaded into GDB all of the selftest
pass (i.e. the fail count is 0), however, when running with an
executable loaded, I am seeing 1 failure (on an x86-64 GNU/Linux
host).
This failure is from the ARM disassembler tests, it appears that the
disassembler somehow gets itself into a state where it thinks it is in
thumb mode; when running the same test without an executable loaded
this doesn't happen.
This commit doesn't fix the ARM disassembler issue, but I thought it
was worth adding this anyway, as this will spot if GDB again starts to
crash when 'maint selftest' is run.
gdb/testsuite/ChangeLog:
* gdb.gdb/unittest.c: New file.
* gdb.gdb/unittest.exp: Run with and without a binary file loaded
into GDB.
Compared to the version linked above this version is updated to take
account of recent changes to the core dump infrastructure in GDB,
there is now more shared infrastructure for core dumping within GDB,
and also some common bare metal core dumping infrastructure. As a
result this patch is smaller than the original proposed patch.
Further, the original patch included some unrelated changes to the
simulator that have been removed from this version.
I have written a ChangeLog entry as the original patch was missing
one.
I have done absolutely no testing of this patch. It is based on the
original submitted patch, which I assume was tested, but after my
modifications things might have been broken, however, the original
patch author has tested this version and reported it as being good:
The core dump format is based around generating an ELF containing
sections for the writable regions of memory that a user could be
using. Which regions are dumped rely on GDB's existing common core
dumping code, GDB will attempt to figure out the stack and heap as
well as copying out writable data sections as identified by the
original ELF.
Register information is added to the core dump using notes, just as it
is for Linux of FreeBSD core dumps. The note types used consist of
the 2 basic types you would expect in a OS based core dump,
NT_PRPSINFO, NT_PRSTATUS, along with the architecture specific
NT_ARM_VFP note.
The data layouts for each note type are described below, in all cases,
all padding fields should be set to zero.
Field 'fname' - null terminated string consisting of the basename of
(up to the fist 15 characters of) the executable. Any additional
space should be set to zero. If there's no executable name then
this field can be set to all zero.
Field 'psargs' - a null terminated string up to 80 characters in
length. Any additional space should be filled with zero. This
field contains the full executable path and any arguments passed
to the executable. If there's nothing sensible to write in this
field then fill it with zero.
Field 'sig' - the signal that stopped this thread. It's implementation
defined what this field actually means. Within GDB this will be
the signal number that the remote target reports as the stop
reason for this thread.
Field 'thread_is' - the thread id for this thread. It's implementation
defined what this field actually means. Within GDB this will be
thread thread-id that is assigned to each remote thread.
Field 'gregs' - holds the general purpose registers $a1 through to $pc
at indices 0 to 15. At index 16 the program status register.
Index 17 should be set to zero.
Note NT_ARM_VFP is optional, its data layout is:
armvfp_t
{
uint64_t regs[32];
uint32_t fpscr;
}
Field 'regs' - holds the 32 d-registers 0 to 31 in order.
Field 'fpscr' - holds the fpscr register.
The rules for ordering the notes is the same as for Linux. The
NT_PRSTATUS note must come before any other notes about additional
register sets. And for multi-threaded targets all registers for a
single thread should be grouped together. This is because only
NT_PRSTATUS includes a thread-id, all additional register notes after
a NT_PRSTATUS are assumed to belong to the same thread until a
different NT_PRSTATUS is seen.
* GDB detects that the longjmp has completed, stops, and enters
check_longjmp_breakpoint_for_call_dummy (in breakpoint.c), and
* GDB tries to unwind the stack in order to check that the dummy
frame (setup for the inferior call) is still on the stack, but
* The unwind fails, possibly due to missing debug information, so
* GDB incorrectly concludes that the inferior has longjmp'd past the
dummy frame, and so deletes the dummy frame, including the dummy
frame breakpoint, but then
* The inferior continues, and eventually returns to the dummy frame,
which is usually (always?) on the stack, the inferior starts
trying to execute the random contents of the stack, this results
in undefined behaviour.
This situation is already warned about in the comment on the function
check_longjmp_breakpoint_for_call_dummy where we say:
You should call this function only at places where it is safe to currently
unwind the whole stack. Failed stack unwind would discard live dummy
frames.
The warning here is fine, the problem is that, even though we call the
function from a location within GDB where we hope to be able to
unwind, sometime the state of the inferior means that the unwind will
not succeed.
This commit tries to improve the situation by adding the following
additional check; when GDB fails to find the dummy frame on the stack,
instead of just assuming that the dummy frame can be garbage
collected, first find the stop_reason for the last frame on the stack.
If this stop_reason indicates that the stack unwinding may have failed
then we assume that the dummy frame is still in use. However, if the
last frame's stop_reason indicates that the stack unwind completed
successfully then we can be confident that the dummy frame is no
longer in use, and we garbage collect it.
Tested on x86-64 GNU/Linux.
gdb/ChangeLog:
* breakpoint.c (check_longjmp_breakpoint_for_call_dummy): Add
check for why the backtrace stopped.
gdb/testsuite/ChangeLog:
* gdb.base/premature-dummy-frame-removal.c: New file.
* gdb.base/premature-dummy-frame-removal.exp: New file.
* gdb.base/premature-dummy-frame-removal.py: New file.
Simon Marchi [Mon, 31 May 2021 16:33:32 +0000 (12:33 -0400)]
gdb: pass signature to allocate_signatured_type and signatured_type constructor
All signatured_type constucted (even those used only for lookups in hash
maps) need a signature. Enforce that by passing the signature all the
way to the signatured_type constructor.
Nelson Chu [Wed, 12 May 2021 15:26:33 +0000 (08:26 -0700)]
RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust.
2021-05-31 Nelson Chu <nelson.chu@sifive.com>
Lifang Xia <lifang_xia@c-sky.com>
The data segment phase exp_seg_relro_adjust means we are still adjusting the
relro segments, so we will get the symbol values which havn't consider the
relro. It is dangerous and we shouldn't do the relaxations at this stage.
Otherwise, we may get the truncated fails when the relax range crossing the
data segment.
One of the solution is that, we use a pointer to monitor the data segment
phase while relaxing, to know whether the relro has been handled or not.
Once we check the phase is exp_seg_relro_adjust, we should skip this round
of relaxations, since the incorrect symbol values will affect the correctness
of relaxations. I think we probably need to record more information about
data segment or alignments in the future, to make sure it is safe to doing
relaxations.
For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get
the following truncated errors when using toolchains, which enable relro:
(.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o
After applying this patch, the truncated errors should be resolved.
However, only linux toolchains support -z relro, so we only test these
two testcases when supporting shared library.
bfd/
PR 27566
* elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer
to monitor the data segment phase.
(bfd_elfNN_riscv_set_data_segment_info): New function called by
after_allocation, to set the data_segment_phase from expld.dataseg.
(_bfd_riscv_relax_section): Don't relax when data_segment_phase is
exp_seg_relro_adjust (0x4).
* elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern.
(bfd_elf64_riscv_set_data_segment_info): Likewise.
ld/
PR 27566
* emultempl/riscvelf.em (after_allocation): Call
riscv_set_data_segment_info to set data segment phase before relaxing.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase.
* testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
Tom Tromey [Sun, 30 May 2021 14:50:57 +0000 (08:50 -0600)]
Set is_debug_types in allocate_signatured_type
All callers of allocate_signatured_type set the is_debug_types flag on
the result -- in fact, they are required to, because this is the sign
that downcasting the object to signatured_type is safe. This patch
moves this assignment into the allocation function.
2021-05-30 Tom Tromey <tom@tromey.com>
* dwarf2/read.c (dwarf2_per_bfd::allocate_signatured_type): Set
is_debug_types.
(create_signatured_type_table_from_index)
(create_signatured_type_table_from_debug_names, add_type_unit)
(read_comp_units_from_section): Update.
Tom Tromey [Sat, 29 May 2021 21:35:07 +0000 (15:35 -0600)]
Remove dwarf2_per_bfd::m_num_psymtabs
Now that CUs and TUs are stored together in all_comp_units, the
m_num_psymtabs member is no longer needed -- it is always identical to
the length of the vector. This patch removes it.
Mike Frysinger [Sat, 29 May 2021 21:57:55 +0000 (17:57 -0400)]
sim: ppc: avoid shadowing errno
If the OS headers define the "errno" symbol, it breaks some of these
funcs that were using "int errno" itself. Rename local vars to "err"
to avoid that, and delete the old "extern int errno".
Mike Frysinger [Sat, 29 May 2021 19:23:24 +0000 (15:23 -0400)]
sim: v850: add pointer casts for execv on Windows
The execv prototypes on Windows via mingw64 include extra const
markings on the argv/envp pointers than what POSIX specifies.
Cast them to void* as a hack to get it working on all platforms.
Mike Frysinger [Sat, 29 May 2021 19:22:17 +0000 (15:22 -0400)]
sim: mn10300: add SIGTRAP fallback
This is a bit of a hack, but it matches the hack we use in other
places in the sim currently. This fixes building for e.g. Windows.
The signal fallback logic needs a bit of love in general at some
point across all sim code.
Mike Frysinger [Sat, 29 May 2021 19:21:21 +0000 (15:21 -0400)]
sim: pull in extra gnulib libs too
Some modules might require extra linking depending on the platform
(e.g. Windows might need -lws2_32), so include the existing extra
gnulib libs setting.
Alan Modra [Fri, 28 May 2021 03:54:16 +0000 (13:24 +0930)]
PowerPC table driven -Mraw disassembly
opcodes/
* ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
Don't special case PPC_OPCODE_RAW.
(lookup_prefix): Likewise.
(lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
(print_insn_powerpc): ..update caller.
* ppc-opc.c (EXT): Define.
(powerpc_opcodes): Mark extended mnemonics with EXT.
(prefix_opcodes, vle_opcodes): Likewise.
(XISEL, XISEL_MASK): Add cr field and simplify.
(powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
all isel variants to where the base mnemonic belongs. Sort dstt,
dststt and dssall.
gas/
* testsuite/gas/ppc/raw.s,
* testsuite/gas/ppc/raw.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Group legacy instructions using the COP0, COP2, COP3 opcodes together
and by their coprocessor number, and move them towards the end of the
opcode table. No functional change.
With the addition of explicit ISA exclusions this is maybe not strictly
necessary anymore as the individual legacy instructions are not supposed
to match ISA levels or CPU implementations that have discarded them or
replaced with a new instruction each, but let's not have them scattered
randomly across blocks of unrelated instruction sets where someone chose
to put them previously. Perhaps they could be put back in alphabetical
order in the main instruction block, but let's leave it for another
occasion.
Add tests for the generic C0, C1, C2, C3 coprocessor instructions.
gas/
* testsuite/gas/mips/c0.d: New test.
* testsuite/gas/mips/mips1@c0.d: New test.
* testsuite/gas/mips/mips2@c0.d: New test.
* testsuite/gas/mips/mips3@c0.d: New test.
* testsuite/gas/mips/mips4@c0.d: New test.
* testsuite/gas/mips/mips5@c0.d: New test.
* testsuite/gas/mips/mips32@c0.d: New test.
* testsuite/gas/mips/mips64@c0.d: New test.
* testsuite/gas/mips/r3000@c0.d: New test.
* testsuite/gas/mips/r3900@c0.d: New test.
* testsuite/gas/mips/r4000@c0.d: New test.
* testsuite/gas/mips/vr5400@c0.d: New test.
* testsuite/gas/mips/r5900@c0.d: New test.
* testsuite/gas/mips/sb1@c0.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c0.d: New test.
* testsuite/gas/mips/octeon@c0.d: New test.
* testsuite/gas/mips/xlr@c0.d: New test.
* testsuite/gas/mips/c1.d: New test.
* testsuite/gas/mips/mips1@c1.d: New test.
* testsuite/gas/mips/mips2@c1.d: New test.
* testsuite/gas/mips/mips3@c1.d: New test.
* testsuite/gas/mips/mips4@c1.d: New test.
* testsuite/gas/mips/mips5@c1.d: New test.
* testsuite/gas/mips/mips32@c1.d: New test.
* testsuite/gas/mips/mips64@c1.d: New test.
* testsuite/gas/mips/mipsr6@c1.d: New test.
* testsuite/gas/mips/r3000@c1.d: New test.
* testsuite/gas/mips/r3900@c1.d: New test.
* testsuite/gas/mips/r4000@c1.d: New test.
* testsuite/gas/mips/vr5400@c1.d: New test.
* testsuite/gas/mips/r5900@c1.d: New test.
* testsuite/gas/mips/sb1@c1.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c1.d: New test.
* testsuite/gas/mips/octeon@c1.d: New test.
* testsuite/gas/mips/xlr@c1.d: New test.
* testsuite/gas/mips/c2.d: New test.
* testsuite/gas/mips/vr5400@c2.d: New test.
* testsuite/gas/mips/r5900@c2.d: New test.
* testsuite/gas/mips/octeon@c2.d: New test.
* testsuite/gas/mips/c3.d: New test.
* testsuite/gas/mips/mips1@c3.d: New test.
* testsuite/gas/mips/mips2@c3.d: New test.
* testsuite/gas/mips/mips32@c3.d: New test.
* testsuite/gas/mips/r3000@c3.d: New test.
* testsuite/gas/mips/r3900@c3.d: New test.
* testsuite/gas/mips/c0.l: New test stderr output.
* testsuite/gas/mips/c2.l: New test stderr output.
* testsuite/gas/mips/c3.l: New test stderr output.
* testsuite/gas/mips/c0.s: New test source.
* testsuite/gas/mips/c1.s: New test source.
* testsuite/gas/mips/c2.s: New test source.
* testsuite/gas/mips/c3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Verify that the RFE instruction is not only accepted where supported,
but rejected where it is not as well.
gas/
* testsuite/gas/mips/mips.exp: Run RFE test across all ISAs.
* testsuite/gas/mips/rfe.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@rfe.d: New test.
* testsuite/gas/mips/mips2@rfe.d: New test.
* testsuite/gas/mips/r3000@rfe.d: New test.
* testsuite/gas/mips/r3900@rfe.d: New test.
* testsuite/gas/mips/rfe.l: New test stderr output.
MIPS/GAS/testsuite: Run coprocessor tests across all ISAs
Verify that individual coprocessor instructions are not only accepted
where supported, but rejected where they are not as well.
gas/
* testsuite/gas/mips/mips.exp: Run coprocessor tests across all
ISAs.
* testsuite/gas/mips/cp0b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0c.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3d.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0b.d: New test.
* testsuite/gas/mips/mips3@cp0b.d: New test.
* testsuite/gas/mips/r3000@cp0b.d: New test.
* testsuite/gas/mips/r3900@cp0b.d: New test.
* testsuite/gas/mips/r4000@cp0b.d: New test.
* testsuite/gas/mips/r5900@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0bl.d: New test.
* testsuite/gas/mips/mips3@cp0bl.d: New test.
* testsuite/gas/mips/r3900@cp0bl.d: New test.
* testsuite/gas/mips/r4000@cp0bl.d: New test.
* testsuite/gas/mips/r5900@cp0bl.d: New test.
* testsuite/gas/mips/mips1@cp0c.d: New test.
* testsuite/gas/mips/mips2@cp0c.d: New test.
* testsuite/gas/mips/mips3@cp0c.d: New test.
* testsuite/gas/mips/mips4@cp0c.d: New test.
* testsuite/gas/mips/mips5@cp0c.d: New test.
* testsuite/gas/mips/r3000@cp0c.d: New test.
* testsuite/gas/mips/r3900@cp0c.d: New test.
* testsuite/gas/mips/r4000@cp0c.d: New test.
* testsuite/gas/mips/vr5400@cp0c.d: New test.
* testsuite/gas/mips/r5900@cp0c.d: New test.
* testsuite/gas/mips/mips1@cp0m.d: New test.
* testsuite/gas/mips/r3000@cp0m.d: New test.
* testsuite/gas/mips/octeon@cp2.d: New test.
* testsuite/gas/mips/mipsr6@cp2b.d: New test.
* testsuite/gas/mips/vr5400@cp2b.d: New test.
* testsuite/gas/mips/octeon@cp2b.d: New test.
* testsuite/gas/mips/mips1@cp2bl.d: New test.
* testsuite/gas/mips/mipsr6@cp2bl.d: New test.
* testsuite/gas/mips/r3000@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2bl.d: New test.
* testsuite/gas/mips/octeon@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2m.d: New test.
* testsuite/gas/mips/r5900@cp2m.d: New test.
* testsuite/gas/mips/octeon@cp2m.d: New test.
* testsuite/gas/mips/mips1@cp2d.d: New test.
* testsuite/gas/mips/r3000@cp2d.d: New test.
* testsuite/gas/mips/r3900@cp2d.d: New test.
* testsuite/gas/mips/vr5400@cp2d.d: New test.
* testsuite/gas/mips/r5900@cp2d.d: New test.
* testsuite/gas/mips/octeon@cp2d.d: New test.
* testsuite/gas/mips/mips1@cp2-64.d: New test.
* testsuite/gas/mips/mips2@cp2-64.d: New test.
* testsuite/gas/mips/mips32@cp2-64.d: New test.
* testsuite/gas/mips/mips32r2@cp2-64.d: New test.
* testsuite/gas/mips/mips32r3@cp2-64.d: New test.
* testsuite/gas/mips/mips32r5@cp2-64.d: New test.
* testsuite/gas/mips/mips32r6@cp2-64.d: New test.
* testsuite/gas/mips/r3000@cp2-64.d: New test.
* testsuite/gas/mips/r3900@cp2-64.d: New test.
* testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test.
* testsuite/gas/mips/mips1@cp3.d: New test.
* testsuite/gas/mips/mips2@cp3.d: New test.
* testsuite/gas/mips/mips32@cp3.d: New test.
* testsuite/gas/mips/r3000@cp3.d: New test.
* testsuite/gas/mips/r3900@cp3.d: New test.
* testsuite/gas/mips/mips1@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3b.d: New test.
* testsuite/gas/mips/mips32@cp3b.d: New test.
* testsuite/gas/mips/r3000@cp3b.d: New test.
* testsuite/gas/mips/r3900@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3bl.d: New test.
* testsuite/gas/mips/mips32@cp3bl.d: New test.
* testsuite/gas/mips/r3900@cp3bl.d: New test.
* testsuite/gas/mips/mips1@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3m.d: New test.
* testsuite/gas/mips/r3000@cp3m.d: New test.
* testsuite/gas/mips/r3900@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3d.d: New test.
* testsuite/gas/mips/cp0b.l: New test stderr output.
* testsuite/gas/mips/cp0bl.l: New test stderr output.
* testsuite/gas/mips/cp0c.l: New test stderr output.
* testsuite/gas/mips/cp0m.l: New test stderr output.
* testsuite/gas/mips/cp2.l: New test stderr output.
* testsuite/gas/mips/cp2-64.l: New test stderr output.
* testsuite/gas/mips/cp2b.l: New test stderr output.
* testsuite/gas/mips/cp2bl.l: New test stderr output.
* testsuite/gas/mips/cp2m.l: New test stderr output.
* testsuite/gas/mips/cp2d.l: New test stderr output.
* testsuite/gas/mips/cp3.l: New test stderr output.
* testsuite/gas/mips/cp3b.l: New test stderr output.
* testsuite/gas/mips/cp3bl.l: New test stderr output.
* testsuite/gas/mips/cp3m.l: New test stderr output.
* testsuite/gas/mips/cp3d.l: New test stderr output.
MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership
Adjust opcode table entries for coprocessor instructions that have been
removed from certain ISA levels or CPU implementations as follows:
- remove CP0 memory access instructions from MIPS II up as the LWC0 and
SWC0 opcodes have been reused for the LL and SC instructions
respectively[1]; strictly speaking LWC0 and SWC0 have never really
been defined in the first place[2], but let's keep them for now in
case an odd implementation did,
- remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as
they have been removed as from those ISAs,
- remove CP0 control register move instructions from MIPS32 up, as they
have been removed as from that ISA[5],
- remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it
has been removed as from those ISAs in favour to ERET,
- remove CP2 instructions from Vr5400 CPUs as their encodings have been
reused for the multimedia instruction set extensions[8] and no CP2
registers exist[9],
- remove CP3 memory access instructions from MIPS III up as coprocessor
3 has been removed as from that ISA[10][11] and from MIPS32 up as the
LWC3 opcode has been reused for the PREF instruction and consequently
all the four memory access instructions removed from the ISA (though
the COP3 opcode has been retained)[12].
Update the testsuite accordingly.
References:
[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding
- MIPS II Architecture", p. A-178
[2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12
[3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS
Technologies, Inc., January 29, 1997, Section 14.25 "CP0
Instructions", Subsection "Branch on Coprocessor 0", p. 285
[4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number:
MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0
Encoding of rs Field", p. 242
[5] same
[6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second
Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000
Opcode Bit Encoding", p. A-182
[8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1",
NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
Section 1.2.3 "CPU Instruction Set Overview", p. 9
[9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2",
NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
Section 19.2 "Multimedia Instruction Format", p. 681
[10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 -
COP3 and CP3 load/store", p. A-176
[11] same, Table A-39 "CPU Instruction Encoding - MIPS III
Architecture", p. A-179
[12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number:
MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding
of the Opcode Field", p. 241
Coprocessor 3 has been removed from the MIPS ISA as from MIPS III[1][2]
with the LDC3 and SDC3 instructions having been replaced with LD and SD
instructions respectively and therefore the doubleword move instructions
from and to that coprocessor have never materialized (for 32-bit ISAs
coprocessor 3 has likewise been removed as from MIPS32r2[3]). Remove
the DMFC3 and DMTC3 instructions from the opcode table then to avoid
confusion.
References:
[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3
and CP3 load/store", p. A-176
[2] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture",
p. A-179
[3] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 2.00, June 9, 2003, Table A-2 "MIPS32 Encoding of the
Opcode Field", p. 317
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
entries and associated comments.
MIPS/GAS/testsuite: Add tests for coprocessor branch instructions
Cover basic CP0, CP2, CP3 branch and branch-likely instructions across
the relevant ISA levels. Omit CP1 branches, covered elsewhere.
gas/
* testsuite/gas/mips/cp0b.d: New test.
* testsuite/gas/mips/cp0bl.d: New test.
* testsuite/gas/mips/cp2b.d: New test.
* testsuite/gas/mips/micromips@cp2b.d: New test.
* testsuite/gas/mips/cp2bl.d: New test.
* testsuite/gas/mips/micromips@cp2bl.d: New test.
* testsuite/gas/mips/cp3b.d: New test.
* testsuite/gas/mips/cp3bl.d: New test.
* testsuite/gas/mips/cp0b.s: New test source.
* testsuite/gas/mips/cp0bl.s: New test source.
* testsuite/gas/mips/cp2b.s: New test source.
* testsuite/gas/mips/cp2bl.s: New test source.
* testsuite/gas/mips/cp3b.s: New test source.
* testsuite/gas/mips/cp3bl.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
and bring the disassembly of the RFE instruction back for the relevant
ISA levels.
It is because the "rfe" opcode table entry was incorrectly moved behind
the catch-all generic "c0" entry for CP0 instructions, causing output
like:
Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and
handle the exclusion for any ISA levels properly in `opcode_is_member'.
Flatten the structure of the `if' statements there. No functional
change for the existing opcode tables.
include/
* opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA
exclusion.
(opcode_is_member): Handle ISA level exclusion.
MIPS/opcodes: Factor out ISA matching against flags
In preparation for the next change factor out code for ISA matching
against instruction flags used in MIPS opcode tables, similarly to how
CPU matching is already done. No functional change, though for clarity
split the single `if' statement into multiple ones and use temporaries
rather than repeated expressions.
include/
* opcode/mips.h (isa_is_member): New inline function, factored
out from...
(opcode_is_member): ... here.
MIPS/opcodes: Add legacy CP1 control register names
The two CP1 control registers defined by legacy ISAs used to be referred
to by various names, such as FCR0, FCR31, FSR, however their documented
full names have always been the Implementation and Revision, and Control
and Status respectively, so the FIR and FCSR acronyms coming from modern
ISA revisions will be just as unambiguous while improving the clarity of
disassembly. Do not update the TX39 though as it did not have an FPU.
opcodes/
* mips-dis.c (mips_cp1_names_mips): New variable.
(mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
"r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
"r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
"r12000", "r14000", "r16000", "mips5", "loongson2e", and
"loongson2f".
gas/
* testsuite/gas/mips/cp1-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
* testsuite/gas/mips/branch-misc-3.d: Update disassembly
according to changes to opcodes.
* testsuite/gas/mips/cp1-names-r3000.d: Likewise.
* testsuite/gas/mips/cp1-names-r4000.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips1.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips2.d: Likewise.
* testsuite/gas/mips/trunc.d: Likewise.
MIPS/GAS/testsuite: Add tests for coprocessor access instructions
Cover basic CP0, CP2, CP3 move, load and store instructions across the
relevant ISA levels. Omit CP0 move and CP1 instructions as they are
covered elsewhere.
gas/
* testsuite/gas/mips/cp0c.d: New test.
* testsuite/gas/mips/cp0m.d: New test.
* testsuite/gas/mips/r3900@cp0m.d: New test.
* testsuite/gas/mips/cp2.d: New test.
* testsuite/gas/mips/micromips@cp2.d: New test.
* testsuite/gas/mips/cp2m.d: New test.
* testsuite/gas/mips/mipsr6@cp2m.d: New test.
* testsuite/gas/mips/micromips@cp2m.d: New test.
* testsuite/gas/mips/cp2d.d: New test.
* testsuite/gas/mips/mipsr6@cp2d.d: New test.
* testsuite/gas/mips/micromips@cp2d.d: New test.
* testsuite/gas/mips/cp2-64.d: New test.
* testsuite/gas/mips/micromips@cp2-64.d: New test.
* testsuite/gas/mips/cp3.d: New test.
* testsuite/gas/mips/cp3m.d: New test.
* testsuite/gas/mips/cp3d.d: New test.
* testsuite/gas/mips/cp0c.s: New test source.
* testsuite/gas/mips/cp0m.s: New test source.
* testsuite/gas/mips/cp2.s: New test source.
* testsuite/gas/mips/cp2m.s: New test source.
* testsuite/gas/mips/cp2d.s: New test source.
* testsuite/gas/mips/cp2-64.s: New test source.
* testsuite/gas/mips/cp3.s: New test source.
* testsuite/gas/mips/cp3m.s: New test source.
* testsuite/gas/mips/cp3d.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/opcodes: Do not use CP0 register names for control registers
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
MIPS/binutils/testsuite: Fix XPA and Virtualization ASE cases
Fix commit 9785fc2a4d22 ("MIPS: Fix XPA base and Virtualization ASE
instruction handling") and explicitly use the `mips:3000' machine for
disassembly across the XPA base and XPA Virtualization ASE test cases,
providing actual coverage for the `virt' and `xpa' disassembler options
and removing failures for targets that default to those ASEs enabled:
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
This is because the test cases rely on these ASEs being disabled for
disassembly by default and expect instructions belonging to these ASEs
not to be shown unless explicitly enabled. The `mips-xpa-virt-4' test
case passes regardless, but we want it to verify the explicit options do
work, so use the `mips:3000' machine to set the defaults there as well.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Use `mips:3000'
machine for disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: Likewise.
In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154ba ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.
Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.
Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
and "mtthc2" to using the `G' rather than `g' operand code for
the coprocessor control register referred.
include/
* opcode/mips.h: Complement change made to opcodes and remove
references to the `g' regular MIPS ISA operand code.
microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1
The DMTC1 instruction operates on a floating-point general register as
its second operand, however in the disassembly of the microMIPS encoding
a floating-point control register is shown instead. This is due to an
incorrect ordering of the two "dmtc1" entries in the opcode table, which
gives precedence to one using the `G' aka coprocessor format over one
using the `S' or floating-point register format.
The coprocessor format, or OP_REG_COPRO, is used so that GAS supports
referring to FPRs by their numbers in assembly, such as $0, $1, etc.
however in the case of CP1/FPU it is also used by the disassembler to
decode those numbers to the names of corresponding control registers.
This in turn causes nonsensical disassembly such as:
dmtc1 a1,c1_fir
in a reference to $f0. It has been like this ever since microMIPS ISA
support has been added.
Correct the ordering of the two entries then by swapping them with each
other, making disassembly output consistent with the regular MIPS DMTC1
instruction as well all the remaining CP1 move instructions. Adjust all
the test cases affected accordingly.
opcodes/
* micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
entries with each other.
gas/
* testsuite/gas/mips/micromips.d: Update disassembly according
to "dmtc1" entry fix with opcodes.
* testsuite/gas/mips/micromips-compact.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
Fix an issue caused by commit f9419b056fe2 ("MIPS gas: code cleanup"),
<https://sourceware.org/ml/binutils/2002-05/msg00192.html>, and replace
the incorrect use of RA with the CFC1 and CTC1 instructions with FCSR.
While the register referred by its number is $31 in both cases, these
instructions operate on the floating-point control register file rather
than general-purpose registers.
gas/
* config/tc-mips.c (FCSR): New macro.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
H.J. Lu [Fri, 28 May 2021 16:34:10 +0000 (09:34 -0700)]
x86: Restore PC16 relocation overflow check
The x86-64 psABI has
---
A program or object file using R_X86_64_8, R_X86_64_16, R_X86_64_PC16
or R_X86_64_PC8 relocations is not conformant to this ABI, these
relocations are only added for documentation purposes.
---
Since x86 PC16 relocations have been used for 16-bit programs in an ELF32
or ELF64 container, PC16 relocation should wrap-around in 16-bit address
space. Revert
Simon Marchi [Thu, 27 May 2021 19:18:49 +0000 (15:18 -0400)]
gdb: fix tab after space indentation issues
I spotted some indentation issues where we had some spaces followed by
tabs at beginning of line, that I wanted to fix. So while at it, I did
a quick grep to find and fix all I could find.
gdb/ChangeLog:
* Fix tab after space indentation issues throughout.
Simon Marchi [Thu, 27 May 2021 19:01:28 +0000 (15:01 -0400)]
gdb: fix some indentation issues
I wrote a small script to spot a pattern of indentation mistakes I saw
happened in breakpoint.c. And while at it I ran it on all files and
fixed what I found. No behavior changes intended, just indentation and
addition / removal of curly braces.
Simon Marchi [Thu, 27 May 2021 18:58:37 +0000 (14:58 -0400)]
gdb: remove iterate_over_breakpoints function
Now that we have range functions that let us use ranged for loops, we
can remove iterate_over_breakpoints in favor of those, which are easier
to read and write. This requires exposing the declaration of
all_breakpoints and all_breakpoints_safe in breakpoint.h, as well as the
supporting types.
Change some users of iterate_over_breakpoints to use all_breakpoints,
when they don't need to delete the breakpoint, and all_breakpoints_safe
otherwise.
gdb/ChangeLog:
* breakpoint.h (iterate_over_breakpoints): Remove. Update
callers to use all_breakpoints or all_breakpoints_safe.
(breakpoint_range, all_breakpoints, breakpoint_safe_range,
all_breakpoints_safe): Move here.
* breakpoint.c (all_breakpoints, all_breakpoints_safe): Make
non-static.
(iterate_over_breakpoints): Remove.
* python/py-finishbreakpoint.c (bpfinishpy_detect_out_scope_cb):
Return void.
* python/py-breakpoint.c (build_bp_list): Add comment, reverse
return value logic.
* guile/scm-breakpoint.c (bpscm_build_bp_list): Return void.
for (bp_location *loc : all_bp_locations_at_addr (address))
{
// use loc
}
The all_bp_locations_at_addr returns a bp_locations_at_addr_range
object, which is really just a wrapper around two std::vector iterators
representing the beginning and end of the interesting range. These
iterators are found when constructing the bp_locations_at_addr_range
object using std::equal_range, which seems a perfect fit for this use
case.
One thing I noticed about the current ALL_BP_LOCATIONS_AT_ADDR is that
if you call it with a NULL start variable, that variable gets filled in
and can be re-used for subsequent iterations. This avoids the cost of
finding the start of the interesting range again for the subsequent
iterations. This happens in build_target_command_list, for example.
The same effect can be achieved by storing the range in a local
variable, it can be iterated on multiple times.
Note that the original comment over ALL_BP_LOCATIONS_AT_ADDR says:
Iterates through locations with address ADDRESS for the currently
selected program space.
I don't see anything restricting the iteration to a given program space,
as we iterate over all bp_locations, which as far as I know contains all
breakpoint locations, regardless of the program space. So I just
dropped that part of the comment.
gdb/ChangeLog:
* breakpoint.c (get_first_locp_gte_addr): Remove.
(ALL_BP_LOCATIONS_AT_ADDR): Remove. Replace all uses with
all_bp_locations_at_addr.
(struct bp_locations_at_addr_range): New.
(all_bp_locations_at_addr): New.
(bp_locations_compare_addrs): New.
Simon Marchi [Thu, 27 May 2021 18:58:37 +0000 (14:58 -0400)]
gdb: add all_bp_locations function
Add the all_bp_locations function to replace the ALL_BP_LOCATIONS macro.
For simplicity, all_bp_locations simply returns a const reference to the
bp_locations vector. But the callers just treat it as a range to
iterate on, so if we ever change the breakpoint location storage, we can
change the all_bp_locations function to return some other range type,
and the callers won't need to be changed.
gdb/ChangeLog:
* breakpoint.c (ALL_BP_LOCATIONS): Remove, update users to use
all_bp_locations.
(all_bp_locations): New.
Simon Marchi [Thu, 27 May 2021 18:58:37 +0000 (14:58 -0400)]
gdb: make bp_locations an std::vector
Change the type of the global location list, bp_locations, to be an
std::vector.
Adjust the users to deal with that, mostly in an obvious way by using
.data() and .size(). The user where it's slightly less obvious is
update_global_location_list. There, we std::move the old location list
out of the global vector into a local variable. The code to fill the
new location list gets simpler, as it's now simply using .push_back(),
no need to count the locations beforehand.
In the rest of update_global_location_list, the code is adjusted to work
with indices instead of `bp_location **`, to iterate on the location
list. I believe it's a bit easier to understand this way. But more
importantly, when we build with _GLIBCXX_DEBUG, the operator[] of the
vector does bound checking, so we will know if we ever access past a
vector size (which we won't if we access by raw pointer). I think that
work can further be done to make that function easier to understand,
notably find better names than "loc" and "loc2" for variables, but
that's work for later.
gdb/ChangeLog:
* breakpoint.c (bp_locations): Change to std::vector, update all
users.
(bp_locations_count): Remove.
(update_global_location_list): Change to work with indices
rather than bp_location**.
Simon Marchi [Thu, 27 May 2021 18:58:36 +0000 (14:58 -0400)]
gdb: add all_tracepoints function
Same idea as the previous patches, but to replace the ALL_TRACEPOINTS
macro. Define a new filtered_iterator that only keeps the breakpoints
for which is_tracepoint returns true (just like the macro did).
I would have like to make it so tracepoint_range yields some
`tracepoint *` instead of some `breakpoint *`, that would help simplify
the callers, who wouldn't have to do the cast themselves. But I didn't
find an obvious way to do it. It can always be added later.
It turns out there is already an all_tracepoints function, which returns
a vector containing all the breakpoints that are tracepoint. Remove it,
most users will just work seamlessly with the new function. The
exception is start_tracing, which iterated multiple times on the vector.
Adapt this one so it iterates multiple times on the returned range.
Since the existing users of all_tracepoints are outside of breakpoint.c,
this requires defining all_tracepoints and a few supporting types in
breakpoint.h. So, move breakpoint_iterator from breakpoint.c to
breakpoint.h.
Simon Marchi [Thu, 27 May 2021 18:58:36 +0000 (14:58 -0400)]
gdb: add all_breakpoints_safe function
Same as the previous patch, but intended to replace the
ALL_BREAKPOINTS_SAFE macro, which allows deleting the current breakpoint
while iterating. The new range type simply wraps the range added by the
previous patch with basic_safe_range.
I didn't remove the ALL_BREAKPOINTS_SAFE macro, because there is one
spot where it's more tricky to remove, in the
check_longjmp_breakpoint_for_call_dummy function. More thought it
needed for this one.
gdb/ChangeLog:
* breakpoint.c (breakpoint_safe_range): New.
(all_breakpoints_safe): New. Use instead of
ALL_BREAKPOINTS_SAFE where possible.
Simon Marchi [Thu, 27 May 2021 18:58:36 +0000 (14:58 -0400)]
gdb: add all_breakpoints function
Introduce the all_breakpoints function, which returns a range that can
be used to iterate on breakpoints. Replace all uses of the
ALL_BREAKPOINTS macro with this.
In one instance, I could replace the breakpoint iteration with a call to
get_breakpoint.
gdb/ChangeLog:
* breakpoint.c (ALL_BREAKPOINTS): Remove, replace all uses with
all_breakpoints.
(breakpoint_iterator): New.
(breakpoint_range): New.
(all_breakpoints): New.
Hannes Domani [Sun, 22 Nov 2020 15:51:30 +0000 (16:51 +0100)]
Add optional full_window argument to TuiWindow.write
To prevent flickering when first calling erase, then write, this new
argument indicates that the passed string contains the full contents of
the window. This fills every unused cell of the window with a space, so
it's not necessary to call erase beforehand.
Simon Marchi [Thu, 27 May 2021 17:59:01 +0000 (13:59 -0400)]
gdb: add option to reverse order of _initialize function calls
An earlier patch in this series fixed a dependency problem between two
_initialize functions. That problem was uncovered by reversing the
order of the initialize function calls.
In short, symtab.c tried to add the alias "maintenance
flush-symbol-cache" for the command "maintenance flush symbol-cache".
Because the "maintenance flush" prefix command was not yet created (it
happens in maint.c, initialized later in this reversed order), the
add_alias_cmd function returned NULL. That result was passed to
deprecate_cmd, which didn't expected that value, and that caused a
segfault. This was fixed by changing alias creation functions to take
the target command as a cmd_list_element, instead of by name.
This patch adds a runtime option to reverse the order of the initialize
calls at will. I chose to use an environment variable for this, over a
parameter (even a "maintenance" one), because:
- The init functions are called before the early init commands are
executed, so we could use -iex to turn this mode on early enough.
This is obvious when you remember that commands / parameters are
created by initialize funcitions :).
- This is not something anybody would want to tweak after startup
anyway.
gdb/ChangeLog:
* make-init-c: Add option to reverse function calls.
Simon Marchi [Thu, 27 May 2021 17:59:01 +0000 (13:59 -0400)]
gdb: add make-init-c script
I would like to modify how the init.c file is generated (its content).
But as it is, a shell script with multiple sed invocations in a Makefile
target, it's not very maintainable. Replace that with a shell script
that does the same, but in a more readable way.
The Makefile rule uses the "-" prefix in front of the for loop, I
presume to ignore any error coming from the fact that xml-builtin.c and
cp-name-parser.c are not found in the srcdir (they are generated source
files). I prefer not to blindly ignore errors, so filter these files
out of INIT_FILES instead (we already filter out other files).
There are no expected meaningful changes to the generated init.c file.
Just the _initialize_all_file declaration that is moved down and "void"
in parenthesis that is removed.
The new regular expression is a bit tighter than the existing one, it
requires the init function to be followed by exactly ` ()`. Update
bpf-tdep.c accordingly.
gdb/ChangeLog:
* Makefile.in (INIT_FILES_FILTER_OUT): New.
(INIT_FILES): Use INIT_FILES_FILTER_OUT.
(stamp-init): Use make-init-c.
* bpf-tdep.c (_initialize_bpf_tdep): Remove "void".
* silent-rules.mk (ECHO_INIT_C): Change.
* make-init-c: New file.
Simon Marchi [Thu, 27 May 2021 17:59:01 +0000 (13:59 -0400)]
gdb: remove add_alias_cmd overload that accepts a string
Same idea as previous patch, but for add_alias_cmd. Remove the overload
that accepts the target command as a string (the target command name),
leaving only the one that takes the cmd_list_element.
gdb/ChangeLog:
* command.h (add_alias_cmd): Accept target as
cmd_list_element. Update callers.
Simon Marchi [Thu, 27 May 2021 17:59:01 +0000 (13:59 -0400)]
gdb: make add_com_alias accept target as a cmd_list_element
The alias creation functions currently accept a name to specify the
target command. They pass this to add_alias_cmd, which needs to lookup
the target command by name.
Given that:
- We don't support creating an alias for a command before that command
exists.
- We always use add_info_alias just after creating that target command,
and therefore have access to the target command's cmd_list_element.
... change add_com_alias to accept the target command as a
cmd_list_element (other functions are done in subsequent patches). This
ensures we don't create the alias before the target command, because you
need to get the cmd_list_element from somewhere when you call the alias
creation function. And it avoids an unecessary command lookup. So it
seems better to me in every aspect.
gdb/ChangeLog:
* command.h (add_com_alias): Accept target as
cmd_list_element. Update callers.
Simon Marchi [Thu, 27 May 2021 17:59:00 +0000 (13:59 -0400)]
gdb/python: use return values of add_setshow functions in add_setshow_generic
In add_setshow_generic, we create set/show commands using add_setshow_*
functions, then look up the commands by name to set the context pointer.
It would be simpler and more efficient to use the return values of the
add_setshow_* functions, do that.
gdb/ChangeLog:
* python/py-param.c (add_setshow_generic): Use return values of
add_setshow functions.
Simon Marchi [Thu, 27 May 2021 17:59:00 +0000 (13:59 -0400)]
gdb: make add_setshow commands return set_show_commands
Some add_set_show commands return a single cmd_list_element, the one for
the "set" command. A subsequent patch will need to access the show
command's cmd_list_element as well. Change these functions to return a
new structure type that holds both pointers.
I initially only modified add_setshow_boolean_cmd (the one I needed),
but I think it's better to change the whole chain to keep everything in
sync.
Tom de Vries [Thu, 27 May 2021 13:22:38 +0000 (15:22 +0200)]
[gdb/symtab] Fix segfault in process_psymtab_comp_unit
When running test-case gdb.dwarf2/dw2-dummy-cu.exp without -readnow, we run
into:
...
(gdb) file outputs/gdb.dwarf2/dw2-dummy-cu/dw2-dummy-cu^M
Reading symbols from outputs/gdb.dwarf2/dw2-dummy-cu/dw2-dummy-cu...^M
ERROR: Couldn't load dw2-dummy-cu into GDB (eof).
...
The problem is that we're running into a segfault:
...
Thread 1 "gdb" received signal SIGSEGV, Segmentation fault.
process_psymtab_comp_unit (this_cu=0x2141090, per_objfile=0x1aa4140,
want_partial_unit=false, pretend_language=language_minimal)
at /home/vries/gdb_versions/devel/src/gdb/dwarf2/read.c:7023
7023 switch (reader.comp_unit_die->tag)
...
due to reader.comp_unit_die == nullptr:
...
(gdb) p reader.comp_unit_die
$1 = (die_info *) 0x0
...
Indeed, there's no CU DIE in the test-case:
...
$ readelf -wi outputs/gdb.dwarf2/dw2-dummy-cu/dw2-dummy-cu
Contents of the .debug_info section:
Tom de Vries [Thu, 27 May 2021 13:22:38 +0000 (15:22 +0200)]
[gdb/testsuite] Prevent proc override in gdb-index.exp
When running these two test-cases in this specific order we get:
...
$ make check 'RUNTESTFLAGS=gdb.dwarf2/gdb-index.exp \
gdb.dwarf2/gdb-add-index-symlink.exp'
...
Running gdb.dwarf2/gdb-index.exp ...
Running gdb.dwarf2/gdb-add-index-symlink.exp ...
FAIL: gdb.dwarf2/gdb-add-index-symlink.exp: gdb-index file created
FAIL: gdb.dwarf2/gdb-add-index-symlink.exp: Unable to call \
gdb-add-index with a symlink to a symfile
...
The problem is that gdb-index.exp introduces a proc add_gdb_index which
overrides the one in lib/gdb.exp and stays active after the test is done.
Consequently it's used in gdb-add-index-symlink.exp, which should use the one
from lib/gdb.exp.
Fix this by renaming proc add_gdb_index in gdb-index.exp.
Tom de Vries [Thu, 27 May 2021 13:22:38 +0000 (15:22 +0200)]
[gdb/symtab] Fix Dwarf Error: cannot find DIE
When loading the debug info package
libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug from openSUSE Leap 15.2, we
run into a dwarf error:
...
$ gdb -q -batch libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug
Dwarf Error: Cannot not find DIE at 0x18a936e7 \
[from module libLLVM.so.10-10.0.1-lp152.30.4.x86_64.debug]
...
The DIE @ 0x18a936e7 does in fact exist, and is part of a CU @ 0x18a23e52.
No error message is printed when using -readnow.
What happens is the following:
- a dwarf2_per_cu_data P is created for the CU.
- a dwarf2_cu A is created for the same CU.
- another dwarf2_cu B is created for the same CU.
- the dwarf2_cu B is set in per_objfile->m_dwarf2_cus, such that
per_objfile->get_cu (P) returns B.
- P->load_all_dies is set to 1.
- all dies are read into the A->partial_dies htab
- dwarf2_cu A is destroyed.
- we try to find the partial_die for the DIE @ 0x18a936e7 in B->partial_dies.
We can't find it, but do not try to load all dies, because P->load_all_dies
is already set to 1.
- an error message is generated.
The question is why we're creating dwarf2_cu A and B for the same CU.
The dwarf2_cu A is created here:
...
(gdb) bt
#0 dwarf2_cu::dwarf2_cu (this=0x79a9660, per_cu=0x23c0b30,
per_objfile=0x1ad01b0) at dwarf2/cu.c:38
#1 0x0000000000675799 in cutu_reader::cutu_reader (this=0x7fffffffd040,
this_cu=0x23c0b30, per_objfile=0x1ad01b0, abbrev_table=0x0,
existing_cu=0x0, skip_partial=false) at dwarf2/read.c:6487
#2 0x0000000000676eb3 in process_psymtab_comp_unit (this_cu=0x23c0b30,
per_objfile=0x1ad01b0, want_partial_unit=false,
pretend_language=language_minimal) at dwarf2/read.c:7028
...
And the dwarf2_cu B is created here:
...
(gdb) bt
#0 dwarf2_cu::dwarf2_cu (this=0x885e8c0, per_cu=0x23c0b30,
per_objfile=0x1ad01b0) at dwarf2/cu.c:38
#1 0x0000000000675799 in cutu_reader::cutu_reader (this=0x7fffffffcc50,
this_cu=0x23c0b30, per_objfile=0x1ad01b0, abbrev_table=0x0,
existing_cu=0x0, skip_partial=false) at dwarf2/read.c:6487
#2 0x0000000000678118 in load_partial_comp_unit (this_cu=0x23c0b30,
per_objfile=0x1ad01b0, existing_cu=0x0) at dwarf2/read.c:7436
#3 0x000000000069721d in find_partial_die (sect_off=(unknown: 0x18a55054),
offset_in_dwz=0, cu=0x0) at dwarf2/read.c:19391
#4 0x000000000069755b in partial_die_info::fixup (this=0x9096900,
cu=0xa6a85f0) at dwarf2/read.c:19512
#5 0x0000000000697586 in partial_die_info::fixup (this=0x8629bb0,
cu=0xa6a85f0) at dwarf2/read.c:19516
#6 0x00000000006787b1 in scan_partial_symbols (first_die=0x8629b40,
lowpc=0x7fffffffcf58, highpc=0x7fffffffcf50, set_addrmap=0, cu=0x79a9660)
at dwarf2/read.c:7563
#7 0x0000000000678878 in scan_partial_symbols (first_die=0x796ebf0,
lowpc=0x7fffffffcf58, highpc=0x7fffffffcf50, set_addrmap=0, cu=0x79a9660)
at dwarf2/read.c:7580
#8 0x0000000000676b82 in process_psymtab_comp_unit_reader
(reader=0x7fffffffd040, info_ptr=0x7fffc1b3f29b, comp_unit_die=0x6ea90f0,
pretend_language=language_minimal) at dwarf2/read.c:6954
#9 0x0000000000676ffd in process_psymtab_comp_unit (this_cu=0x23c0b30,
per_objfile=0x1ad01b0, want_partial_unit=false,
pretend_language=language_minimal) at dwarf2/read.c:7057
...
So in frame #9, a cutu_reader is created with dwarf2_cu A. Then a fixup takes
us to the following CU @ 0x18aa33d6, in frame #5. And a similar fixup in
frame #4 takes us back to CU @ 0x18a23e52. At that point, there's no
information available that we're already trying to read that CU, and we end up
creating another cutu_reader with dwarf2_cu B.
It seems that there are two related problems:
- creating two dwarf2_cu's is not optimal
- the unoptimal case is not handled correctly
This patch addresses the last problem, by moving the load_all_dies flag from
dwarf2_per_cu_data to dwarf2_cu, such that it is paired with the partial_dies
field, which ensures that the two can be kept in sync.
Simon Marchi [Thu, 27 May 2021 03:31:29 +0000 (23:31 -0400)]
Revert "gdb: change dwarf_die_debug to bool"
This was wrong: dwarf_die_debug is used as an integer, for example where
it is passed to dump_die. It is documented in the command's help, which
I missed the first time.
to indicate that 16-bit mode instructions are used in the object to
allow linker to properly perform relocation overflow check for 16-bit
PC-relative relocations in 16-bit mode instructions.
1. Update x86 assembler to always generate the GNU property note with
GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object.
2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if
input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16.
bfd/
PR ld/27905
* elf32-i386.c: Include "libiberty.h".
(elf_howto_table): Add 16-bit R_386_PC16 entry.
(elf_i386_rtype_to_howto): Add a BFD argument. Use 16-bit
R_386_PC16 if input has 16-bit mode instructions.
(elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto
call.
(elf_i386_tls_transition): Likewise.
(elf_i386_relocate_section): Likewise.
* elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit
R_X86_64_PC16 entry.
(elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input
has 16-bit mode instructions.
* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set
elf_x86_has_code16 if relocatable input is marked with
GNU_PROPERTY_X86_FEATURE_2_CODE16.
* elfxx-x86.h (elf_x86_obj_tdata): Add has_code16.
(elf_x86_has_code16): New.
binutils/
PR ld/27905
* readelf.c (decode_x86_feature_2): Support
GNU_PROPERTY_X86_FEATURE_2_CODE16.
gas/
PR ld/27905
* config/tc-i386.c (set_code_flag): Update x86_feature_2_used
with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF
object.
(set_16bit_gcc_code_flag): Likewise.
(x86_cleanup): Always generate the GNU property note if
x86_feature_2_used isn't 0.
* testsuite/gas/i386/code16-2.d: New file.
* testsuite/gas/i386/code16-2.s: Likewise.
* testsuite/gas/i386/x86-64-code16-2.d: Likewise.
* testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2.
Simon Marchi [Wed, 26 May 2021 13:27:54 +0000 (09:27 -0400)]
gdb: don't zero-initialize reg_buffer contents
The reg_buffer constructor zero-initializes (value-initializes, in C++
speak) the gdb_bytes of the m_registers array. This is not necessary,
as these bytes are only meaningful if the corresponding register_status
is REG_VALID. If the corresponding register_status is REG_VALID, then
they will have been overwritten with the actual register data when
reading the registers from the system into the reg_buffer.
Fix that by removing the empty parenthesis following the new expression,
meaning that the bytes will now be default-initialized, meaning they'll
be left uninitialized. For reference, this is explained here:
These new expressions were added in 835dcf92618e ("Use std::unique_ptr
in reg_buffer"). As mentioned in that commit message, the use of
value-initialisation was done on purpose to keep existing behavior, but
now there is some data that suggest it would be beneficial not to do it,
which is why I suggest changing it.
This doesn't make a big difference on typical architectures where the
register buffer is not that big. However, on ROCm (AMD GPU), the
register buffer is about 65000 bytes big, so the reg_buffer constructor
shows up in profiling. If you want to make some tests and profile it on
a standard system, it's always possible to change:
- m_registers.reset (new gdb_byte[m_descr->sizeof_raw_registers] ());
+ m_registers.reset (new gdb_byte[65000] ());
and run a program that constantly hits a breakpoint with a false
condition. For example, by doing this change and running the following
program:
static void break_here () {}
int main ()
{
for (int i = 0; i < 100000; i++)
break_here ();
}
with the following GDB incantation:
/usr/bin/time ./gdb -nx --data-directory=data-directory -q test -ex "b break_here if 0" -ex r -batch
Tom Tromey [Wed, 26 May 2021 13:02:51 +0000 (07:02 -0600)]
Introduce htab_delete_entry
In a bigger series I'm working on, it is convenient to have a
libiberty hash table that manages objects allocated with 'new'. To
make this simpler, I wrote a small template function to serve as a
concise wrapper. Then I realized that this could be reused in a few
other places.
gdb/ChangeLog
2021-05-26 Tom Tromey <tom@tromey.com>
* dwarf2/read.c (allocate_type_unit_groups_table)
(handle_DW_AT_stmt_list, allocate_dwo_file_hash_table): Use
htab_delete_entry.
(free_line_header_voidp): Remove.
* completer.c
(completion_tracker::completion_hash_entry::deleter): Remove.
(completion_tracker::discard_completions): Use htab_delete_entry.
* utils.h (htab_delete_entry): New template function.
Nelson Chu [Wed, 26 May 2021 02:34:13 +0000 (10:34 +0800)]
RISC-V: Allow to link the objects with unknown prefixed extensions.
Since the policies of GNU and llvm toolchain are different for now,
current binutils mainline cannot accept any draft extensions, including
rvv, zfh, .... The Clang/LLVM allows these draft stuff on mainline,
but the GNU ld might be used with them, so this causes the link time
problems.
The patch allows ld to link the objects with unknown prefixed extensions,
which are probably generated by LLVM or customized toolchains.
bfd/
* elfxx-riscv.h (check_unknown_prefixed_ext): New bool.
* elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the
prefixed extension name if check_unknown_prefixed_ext is false.
* elfnn-riscv.c (riscv_merge_arch_attr_info): Set
check_unknown_prefixed_ext to false for linker.
gas/
* config/tc-riscv.c (riscv_set_arch): Set
check_unknown_prefixed_ext to true for assembler.
Tamar Christina [Tue, 25 May 2021 15:04:04 +0000 (16:04 +0100)]
Arm: Fix forward thumb references [PR gas/25235]
When assembling a forward reference the symbol will be unknown and so during
do_t_adr we cannot set the thumb bit. The bit it set so early to prevent
relaxations that are invalid. i.e. relaxing a Thumb2 to Thumb1 insn when the
symbol is Thumb.
But because it's done so early we miss the case for forward references.
This patch changes it so that we additionally check the thumb bit during the
internal relocation processing.
In principle we should be able to only set the bit during reloc processing but
that would require changes to the other relocations that the instruction could
be relaxed to.
This approach still allows early relaxations (which means that we have less
iteration of internal reloc processing) while still fixing the forward reference
case.
gas/ChangeLog:
2021-05-24 Tamar Christina <tamar.christina@arm.com>
PR gas/25235
* config/tc-arm.c (md_convert_frag): Set LSB when Thumb symbol.
(relax_adr): Thumb symbols 4 bytes.
* testsuite/gas/arm/pr25235.d: New test.
* testsuite/gas/arm/pr25235.s: New test.
Alan Modra [Tue, 25 May 2021 05:36:49 +0000 (15:06 +0930)]
[GOLD] PR27815, gold fails to build with latest GCC
Don't use nullptr, it requires -std=c++11 on versions of gcc prior to
6.1. It would be possible to arrange to pass -std=c++11 automatically
when required (top level configure does that for gcc builds) but that
seems overkill and since we're not up-to-date on the top level config
files would mean someone would need to sync those over.
PR gold/27815
* gc.h (gc_process_relocs): Use cast in Section_id constructor.
projects / thirdparty / binutils-gdb.git / log
