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43e9d192 | 1 | /* Common hooks for AArch64. |
99dee823 | 2 | Copyright (C) 2012-2021 Free Software Foundation, Inc. |
43e9d192 IB |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 3, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
01736018 | 22 | #define INCLUDE_STRING |
43e9d192 IB |
23 | #include "system.h" |
24 | #include "coretypes.h" | |
25 | #include "tm.h" | |
4d0cdd0c | 26 | #include "memmodel.h" |
43e9d192 IB |
27 | #include "tm_p.h" |
28 | #include "common/common-target.h" | |
29 | #include "common/common-target-def.h" | |
30 | #include "opts.h" | |
31 | #include "flags.h" | |
054b4005 | 32 | #include "diagnostic.h" |
43e9d192 IB |
33 | |
34 | #ifdef TARGET_BIG_ENDIAN_DEFAULT | |
35 | #undef TARGET_DEFAULT_TARGET_FLAGS | |
36 | #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END) | |
37 | #endif | |
38 | ||
39 | #undef TARGET_HANDLE_OPTION | |
40 | #define TARGET_HANDLE_OPTION aarch64_handle_option | |
41 | ||
42 | #undef TARGET_OPTION_OPTIMIZATION_TABLE | |
43 | #define TARGET_OPTION_OPTIMIZATION_TABLE aarch_option_optimization_table | |
4ca82fc9 TC |
44 | #undef TARGET_OPTION_INIT_STRUCT |
45 | #define TARGET_OPTION_INIT_STRUCT aarch64_option_init_struct | |
43e9d192 IB |
46 | |
47 | /* Set default optimization options. */ | |
48 | static const struct default_options aarch_option_optimization_table[] = | |
49 | { | |
50 | /* Enable section anchors by default at -O1 or higher. */ | |
51 | { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, | |
af3b4514 RR |
52 | /* Disable fomit-frame-pointer by default. */ |
53 | { OPT_LEVELS_ALL, OPT_fomit_frame_pointer, NULL, 0 }, | |
de72c50f WD |
54 | /* Enable -fsched-pressure by default when optimizing. */ |
55 | { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 }, | |
473cec55 IB |
56 | /* Enable redundant extension instructions removal at -O2 and higher. */ |
57 | { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, | |
b39036d2 RR |
58 | #if (TARGET_DEFAULT_ASYNC_UNWIND_TABLES == 1) |
59 | { OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 }, | |
60 | { OPT_LEVELS_ALL, OPT_funwind_tables, NULL, 1}, | |
61 | #endif | |
8100e93b ML |
62 | { OPT_LEVELS_ALL, OPT__param_stack_clash_protection_guard_size_, NULL, |
63 | DEFAULT_STK_CLASH_GUARD_SIZE == 0 ? 16 : DEFAULT_STK_CLASH_GUARD_SIZE }, | |
64 | ||
43e9d192 IB |
65 | { OPT_LEVELS_NONE, 0, NULL, 0 } |
66 | }; | |
67 | ||
68 | /* Implement TARGET_HANDLE_OPTION. | |
69 | This function handles the target specific options for CPU/target selection. | |
70 | ||
ffee7aa9 JG |
71 | -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU. |
72 | If either of -march or -mtune is given, they override their | |
73 | respective component of -mcpu. This logic is implemented | |
74 | in config/aarch64/aarch64.c:aarch64_override_options. */ | |
43e9d192 | 75 | |
5a2c8331 | 76 | bool |
43e9d192 IB |
77 | aarch64_handle_option (struct gcc_options *opts, |
78 | struct gcc_options *opts_set ATTRIBUTE_UNUSED, | |
79 | const struct cl_decoded_option *decoded, | |
80 | location_t loc ATTRIBUTE_UNUSED) | |
81 | { | |
82 | size_t code = decoded->opt_index; | |
83 | const char *arg = decoded->arg; | |
5a2c8331 | 84 | int val = decoded->value; |
43e9d192 IB |
85 | |
86 | switch (code) | |
87 | { | |
88 | case OPT_march_: | |
89 | opts->x_aarch64_arch_string = arg; | |
43e9d192 IB |
90 | return true; |
91 | ||
92 | case OPT_mcpu_: | |
93 | opts->x_aarch64_cpu_string = arg; | |
43e9d192 IB |
94 | return true; |
95 | ||
96 | case OPT_mtune_: | |
97 | opts->x_aarch64_tune_string = arg; | |
98 | return true; | |
99 | ||
5a2c8331 KT |
100 | case OPT_mgeneral_regs_only: |
101 | opts->x_target_flags |= MASK_GENERAL_REGS_ONLY; | |
102 | return true; | |
103 | ||
104 | case OPT_mfix_cortex_a53_835769: | |
105 | opts->x_aarch64_fix_a53_err835769 = val; | |
106 | return true; | |
107 | ||
108 | case OPT_mstrict_align: | |
675d044c SD |
109 | if (val) |
110 | opts->x_target_flags |= MASK_STRICT_ALIGN; | |
111 | else | |
112 | opts->x_target_flags &= ~MASK_STRICT_ALIGN; | |
5a2c8331 KT |
113 | return true; |
114 | ||
115 | case OPT_momit_leaf_frame_pointer: | |
48090169 | 116 | opts->x_flag_omit_leaf_frame_pointer = val; |
5a2c8331 KT |
117 | return true; |
118 | ||
9e02b45f ML |
119 | case OPT_moutline_atomics: |
120 | opts->x_aarch64_flag_outline_atomics = val; | |
121 | return true; | |
122 | ||
43e9d192 IB |
123 | default: |
124 | return true; | |
125 | } | |
126 | } | |
127 | ||
054b4005 JG |
128 | /* An ISA extension in the co-processor and main instruction set space. */ |
129 | struct aarch64_option_extension | |
130 | { | |
131 | const char *const name; | |
28108a53 MM |
132 | const uint64_t flag_canonical; |
133 | const uint64_t flags_on; | |
134 | const uint64_t flags_off; | |
4ca82fc9 | 135 | const bool is_synthetic; |
054b4005 JG |
136 | }; |
137 | ||
138 | /* ISA extensions in AArch64. */ | |
139 | static const struct aarch64_option_extension all_extensions[] = | |
140 | { | |
4ca82fc9 TC |
141 | #define AARCH64_OPT_EXTENSION(NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, \ |
142 | SYNTHETIC, Z) \ | |
143 | {NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, SYNTHETIC}, | |
144 | #include "config/aarch64/aarch64-option-extensions.def" | |
145 | {NULL, 0, 0, 0, false} | |
146 | }; | |
147 | ||
148 | /* A copy of the ISA extensions list for AArch64 sorted by the popcount of | |
149 | bits and extension turned on. Cached for efficiency. */ | |
150 | static struct aarch64_option_extension all_extensions_by_on[] = | |
151 | { | |
152 | #define AARCH64_OPT_EXTENSION(NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, \ | |
153 | SYNTHETIC, Z) \ | |
154 | {NAME, FLAG_CANONICAL, FLAGS_ON, FLAGS_OFF, SYNTHETIC}, | |
054b4005 | 155 | #include "config/aarch64/aarch64-option-extensions.def" |
4ca82fc9 | 156 | {NULL, 0, 0, 0, false} |
054b4005 JG |
157 | }; |
158 | ||
159 | struct processor_name_to_arch | |
160 | { | |
161 | const std::string processor_name; | |
162 | const enum aarch64_arch arch; | |
28108a53 | 163 | const uint64_t flags; |
054b4005 JG |
164 | }; |
165 | ||
166 | struct arch_to_arch_name | |
167 | { | |
168 | const enum aarch64_arch arch; | |
169 | const std::string arch_name; | |
28108a53 | 170 | const uint64_t flags; |
054b4005 JG |
171 | }; |
172 | ||
173 | /* Map processor names to the architecture revision they implement and | |
174 | the default set of architectural feature flags they support. */ | |
175 | static const struct processor_name_to_arch all_cores[] = | |
176 | { | |
e8fcc9fa | 177 | #define AARCH64_CORE(NAME, X, IDENT, ARCH_IDENT, FLAGS, COSTS, IMP, PART, VARIANT) \ |
054b4005 JG |
178 | {NAME, AARCH64_ARCH_##ARCH_IDENT, FLAGS}, |
179 | #include "config/aarch64/aarch64-cores.def" | |
054b4005 JG |
180 | {"generic", AARCH64_ARCH_8A, AARCH64_FL_FOR_ARCH8}, |
181 | {"", aarch64_no_arch, 0} | |
182 | }; | |
183 | ||
184 | /* Map architecture revisions to their string representation. */ | |
185 | static const struct arch_to_arch_name all_architectures[] = | |
186 | { | |
187 | #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH, FLAGS) \ | |
04a99ebe | 188 | {AARCH64_ARCH_##ARCH_IDENT, NAME, FLAGS}, |
054b4005 | 189 | #include "config/aarch64/aarch64-arches.def" |
04a99ebe | 190 | {aarch64_no_arch, "", 0} |
054b4005 JG |
191 | }; |
192 | ||
04a99ebe JG |
193 | /* Parse the architecture extension string STR and update ISA_FLAGS |
194 | with the architecture features turned on or off. Return a | |
c7887347 ML |
195 | aarch64_parse_opt_result describing the result. |
196 | When the STR string contains an invalid extension, | |
197 | a copy of the string is created and stored to INVALID_EXTENSION. */ | |
04a99ebe JG |
198 | |
199 | enum aarch64_parse_opt_result | |
28108a53 | 200 | aarch64_parse_extension (const char *str, uint64_t *isa_flags, |
c7887347 | 201 | std::string *invalid_extension) |
04a99ebe JG |
202 | { |
203 | /* The extension string is parsed left to right. */ | |
204 | const struct aarch64_option_extension *opt = NULL; | |
205 | ||
206 | /* Flag to say whether we are adding or removing an extension. */ | |
207 | int adding_ext = -1; | |
208 | ||
209 | while (str != NULL && *str != 0) | |
210 | { | |
211 | const char *ext; | |
212 | size_t len; | |
213 | ||
214 | str++; | |
215 | ext = strchr (str, '+'); | |
216 | ||
217 | if (ext != NULL) | |
218 | len = ext - str; | |
219 | else | |
220 | len = strlen (str); | |
221 | ||
222 | if (len >= 2 && strncmp (str, "no", 2) == 0) | |
223 | { | |
224 | adding_ext = 0; | |
225 | len -= 2; | |
226 | str += 2; | |
227 | } | |
228 | else if (len > 0) | |
229 | adding_ext = 1; | |
230 | ||
231 | if (len == 0) | |
232 | return AARCH64_PARSE_MISSING_ARG; | |
233 | ||
234 | ||
235 | /* Scan over the extensions table trying to find an exact match. */ | |
236 | for (opt = all_extensions; opt->name != NULL; opt++) | |
237 | { | |
238 | if (strlen (opt->name) == len && strncmp (opt->name, str, len) == 0) | |
239 | { | |
240 | /* Add or remove the extension. */ | |
241 | if (adding_ext) | |
242 | *isa_flags |= (opt->flags_on | opt->flag_canonical); | |
243 | else | |
244 | *isa_flags &= ~(opt->flags_off | opt->flag_canonical); | |
245 | break; | |
246 | } | |
247 | } | |
248 | ||
249 | if (opt->name == NULL) | |
250 | { | |
251 | /* Extension not found in list. */ | |
c7887347 ML |
252 | if (invalid_extension) |
253 | *invalid_extension = std::string (str, len); | |
04a99ebe JG |
254 | return AARCH64_PARSE_INVALID_FEATURE; |
255 | } | |
256 | ||
257 | str = ext; | |
258 | }; | |
259 | ||
260 | return AARCH64_PARSE_OK; | |
261 | } | |
262 | ||
c7887347 ML |
263 | /* Append all architecture extension candidates to the CANDIDATES vector. */ |
264 | ||
265 | void | |
266 | aarch64_get_all_extension_candidates (auto_vec<const char *> *candidates) | |
267 | { | |
268 | const struct aarch64_option_extension *opt; | |
269 | for (opt = all_extensions; opt->name != NULL; opt++) | |
270 | candidates->safe_push (opt->name); | |
271 | } | |
272 | ||
4ca82fc9 TC |
273 | /* Comparer to sort aarch64's feature extensions by population count. Largest |
274 | first. */ | |
275 | ||
276 | typedef const struct aarch64_option_extension opt_ext; | |
277 | ||
278 | int opt_ext_cmp (const void* a, const void* b) | |
279 | { | |
280 | opt_ext *opt_a = (opt_ext *)a; | |
281 | opt_ext *opt_b = (opt_ext *)b; | |
282 | ||
283 | /* We consider the total set of bits an options turns on to be the union of | |
284 | the singleton set containing the option itself and the set of options it | |
285 | turns on as a dependency. As an example +dotprod turns on FL_DOTPROD and | |
286 | FL_SIMD. As such the set of bits represented by this option is | |
287 | {FL_DOTPROD, FL_SIMD}. */ | |
28108a53 MM |
288 | uint64_t total_flags_a = opt_a->flag_canonical & opt_a->flags_on; |
289 | uint64_t total_flags_b = opt_b->flag_canonical & opt_b->flags_on; | |
4ca82fc9 TC |
290 | int popcnt_a = popcount_hwi ((HOST_WIDE_INT)total_flags_a); |
291 | int popcnt_b = popcount_hwi ((HOST_WIDE_INT)total_flags_b); | |
292 | int order = popcnt_b - popcnt_a; | |
293 | ||
294 | /* If they have the same amount of bits set, give it a more | |
295 | deterministic ordering by using the value of the bits themselves. */ | |
28108a53 MM |
296 | if (order != 0) |
297 | return order; | |
4ca82fc9 | 298 | |
28108a53 MM |
299 | if (total_flags_a != total_flags_b) |
300 | return total_flags_a < total_flags_b ? 1 : -1; | |
301 | ||
302 | return 0; | |
4ca82fc9 TC |
303 | } |
304 | ||
305 | /* Implement TARGET_OPTION_INIT_STRUCT. */ | |
306 | ||
307 | static void | |
308 | aarch64_option_init_struct (struct gcc_options *opts ATTRIBUTE_UNUSED) | |
309 | { | |
310 | /* Sort the extensions based on how many bits they set, order the larger | |
311 | counts first. We sort the list because this makes processing the | |
312 | feature bits O(n) instead of O(n^2). While n is small, the function | |
313 | to calculate the feature strings is called on every options push, | |
314 | pop and attribute change (arm_neon headers, lto etc all cause this to | |
315 | happen quite frequently). It is a trade-off between time and space and | |
316 | so time won. */ | |
317 | int n_extensions | |
318 | = sizeof (all_extensions) / sizeof (struct aarch64_option_extension); | |
319 | qsort (&all_extensions_by_on, n_extensions, | |
320 | sizeof (struct aarch64_option_extension), opt_ext_cmp); | |
321 | } | |
322 | ||
323 | /* Checks to see if enough bits from the option OPT are enabled in | |
324 | ISA_FLAG_BITS to be able to replace the individual options with the | |
325 | canonicalized version of the option. This is done based on two rules: | |
326 | ||
327 | 1) Synthetic groups, such as +crypto we only care about the bits that are | |
328 | turned on. e.g. +aes+sha2 can be replaced with +crypto. | |
329 | ||
330 | 2) Options that themselves have a bit, such as +rdma, in this case, all the | |
331 | feature bits they turn on must be available and the bit for the option | |
332 | itself must be. In this case it's effectively a reduction rather than a | |
333 | grouping. e.g. +fp+simd is not enough to turn on +rdma, for that you would | |
334 | need +rdma+fp+simd which is reduced down to +rdma. | |
335 | */ | |
336 | ||
337 | static bool | |
28108a53 | 338 | aarch64_contains_opt (uint64_t isa_flag_bits, opt_ext *opt) |
4ca82fc9 | 339 | { |
28108a53 | 340 | uint64_t flags_check |
4ca82fc9 TC |
341 | = opt->is_synthetic ? opt->flags_on : opt->flag_canonical; |
342 | ||
343 | return (isa_flag_bits & flags_check) == flags_check; | |
344 | } | |
345 | ||
04a99ebe JG |
346 | /* Return a string representation of ISA_FLAGS. DEFAULT_ARCH_FLAGS |
347 | gives the default set of flags which are implied by whatever -march | |
348 | we'd put out. Our job is to figure out the minimal set of "+" and | |
349 | "+no" feature flags to put out, and to put them out grouped such | |
350 | that all the "+" flags come before the "+no" flags. */ | |
054b4005 JG |
351 | |
352 | std::string | |
28108a53 MM |
353 | aarch64_get_extension_string_for_isa_flags (uint64_t isa_flags, |
354 | uint64_t default_arch_flags) | |
054b4005 JG |
355 | { |
356 | const struct aarch64_option_extension *opt = NULL; | |
357 | std::string outstr = ""; | |
358 | ||
28108a53 | 359 | uint64_t isa_flag_bits = isa_flags; |
04a99ebe | 360 | |
4ca82fc9 TC |
361 | /* Pass one: Minimize the search space by reducing the set of options |
362 | to the smallest set that still turns on the same features as before in | |
363 | conjunction with the bits that are turned on by default for the selected | |
364 | architecture. */ | |
365 | for (opt = all_extensions_by_on; opt->name != NULL; opt++) | |
366 | { | |
367 | /* If the bit is on by default, then all the options it turns on are also | |
368 | on by default due to the transitive dependencies. | |
369 | ||
370 | If the option is enabled explicitly in the set then we need to emit | |
371 | an option for it. Since this list is sorted by extensions setting the | |
372 | largest number of featers first, we can be sure that nothing else will | |
373 | ever need to set the bits we already set. Consider the following | |
374 | situation: | |
375 | ||
376 | Feat1 = A + B + C | |
377 | Feat2 = A + B | |
378 | Feat3 = A + D | |
379 | Feat4 = B + C | |
380 | Feat5 = C | |
381 | ||
382 | The following results are expected: | |
383 | ||
384 | A + C = A + Feat5 | |
385 | B + C = Feat4 | |
386 | Feat4 + A = Feat1 | |
387 | Feat2 + Feat5 = Feat1 | |
388 | Feat1 + C = Feat1 | |
389 | Feat3 + Feat4 = Feat1 + D | |
390 | ||
391 | This search assumes that all invidual feature bits are use visible, | |
392 | in other words the user must be able to do +A, +B, +C and +D. */ | |
393 | if (aarch64_contains_opt (isa_flag_bits | default_arch_flags, opt)) | |
04a99ebe | 394 | { |
4ca82fc9 TC |
395 | /* We remove all the dependent bits, to prevent them from being turned |
396 | on twice. This only works because we assume that all there are | |
397 | individual options to set all bits standalone. */ | |
53161358 TC |
398 | |
399 | /* PR target/94396. | |
400 | ||
401 | For flags which would already imply a bit that's on by default (e.g | |
402 | fp16fml which implies +fp,+fp16) we must emit the flags that are not | |
403 | on by default. i.e. in Armv8.4-a +fp16fml is default if +fp16. So | |
404 | if a user passes armv8.4-a+fp16 (or +fp16fml) then we need to emit | |
405 | +fp16. But if +fp16fml is used in an architecture where it is | |
406 | completely optional we only have to emit the canonical flag. */ | |
407 | uint64_t toggle_bits = opt->flags_on & default_arch_flags; | |
408 | /* Now check to see if the canonical flag is on by default. If it | |
409 | is not then enabling it will enable all bits in flags_on. */ | |
410 | if ((opt->flag_canonical & default_arch_flags) == 0) | |
411 | toggle_bits = opt->flags_on; | |
412 | ||
413 | isa_flag_bits &= ~toggle_bits; | |
4ca82fc9 | 414 | isa_flag_bits |= opt->flag_canonical; |
04a99ebe | 415 | } |
4ca82fc9 TC |
416 | } |
417 | ||
418 | /* By toggling bits on and off, we may have set bits on that are already | |
419 | enabled by default. So we mask the default set out so we don't emit an | |
420 | option for them. Instead of checking for this each time during Pass One | |
421 | we just mask all default bits away at the end. */ | |
422 | isa_flag_bits &= ~default_arch_flags; | |
423 | ||
424 | /* We now have the smallest set of features we need to process. A subsequent | |
425 | linear scan of the bits in isa_flag_bits will allow us to print the ext | |
426 | names. However as a special case if CRC was enabled before, always print | |
427 | it. This is required because some CPUs have an incorrect specification | |
428 | in older assemblers. Even though CRC should be the default for these | |
786177a3 AC |
429 | cases the -mcpu values won't turn it on. |
430 | ||
431 | Note that assemblers with Armv8-R AArch64 support should not have this | |
432 | issue, so we don't need this fix when targeting Armv8-R. */ | |
433 | if ((isa_flags & AARCH64_ISA_CRC) && !AARCH64_ISA_V8_R) | |
4ca82fc9 TC |
434 | isa_flag_bits |= AARCH64_ISA_CRC; |
435 | ||
436 | /* Pass Two: | |
437 | Print the option names that we're sure we must turn on. These are only | |
438 | optional extension names. Mandatory ones have already been removed and | |
439 | ones we explicitly want off have been too. */ | |
440 | for (opt = all_extensions_by_on; opt->name != NULL; opt++) | |
441 | { | |
442 | if (isa_flag_bits & opt->flag_canonical) | |
443 | { | |
444 | outstr += "+"; | |
445 | outstr += opt->name; | |
446 | } | |
447 | } | |
448 | ||
449 | /* Pass Three: | |
450 | Print out a +no for any mandatory extension that we are | |
451 | turning off. By this point aarch64_parse_extension would have ensured | |
452 | that any optional extensions are turned off. The only things left are | |
453 | things that can't be turned off usually, e.g. something that is on by | |
454 | default because it's mandatory and we want it off. For turning off bits | |
455 | we don't guarantee the smallest set of flags, but instead just emit all | |
456 | options the user has specified. | |
457 | ||
458 | The assembler requires all +<opts> to be printed before +no<opts>. */ | |
459 | for (opt = all_extensions_by_on; opt->name != NULL; opt++) | |
460 | { | |
461 | if ((~isa_flags) & opt->flag_canonical | |
462 | && !((~default_arch_flags) & opt->flag_canonical)) | |
463 | { | |
464 | outstr += "+no"; | |
465 | outstr += opt->name; | |
466 | } | |
467 | } | |
04a99ebe | 468 | |
054b4005 JG |
469 | return outstr; |
470 | } | |
682287fb | 471 | |
054b4005 JG |
472 | /* Attempt to rewrite NAME, which has been passed on the command line |
473 | as a -mcpu option to an equivalent -march value. If we can do so, | |
474 | return the new string, otherwise return an error. */ | |
682287fb JG |
475 | |
476 | const char * | |
477 | aarch64_rewrite_selected_cpu (const char *name) | |
478 | { | |
054b4005 | 479 | std::string original_string (name); |
04a99ebe | 480 | std::string extension_str; |
054b4005 JG |
481 | std::string processor; |
482 | size_t extension_pos = original_string.find_first_of ('+'); | |
682287fb | 483 | |
054b4005 JG |
484 | /* Strip and save the extension string. */ |
485 | if (extension_pos != std::string::npos) | |
486 | { | |
487 | processor = original_string.substr (0, extension_pos); | |
04a99ebe JG |
488 | extension_str = original_string.substr (extension_pos, |
489 | std::string::npos); | |
054b4005 JG |
490 | } |
491 | else | |
492 | { | |
493 | /* No extensions. */ | |
494 | processor = original_string; | |
495 | } | |
efb25f54 | 496 | |
054b4005 JG |
497 | const struct processor_name_to_arch* p_to_a; |
498 | for (p_to_a = all_cores; | |
499 | p_to_a->arch != aarch64_no_arch; | |
500 | p_to_a++) | |
501 | { | |
502 | if (p_to_a->processor_name == processor) | |
503 | break; | |
504 | } | |
efb25f54 | 505 | |
054b4005 JG |
506 | const struct arch_to_arch_name* a_to_an; |
507 | for (a_to_an = all_architectures; | |
508 | a_to_an->arch != aarch64_no_arch; | |
509 | a_to_an++) | |
510 | { | |
511 | if (a_to_an->arch == p_to_a->arch) | |
512 | break; | |
513 | } | |
682287fb | 514 | |
054b4005 JG |
515 | /* We couldn't find that proceesor name, or the processor name we |
516 | found does not map to an architecture we understand. */ | |
517 | if (p_to_a->arch == aarch64_no_arch | |
518 | || a_to_an->arch == aarch64_no_arch) | |
a3f9f006 | 519 | fatal_error (input_location, "unknown value %qs for %<-mcpu%>", name); |
054b4005 | 520 | |
1ec77eed | 521 | uint64_t extensions = p_to_a->flags; |
c7887347 | 522 | aarch64_parse_extension (extension_str.c_str (), &extensions, NULL); |
04a99ebe | 523 | |
054b4005 | 524 | std::string outstr = a_to_an->arch_name |
04a99ebe JG |
525 | + aarch64_get_extension_string_for_isa_flags (extensions, |
526 | a_to_an->flags); | |
054b4005 JG |
527 | |
528 | /* We are going to memory leak here, nobody elsewhere | |
529 | in the callchain is going to clean up after us. The alternative is | |
530 | to allocate a static buffer, and assert that it is big enough for our | |
531 | modified string, which seems much worse! */ | |
532 | return xstrdup (outstr.c_str ()); | |
682287fb JG |
533 | } |
534 | ||
535 | /* Called by the driver to rewrite a name passed to the -mcpu | |
536 | argument in preparation to be passed to the assembler. The | |
1c05df59 JG |
537 | names passed from the commend line will be in ARGV, we want |
538 | to use the right-most argument, which should be in | |
539 | ARGV[ARGC - 1]. ARGC should always be greater than 0. */ | |
682287fb JG |
540 | |
541 | const char * | |
542 | aarch64_rewrite_mcpu (int argc, const char **argv) | |
543 | { | |
1c05df59 JG |
544 | gcc_assert (argc); |
545 | return aarch64_rewrite_selected_cpu (argv[argc - 1]); | |
682287fb JG |
546 | } |
547 | ||
4ca82fc9 TC |
548 | struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; |
549 | ||
682287fb JG |
550 | #undef AARCH64_CPU_NAME_LENGTH |
551 |