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Merge tree-ssa-20020619-branch into mainline.
[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
CommitLineData
340f6494 1/* Subroutines for insn-output.c for Renesas H8/300.
aefc5826 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
6d6b0a12 3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
48837e29
DE		 4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
07aae5c2 6
8aa063fb 7This file is part of GCC.
07aae5c2 8
8aa063fb 9GCC is free software; you can redistribute it and/or modify
07aae5c2
SC		 10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
8aa063fb 14GCC is distributed in the hope that it will be useful,
07aae5c2
SC		 15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
8aa063fb 20along with GCC; see the file COPYING. If not, write to
97aadbb9
RK		 21the Free Software Foundation, 59 Temple Place - Suite 330,
22Boston, MA 02111-1307, USA. */
07aae5c2 23
07aae5c2 24#include "config.h"
c5c76735 25#include "system.h"
4977bab6
ZW		 26#include "coretypes.h"
27#include "tm.h"
07aae5c2 28#include "rtl.h"
bf6bb899 29#include "tree.h"
07aae5c2
SC		 30#include "regs.h"
31#include "hard-reg-set.h"
32#include "real.h"
33#include "insn-config.h"
34#include "conditions.h"
07aae5c2
SC		 35#include "output.h"
36#include "insn-attr.h"
37#include "flags.h"
38#include "recog.h"
39#include "expr.h"
bf6bb899 40#include "function.h"
c15c90bb 41#include "optabs.h"
441d04c6 42#include "toplev.h"
8b97c5f8 43#include "c-pragma.h"
441d04c6 44#include "tm_p.h"
f2a9645f 45#include "ggc.h"
672a6f42
NB		 46#include "target.h"
47#include "target-def.h"
07aae5c2
SC		 48
49/* Forward declarations. */
cb713a8d
KH		 50static const char *byte_reg (rtx, int);
51static int h8300_interrupt_function_p (tree);
3cfa3702 52static int h8300_saveall_function_p (tree);
cb713a8d
KH		 53static int h8300_monitor_function_p (tree);
54static int h8300_os_task_function_p (tree);
81ad9ded 55static void h8300_emit_stack_adjustment (int, unsigned int);
cb713a8d
KH		 56static int round_frame_size (int);
57static unsigned int compute_saved_regs (void);
58static void push (int);
59static void pop (int);
60static const char *cond_string (enum rtx_code);
61static unsigned int h8300_asm_insn_count (const char *);
cb713a8d
KH		 62static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
63static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
64static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
ede75ee8 65#ifndef OBJECT_FORMAT_ELF
cb713a8d 66static void h8300_asm_named_section (const char *, unsigned int);
ede75ee8 67#endif
cb713a8d
KH		 68static int h8300_and_costs (rtx);
69static int h8300_shift_costs (rtx);
f5b65a56 70
48837e29
DE		 71/* CPU_TYPE, says what cpu we're compiling for. */
72int cpu_type;
73
e392d367
KH		 74/* True if a #pragma interrupt has been seen for the current function. */
75static int pragma_interrupt;
07aae5c2
SC		 76
77/* True if a #pragma saveall has been seen for the current function. */
0869f126 78static int pragma_saveall;
07aae5c2 79
441d04c6 80static const char *const names_big[] =
07e4d94e 81{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
48837e29 82
441d04c6 83static const char *const names_extended[] =
07e4d94e 84{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
48837e29 85
441d04c6 86static const char *const names_upper_extended[] =
07e4d94e 87{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
48837e29
DE		 88
89/* Points to one of the above. */
90/* ??? The above could be put in an array indexed by CPU_TYPE. */
441d04c6 91const char * const *h8_reg_names;
48837e29
DE		 92
93/* Various operations needed by the following, indexed by CPU_TYPE. */
48837e29 94
441d04c6 95const char *h8_push_op, *h8_pop_op, *h8_mov_op;
dc66a1c4
RH		 96
97/* Machine-specific symbol_ref flags. */
98#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
99#define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
100#define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
672a6f42 101\f
c4dfc70c
DD		 102/* See below where shifts are handled for explanation of this enum. */
103
104enum shift_alg
105{
106 SHIFT_INLINE,
107 SHIFT_ROT_AND,
108 SHIFT_SPECIAL,
109 SHIFT_LOOP
110};
111
112/* Symbols of the various shifts which can be used as indices. */
113
114enum shift_type
115{
116 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
117};
118
119/* Macros to keep the shift algorithm tables small. */
120#define INL SHIFT_INLINE
121#define ROT SHIFT_ROT_AND
122#define LOP SHIFT_LOOP
123#define SPC SHIFT_SPECIAL
124
125/* The shift algorithms for each machine, mode, shift type, and shift
126 count are defined below. The three tables below correspond to
127 QImode, HImode, and SImode, respectively. Each table is organized
f411c849 128 by, in the order of indices, machine, shift type, and shift count. */
c4dfc70c
DD		 129
130static enum shift_alg shift_alg_qi[3][3][8] = {
131 {
132 /* TARGET_H8300 */
133 /* 0 1 2 3 4 5 6 7 */
134 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
135 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
136 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
137 },
138 {
139 /* TARGET_H8300H */
140 /* 0 1 2 3 4 5 6 7 */
141 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
142 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
143 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
144 },
145 {
146 /* TARGET_H8300S */
147 /* 0 1 2 3 4 5 6 7 */
148 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
149 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
150 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
151 }
152};
153
154static enum shift_alg shift_alg_hi[3][3][16] = {
155 {
156 /* TARGET_H8300 */
157 /* 0 1 2 3 4 5 6 7 */
158 /* 8 9 10 11 12 13 14 15 */
159 { INL, INL, INL, INL, INL, INL, INL, SPC,
160 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
161 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
162 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
163 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
164 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
165 },
166 {
167 /* TARGET_H8300H */
168 /* 0 1 2 3 4 5 6 7 */
169 /* 8 9 10 11 12 13 14 15 */
170 { INL, INL, INL, INL, INL, INL, INL, SPC,
171 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, INL, SPC,
173 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC,
175 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
176 },
177 {
178 /* TARGET_H8300S */
179 /* 0 1 2 3 4 5 6 7 */
180 /* 8 9 10 11 12 13 14 15 */
181 { INL, INL, INL, INL, INL, INL, INL, INL,
182 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
183 { INL, INL, INL, INL, INL, INL, INL, INL,
184 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
185 { INL, INL, INL, INL, INL, INL, INL, INL,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
187 }
188};
189
190static enum shift_alg shift_alg_si[3][3][32] = {
191 {
192 /* TARGET_H8300 */
193 /* 0 1 2 3 4 5 6 7 */
194 /* 8 9 10 11 12 13 14 15 */
195 /* 16 17 18 19 20 21 22 23 */
196 /* 24 25 26 27 28 29 30 31 */
197 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
198 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
199 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
200 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
201 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
202 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
203 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
204 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
206 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
207 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
208 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
209 },
210 {
211 /* TARGET_H8300H */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 /* 16 17 18 19 20 21 22 23 */
215 /* 24 25 26 27 28 29 30 31 */
216 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
217 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
218 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 219 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 220 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
222 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
1e5bdc40 223 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 224 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
225 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
227 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
228 },
229 {
230 /* TARGET_H8300S */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 /* 16 17 18 19 20 21 22 23 */
234 /* 24 25 26 27 28 29 30 31 */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
237 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 238 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
c4dfc70c
DD		 239 { INL, INL, INL, INL, INL, INL, INL, INL,
240 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
1e5bdc40 242 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
c4dfc70c
DD		 243 { INL, INL, INL, INL, INL, INL, INL, INL,
244 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
247 }
248};
249
250#undef INL
251#undef ROT
252#undef LOP
253#undef SPC
254
255enum h8_cpu
256{
257 H8_300,
258 H8_300H,
259 H8_S
260};
261
48837e29
DE		 262/* Initialize various cpu specific globals at start up. */
263
264void
cb713a8d 265h8300_init_once (void)
48837e29 266{
cbf1b2da
KH		 267 static const char *const h8_push_ops[2] = { "push" , "push.l" };
268 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
269 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
270
48837e29
DE		 271 if (TARGET_H8300)
272 {
273 cpu_type = (int) CPU_H8300;
274 h8_reg_names = names_big;
275 }
276 else
277 {
3db11b5c 278 /* For this we treat the H8/300H and H8S the same. */
48837e29
DE		 279 cpu_type = (int) CPU_H8300H;
280 h8_reg_names = names_extended;
281 }
282 h8_push_op = h8_push_ops[cpu_type];
283 h8_pop_op = h8_pop_ops[cpu_type];
284 h8_mov_op = h8_mov_ops[cpu_type];
17f0f8fa
KH		 285
286 if (!TARGET_H8300S && TARGET_MAC)
400500c4 287 {
c725bd79 288 error ("-ms2600 is used without -ms");
ec5b0c68 289 target_flags |= MASK_H8300S;
400500c4 290 }
920e86b8 291
39ba95b5
VK		 292 if (TARGET_H8300 && TARGET_NORMAL_MODE)
293 {
92d4b8a0 294 error ("-mn is used without -mh or -ms");
39ba95b5
VK		 295 target_flags ^= MASK_NORMAL_MODE;
296 }
c4dfc70c 297
8bd06267 298 /* Some of the shifts are optimized for speed by default.
c4dfc70c 299 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
8bd06267 300 If optimizing for size, change shift_alg for those shift to
c4dfc70c 301 SHIFT_LOOP. */
b6894857 302 if (optimize_size)
c4dfc70c 303 {
b6894857
KH		 304 /* H8/300 */
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
307 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
308 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
c4dfc70c 309
b6894857
KH		 310 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
311 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 312
b6894857
KH		 313 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
314 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 315
b6894857
KH		 316 /* H8/300H */
317 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
318 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
c4dfc70c 319
b6894857
KH		 320 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
321 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
c4dfc70c 322
b6894857
KH		 323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
325 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
326 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c
DD		 327
328 /* H8S */
b6894857 329 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
c4dfc70c 330 }
48837e29 331}
07aae5c2 332
e9eba255
KH		 333/* Return the byte register name for a register rtx X. B should be 0
334 if you want a lower byte register. B should be 1 if you want an
335 upper byte register. */
336
9c188705 337static const char *
cb713a8d 338byte_reg (rtx x, int b)
07aae5c2 339{
9cbcd983
KH		 340 static const char *const names_small[] = {
341 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
342 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
343 };
07aae5c2 344
500fc80f
KH		 345 if (!REG_P (x))
346 abort ();
347
07aae5c2
SC		 348 return names_small[REGNO (x) * 2 + b];
349}
350
351/* REGNO must be saved/restored across calls if this macro is true. */
48837e29 352
9cbcd983 353#define WORD_REG_USED(regno) \
d60004ee 354 (regno < SP_REG \
9cbcd983
KH		 355 /* No need to save registers if this function will not return. */ \
356 && ! TREE_THIS_VOLATILE (current_function_decl) \
3cfa3702 357 && (h8300_saveall_function_p (current_function_decl) \
9cbcd983
KH		 358 /* Save any call saved register that was used. */ \
359 || (regs_ever_live[regno] && !call_used_regs[regno]) \
360 /* Save the frame pointer if it was used. */ \
1807b726 361 || (regno == HARD_FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
9cbcd983 362 /* Save any register used in an interrupt handler. */ \
e392d367
KH		 363 || (h8300_current_function_interrupt_function_p () \
364 && regs_ever_live[regno]) \
9cbcd983
KH		 365 /* Save call clobbered registers in non-leaf interrupt \
366 handlers. */ \
e392d367 367 || (h8300_current_function_interrupt_function_p () \
9cbcd983 368 && call_used_regs[regno] \
fc80ea73 369 && !current_function_is_leaf)))
07aae5c2
SC		 370
371/* Output assembly language to FILE for the operation OP with operand size
48837e29 372 SIZE to adjust the stack pointer. */
48837e29 373
07aae5c2 374static void
81ad9ded 375h8300_emit_stack_adjustment (int sign, unsigned int size)
07aae5c2 376{
72b1de44
KH		 377 /* If the frame size is 0, we don't have anything to do. */
378 if (size == 0)
f8b58e56 379 return;
72b1de44 380
68ee6df6
KH		 381 /* H8/300 cannot add/subtract a large constant with a single
382 instruction. If a temporary register is available, load the
383 constant to it and then do the addition. */
384 if (TARGET_H8300
385 && size > 4
386 && !h8300_current_function_interrupt_function_p ()
6de9cd9a 387 && !(cfun->static_chain_decl != NULL && sign < 0))
f8f26adc 388 {
68ee6df6 389 rtx r3 = gen_rtx_REG (Pmode, 3);
72b1de44
KH		 390 emit_insn (gen_movhi (r3, GEN_INT (sign * size)));
391 emit_insn (gen_addhi3 (stack_pointer_rtx,
392 stack_pointer_rtx, r3));
7b3d4613
KH		 393 }
394 else
395 {
68ee6df6
KH		 396 /* The stack adjustment made here is further optimized by the
397 splitter. In case of H8/300, the splitter always splits the
398 addition emitted here to make the adjustment
399 interrupt-safe. */
72b1de44
KH		 400 if (Pmode == HImode)
401 emit_insn (gen_addhi3 (stack_pointer_rtx,
402 stack_pointer_rtx, GEN_INT (sign * size)));
403 else
404 emit_insn (gen_addsi3 (stack_pointer_rtx,
405 stack_pointer_rtx, GEN_INT (sign * size)));
07aae5c2
SC		 406 }
407}
408
8682223f
KH		 409/* Round up frame size SIZE. */
410
411static int
cb713a8d 412round_frame_size (int size)
8682223f 413{
489eda65
KH		 414 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
415 & -STACK_BOUNDARY / BITS_PER_UNIT);
8682223f
KH		 416}
417
418/* Compute which registers to push/pop.
419 Return a bit vector of registers. */
420
421static unsigned int
cb713a8d 422compute_saved_regs (void)
8682223f
KH		 423{
424 unsigned int saved_regs = 0;
425 int regno;
426
427 /* Construct a bit vector of registers to be pushed/popped. */
1807b726 428 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
8682223f
KH		 429 {
430 if (WORD_REG_USED (regno))
431 saved_regs |= 1 << regno;
432 }
433
434 /* Don't push/pop the frame pointer as it is treated separately. */
435 if (frame_pointer_needed)
1807b726 436 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
8682223f
KH		 437
438 return saved_regs;
439}
440
68ee6df6 441/* Emit an insn to push register RN. */
8682223f
KH		 442
443static void
cb713a8d 444push (int rn)
8682223f 445{
68ee6df6
KH		 446 rtx reg = gen_rtx_REG (word_mode, rn);
447 rtx x;
448
513f31eb 449 if (TARGET_H8300)
68ee6df6 450 x = gen_push_h8300 (reg);
f24f0897 451 else if (!TARGET_NORMAL_MODE)
32da7865 452 x = gen_push_h8300hs_advanced (reg);
f24f0897
KH		 453 else
454 x = gen_push_h8300hs_normal (reg);
68ee6df6
KH		 455 x = emit_insn (x);
456 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
8682223f
KH		 457}
458
68ee6df6 459/* Emit an insn to pop register RN. */
8682223f
KH		 460
461static void
cb713a8d 462pop (int rn)
8682223f 463{
68ee6df6
KH		 464 rtx reg = gen_rtx_REG (word_mode, rn);
465 rtx x;
466
513f31eb 467 if (TARGET_H8300)
68ee6df6 468 x = gen_pop_h8300 (reg);
f24f0897 469 else if (!TARGET_NORMAL_MODE)
32da7865 470 x = gen_pop_h8300hs_advanced (reg);
f24f0897
KH		 471 else
472 x = gen_pop_h8300hs_normal (reg);
68ee6df6
KH		 473 x = emit_insn (x);
474 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
8682223f 475}
07aae5c2 476
f0b6f9a6 477/* This is what the stack looks like after the prolog of
07aae5c2
SC		 478 a function with a frame has been set up:
479
48837e29
DE		 480 <args>
481 PC
482 FP <- fp
483 <locals>
8bd06267 484 <saved registers> <- sp
07aae5c2
SC		 485
486 This is what the stack looks like after the prolog of
487 a function which doesn't have a frame:
488
48837e29
DE		 489 <args>
490 PC
491 <locals>
8bd06267 492 <saved registers> <- sp
07aae5c2
SC		 493*/
494
68ee6df6 495/* Generate RTL code for the function prologue. */
8682223f 496
68ee6df6 497void
cb713a8d 498h8300_expand_prologue (void)
07aae5c2 499{
e651d484 500 int regno;
8682223f 501 int saved_regs;
cda4bd43 502 int n_regs;
07aae5c2 503
fabe72bb
JL		 504 /* If the current function has the OS_Task attribute set, then
505 we have a naked prologue. */
506 if (h8300_os_task_function_p (current_function_decl))
68ee6df6 507 return;
fabe72bb
JL		 508
509 if (h8300_monitor_function_p (current_function_decl))
68ee6df6
KH		 510 /* My understanding of monitor functions is they act just like
511 interrupt functions, except the prologue must mask
512 interrupts. */
513 emit_insn (gen_monitor_prologue ());
fabe72bb 514
48837e29
DE		 515 if (frame_pointer_needed)
516 {
07e4d94e 517 /* Push fp. */
1807b726 518 push (HARD_FRAME_POINTER_REGNUM);
6552458a 519 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
a1616dd9 520 }
48837e29 521
8682223f
KH		 522 /* Push the rest of the registers in ascending order. */
523 saved_regs = compute_saved_regs ();
e651d484 524 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
cda4bd43 525 {
cda4bd43 526 n_regs = 1;
8682223f 527 if (saved_regs & (1 << regno))
a1616dd9
JL		 528 {
529 if (TARGET_H8300S)
530 {
cda4bd43
KH		 531 /* See how many registers we can push at the same time. */
532 if ((regno == 0 || regno == 4)
8682223f 533 && ((saved_regs >> regno) & 0x0f) == 0x0f)
cda4bd43
KH		 534 n_regs = 4;
535
536 else if ((regno == 0 || regno == 4)
8682223f 537 && ((saved_regs >> regno) & 0x07) == 0x07)
cda4bd43
KH		 538 n_regs = 3;
539
540 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
8682223f 541 && ((saved_regs >> regno) & 0x03) == 0x03)
cda4bd43 542 n_regs = 2;
a1616dd9 543 }
cda4bd43 544
e8a68017
KH		 545 switch (n_regs)
546 {
547 case 1:
68ee6df6 548 push (regno);
e8a68017
KH		 549 break;
550 case 2:
68ee6df6
KH		 551 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
552 gen_rtx_REG (SImode, regno + 1)));
e8a68017
KH		 553 break;
554 case 3:
68ee6df6
KH		 555 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
556 gen_rtx_REG (SImode, regno + 1),
557 gen_rtx_REG (SImode, regno + 2)));
e8a68017
KH		 558 break;
559 case 4:
68ee6df6
KH		 560 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
561 gen_rtx_REG (SImode, regno + 1),
562 gen_rtx_REG (SImode, regno + 2),
563 gen_rtx_REG (SImode, regno + 3)));
e8a68017
KH		 564 break;
565 default:
566 abort ();
567 }
07aae5c2
SC		 568 }
569 }
1807b726
KH		 570
571 /* Leave room for locals. */
572 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
07aae5c2
SC		 573}
574
e9eba255
KH		 575/* Return nonzero if we can use "rts" for the function currently being
576 compiled. */
577
68ee6df6 578int
cb713a8d 579h8300_can_use_return_insn_p (void)
68ee6df6
KH		 580{
581 return (reload_completed
582 && !frame_pointer_needed
583 && get_frame_size () == 0
584 && compute_saved_regs () == 0);
585}
07aae5c2 586
68ee6df6
KH		 587/* Generate RTL code for the function epilogue. */
588
589void
cb713a8d 590h8300_expand_epilogue (void)
07aae5c2 591{
e651d484 592 int regno;
8682223f 593 int saved_regs;
cda4bd43 594 int n_regs;
07aae5c2 595
e392d367 596 if (h8300_os_task_function_p (current_function_decl))
68ee6df6
KH		 597 /* OS_Task epilogues are nearly naked -- they just have an
598 rts instruction. */
599 return;
07aae5c2 600
1807b726
KH		 601 /* Deallocate locals. */
602 h8300_emit_stack_adjustment (1, round_frame_size (get_frame_size ()));
603
8682223f
KH		 604 /* Pop the saved registers in descending order. */
605 saved_regs = compute_saved_regs ();
e651d484 606 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
cda4bd43 607 {
cda4bd43 608 n_regs = 1;
8682223f 609 if (saved_regs & (1 << regno))
07aae5c2 610 {
a1616dd9
JL		 611 if (TARGET_H8300S)
612 {
cda4bd43
KH		 613 /* See how many registers we can pop at the same time. */
614 if ((regno == 7 || regno == 3)
8682223f 615 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
cda4bd43
KH		 616 n_regs = 4;
617
618 else if ((regno == 6 || regno == 2)
8682223f 619 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
cda4bd43
KH		 620 n_regs = 3;
621
622 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
8682223f 623 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
cda4bd43 624 n_regs = 2;
a1616dd9 625 }
cda4bd43 626
e8a68017
KH		 627 switch (n_regs)
628 {
629 case 1:
68ee6df6 630 pop (regno);
e8a68017
KH		 631 break;
632 case 2:
68ee6df6
KH		 633 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
634 gen_rtx_REG (SImode, regno)));
e8a68017
KH		 635 break;
636 case 3:
68ee6df6
KH		 637 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
638 gen_rtx_REG (SImode, regno - 1),
639 gen_rtx_REG (SImode, regno)));
e8a68017
KH		 640 break;
641 case 4:
68ee6df6
KH		 642 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
643 gen_rtx_REG (SImode, regno - 2),
644 gen_rtx_REG (SImode, regno - 1),
645 gen_rtx_REG (SImode, regno)));
e8a68017
KH		 646 break;
647 default:
648 abort ();
649 }
07aae5c2 650 }
07aae5c2 651 }
48837e29 652
07e4d94e 653 /* Pop frame pointer if we had one. */
a1616dd9 654 if (frame_pointer_needed)
1807b726 655 pop (HARD_FRAME_POINTER_REGNUM);
68ee6df6 656}
a1616dd9 657
e392d367
KH		 658/* Return nonzero if the current function is an interrupt
659 function. */
660
661int
cb713a8d 662h8300_current_function_interrupt_function_p (void)
e392d367
KH		 663{
664 return (h8300_interrupt_function_p (current_function_decl)
665 || h8300_monitor_function_p (current_function_decl));
666}
667
48837e29
DE		 668/* Output assembly code for the start of the file. */
669
1bc7c5b6
ZW		 670static void
671h8300_file_start (void)
48837e29 672{
1bc7c5b6 673 default_file_start ();
8bd06267 674
48837e29 675 if (TARGET_H8300H)
1bc7c5b6 676 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
a1616dd9 677 else if (TARGET_H8300S)
1bc7c5b6 678 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
48837e29
DE		 679}
680
681/* Output assembly language code for the end of file. */
682
a5fe455b 683static void
cb713a8d 684h8300_file_end (void)
48837e29 685{
a5fe455b 686 fputs ("\t.end\n", asm_out_file);
07aae5c2
SC		 687}
688\f
68560db3 689/* Return true if OP is a valid source operand for an integer move
07aae5c2 690 instruction. */
48837e29 691
07aae5c2 692int
cb713a8d 693general_operand_src (rtx op, enum machine_mode mode)
07aae5c2 694{
ff6e1a2f
KH		 695 if (GET_MODE (op) == mode
696 && GET_CODE (op) == MEM
697 && GET_CODE (XEXP (op, 0)) == POST_INC)
48837e29 698 return 1;
07aae5c2
SC		 699 return general_operand (op, mode);
700}
701
702/* Return true if OP is a valid destination operand for an integer move
5660465a 703 instruction. */
48837e29 704
07aae5c2 705int
cb713a8d 706general_operand_dst (rtx op, enum machine_mode mode)
07aae5c2 707{
ff6e1a2f
KH		 708 if (GET_MODE (op) == mode
709 && GET_CODE (op) == MEM
710 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
48837e29 711 return 1;
07aae5c2
SC		 712 return general_operand (op, mode);
713}
48837e29 714
4d4d89e2
KH		 715/* Return true if OP is a constant that contains only one 1 in its
716 binary representation. */
48837e29
DE		 717
718int
cb713a8d 719single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
48837e29 720{
4d4d89e2
KH		 721 if (GET_CODE (operand) == CONST_INT)
722 {
723 /* We really need to do this masking because 0x80 in QImode is
724 represented as -128 for example. */
ef378bbe 725 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
4d4d89e2
KH		 726 return 1;
727 }
728
729 return 0;
730}
731
732/* Return true if OP is a constant that contains only one 0 in its
733 binary representation. */
734
735int
cb713a8d 736single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
4d4d89e2
KH		 737{
738 if (GET_CODE (operand) == CONST_INT)
739 {
740 /* We really need to do this masking because 0x80 in QImode is
741 represented as -128 for example. */
ef378bbe 742 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
4d4d89e2
KH		 743 return 1;
744 }
745
746 return 0;
48837e29
DE		 747}
748
48837e29
DE		 749/* Return true if OP is a valid call operand. */
750
751int
cb713a8d 752call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
48837e29
DE		 753{
754 if (GET_CODE (op) == MEM)
755 {
756 rtx inside = XEXP (op, 0);
757 if (register_operand (inside, Pmode))
758 return 1;
759 if (CONSTANT_ADDRESS_P (inside))
760 return 1;
761 }
762 return 0;
763}
764
22c9a795 765/* Return 1 if an addition/subtraction of a constant integer can be
997e5af8 766 transformed into two consecutive adds/subs that are faster than the
22c9a795 767 straightforward way. Otherwise, return 0. */
997e5af8 768
3b7d443c 769int
cb713a8d 770two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
3b7d443c
JL		 771{
772 if (GET_CODE (op) == CONST_INT)
773 {
009ac3d3 774 HOST_WIDE_INT value = INTVAL (op);
3b7d443c 775
997e5af8
KH		 776 /* Force VALUE to be positive so that we do not have to consider
777 the negative case. */
778 if (value < 0)
779 value = -value;
009ac3d3
RH		 780 if (TARGET_H8300H || TARGET_H8300S)
781 {
997e5af8
KH		 782 /* A constant addition/subtraction takes 2 states in QImode,
783 4 states in HImode, and 6 states in SImode. Thus, the
784 only case we can win is when SImode is used, in which
c59ff527 785 case, two adds/subs are used, taking 4 states. */
997e5af8
KH		 786 if (mode == SImode
787 && (value == 2 + 1
788 || value == 4 + 1
789 || value == 4 + 2
790 || value == 4 + 4))
22c9a795 791 return 1;
009ac3d3
RH		 792 }
793 else
794 {
ae19f5ef
KH		 795 /* We do not profit directly by splitting addition or
796 subtraction of 3 and 4. However, since these are
797 implemented as a sequence of adds or subs, they do not
798 clobber (cc0) unlike a sequence of add.b and add.x. */
799 if (mode == HImode
997e5af8
KH		 800 && (value == 2 + 1
801 || value == 2 + 2))
009ac3d3
RH		 802 return 1;
803 }
804 }
e6219736 805
e6219736
JL		 806 return 0;
807}
808
3cee1a78
KH		 809/* Split an add of a small constant into two adds/subs insns.
810
811 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
812 instead of adds/subs. */
009ac3d3
RH		 813
814void
cb713a8d 815split_adds_subs (enum machine_mode mode, rtx *operands)
3b7d443c 816{
009ac3d3
RH		 817 HOST_WIDE_INT val = INTVAL (operands[1]);
818 rtx reg = operands[0];
9492393e
KH		 819 HOST_WIDE_INT sign = 1;
820 HOST_WIDE_INT amount;
590734b6 821 rtx (*gen_add) (rtx, rtx, rtx);
3b7d443c 822
9492393e
KH		 823 /* Force VAL to be positive so that we do not have to consider the
824 sign. */
825 if (val < 0)
3b7d443c 826 {
9492393e
KH		 827 val = -val;
828 sign = -1;
829 }
3b7d443c 830
3cee1a78
KH		 831 switch (mode)
832 {
833 case HImode:
590734b6 834 gen_add = gen_addhi3;
3cee1a78
KH		 835 break;
836
837 case SImode:
590734b6 838 gen_add = gen_addsi3;
3cee1a78
KH		 839 break;
840
841 default:
842 abort ();
843 }
844
9492393e
KH		 845 /* Try different amounts in descending order. */
846 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
847 amount > 0;
848 amount /= 2)
849 {
1a63219b 850 for (; val >= amount; val -= amount)
590734b6 851 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
3b7d443c
JL		 852 }
853
9492393e 854 return;
3b7d443c
JL		 855}
856
f5b65a56
JL		 857/* Return true if OP is a valid call operand, and OP represents
858 an operand for a small call (4 bytes instead of 6 bytes). */
859
860int
cb713a8d 861small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
f5b65a56
JL		 862{
863 if (GET_CODE (op) == MEM)
864 {
865 rtx inside = XEXP (op, 0);
866
867 /* Register indirect is a small call. */
868 if (register_operand (inside, Pmode))
869 return 1;
870
dc66a1c4 871 /* A call through the function vector is a small call too. */
f5b65a56 872 if (GET_CODE (inside) == SYMBOL_REF
dc66a1c4 873 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
f5b65a56
JL		 874 return 1;
875 }
876 /* Otherwise it's a large call. */
877 return 0;
878}
879
48837e29
DE		 880/* Return true if OP is a valid jump operand. */
881
882int
cb713a8d 883jump_address_operand (rtx op, enum machine_mode mode)
48837e29
DE		 884{
885 if (GET_CODE (op) == REG)
886 return mode == Pmode;
887
888 if (GET_CODE (op) == MEM)
889 {
890 rtx inside = XEXP (op, 0);
891 if (register_operand (inside, Pmode))
892 return 1;
893 if (CONSTANT_ADDRESS_P (inside))
894 return 1;
895 }
896 return 0;
897}
898
43a88a8c 899/* Recognize valid operands for bit-field instructions. */
48837e29 900
48837e29 901int
cb713a8d 902bit_operand (rtx op, enum machine_mode mode)
48837e29 903{
f411c849 904 /* We can accept any general operand, except that MEM operands must
48837e29
DE		 905 be limited to those that use addresses valid for the 'U' constraint. */
906 if (!general_operand (op, mode))
907 return 0;
908
909 /* Accept any mem during RTL generation. Otherwise, the code that does
910 insv and extzv will think that we can not handle memory. However,
911 to avoid reload problems, we only accept 'U' MEM operands after RTL
912 generation. This means that any named pattern which uses this predicate
913 must force its operands to match 'U' before emitting RTL. */
914
915 if (GET_CODE (op) == REG)
916 return 1;
917 if (GET_CODE (op) == SUBREG)
918 return 1;
6620997b
KH		 919 return (GET_CODE (op) == MEM
920 && EXTRA_CONSTRAINT (op, 'U'));
48837e29
DE		 921}
922
e9eba255
KH		 923/* Return nonzero if OP is a MEM suitable for bit manipulation insns. */
924
887a8bd9 925int
cb713a8d 926bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
887a8bd9
JL		 927{
928 return (GET_CODE (op) == MEM
929 && EXTRA_CONSTRAINT (op, 'U'));
930}
931
07aae5c2 932/* Handle machine specific pragmas for compatibility with existing
48837e29 933 compilers for the H8/300.
07aae5c2 934
f411c849 935 pragma saveall generates prologue/epilogue code which saves and
07aae5c2 936 restores all the registers on function entry.
48837e29 937
07aae5c2
SC		 938 pragma interrupt saves and restores all registers, and exits with
939 an rte instruction rather than an rts. A pointer to a function
940 with this attribute may be safely used in an interrupt vector. */
48837e29 941
8b97c5f8 942void
cb713a8d 943h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
07aae5c2 944{
e392d367 945 pragma_interrupt = 1;
8b97c5f8 946}
05a81fe5 947
8b97c5f8 948void
cb713a8d 949h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
8b97c5f8
ZW		 950{
951 pragma_saveall = 1;
07aae5c2 952}
8b97c5f8 953
64bead4c
KH		 954/* If the next function argument with MODE and TYPE is to be passed in
955 a register, return a reg RTX for the hard register in which to pass
956 the argument. CUM represents the state after the last argument.
957 If the argument is to be pushed, NULL_RTX is returned. */
48837e29 958
07aae5c2 959rtx
cb713a8d
KH		 960function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
961 tree type, int named)
07aae5c2 962{
0ea6f6a0
KH		 963 static const char *const hand_list[] = {
964 "__main",
965 "__cmpsi2",
966 "__divhi3",
967 "__modhi3",
968 "__udivhi3",
969 "__umodhi3",
970 "__divsi3",
971 "__modsi3",
972 "__udivsi3",
973 "__umodsi3",
974 "__mulhi3",
975 "__mulsi3",
976 "__reg_memcpy",
977 "__reg_memset",
978 "__ucmpsi2",
979 0,
980 };
981
7192cbf1 982 rtx result = NULL_RTX;
441d04c6 983 const char *fname;
48837e29
DE		 984 int regpass = 0;
985
dd07092e
JL		 986 /* Never pass unnamed arguments in registers. */
987 if (!named)
7192cbf1 988 return NULL_RTX;
dd07092e 989
48837e29
DE		 990 /* Pass 3 regs worth of data in regs when user asked on the command line. */
991 if (TARGET_QUICKCALL)
992 regpass = 3;
993
994 /* If calling hand written assembler, use 4 regs of args. */
48837e29
DE		 995 if (cum->libcall)
996 {
441d04c6 997 const char * const *p;
48837e29
DE		 998
999 fname = XSTR (cum->libcall, 0);
1000
1001 /* See if this libcall is one of the hand coded ones. */
48837e29
DE		 1002 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1003 ;
07aae5c2 1004
48837e29
DE		 1005 if (*p)
1006 regpass = 4;
1007 }
1008
1009 if (regpass)
1010 {
1011 int size;
1012
1013 if (mode == BLKmode)
1014 size = int_size_in_bytes (type);
1015 else
1016 size = GET_MODE_SIZE (mode);
1017
15e0e275
KH		 1018 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1019 && cum->nbytes / UNITS_PER_WORD <= 3)
1020 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
48837e29 1021 }
07aae5c2 1022
48837e29
DE		 1023 return result;
1024}
1025\f
e9eba255
KH		 1026/* Compute the cost of an and insn. */
1027
3c50106f 1028static int
cb713a8d 1029h8300_and_costs (rtx x)
73cc75e9
KH		 1030{
1031 rtx operands[4];
1032
1033 if (GET_MODE (x) == QImode)
1034 return 1;
1035
1036 if (GET_MODE (x) != HImode
1037 && GET_MODE (x) != SImode)
1038 return 100;
1039
1040 operands[0] = NULL;
1041 operands[1] = NULL;
1042 operands[2] = XEXP (x, 1);
1043 operands[3] = x;
4f4ebda3 1044 return compute_logical_op_length (GET_MODE (x), operands) / 2;
73cc75e9
KH		 1045}
1046
e9eba255
KH		 1047/* Compute the cost of a shift insn. */
1048
3c50106f 1049static int
cb713a8d 1050h8300_shift_costs (rtx x)
ae557002
KH		 1051{
1052 rtx operands[4];
1053
1054 if (GET_MODE (x) != QImode
1055 && GET_MODE (x) != HImode
1056 && GET_MODE (x) != SImode)
1057 return 100;
1058
1059 operands[0] = NULL;
1060 operands[1] = NULL;
1061 operands[2] = XEXP (x, 1);
1062 operands[3] = x;
4f4ebda3 1063 return compute_a_shift_length (NULL, operands) / 2;
ae557002 1064}
3c50106f 1065
e9eba255
KH		 1066/* Worker function for TARGET_RTX_COSTS. */
1067
3c50106f 1068static bool
cb713a8d 1069h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
3c50106f
RH		 1070{
1071 switch (code)
1072 {
08dca707
KH		 1073 case CONST_INT:
1074 {
1075 HOST_WIDE_INT n = INTVAL (x);
1076
1077 if (-4 <= n || n <= 4)
1078 {
1079 switch ((int) n)
1080 {
1081 case 0:
1082 *total = 0;
1083 return true;
1084 case 1:
1085 case 2:
1086 case -1:
1087 case -2:
1088 *total = 0 + (outer_code == SET);
1089 return true;
1090 case 4:
1091 case -4:
1092 if (TARGET_H8300H || TARGET_H8300S)
1093 *total = 0 + (outer_code == SET);
1094 else
1095 *total = 1;
1096 return true;
1097 }
1098 }
1099 *total = 1;
1100 return true;
1101 }
1102
1103 case CONST:
1104 case LABEL_REF:
1105 case SYMBOL_REF:
1106 *total = 3;
1107 return true;
1108
1109 case CONST_DOUBLE:
1110 *total = 20;
1111 return true;
1112
3c50106f
RH		 1113 case AND:
1114 *total = COSTS_N_INSNS (h8300_and_costs (x));
1115 return true;
1116
1117 /* We say that MOD and DIV are so expensive because otherwise we'll
1118 generate some really horrible code for division of a power of two. */
1119 case MOD:
1120 case DIV:
1121 *total = 60;
1122 return true;
1123
1124 case MULT:
1125 *total = 20;
1126 return true;
1127
1128 case ASHIFT:
1129 case ASHIFTRT:
1130 case LSHIFTRT:
1131 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1132 return true;
1133
1134 case ROTATE:
1135 case ROTATERT:
1136 if (GET_MODE (x) == HImode)
1137 *total = 2;
1138 else
1139 *total = 8;
1140 return true;
1141
1142 default:
08dca707 1143 *total = 4;
3c50106f
RH		 1144 return true;
1145 }
1146}
48837e29 1147\f
07aae5c2
SC		 1148/* Documentation for the machine specific operand escapes:
1149
48837e29
DE		 1150 'E' like s but negative.
1151 'F' like t but negative.
1152 'G' constant just the negative
15dc331e
JL		 1153 'R' print operand as a byte:8 address if appropriate, else fall back to
1154 'X' handling.
48837e29 1155 'S' print operand as a long word
07aae5c2 1156 'T' print operand as a word
48837e29
DE		 1157 'V' find the set bit, and print its number.
1158 'W' find the clear bit, and print its number.
1159 'X' print operand as a byte
07aae5c2 1160 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
15dc331e 1161 If this operand isn't a register, fall back to 'R' handling.
48837e29 1162 'Z' print int & 7.
b059c02a 1163 'c' print the opcode corresponding to rtl
48837e29
DE		 1164 'e' first word of 32 bit value - if reg, then least reg. if mem
1165 then least. if const then most sig word
1166 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1167 then +2. if const then least sig word
07aae5c2
SC		 1168 'j' print operand as condition code.
1169 'k' print operand as reverse condition code.
48837e29
DE		 1170 's' print as low byte of 16 bit value
1171 't' print as high byte of 16 bit value
1172 'w' print as low byte of 32 bit value
1173 'x' print as 2nd byte of 32 bit value
1174 'y' print as 3rd byte of 32 bit value
1175 'z' print as msb of 32 bit value
1176*/
07aae5c2
SC		 1177
1178/* Return assembly language string which identifies a comparison type. */
1179
441d04c6 1180static const char *
cb713a8d 1181cond_string (enum rtx_code code)
07aae5c2
SC		 1182{
1183 switch (code)
1184 {
1185 case NE:
1186 return "ne";
1187 case EQ:
1188 return "eq";
1189 case GE:
1190 return "ge";
1191 case GT:
1192 return "gt";
1193 case LE:
1194 return "le";
1195 case LT:
1196 return "lt";
1197 case GEU:
1198 return "hs";
1199 case GTU:
1200 return "hi";
1201 case LEU:
1202 return "ls";
1203 case LTU:
1204 return "lo";
1205 default:
1206 abort ();
1207 }
1208}
1209
1210/* Print operand X using operand code CODE to assembly language output file
1211 FILE. */
1212
1213void
cb713a8d 1214print_operand (FILE *file, rtx x, int code)
07aae5c2 1215{
269c14e1 1216 /* This is used for communication between codes V,W,Z and Y. */
07aae5c2
SC		 1217 static int bitint;
1218
1219 switch (code)
1220 {
48837e29
DE		 1221 case 'E':
1222 switch (GET_CODE (x))
1223 {
1224 case REG:
1225 fprintf (file, "%sl", names_big[REGNO (x)]);
1226 break;
1227 case CONST_INT:
b47900aa 1228 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
48837e29
DE		 1229 break;
1230 default:
1231 abort ();
1232 }
1233 break;
1234 case 'F':
1235 switch (GET_CODE (x))
1236 {
1237 case REG:
1238 fprintf (file, "%sh", names_big[REGNO (x)]);
1239 break;
1240 case CONST_INT:
b47900aa 1241 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
48837e29
DE		 1242 break;
1243 default:
1244 abort ();
1245 }
1246 break;
07aae5c2
SC		 1247 case 'G':
1248 if (GET_CODE (x) != CONST_INT)
1249 abort ();
b47900aa 1250 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
07aae5c2 1251 break;
48837e29
DE		 1252 case 'S':
1253 if (GET_CODE (x) == REG)
1254 fprintf (file, "%s", names_extended[REGNO (x)]);
07aae5c2 1255 else
48837e29 1256 goto def;
07aae5c2 1257 break;
48837e29
DE		 1258 case 'T':
1259 if (GET_CODE (x) == REG)
1260 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1261 else
48837e29 1262 goto def;
07aae5c2 1263 break;
48837e29 1264 case 'V':
4d4d89e2 1265 bitint = exact_log2 (INTVAL (x) & 0xff);
48837e29 1266 if (bitint == -1)
07aae5c2 1267 abort ();
4d4d89e2 1268 fprintf (file, "#%d", bitint);
07aae5c2 1269 break;
48837e29 1270 case 'W':
07aae5c2
SC		 1271 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1272 if (bitint == -1)
1273 abort ();
4d4d89e2 1274 fprintf (file, "#%d", bitint);
07aae5c2 1275 break;
15dc331e 1276 case 'R':
48837e29
DE		 1277 case 'X':
1278 if (GET_CODE (x) == REG)
1279 fprintf (file, "%s", byte_reg (x, 0));
1280 else
1281 goto def;
1282 break;
1283 case 'Y':
07aae5c2
SC		 1284 if (bitint == -1)
1285 abort ();
48837e29
DE		 1286 if (GET_CODE (x) == REG)
1287 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1288 else
15dc331e 1289 print_operand (file, x, 'R');
48837e29
DE		 1290 bitint = -1;
1291 break;
1292 case 'Z':
1293 bitint = INTVAL (x);
07aae5c2
SC		 1294 fprintf (file, "#%d", bitint & 7);
1295 break;
b059c02a
KH		 1296 case 'c':
1297 switch (GET_CODE (x))
1298 {
1299 case IOR:
1300 fprintf (file, "or");
1301 break;
1302 case XOR:
1303 fprintf (file, "xor");
1304 break;
5abfd1af
KH		 1305 case AND:
1306 fprintf (file, "and");
1307 break;
b059c02a
KH		 1308 default:
1309 break;
1310 }
1311 break;
07aae5c2
SC		 1312 case 'e':
1313 switch (GET_CODE (x))
1314 {
1315 case REG:
48837e29
DE		 1316 if (TARGET_H8300)
1317 fprintf (file, "%s", names_big[REGNO (x)]);
1318 else
1319 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
07aae5c2
SC		 1320 break;
1321 case MEM:
07aae5c2
SC		 1322 print_operand (file, x, 0);
1323 break;
1324 case CONST_INT:
b47900aa 1325 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
07aae5c2 1326 break;
808fbfac
JL		 1327 case CONST_DOUBLE:
1328 {
1329 long val;
1330 REAL_VALUE_TYPE rv;
1331 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1332 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1333 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
808fbfac
JL		 1334 break;
1335 }
07aae5c2
SC		 1336 default:
1337 abort ();
1338 break;
1339 }
1340 break;
07aae5c2
SC		 1341 case 'f':
1342 switch (GET_CODE (x))
1343 {
1344 case REG:
48837e29
DE		 1345 if (TARGET_H8300)
1346 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1347 else
1348 fprintf (file, "%s", names_big[REGNO (x)]);
07aae5c2 1349 break;
07aae5c2 1350 case MEM:
b72f00af 1351 x = adjust_address (x, HImode, 2);
07aae5c2
SC		 1352 print_operand (file, x, 0);
1353 break;
07aae5c2 1354 case CONST_INT:
b47900aa 1355 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
07aae5c2 1356 break;
808fbfac
JL		 1357 case CONST_DOUBLE:
1358 {
1359 long val;
1360 REAL_VALUE_TYPE rv;
1361 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1362 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1363 fprintf (file, "#%ld", (val & 0xffff));
808fbfac
JL		 1364 break;
1365 }
07aae5c2
SC		 1366 default:
1367 abort ();
1368 }
1369 break;
07aae5c2 1370 case 'j':
761c70aa 1371 fputs (cond_string (GET_CODE (x)), file);
07aae5c2 1372 break;
07aae5c2 1373 case 'k':
761c70aa 1374 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
07aae5c2 1375 break;
48837e29
DE		 1376 case 's':
1377 if (GET_CODE (x) == CONST_INT)
b47900aa 1378 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
48837e29
DE		 1379 else
1380 fprintf (file, "%s", byte_reg (x, 0));
1381 break;
1382 case 't':
1383 if (GET_CODE (x) == CONST_INT)
b47900aa 1384 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29
DE		 1385 else
1386 fprintf (file, "%s", byte_reg (x, 1));
1387 break;
48837e29
DE		 1388 case 'w':
1389 if (GET_CODE (x) == CONST_INT)
b47900aa 1390 fprintf (file, "#%ld", INTVAL (x) & 0xff);
48837e29 1391 else
a1616dd9
JL		 1392 fprintf (file, "%s",
1393 byte_reg (x, TARGET_H8300 ? 2 : 0));
48837e29
DE		 1394 break;
1395 case 'x':
1396 if (GET_CODE (x) == CONST_INT)
b47900aa 1397 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
48837e29 1398 else
a1616dd9
JL		 1399 fprintf (file, "%s",
1400 byte_reg (x, TARGET_H8300 ? 3 : 1));
48837e29
DE		 1401 break;
1402 case 'y':
1403 if (GET_CODE (x) == CONST_INT)
b47900aa 1404 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
48837e29
DE		 1405 else
1406 fprintf (file, "%s", byte_reg (x, 0));
1407 break;
1408 case 'z':
1409 if (GET_CODE (x) == CONST_INT)
b47900aa 1410 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
48837e29
DE		 1411 else
1412 fprintf (file, "%s", byte_reg (x, 1));
1413 break;
1414
07aae5c2 1415 default:
48837e29 1416 def:
07aae5c2
SC		 1417 switch (GET_CODE (x))
1418 {
1419 case REG:
48837e29
DE		 1420 switch (GET_MODE (x))
1421 {
1422 case QImode:
269c14e1 1423#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
48837e29
DE		 1424 fprintf (file, "%s", byte_reg (x, 0));
1425#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1426 fprintf (file, "%s", names_big[REGNO (x)]);
1427#endif
1428 break;
1429 case HImode:
1430 fprintf (file, "%s", names_big[REGNO (x)]);
1431 break;
1432 case SImode:
8977e8a7 1433 case SFmode:
48837e29
DE		 1434 fprintf (file, "%s", names_extended[REGNO (x)]);
1435 break;
1436 default:
1437 abort ();
1438 }
07aae5c2
SC		 1439 break;
1440
1441 case MEM:
87e4ee91
KH		 1442 {
1443 rtx addr = XEXP (x, 0);
1444
1445 fprintf (file, "@");
1446 output_address (addr);
1447
bc8db8a1
KH		 1448 /* We fall back from smaller addressing to larger
1449 addressing in various ways depending on CODE. */
1450 switch (code)
1451 {
1452 case 'R':
1453 /* Used for mov.b and bit operations. */
7c143ed2 1454 if (h8300_eightbit_constant_address_p (addr))
bc8db8a1
KH		 1455 {
1456 fprintf (file, ":8");
1457 break;
1458 }
1459
1460 /* Fall through. We should not get here if we are
1461 processing bit operations on H8/300 or H8/300H
1462 because 'U' constraint does not allow bit
1463 operations on the tiny area on these machines. */
1464
1465 case 'T':
1466 case 'S':
1467 /* Used for mov.w and mov.l. */
56b8e164 1468 if (h8300_tiny_constant_address_p (addr))
bc8db8a1
KH		 1469 fprintf (file, ":16");
1470 break;
1471 default:
1472 break;
1473 }
87e4ee91 1474 }
07aae5c2
SC		 1475 break;
1476
1477 case CONST_INT:
1478 case SYMBOL_REF:
1479 case CONST:
1480 case LABEL_REF:
1481 fprintf (file, "#");
1482 print_operand_address (file, x);
1483 break;
808fbfac
JL		 1484 case CONST_DOUBLE:
1485 {
1486 long val;
1487 REAL_VALUE_TYPE rv;
1488 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1489 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
441d04c6 1490 fprintf (file, "#%ld", val);
808fbfac
JL		 1491 break;
1492 }
441d04c6
KG		 1493 default:
1494 break;
07aae5c2
SC		 1495 }
1496 }
1497}
1498
1499/* Output assembly language output for the address ADDR to FILE. */
1500
1501void
cb713a8d 1502print_operand_address (FILE *file, rtx addr)
07aae5c2
SC		 1503{
1504 switch (GET_CODE (addr))
1505 {
1506 case REG:
48837e29 1507 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
07aae5c2
SC		 1508 break;
1509
1510 case PRE_DEC:
48837e29 1511 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1512 break;
1513
1514 case POST_INC:
48837e29 1515 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
07aae5c2
SC		 1516 break;
1517
1518 case PLUS:
1519 fprintf (file, "(");
1520 if (GET_CODE (XEXP (addr, 0)) == REG)
1521 {
1522 /* reg,foo */
1523 print_operand_address (file, XEXP (addr, 1));
1524 fprintf (file, ",");
1525 print_operand_address (file, XEXP (addr, 0));
1526 }
1527 else
1528 {
1529 /* foo+k */
1530 print_operand_address (file, XEXP (addr, 0));
1531 fprintf (file, "+");
1532 print_operand_address (file, XEXP (addr, 1));
1533 }
1534 fprintf (file, ")");
1535 break;
1536
1537 case CONST_INT:
48837e29 1538 {
64530b82 1539 /* Since the H8/300 only has 16 bit pointers, negative values are also
48837e29
DE		 1540 those >= 32768. This happens for example with pointer minus a
1541 constant. We don't want to turn (char *p - 2) into
1542 (char *p + 65534) because loop unrolling can build upon this
1543 (IE: char *p + 131068). */
1544 int n = INTVAL (addr);
1545 if (TARGET_H8300)
1546 n = (int) (short) n;
7a770d8b 1547 fprintf (file, "%d", n);
48837e29
DE		 1548 break;
1549 }
07aae5c2
SC		 1550
1551 default:
1552 output_addr_const (file, addr);
1553 break;
1554 }
1555}
1556\f
07aae5c2
SC		 1557/* Output all insn addresses and their sizes into the assembly language
1558 output file. This is helpful for debugging whether the length attributes
1559 in the md file are correct. This is not meant to be a user selectable
1560 option. */
1561
1562void
cb713a8d
KH		 1563final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1564 int num_operands ATTRIBUTE_UNUSED)
07aae5c2
SC		 1565{
1566 /* This holds the last insn address. */
1567 static int last_insn_address = 0;
1568
7798db98 1569 const int uid = INSN_UID (insn);
07aae5c2
SC		 1570
1571 if (TARGET_ADDRESSES)
1572 {
9d98a694
AO		 1573 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1574 INSN_ADDRESSES (uid) - last_insn_address);
1575 last_insn_address = INSN_ADDRESSES (uid);
07aae5c2
SC		 1576 }
1577}
1578
48837e29
DE		 1579/* Prepare for an SI sized move. */
1580
1581int
1a793acf 1582h8300_expand_movsi (rtx operands[])
07aae5c2 1583{
48837e29
DE		 1584 rtx src = operands[1];
1585 rtx dst = operands[0];
1586 if (!reload_in_progress && !reload_completed)
1587 {
1588 if (!register_operand (dst, GET_MODE (dst)))
1589 {
1590 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1591 emit_move_insn (tmp, src);
1592 operands[1] = tmp;
1593 }
1594 }
1595 return 0;
1596}
1597
1598/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
07e4d94e
KH		 1599 Define the offset between two registers, one to be eliminated, and
1600 the other its replacement, at the start of a routine. */
07aae5c2 1601
48837e29 1602int
cb713a8d 1603h8300_initial_elimination_offset (int from, int to)
48837e29 1604{
d18ad191
KH		 1605 /* The number of bytes that the return address takes on the stack. */
1606 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
48837e29 1607
1807b726
KH		 1608 /* The number of bytes that the saved frame pointer takes on the stack. */
1609 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1610
1611 /* The number of bytes that the saved registers, excluding the frame
1612 pointer, take on the stack. */
1613 int saved_regs_size = 0;
48837e29 1614
1807b726
KH		 1615 /* The number of bytes that the locals takes on the stack. */
1616 int frame_size = round_frame_size (get_frame_size ());
48837e29 1617
1807b726 1618 int regno;
48837e29 1619
1807b726
KH		 1620 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1621 if (WORD_REG_USED (regno))
1622 saved_regs_size += UNITS_PER_WORD;
48837e29 1623
1807b726
KH		 1624 /* Adjust saved_regs_size because the above loop took the frame
1625 pointer int account. */
1626 saved_regs_size -= fp_size;
39ba95b5 1627
1807b726
KH		 1628 if (to == HARD_FRAME_POINTER_REGNUM)
1629 {
1630 switch (from)
1631 {
1632 case ARG_POINTER_REGNUM:
1633 return pc_size + fp_size;
1634 case RETURN_ADDRESS_POINTER_REGNUM:
1635 return fp_size;
1636 case FRAME_POINTER_REGNUM:
1637 return -saved_regs_size;
1638 default:
1639 abort ();
1640 }
1641 }
1642 else if (to == STACK_POINTER_REGNUM)
1643 {
1644 switch (from)
1645 {
1646 case ARG_POINTER_REGNUM:
1647 return pc_size + saved_regs_size + frame_size;
1648 case RETURN_ADDRESS_POINTER_REGNUM:
1649 return saved_regs_size + frame_size;
1650 case FRAME_POINTER_REGNUM:
1651 return frame_size;
1652 default:
1653 abort ();
1654 }
1655 }
1656 else
1657 abort ();
48837e29
DE		 1658}
1659
e9eba255
KH		 1660/* Worker function for RETURN_ADDR_RTX. */
1661
1aae372e 1662rtx
cb713a8d 1663h8300_return_addr_rtx (int count, rtx frame)
1aae372e
JL		 1664{
1665 rtx ret;
1666
1667 if (count == 0)
1668 ret = gen_rtx_MEM (Pmode,
1669 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1670 else if (flag_omit_frame_pointer)
1671 return (rtx) 0;
1672 else
1673 ret = gen_rtx_MEM (Pmode,
1674 memory_address (Pmode,
1675 plus_constant (frame, UNITS_PER_WORD)));
1676 set_mem_alias_set (ret, get_frame_alias_set ());
1677 return ret;
1678}
1679
48837e29
DE		 1680/* Update the condition code from the insn. */
1681
441d04c6 1682void
cb713a8d 1683notice_update_cc (rtx body, rtx insn)
48837e29 1684{
d99c740f
KH		 1685 rtx set;
1686
48837e29
DE		 1687 switch (get_attr_cc (insn))
1688 {
1689 case CC_NONE:
269c14e1 1690 /* Insn does not affect CC at all. */
48837e29
DE		 1691 break;
1692
1693 case CC_NONE_0HIT:
269c14e1 1694 /* Insn does not change CC, but the 0'th operand has been changed. */
48837e29 1695 if (cc_status.value1 != 0
1ccbefce 1696 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
48837e29 1697 cc_status.value1 = 0;
d4d6d0ce
KH		 1698 if (cc_status.value2 != 0
1699 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1700 cc_status.value2 = 0;
48837e29
DE		 1701 break;
1702
065bbfe6 1703 case CC_SET_ZN:
1ccbefce 1704 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
269c14e1
DE		 1705 The V flag is unusable. The C flag may or may not be known but
1706 that's ok because alter_cond will change tests to use EQ/NE. */
48837e29 1707 CC_STATUS_INIT;
269c14e1 1708 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
d99c740f
KH		 1709 set = single_set (insn);
1710 cc_status.value1 = SET_SRC (set);
1711 if (SET_DEST (set) != cc0_rtx)
1712 cc_status.value2 = SET_DEST (set);
48837e29
DE		 1713 break;
1714
065bbfe6 1715 case CC_SET_ZNV:
1ccbefce 1716 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
065bbfe6
JL		 1717 The C flag may or may not be known but that's ok because
1718 alter_cond will change tests to use EQ/NE. */
1719 CC_STATUS_INIT;
1720 cc_status.flags |= CC_NO_CARRY;
d99c740f
KH		 1721 set = single_set (insn);
1722 cc_status.value1 = SET_SRC (set);
1723 if (SET_DEST (set) != cc0_rtx)
c8fcf20c
KH		 1724 {
1725 /* If the destination is STRICT_LOW_PART, strip off
1726 STRICT_LOW_PART. */
1727 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1728 cc_status.value2 = XEXP (SET_DEST (set), 0);
1729 else
1730 cc_status.value2 = SET_DEST (set);
1731 }
065bbfe6
JL		 1732 break;
1733
269c14e1
DE		 1734 case CC_COMPARE:
1735 /* The insn is a compare instruction. */
48837e29 1736 CC_STATUS_INIT;
269c14e1 1737 cc_status.value1 = SET_SRC (body);
48837e29
DE		 1738 break;
1739
48837e29 1740 case CC_CLOBBER:
269c14e1 1741 /* Insn doesn't leave CC in a usable state. */
48837e29
DE		 1742 CC_STATUS_INIT;
1743 break;
07aae5c2 1744 }
48837e29
DE		 1745}
1746
8ccf5d5f
KH		 1747/* Return nonzero if X is a stack pointer. */
1748
1749int
cb713a8d 1750stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
8ccf5d5f
KH		 1751{
1752 return x == stack_pointer_rtx;
1753}
1754
8ccf5d5f
KH		 1755/* Return nonzero if X is a constant whose absolute value is greater
1756 than 2. */
1757
1758int
cb713a8d 1759const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
8ccf5d5f
KH		 1760{
1761 return (GET_CODE (x) == CONST_INT
1762 && abs (INTVAL (x)) > 2);
1763}
1764
1765/* Return nonzero if X is a constant whose absolute value is no
1766 smaller than 8. */
1767
1768int
cb713a8d 1769const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
8ccf5d5f
KH		 1770{
1771 return (GET_CODE (x) == CONST_INT
1772 && abs (INTVAL (x)) >= 8);
1773}
1774
2873836b
KH		 1775/* Return nonzero if X is a constant expressible in QImode. */
1776
1777int
cb713a8d 1778const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2873836b
KH		 1779{
1780 return (GET_CODE (x) == CONST_INT
1781 && (INTVAL (x) & 0xff) == INTVAL (x));
1782}
1783
1784/* Return nonzero if X is a constant expressible in HImode. */
1785
1786int
cb713a8d 1787const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2873836b
KH		 1788{
1789 return (GET_CODE (x) == CONST_INT
1790 && (INTVAL (x) & 0xffff) == INTVAL (x));
1791}
1792
f9d2de4d
KH		 1793/* Return nonzero if X is a constant suitable for inc/dec. */
1794
1795int
cb713a8d 1796incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
f9d2de4d
KH		 1797{
1798 return (GET_CODE (x) == CONST_INT
1799 && (CONST_OK_FOR_M (INTVAL (x))
1800 || CONST_OK_FOR_O (INTVAL (x))));
1801}
1802
1803/* Return nonzero if X is either EQ or NE. */
1804
1805int
cb713a8d 1806eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
f9d2de4d
KH		 1807{
1808 enum rtx_code code = GET_CODE (x);
1809
1810 return (code == EQ || code == NE);
1811}
1812
0e26895c 1813/* Return nonzero if X is either GT or LE. */
9a2dd2dd
KH		 1814
1815int
cb713a8d 1816gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
9a2dd2dd
KH		 1817{
1818 enum rtx_code code = GET_CODE (x);
1819
0e26895c 1820 return (code == GT || code == LE);
9a2dd2dd
KH		 1821}
1822
717d8b71
KH		 1823/* Return nonzero if X is either GTU or LEU. */
1824
1825int
cb713a8d 1826gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
717d8b71
KH		 1827{
1828 enum rtx_code code = GET_CODE (x);
1829
1830 return (code == GTU || code == LEU);
1831}
1832
b059c02a
KH		 1833/* Return nonzero if X is either IOR or XOR. */
1834
1835int
cb713a8d 1836iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
b059c02a
KH		 1837{
1838 enum rtx_code code = GET_CODE (x);
1839
1840 return (code == IOR || code == XOR);
1841}
1842
07e4d94e 1843/* Recognize valid operators for bit instructions. */
48837e29
DE		 1844
1845int
cb713a8d 1846bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
48837e29
DE		 1847{
1848 enum rtx_code code = GET_CODE (x);
07aae5c2 1849
48837e29
DE		 1850 return (code == XOR
1851 || code == AND
1852 || code == IOR);
07aae5c2 1853}
48837e29 1854\f
7948a9ea
KH		 1855/* Return the length of mov instruction. */
1856
1857unsigned int
1858compute_mov_length (rtx *operands)
1859{
1860 /* If the mov instruction involves a memory operand, we compute the
1861 length, assuming the largest addressing mode is used, and then
1862 adjust later in the function. Otherwise, we compute and return
1863 the exact length in one step. */
1864 enum machine_mode mode = GET_MODE (operands[0]);
1865 rtx dest = operands[0];
1866 rtx src = operands[1];
1867 rtx addr;
1868
1869 if (GET_CODE (src) == MEM)
1870 addr = XEXP (src, 0);
1871 else if (GET_CODE (dest) == MEM)
1872 addr = XEXP (dest, 0);
1873 else
1874 addr = NULL_RTX;
1875
1876 if (TARGET_H8300)
1877 {
1878 unsigned int base_length;
1879
1880 switch (mode)
1881 {
1882 case QImode:
1883 if (addr == NULL_RTX)
1884 return 2;
1885
1886 /* The eightbit addressing is available only in QImode, so
1887 go ahead and take care of it. */
1888 if (h8300_eightbit_constant_address_p (addr))
1889 return 2;
1890
1891 base_length = 4;
1892 break;
1893
1894 case HImode:
1895 if (addr == NULL_RTX)
1896 {
1897 if (REG_P (src))
1898 return 2;
1899
1900 if (src == const0_rtx)
1901 return 2;
1902
1903 return 4;
1904 }
1905
1906 base_length = 4;
1907 break;
1908
1909 case SImode:
1910 if (addr == NULL_RTX)
1911 {
1912 if (REG_P (src))
1913 return 4;
1914
1915 if (GET_CODE (src) == CONST_INT)
1916 {
1917 if (src == const0_rtx)
1918 return 4;
1919
1920 if ((INTVAL (src) & 0xffff) == 0)
1921 return 6;
1922
1923 if ((INTVAL (src) & 0xffff) == 0)
1924 return 6;
f5139cc5
KH		 1925
1926 if ((INTVAL (src) & 0xffff)
1927 == ((INTVAL (src) >> 16) & 0xffff))
1928 return 6;
7948a9ea
KH		 1929 }
1930 return 8;
1931 }
1932
1933 base_length = 8;
1934 break;
1935
1936 case SFmode:
1937 if (addr == NULL_RTX)
1938 {
1939 if (REG_P (src))
1940 return 4;
1941
2c4a71b3
KH		 1942 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
1943 return 4;
1944
81983b04 1945 return 8;
7948a9ea
KH		 1946 }
1947
1948 base_length = 8;
1949 break;
1950
1951 default:
1952 abort ();
1953 }
1954
1955 /* Adjust the length based on the addressing mode used.
1956 Specifically, we subtract the difference between the actual
1957 length and the longest one, which is @(d:16,Rs). For SImode
1958 and SFmode, we double the adjustment because two mov.w are
1959 used to do the job. */
1960
1961 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1962 if (GET_CODE (addr) == PRE_DEC
1963 || GET_CODE (addr) == POST_INC)
1964 {
1965 if (mode == QImode || mode == HImode)
1966 return base_length - 2;
1967 else
1968 /* In SImode and SFmode, we use two mov.w instructions, so
2a43945f 1969 double the adjustment. */
7948a9ea
KH		 1970 return base_length - 4;
1971 }
1972
1973 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1974 in SImode and SFmode, the second mov.w involves an address
1975 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1976 only 2 bytes. */
1977 if (GET_CODE (addr) == REG)
1978 return base_length - 2;
1979
1980 return base_length;
1981 }
1982 else
1983 {
1984 unsigned int base_length;
1985
1986 switch (mode)
1987 {
1988 case QImode:
1989 if (addr == NULL_RTX)
1990 return 2;
1991
1992 /* The eightbit addressing is available only in QImode, so
1993 go ahead and take care of it. */
1994 if (h8300_eightbit_constant_address_p (addr))
1995 return 2;
1996
1997 base_length = 8;
1998 break;
1999
2000 case HImode:
2001 if (addr == NULL_RTX)
2002 {
2003 if (REG_P (src))
2004 return 2;
2005
2006 if (src == const0_rtx)
2007 return 2;
2008
2009 return 4;
2010 }
2011
2012 base_length = 8;
2013 break;
2014
2015 case SImode:
2016 if (addr == NULL_RTX)
2017 {
2018 if (REG_P (src))
2019 {
2020 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2021 return 4;
2022 else
2023 return 2;
2024 }
2025
2026 if (GET_CODE (src) == CONST_INT)
2027 {
2028 int val = INTVAL (src);
2029
2030 if (val == 0)
2031 return 2;
2032
2033 if (val == (val & 0x00ff) || val == (val & 0xff00))
2034 return 4;
80e58519 2035
7948a9ea
KH		 2036 switch (val & 0xffffffff)
2037 {
2038 case 0xffffffff:
2039 case 0xfffffffe:
2040 case 0xfffffffc:
2041 case 0x0000ffff:
2042 case 0x0000fffe:
2043 case 0xffff0000:
2044 case 0xfffe0000:
2045 case 0x00010000:
2046 case 0x00020000:
2047 return 4;
2048 }
2049 }
2050 return 6;
2051 }
2052
2053 base_length = 10;
2054 break;
2055
2056 case SFmode:
2057 if (addr == NULL_RTX)
2058 {
2059 if (REG_P (src))
2060 return 2;
2061
fad37371 2062 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
7948a9ea 2063 return 2;
2c4a71b3 2064
7948a9ea
KH		 2065 return 6;
2066 }
2067
2068 base_length = 10;
2069 break;
2070
2071 default:
2072 abort ();
2073 }
2074
2075 /* Adjust the length based on the addressing mode used.
2076 Specifically, we subtract the difference between the actual
2077 length and the longest one, which is @(d:24,ERs). */
2078
2079 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2080 if (GET_CODE (addr) == PRE_DEC
2081 || GET_CODE (addr) == POST_INC)
2082 return base_length - 6;
2083
2084 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2085 if (GET_CODE (addr) == REG)
2086 return base_length - 6;
2087
2088 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2089 longest. */
2090 if (GET_CODE (addr) == PLUS
2091 && GET_CODE (XEXP (addr, 0)) == REG
2092 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2093 && INTVAL (XEXP (addr, 1)) > -32768
2094 && INTVAL (XEXP (addr, 1)) < 32767)
2095 return base_length - 4;
2096
2097 /* @aa:16 is 4 bytes shorter than the longest. */
2098 if (h8300_tiny_constant_address_p (addr))
2099 return base_length - 4;
2100
2101 /* @aa:24 is 2 bytes shorter than the longest. */
2102 if (CONSTANT_P (addr))
2103 return base_length - 2;
2104
2105 return base_length;
2106 }
2107}
2108\f
e9eba255
KH		 2109/* Output an addition insn. */
2110
366a7b27 2111const char *
cb713a8d 2112output_plussi (rtx *operands)
7d6ac401
KH		 2113{
2114 enum machine_mode mode = GET_MODE (operands[0]);
2115
2116 if (mode != SImode)
2117 abort ();
2118
2119 if (TARGET_H8300)
2120 {
cfedf91b
KH		 2121 if (GET_CODE (operands[2]) == REG)
2122 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2123
2124 if (GET_CODE (operands[2]) == CONST_INT)
2125 {
2126 HOST_WIDE_INT n = INTVAL (operands[2]);
2127
2128 if ((n & 0xffffff) == 0)
2129 return "add\t%z2,%z0";
2130 if ((n & 0xffff) == 0)
2131 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2132 if ((n & 0xff) == 0)
2133 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2134 }
2135
2136 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
7d6ac401
KH		 2137 }
2138 else
2139 {
2140 if (GET_CODE (operands[2]) == REG)
2141 return "add.l\t%S2,%S0";
2142
2143 if (GET_CODE (operands[2]) == CONST_INT)
2144 {
2145 HOST_WIDE_INT intval = INTVAL (operands[2]);
2146
2147 /* See if we can finish with 2 bytes. */
2148
9ac7ebba 2149 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 2150 {
2151 case 0x00000001:
2152 case 0x00000002:
2153 case 0x00000004:
2154 return "adds\t%2,%S0";
2155
2156 case 0xffffffff:
2157 case 0xfffffffe:
2158 case 0xfffffffc:
2159 return "subs\t%G2,%S0";
2160
2161 case 0x00010000:
2162 case 0x00020000:
2163 operands[2] = GEN_INT (intval >> 16);
2164 return "inc.w\t%2,%e0";
2165
2166 case 0xffff0000:
2167 case 0xfffe0000:
2168 operands[2] = GEN_INT (intval >> 16);
2169 return "dec.w\t%G2,%e0";
2170 }
2171
2172 /* See if we can finish with 4 bytes. */
2173 if ((intval & 0xffff) == 0)
2174 {
2175 operands[2] = GEN_INT (intval >> 16);
2176 return "add.w\t%2,%e0";
2177 }
2178 }
2179
2180 return "add.l\t%S2,%S0";
2181 }
2182}
2183
e9eba255
KH		 2184/* Compute the length of an addition insn. */
2185
7d6ac401 2186unsigned int
cb713a8d 2187compute_plussi_length (rtx *operands)
7d6ac401
KH		 2188{
2189 enum machine_mode mode = GET_MODE (operands[0]);
2190
2191 if (mode != SImode)
2192 abort ();
2193
2194 if (TARGET_H8300)
2195 {
cfedf91b
KH		 2196 if (GET_CODE (operands[2]) == REG)
2197 return 6;
2198
2199 if (GET_CODE (operands[2]) == CONST_INT)
2200 {
2201 HOST_WIDE_INT n = INTVAL (operands[2]);
2202
2203 if ((n & 0xffffff) == 0)
2204 return 2;
2205 if ((n & 0xffff) == 0)
2206 return 4;
2207 if ((n & 0xff) == 0)
2208 return 6;
2209 }
2210
2211 return 8;
7d6ac401
KH		 2212 }
2213 else
2214 {
2215 if (GET_CODE (operands[2]) == REG)
2216 return 2;
2217
2218 if (GET_CODE (operands[2]) == CONST_INT)
2219 {
2220 HOST_WIDE_INT intval = INTVAL (operands[2]);
2221
2222 /* See if we can finish with 2 bytes. */
2223
9ac7ebba 2224 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 2225 {
2226 case 0x00000001:
2227 case 0x00000002:
2228 case 0x00000004:
2229 return 2;
2230
2231 case 0xffffffff:
2232 case 0xfffffffe:
2233 case 0xfffffffc:
2234 return 2;
2235
2236 case 0x00010000:
2237 case 0x00020000:
2238 return 2;
2239
2240 case 0xffff0000:
2241 case 0xfffe0000:
2242 return 2;
2243 }
2244
2245 /* See if we can finish with 4 bytes. */
2246 if ((intval & 0xffff) == 0)
2247 return 4;
2248 }
2249
2250 return 6;
2251 }
2252}
2253
e9eba255
KH		 2254/* Compute which flag bits are valid after an addition insn. */
2255
87a902e4 2256int
cb713a8d 2257compute_plussi_cc (rtx *operands)
7d6ac401
KH		 2258{
2259 enum machine_mode mode = GET_MODE (operands[0]);
2260
2261 if (mode != SImode)
2262 abort ();
2263
2264 if (TARGET_H8300)
2265 {
cfedf91b 2266 return CC_CLOBBER;
7d6ac401
KH		 2267 }
2268 else
2269 {
2270 if (GET_CODE (operands[2]) == REG)
2271 return CC_SET_ZN;
2272
2273 if (GET_CODE (operands[2]) == CONST_INT)
2274 {
2275 HOST_WIDE_INT intval = INTVAL (operands[2]);
2276
2277 /* See if we can finish with 2 bytes. */
2278
9ac7ebba 2279 switch ((unsigned int) intval & 0xffffffff)
7d6ac401
KH		 2280 {
2281 case 0x00000001:
2282 case 0x00000002:
2283 case 0x00000004:
2284 return CC_NONE_0HIT;
2285
2286 case 0xffffffff:
2287 case 0xfffffffe:
2288 case 0xfffffffc:
2289 return CC_NONE_0HIT;
2290
2291 case 0x00010000:
2292 case 0x00020000:
2293 return CC_CLOBBER;
2294
2295 case 0xffff0000:
2296 case 0xfffe0000:
2297 return CC_CLOBBER;
2298 }
2299
2300 /* See if we can finish with 4 bytes. */
2301 if ((intval & 0xffff) == 0)
2302 return CC_CLOBBER;
2303 }
2304
2305 return CC_SET_ZN;
2306 }
2307}
2308\f
e9eba255
KH		 2309/* Output a logical insn. */
2310
7d6ac401 2311const char *
cb713a8d 2312output_logical_op (enum machine_mode mode, rtx *operands)
366a7b27 2313{
b42cff6b
KH		 2314 /* Figure out the logical op that we need to perform. */
2315 enum rtx_code code = GET_CODE (operands[3]);
366a7b27 2316 /* Pretend that every byte is affected if both operands are registers. */
7798db98 2317 const unsigned HOST_WIDE_INT intval =
366a7b27
KH		 2318 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2319 ? INTVAL (operands[2]) : 0x55555555);
2320 /* The determinant of the algorithm. If we perform an AND, 0
2321 affects a bit. Otherwise, 1 affects a bit. */
7798db98 2322 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 2323 /* Break up DET into pieces. */
2324 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2325 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 2326 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2327 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 2328 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2329 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2330 int lower_half_easy_p = 0;
2331 int upper_half_easy_p = 0;
366a7b27
KH		 2332 /* The name of an insn. */
2333 const char *opname;
2334 char insn_buf[100];
2335
2336 switch (code)
2337 {
2338 case AND:
2339 opname = "and";
2340 break;
2341 case IOR:
2342 opname = "or";
2343 break;
2344 case XOR:
2345 opname = "xor";
2346 break;
2347 default:
2348 abort ();
2349 }
2350
2351 switch (mode)
2352 {
2353 case HImode:
2354 /* First, see if we can finish with one insn. */
2355 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 2356 && b0 != 0
2357 && b1 != 0)
366a7b27
KH		 2358 {
2359 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2360 output_asm_insn (insn_buf, operands);
2361 }
2362 else
2363 {
2364 /* Take care of the lower byte. */
c5e7ce43 2365 if (b0 != 0)
366a7b27
KH		 2366 {
2367 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2368 output_asm_insn (insn_buf, operands);
2369 }
2370 /* Take care of the upper byte. */
c5e7ce43 2371 if (b1 != 0)
366a7b27
KH		 2372 {
2373 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2374 output_asm_insn (insn_buf, operands);
2375 }
2376 }
2377 break;
2378 case SImode:
f9ac2f95
KH		 2379 if (TARGET_H8300H || TARGET_H8300S)
2380 {
2381 /* Determine if the lower half can be taken care of in no more
2382 than two bytes. */
2383 lower_half_easy_p = (b0 == 0
2384 || b1 == 0
2385 || (code != IOR && w0 == 0xffff));
2386
2387 /* Determine if the upper half can be taken care of in no more
2388 than two bytes. */
2389 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2390 || (code == AND && w1 == 0xff00));
2391 }
366a7b27 2392
f9ac2f95
KH		 2393 /* Check if doing everything with one insn is no worse than
2394 using multiple insns. */
366a7b27 2395 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 2396 && w0 != 0 && w1 != 0
472f2723
KH		 2397 && !(lower_half_easy_p && upper_half_easy_p)
2398 && !(code == IOR && w1 == 0xffff
2399 && (w0 & 0x8000) != 0 && lower_half_easy_p))
366a7b27
KH		 2400 {
2401 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2402 output_asm_insn (insn_buf, operands);
2403 }
2404 else
2405 {
2406 /* Take care of the lower and upper words individually. For
2407 each word, we try different methods in the order of
2408
2409 1) the special insn (in case of AND or XOR),
2410 2) the word-wise insn, and
2411 3) The byte-wise insn. */
c5e7ce43 2412 if (w0 == 0xffff
6dfa4005 2413 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 2414 output_asm_insn ((code == AND)
187462ac 2415 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
366a7b27
KH		 2416 operands);
2417 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 2418 && (b0 != 0)
2419 && (b1 != 0))
366a7b27
KH		 2420 {
2421 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2422 output_asm_insn (insn_buf, operands);
2423 }
2424 else
2425 {
c5e7ce43 2426 if (b0 != 0)
366a7b27
KH		 2427 {
2428 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2429 output_asm_insn (insn_buf, operands);
2430 }
c5e7ce43 2431 if (b1 != 0)
366a7b27
KH		 2432 {
2433 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2434 output_asm_insn (insn_buf, operands);
2435 }
2436 }
2437
c5e7ce43 2438 if ((w1 == 0xffff)
6dfa4005 2439 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
366a7b27 2440 output_asm_insn ((code == AND)
187462ac 2441 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
366a7b27 2442 operands);
472f2723
KH		 2443 else if ((TARGET_H8300H || TARGET_H8300S)
2444 && code == IOR
2445 && w1 == 0xffff
2446 && (w0 & 0x8000) != 0)
2447 {
2448 output_asm_insn ("exts.l\t%S0", operands);
2449 }
a6e8d113
KH		 2450 else if ((TARGET_H8300H || TARGET_H8300S)
2451 && code == AND
c5e7ce43 2452 && w1 == 0xff00)
a6e8d113 2453 {
dc5f17ec 2454 output_asm_insn ("extu.w\t%e0", operands);
a6e8d113 2455 }
366a7b27
KH		 2456 else if (TARGET_H8300H || TARGET_H8300S)
2457 {
c5e7ce43 2458 if (w1 != 0)
366a7b27
KH		 2459 {
2460 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2461 output_asm_insn (insn_buf, operands);
2462 }
2463 }
2464 else
2465 {
c5e7ce43 2466 if (b2 != 0)
366a7b27
KH		 2467 {
2468 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2469 output_asm_insn (insn_buf, operands);
2470 }
c5e7ce43 2471 if (b3 != 0)
366a7b27
KH		 2472 {
2473 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2474 output_asm_insn (insn_buf, operands);
2475 }
2476 }
2477 }
2478 break;
2479 default:
2480 abort ();
2481 }
2482 return "";
2483}
40367e2d 2484
e9eba255
KH		 2485/* Compute the length of a logical insn. */
2486
40367e2d 2487unsigned int
cb713a8d 2488compute_logical_op_length (enum machine_mode mode, rtx *operands)
40367e2d 2489{
b42cff6b
KH		 2490 /* Figure out the logical op that we need to perform. */
2491 enum rtx_code code = GET_CODE (operands[3]);
40367e2d 2492 /* Pretend that every byte is affected if both operands are registers. */
7798db98 2493 const unsigned HOST_WIDE_INT intval =
40367e2d
KH		 2494 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2495 ? INTVAL (operands[2]) : 0x55555555);
2496 /* The determinant of the algorithm. If we perform an AND, 0
2497 affects a bit. Otherwise, 1 affects a bit. */
7798db98 2498 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 2499 /* Break up DET into pieces. */
2500 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2501 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
c5e7ce43
KH		 2502 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2503 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
f9ac2f95
KH		 2504 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2505 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2506 int lower_half_easy_p = 0;
2507 int upper_half_easy_p = 0;
40367e2d
KH		 2508 /* Insn length. */
2509 unsigned int length = 0;
2510
2511 switch (mode)
2512 {
2513 case HImode:
2514 /* First, see if we can finish with one insn. */
2515 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 2516 && b0 != 0
2517 && b1 != 0)
40367e2d
KH		 2518 {
2519 if (REG_P (operands[2]))
2520 length += 2;
2521 else
2522 length += 4;
2523 }
2524 else
2525 {
2526 /* Take care of the lower byte. */
c5e7ce43 2527 if (b0 != 0)
40367e2d
KH		 2528 length += 2;
2529
2530 /* Take care of the upper byte. */
c5e7ce43 2531 if (b1 != 0)
40367e2d
KH		 2532 length += 2;
2533 }
2534 break;
2535 case SImode:
f9ac2f95
KH		 2536 if (TARGET_H8300H || TARGET_H8300S)
2537 {
2538 /* Determine if the lower half can be taken care of in no more
2539 than two bytes. */
2540 lower_half_easy_p = (b0 == 0
2541 || b1 == 0
2542 || (code != IOR && w0 == 0xffff));
2543
2544 /* Determine if the upper half can be taken care of in no more
2545 than two bytes. */
2546 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2547 || (code == AND && w1 == 0xff00));
2548 }
40367e2d 2549
f9ac2f95
KH		 2550 /* Check if doing everything with one insn is no worse than
2551 using multiple insns. */
40367e2d 2552 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 2553 && w0 != 0 && w1 != 0
472f2723
KH		 2554 && !(lower_half_easy_p && upper_half_easy_p)
2555 && !(code == IOR && w1 == 0xffff
2556 && (w0 & 0x8000) != 0 && lower_half_easy_p))
40367e2d
KH		 2557 {
2558 if (REG_P (operands[2]))
2559 length += 4;
2560 else
2561 length += 6;
2562 }
2563 else
2564 {
2565 /* Take care of the lower and upper words individually. For
2566 each word, we try different methods in the order of
2567
2568 1) the special insn (in case of AND or XOR),
2569 2) the word-wise insn, and
2570 3) The byte-wise insn. */
c5e7ce43 2571 if (w0 == 0xffff
40367e2d
KH		 2572 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2573 {
2574 length += 2;
2575 }
2576 else if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 2577 && (b0 != 0)
2578 && (b1 != 0))
40367e2d
KH		 2579 {
2580 length += 4;
2581 }
2582 else
2583 {
c5e7ce43 2584 if (b0 != 0)
40367e2d
KH		 2585 length += 2;
2586
c5e7ce43 2587 if (b1 != 0)
40367e2d
KH		 2588 length += 2;
2589 }
2590
c5e7ce43 2591 if (w1 == 0xffff
40367e2d
KH		 2592 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2593 {
2594 length += 2;
2595 }
472f2723
KH		 2596 else if ((TARGET_H8300H || TARGET_H8300S)
2597 && code == IOR
2598 && w1 == 0xffff
2599 && (w0 & 0x8000) != 0)
2600 {
2601 length += 2;
2602 }
a6e8d113
KH		 2603 else if ((TARGET_H8300H || TARGET_H8300S)
2604 && code == AND
c5e7ce43 2605 && w1 == 0xff00)
a6e8d113
KH		 2606 {
2607 length += 2;
2608 }
40367e2d
KH		 2609 else if (TARGET_H8300H || TARGET_H8300S)
2610 {
c5e7ce43 2611 if (w1 != 0)
40367e2d
KH		 2612 length += 4;
2613 }
2614 else
2615 {
c5e7ce43 2616 if (b2 != 0)
40367e2d
KH		 2617 length += 2;
2618
c5e7ce43 2619 if (b3 != 0)
40367e2d
KH		 2620 length += 2;
2621 }
2622 }
2623 break;
2624 default:
2625 abort ();
2626 }
2627 return length;
2628}
b42cff6b 2629
e9eba255
KH		 2630/* Compute which flag bits are valid after a logical insn. */
2631
b42cff6b 2632int
cb713a8d 2633compute_logical_op_cc (enum machine_mode mode, rtx *operands)
b42cff6b
KH		 2634{
2635 /* Figure out the logical op that we need to perform. */
2636 enum rtx_code code = GET_CODE (operands[3]);
2637 /* Pretend that every byte is affected if both operands are registers. */
7798db98 2638 const unsigned HOST_WIDE_INT intval =
b42cff6b
KH		 2639 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2640 ? INTVAL (operands[2]) : 0x55555555);
2641 /* The determinant of the algorithm. If we perform an AND, 0
2642 affects a bit. Otherwise, 1 affects a bit. */
7798db98 2643 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
f9ac2f95
KH		 2644 /* Break up DET into pieces. */
2645 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2646 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2647 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2648 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2649 int lower_half_easy_p = 0;
2650 int upper_half_easy_p = 0;
b42cff6b
KH		 2651 /* Condition code. */
2652 enum attr_cc cc = CC_CLOBBER;
2653
2654 switch (mode)
2655 {
2656 case HImode:
2657 /* First, see if we can finish with one insn. */
2658 if ((TARGET_H8300H || TARGET_H8300S)
c5e7ce43
KH		 2659 && b0 != 0
2660 && b1 != 0)
b42cff6b
KH		 2661 {
2662 cc = CC_SET_ZNV;
2663 }
2664 break;
2665 case SImode:
f9ac2f95
KH		 2666 if (TARGET_H8300H || TARGET_H8300S)
2667 {
2668 /* Determine if the lower half can be taken care of in no more
2669 than two bytes. */
2670 lower_half_easy_p = (b0 == 0
2671 || b1 == 0
2672 || (code != IOR && w0 == 0xffff));
2673
2674 /* Determine if the upper half can be taken care of in no more
2675 than two bytes. */
2676 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2677 || (code == AND && w1 == 0xff00));
2678 }
b42cff6b 2679
f9ac2f95
KH		 2680 /* Check if doing everything with one insn is no worse than
2681 using multiple insns. */
b42cff6b 2682 if ((TARGET_H8300H || TARGET_H8300S)
f9ac2f95 2683 && w0 != 0 && w1 != 0
472f2723
KH		 2684 && !(lower_half_easy_p && upper_half_easy_p)
2685 && !(code == IOR && w1 == 0xffff
2686 && (w0 & 0x8000) != 0 && lower_half_easy_p))
b42cff6b
KH		 2687 {
2688 cc = CC_SET_ZNV;
2689 }
472f2723
KH		 2690 else
2691 {
2692 if ((TARGET_H8300H || TARGET_H8300S)
2693 && code == IOR
2694 && w1 == 0xffff
2695 && (w0 & 0x8000) != 0)
2696 {
2697 cc = CC_SET_ZNV;
2698 }
2699 }
b42cff6b
KH		 2700 break;
2701 default:
2702 abort ();
2703 }
2704 return cc;
2705}
366a7b27 2706\f
8981ecd3
KH		 2707/* Expand a conditional branch. */
2708
2709void
2710h8300_expand_branch (enum rtx_code code, rtx label)
2711{
2712 rtx tmp;
2713
2714 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
2715 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
2716 gen_rtx_LABEL_REF (VOIDmode, label),
2717 pc_rtx);
2718 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
2719}
2720\f
48837e29
DE		 2721/* Shifts.
2722
005e3e05
KH		 2723 We devote a fair bit of code to getting efficient shifts since we
2724 can only shift one bit at a time on the H8/300 and H8/300H and only
3db11b5c 2725 one or two bits at a time on the H8S.
005e3e05
KH		 2726
2727 All shift code falls into one of the following ways of
2728 implementation:
2729
2730 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2731 when a straight line shift is about the same size or smaller than
2732 a loop.
2733
2734 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2735 off the bits we don't need. This is used when only a few of the
2736 bits in the original value will survive in the shifted value.
2737
2738 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2739 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2740 shifts can be added if the shift count is slightly more than 8 or
2741 16. This case also includes other oddballs that are not worth
f411c849 2742 explaining here.
005e3e05 2743
3db11b5c 2744 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
005e3e05 2745
5ec0b66e
KH		 2746 For each shift count, we try to use code that has no trade-off
2747 between code size and speed whenever possible.
2748
2749 If the trade-off is unavoidable, we try to be reasonable.
2750 Specifically, the fastest version is one instruction longer than
2751 the shortest version, we take the fastest version. We also provide
2752 the use a way to switch back to the shortest version with -Os.
2753
2754 For the details of the shift algorithms for various shift counts,
2755 refer to shift_alg_[qhs]i. */
07aae5c2
SC		 2756
2757int
cb713a8d 2758nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
48837e29
DE		 2759{
2760 switch (GET_CODE (x))
2761 {
2762 case ASHIFTRT:
2763 case LSHIFTRT:
2764 case ASHIFT:
2765 return 1;
2766
2767 default:
2768 return 0;
2769 }
2770}
2771
317d21e9 2772/* Emit code to do shifts. */
48837e29 2773
317d21e9 2774void
cb713a8d 2775expand_a_shift (enum machine_mode mode, int code, rtx operands[])
07aae5c2 2776{
07aae5c2
SC		 2777 emit_move_insn (operands[0], operands[1]);
2778
07e4d94e
KH		 2779 /* Need a loop to get all the bits we want - we generate the
2780 code at emit time, but need to allocate a scratch reg now. */
48837e29 2781
c5c76735
JL		 2782 emit_insn (gen_rtx_PARALLEL
2783 (VOIDmode,
48837e29 2784 gen_rtvec (2,
c5c76735 2785 gen_rtx_SET (VOIDmode, operands[0],
0f4c242b
KH		 2786 gen_rtx_fmt_ee (code, mode,
2787 operands[0], operands[2])),
c5c76735
JL		 2788 gen_rtx_CLOBBER (VOIDmode,
2789 gen_rtx_SCRATCH (QImode)))));
48837e29
DE		 2790}
2791
48837e29
DE		 2792/* Symbols of the various modes which can be used as indices. */
2793
2794enum shift_mode
1a63219b
KH		 2795{
2796 QIshift, HIshift, SIshift
2797};
48837e29 2798
269c14e1
DE		 2799/* For single bit shift insns, record assembler and what bits of the
2800 condition code are valid afterwards (represented as various CC_FOO
2801 bits, 0 means CC isn't left in a usable state). */
48837e29
DE		 2802
2803struct shift_insn
2804{
8b60264b
KG		 2805 const char *const assembler;
2806 const int cc_valid;
48837e29
DE		 2807};
2808
2809/* Assembler instruction shift table.
2810
2811 These tables are used to look up the basic shifts.
07e4d94e 2812 They are indexed by cpu, shift_type, and mode. */
07aae5c2 2813
48837e29
DE		 2814static const struct shift_insn shift_one[2][3][3] =
2815{
2816/* H8/300 */
2817 {
2818/* SHIFT_ASHIFT */
2819 {
45ca2106
KH		 2820 { "shll\t%X0", CC_SET_ZNV },
2821 { "add.w\t%T0,%T0", CC_SET_ZN },
2822 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
48837e29
DE		 2823 },
2824/* SHIFT_LSHIFTRT */
2825 {
45ca2106
KH		 2826 { "shlr\t%X0", CC_SET_ZNV },
2827 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2828 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 2829 },
2830/* SHIFT_ASHIFTRT */
2831 {
45ca2106
KH		 2832 { "shar\t%X0", CC_SET_ZNV },
2833 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2834 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
48837e29
DE		 2835 }
2836 },
2837/* H8/300H */
2838 {
2839/* SHIFT_ASHIFT */
2840 {
45ca2106
KH		 2841 { "shll.b\t%X0", CC_SET_ZNV },
2842 { "shll.w\t%T0", CC_SET_ZNV },
2843 { "shll.l\t%S0", CC_SET_ZNV }
48837e29
DE		 2844 },
2845/* SHIFT_LSHIFTRT */
2846 {
45ca2106
KH		 2847 { "shlr.b\t%X0", CC_SET_ZNV },
2848 { "shlr.w\t%T0", CC_SET_ZNV },
2849 { "shlr.l\t%S0", CC_SET_ZNV }
48837e29
DE		 2850 },
2851/* SHIFT_ASHIFTRT */
2852 {
45ca2106
KH		 2853 { "shar.b\t%X0", CC_SET_ZNV },
2854 { "shar.w\t%T0", CC_SET_ZNV },
2855 { "shar.l\t%S0", CC_SET_ZNV }
48837e29
DE		 2856 }
2857 }
2858};
07aae5c2 2859
51c0c1d7
JL		 2860static const struct shift_insn shift_two[3][3] =
2861{
2862/* SHIFT_ASHIFT */
2863 {
45ca2106
KH		 2864 { "shll.b\t#2,%X0", CC_SET_ZNV },
2865 { "shll.w\t#2,%T0", CC_SET_ZNV },
2866 { "shll.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 2867 },
2868/* SHIFT_LSHIFTRT */
2869 {
45ca2106
KH		 2870 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2871 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2872 { "shlr.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 2873 },
2874/* SHIFT_ASHIFTRT */
2875 {
45ca2106
KH		 2876 { "shar.b\t#2,%X0", CC_SET_ZNV },
2877 { "shar.w\t#2,%T0", CC_SET_ZNV },
2878 { "shar.l\t#2,%S0", CC_SET_ZNV }
51c0c1d7
JL		 2879 }
2880};
2881
48837e29
DE		 2882/* Rotates are organized by which shift they'll be used in implementing.
2883 There's no need to record whether the cc is valid afterwards because
2884 it is the AND insn that will decide this. */
07aae5c2 2885
48837e29
DE		 2886static const char *const rotate_one[2][3][3] =
2887{
2888/* H8/300 */
2889 {
2890/* SHIFT_ASHIFT */
2891 {
51c0c1d7
JL		 2892 "rotr\t%X0",
2893 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
48837e29
DE		 2894 0
2895 },
2896/* SHIFT_LSHIFTRT */
2897 {
51c0c1d7
JL		 2898 "rotl\t%X0",
2899 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29
DE		 2900 0
2901 },
2902/* SHIFT_ASHIFTRT */
2903 {
51c0c1d7
JL		 2904 "rotl\t%X0",
2905 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
48837e29 2906 0
07aae5c2 2907 }
48837e29
DE		 2908 },
2909/* H8/300H */
2910 {
2911/* SHIFT_ASHIFT */
2912 {
51c0c1d7
JL		 2913 "rotr.b\t%X0",
2914 "rotr.w\t%T0",
2915 "rotr.l\t%S0"
48837e29
DE		 2916 },
2917/* SHIFT_LSHIFTRT */
07aae5c2 2918 {
51c0c1d7
JL		 2919 "rotl.b\t%X0",
2920 "rotl.w\t%T0",
2921 "rotl.l\t%S0"
48837e29
DE		 2922 },
2923/* SHIFT_ASHIFTRT */
2924 {
51c0c1d7
JL		 2925 "rotl.b\t%X0",
2926 "rotl.w\t%T0",
2927 "rotl.l\t%S0"
48837e29
DE		 2928 }
2929 }
2930};
2931
51c0c1d7
JL		 2932static const char *const rotate_two[3][3] =
2933{
2934/* SHIFT_ASHIFT */
2935 {
2936 "rotr.b\t#2,%X0",
2937 "rotr.w\t#2,%T0",
2938 "rotr.l\t#2,%S0"
2939 },
2940/* SHIFT_LSHIFTRT */
2941 {
2942 "rotl.b\t#2,%X0",
2943 "rotl.w\t#2,%T0",
2944 "rotl.l\t#2,%S0"
2945 },
2946/* SHIFT_ASHIFTRT */
2947 {
2948 "rotl.b\t#2,%X0",
2949 "rotl.w\t#2,%T0",
2950 "rotl.l\t#2,%S0"
2951 }
2952};
2953
35fb3d1f
KH		 2954struct shift_info {
2955 /* Shift algorithm. */
2956 enum shift_alg alg;
2957
2958 /* The number of bits to be shifted by shift1 and shift2. Valid
2959 when ALG is SHIFT_SPECIAL. */
2960 unsigned int remainder;
2961
2962 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2963 const char *special;
2964
2965 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 2966 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 2967 const char *shift1;
2968
2969 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
9cd10576 2970 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
35fb3d1f
KH		 2971 const char *shift2;
2972
45ca2106
KH		 2973 /* CC status for SHIFT_INLINE. */
2974 int cc_inline;
2975
2976 /* CC status for SHIFT_SPECIAL. */
2977 int cc_special;
35fb3d1f
KH		 2978};
2979
cb713a8d
KH		 2980static void get_shift_alg (enum shift_type,
2981 enum shift_mode, unsigned int,
2982 struct shift_info *);
441d04c6 2983
c009a745
KH		 2984/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2985 best algorithm for doing the shift. The assembler code is stored
5ec0b66e
KH		 2986 in the pointers in INFO. We achieve the maximum efficiency in most
2987 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2988 SImode in particular have a lot of room to optimize.
2989
2990 We first determine the strategy of the shift algorithm by a table
2991 lookup. If that tells us to use a hand crafted assembly code, we
2992 go into the big switch statement to find what that is. Otherwise,
2993 we resort to a generic way, such as inlining. In either case, the
2994 result is returned through INFO. */
48837e29 2995
cb33eb17 2996static void
cb713a8d
KH		 2997get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2998 unsigned int count, struct shift_info *info)
48837e29 2999{
b9b575e6 3000 enum h8_cpu cpu;
769828ab
KH		 3001
3002 /* Find the target CPU. */
3003 if (TARGET_H8300)
b9b575e6 3004 cpu = H8_300;
769828ab 3005 else if (TARGET_H8300H)
b9b575e6 3006 cpu = H8_300H;
769828ab 3007 else
b9b575e6 3008 cpu = H8_S;
769828ab 3009
96eaf358 3010 /* Find the shift algorithm. */
b9b575e6 3011 info->alg = SHIFT_LOOP;
48837e29
DE		 3012 switch (shift_mode)
3013 {
3014 case QIshift:
b9b575e6 3015 if (count < GET_MODE_BITSIZE (QImode))
96eaf358
KH		 3016 info->alg = shift_alg_qi[cpu][shift_type][count];
3017 break;
769828ab 3018
96eaf358 3019 case HIshift:
b9b575e6 3020 if (count < GET_MODE_BITSIZE (HImode))
96eaf358
KH		 3021 info->alg = shift_alg_hi[cpu][shift_type][count];
3022 break;
3023
3024 case SIshift:
b9b575e6 3025 if (count < GET_MODE_BITSIZE (SImode))
96eaf358
KH		 3026 info->alg = shift_alg_si[cpu][shift_type][count];
3027 break;
3028
3029 default:
3030 abort ();
3031 }
3032
3033 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
3034 switch (info->alg)
3035 {
3036 case SHIFT_INLINE:
3037 info->remainder = count;
3038 /* Fall through. */
3039
3040 case SHIFT_LOOP:
3041 /* It is up to the caller to know that looping clobbers cc. */
3042 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3043 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106 3044 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
96eaf358
KH		 3045 goto end;
3046
3047 case SHIFT_ROT_AND:
3048 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
3049 info->shift2 = rotate_two[shift_type][shift_mode];
45ca2106 3050 info->cc_inline = CC_CLOBBER;
96eaf358
KH		 3051 goto end;
3052
3053 case SHIFT_SPECIAL:
3054 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3055 info->remainder = 0;
3056 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3057 info->shift2 = shift_two[shift_type][shift_mode].assembler;
45ca2106
KH		 3058 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3059 info->cc_special = CC_CLOBBER;
96eaf358
KH		 3060 break;
3061 }
51c0c1d7 3062
96eaf358
KH		 3063 /* Here we only deal with SHIFT_SPECIAL. */
3064 switch (shift_mode)
3065 {
3066 case QIshift:
769828ab
KH		 3067 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3068 through the entire value. */
3069 if (shift_type == SHIFT_ASHIFTRT && count == 7)
3070 {
3071 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
692b7eb3 3072 goto end;
769828ab
KH		 3073 }
3074 abort ();
3075
3076 case HIshift:
769828ab 3077 if (count == 7)
51c0c1d7 3078 {
a77b1dbc 3079 switch (shift_type)
51c0c1d7 3080 {
a77b1dbc
KH		 3081 case SHIFT_ASHIFT:
3082 if (TARGET_H8300)
3083 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3084 else
3085 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
692b7eb3 3086 goto end;
a77b1dbc
KH		 3087 case SHIFT_LSHIFTRT:
3088 if (TARGET_H8300)
3089 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3090 else
3091 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
692b7eb3 3092 goto end;
a77b1dbc 3093 case SHIFT_ASHIFTRT:
35fb3d1f 3094 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
692b7eb3 3095 goto end;
48837e29 3096 }
07aae5c2 3097 }
b30686ec 3098 else if ((8 <= count && count <= 13)
a38b3eea 3099 || (TARGET_H8300S && count == 14))
07aae5c2 3100 {
a7812c0b
KH		 3101 info->remainder = count - 8;
3102
51c0c1d7 3103 switch (shift_type)
48837e29 3104 {
51c0c1d7 3105 case SHIFT_ASHIFT:
35fb3d1f 3106 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
692b7eb3 3107 goto end;
51c0c1d7 3108 case SHIFT_LSHIFTRT:
a7612343
KH		 3109 if (TARGET_H8300)
3110 {
3111 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3112 info->shift1 = "shlr.b\t%s0";
45ca2106 3113 info->cc_inline = CC_SET_ZNV;
a7612343
KH		 3114 }
3115 else
3116 {
3117 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
45ca2106 3118 info->cc_special = CC_SET_ZNV;
a7612343 3119 }
692b7eb3 3120 goto end;
51c0c1d7
JL		 3121 case SHIFT_ASHIFTRT:
3122 if (TARGET_H8300)
a7612343
KH		 3123 {
3124 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3125 info->shift1 = "shar.b\t%s0";
a7612343 3126 }
51c0c1d7 3127 else
a7612343
KH		 3128 {
3129 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
45ca2106 3130 info->cc_special = CC_SET_ZNV;
a7612343 3131 }
692b7eb3 3132 goto end;
51c0c1d7
JL		 3133 }
3134 }
5e98fba2
DD		 3135 else if (count == 14)
3136 {
3137 switch (shift_type)
3138 {
3139 case SHIFT_ASHIFT:
3140 if (TARGET_H8300)
3141 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3142 goto end;
3143 case SHIFT_LSHIFTRT:
3144 if (TARGET_H8300)
3145 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3146 goto end;
3147 case SHIFT_ASHIFTRT:
3148 if (TARGET_H8300)
3149 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3150 else if (TARGET_H8300H)
45ca2106
KH		 3151 {
3152 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3153 info->cc_special = CC_SET_ZNV;
3154 }
5e98fba2 3155 else /* TARGET_H8300S */
b30686ec 3156 abort ();
5e98fba2
DD		 3157 goto end;
3158 }
3159 }
1e41e866 3160 else if (count == 15)
51c0c1d7 3161 {
1e41e866
KH		 3162 switch (shift_type)
3163 {
3164 case SHIFT_ASHIFT:
3165 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3166 goto end;
3167 case SHIFT_LSHIFTRT:
3168 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3169 goto end;
3170 case SHIFT_ASHIFTRT:
3171 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3172 goto end;
3173 }
07aae5c2 3174 }
769828ab 3175 abort ();
51c0c1d7 3176
48837e29 3177 case SIshift:
1e41e866 3178 if (TARGET_H8300 && 8 <= count && count <= 9)
48837e29 3179 {
1e41e866
KH		 3180 info->remainder = count - 8;
3181
51c0c1d7 3182 switch (shift_type)
48837e29 3183 {
51c0c1d7 3184 case SHIFT_ASHIFT:
35fb3d1f 3185 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
692b7eb3 3186 goto end;
51c0c1d7 3187 case SHIFT_LSHIFTRT:
35fb3d1f 3188 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
1e41e866 3189 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
692b7eb3 3190 goto end;
51c0c1d7 3191 case SHIFT_ASHIFTRT:
35fb3d1f 3192 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
692b7eb3 3193 goto end;
48837e29 3194 }
48837e29 3195 }
e6bcfef9
JS		 3196 else if (count == 8 && !TARGET_H8300)
3197 {
3198 switch (shift_type)
3199 {
3200 case SHIFT_ASHIFT:
35fb3d1f 3201 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
692b7eb3 3202 goto end;
e6bcfef9 3203 case SHIFT_LSHIFTRT:
35fb3d1f 3204 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 3205 goto end;
e6bcfef9 3206 case SHIFT_ASHIFTRT:
35fb3d1f 3207 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
692b7eb3 3208 goto end;
e6bcfef9
JS		 3209 }
3210 }
1e41e866
KH		 3211 else if (count == 15 && TARGET_H8300)
3212 {
3213 switch (shift_type)
3214 {
3215 case SHIFT_ASHIFT:
3216 abort ();
3217 case SHIFT_LSHIFTRT:
a35abc3c 3218 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
1e41e866
KH		 3219 goto end;
3220 case SHIFT_ASHIFTRT:
a35abc3c 3221 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
1e41e866
KH		 3222 goto end;
3223 }
3224 }
dd69e230
KH		 3225 else if (count == 15 && !TARGET_H8300)
3226 {
3227 switch (shift_type)
3228 {
3229 case SHIFT_ASHIFT:
3230 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
45ca2106 3231 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 3232 goto end;
3233 case SHIFT_LSHIFTRT:
18cf8dda 3234 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
45ca2106 3235 info->cc_special = CC_SET_ZNV;
dd69e230 3236 goto end;
aefc5826
KH		 3237 case SHIFT_ASHIFTRT:
3238 abort ();
dd69e230
KH		 3239 }
3240 }
1e41e866 3241 else if ((TARGET_H8300 && 16 <= count && count <= 20)
a7812c0b 3242 || (TARGET_H8300H && 16 <= count && count <= 19)
e0f19bd0 3243 || (TARGET_H8300S && 16 <= count && count <= 21))
48837e29 3244 {
a7812c0b
KH		 3245 info->remainder = count - 16;
3246
48837e29
DE		 3247 switch (shift_type)
3248 {
3249 case SHIFT_ASHIFT:
35fb3d1f 3250 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
1e41e866 3251 if (TARGET_H8300)
b30686ec 3252 info->shift1 = "add.w\t%e0,%e0";
692b7eb3 3253 goto end;
51c0c1d7 3254 case SHIFT_LSHIFTRT:
1e41e866
KH		 3255 if (TARGET_H8300)
3256 {
a7612343
KH		 3257 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3258 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
1e41e866
KH		 3259 }
3260 else
3261 {
a7612343 3262 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
45ca2106 3263 info->cc_special = CC_SET_ZNV;
1e41e866 3264 }
692b7eb3 3265 goto end;
51c0c1d7
JL		 3266 case SHIFT_ASHIFTRT:
3267 if (TARGET_H8300)
1e41e866
KH		 3268 {
3269 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3270 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3271 }
51c0c1d7 3272 else
1e41e866
KH		 3273 {
3274 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
45ca2106 3275 info->cc_special = CC_SET_ZNV;
1e41e866 3276 }
692b7eb3 3277 goto end;
51c0c1d7
JL		 3278 }
3279 }
1e41e866 3280 else if (TARGET_H8300 && 24 <= count && count <= 28)
f9477efd
KH		 3281 {
3282 info->remainder = count - 24;
f0b6f9a6 3283
f9477efd
KH		 3284 switch (shift_type)
3285 {
3286 case SHIFT_ASHIFT:
3287 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3288 info->shift1 = "shll.b\t%z0";
45ca2106 3289 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 3290 goto end;
3291 case SHIFT_LSHIFTRT:
3292 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3293 info->shift1 = "shlr.b\t%w0";
45ca2106 3294 info->cc_inline = CC_SET_ZNV;
f9477efd
KH		 3295 goto end;
3296 case SHIFT_ASHIFTRT:
3297 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3298 info->shift1 = "shar.b\t%w0";
45ca2106 3299 info->cc_inline = CC_SET_ZNV;
7f473594
KH		 3300 goto end;
3301 }
3302 }
4a4ae922
KH		 3303 else if ((TARGET_H8300H && count == 24)
3304 || (TARGET_H8300S && 24 <= count && count <= 25))
e6bcfef9 3305 {
4a4ae922
KH		 3306 info->remainder = count - 24;
3307
e6bcfef9
JS		 3308 switch (shift_type)
3309 {
3310 case SHIFT_ASHIFT:
35fb3d1f 3311 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
692b7eb3 3312 goto end;
e6bcfef9 3313 case SHIFT_LSHIFTRT:
35fb3d1f 3314 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
45ca2106 3315 info->cc_special = CC_SET_ZNV;
692b7eb3 3316 goto end;
e6bcfef9 3317 case SHIFT_ASHIFTRT:
35fb3d1f 3318 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
45ca2106 3319 info->cc_special = CC_SET_ZNV;
692b7eb3 3320 goto end;
e6bcfef9
JS		 3321 }
3322 }
1e5bdc40
KH		 3323 else if (!TARGET_H8300 && count == 28)
3324 {
3325 switch (shift_type)
3326 {
3327 case SHIFT_ASHIFT:
3328 if (TARGET_H8300H)
3329 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3330 else
3331 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 3332 goto end;
3333 case SHIFT_LSHIFTRT:
3334 if (TARGET_H8300H)
45ca2106
KH		 3335 {
3336 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3337 info->cc_special = CC_SET_ZNV;
3338 }
1e5bdc40 3339 else
a7612343 3340 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 3341 goto end;
3342 case SHIFT_ASHIFTRT:
3343 abort ();
3344 }
3345 }
3346 else if (!TARGET_H8300 && count == 29)
3347 {
3348 switch (shift_type)
3349 {
3350 case SHIFT_ASHIFT:
3351 if (TARGET_H8300H)
3352 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3353 else
3354 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 3355 goto end;
3356 case SHIFT_LSHIFTRT:
3357 if (TARGET_H8300H)
45ca2106
KH		 3358 {
3359 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3360 info->cc_special = CC_SET_ZNV;
3361 }
1e5bdc40 3362 else
45ca2106
KH		 3363 {
3364 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3365 info->cc_special = CC_SET_ZNV;
3366 }
1e5bdc40
KH		 3367 goto end;
3368 case SHIFT_ASHIFTRT:
3369 abort ();
3370 }
3371 }
3372 else if (!TARGET_H8300 && count == 30)
3373 {
3374 switch (shift_type)
3375 {
3376 case SHIFT_ASHIFT:
3377 if (TARGET_H8300H)
3378 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3379 else
3380 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
1e5bdc40
KH		 3381 goto end;
3382 case SHIFT_LSHIFTRT:
3383 if (TARGET_H8300H)
a7612343 3384 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
1e5bdc40 3385 else
a7612343 3386 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
1e5bdc40
KH		 3387 goto end;
3388 case SHIFT_ASHIFTRT:
3389 abort ();
3390 }
3391 }
48837e29
DE		 3392 else if (count == 31)
3393 {
dd69e230 3394 if (TARGET_H8300)
48837e29 3395 {
dd69e230
KH		 3396 switch (shift_type)
3397 {
3398 case SHIFT_ASHIFT:
3399 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3400 goto end;
3401 case SHIFT_LSHIFTRT:
3402 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3403 goto end;
3404 case SHIFT_ASHIFTRT:
3405 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3406 goto end;
3407 }
48837e29
DE		 3408 }
3409 else
3410 {
dd69e230 3411 switch (shift_type)
48837e29 3412 {
dd69e230
KH		 3413 case SHIFT_ASHIFT:
3414 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
45ca2106 3415 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 3416 goto end;
3417 case SHIFT_LSHIFTRT:
3418 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
45ca2106 3419 info->cc_special = CC_SET_ZNV;
dd69e230
KH		 3420 goto end;
3421 case SHIFT_ASHIFTRT:
a7612343 3422 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
45ca2106 3423 info->cc_special = CC_SET_ZNV;
692b7eb3 3424 goto end;
48837e29 3425 }
48837e29
DE		 3426 }
3427 }
769828ab 3428 abort ();
51c0c1d7 3429
48837e29
DE		 3430 default:
3431 abort ();
07aae5c2 3432 }
48837e29 3433
cb33eb17
KH		 3434 end:
3435 if (!TARGET_H8300S)
3436 info->shift2 = NULL;
07aae5c2
SC		 3437}
3438
be1e06df
KH		 3439/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3440 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3441
3442int
cb713a8d 3443h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
be1e06df 3444{
b9b575e6 3445 enum h8_cpu cpu;
be1e06df
KH		 3446 int a, lr, ar;
3447
3448 if (GET_MODE_BITSIZE (mode) <= count)
3449 return 1;
3450
3451 /* Find out the target CPU. */
3452 if (TARGET_H8300)
b9b575e6 3453 cpu = H8_300;
be1e06df 3454 else if (TARGET_H8300H)
b9b575e6 3455 cpu = H8_300H;
be1e06df 3456 else
b9b575e6 3457 cpu = H8_S;
be1e06df
KH		 3458
3459 /* Find the shift algorithm. */
3460 switch (mode)
3461 {
3462 case QImode:
3463 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3464 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3465 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3466 break;
3467
3468 case HImode:
3469 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3470 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3471 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3472 break;
3473
3474 case SImode:
3475 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3476 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3477 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3478 break;
3479
3480 default:
3481 abort ();
3482 }
3483
aa2fb4dd 3484 /* On H8/300H, count == 8 uses a scratch register. */
be1e06df 3485 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
75a3503b 3486 || (TARGET_H8300H && mode == SImode && count == 8));
be1e06df
KH		 3487}
3488
e9eba255 3489/* Output the assembler code for doing shifts. */
48837e29 3490
441d04c6 3491const char *
cb713a8d 3492output_a_shift (rtx *operands)
07aae5c2 3493{
48837e29 3494 static int loopend_lab;
48837e29
DE		 3495 rtx shift = operands[3];
3496 enum machine_mode mode = GET_MODE (shift);
3497 enum rtx_code code = GET_CODE (shift);
3498 enum shift_type shift_type;
3499 enum shift_mode shift_mode;
35fb3d1f 3500 struct shift_info info;
48837e29
DE		 3501
3502 loopend_lab++;
3503
3504 switch (mode)
3505 {
3506 case QImode:
3507 shift_mode = QIshift;
3508 break;
3509 case HImode:
3510 shift_mode = HIshift;
3511 break;
3512 case SImode:
3513 shift_mode = SIshift;
3514 break;
3515 default:
3516 abort ();
3517 }
07aae5c2 3518
48837e29 3519 switch (code)
07aae5c2 3520 {
48837e29
DE		 3521 case ASHIFTRT:
3522 shift_type = SHIFT_ASHIFTRT;
3523 break;
3524 case LSHIFTRT:
3525 shift_type = SHIFT_LSHIFTRT;
3526 break;
3527 case ASHIFT:
3528 shift_type = SHIFT_ASHIFT;
3529 break;
3530 default:
3531 abort ();
3532 }
07aae5c2 3533
48837e29
DE		 3534 if (GET_CODE (operands[2]) != CONST_INT)
3535 {
cd9b5ca8
KH		 3536 /* This case must be taken care of by one of the two splitters
3537 that convert a variable shift into a loop. */
3538 abort ();
48837e29
DE		 3539 }
3540 else
3541 {
3542 int n = INTVAL (operands[2]);
48837e29
DE		 3543
3544 /* If the count is negative, make it 0. */
3545 if (n < 0)
3546 n = 0;
3547 /* If the count is too big, truncate it.
3548 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3549 do the intuitive thing. */
64530b82 3550 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
48837e29
DE		 3551 n = GET_MODE_BITSIZE (mode);
3552
cb33eb17 3553 get_shift_alg (shift_type, shift_mode, n, &info);
48837e29 3554
cb33eb17 3555 switch (info.alg)
48837e29 3556 {
cb33eb17
KH		 3557 case SHIFT_SPECIAL:
3558 output_asm_insn (info.special, operands);
3559 /* Fall through. */
3560
48837e29 3561 case SHIFT_INLINE:
cb33eb17
KH		 3562 n = info.remainder;
3563
51c0c1d7 3564 /* Emit two bit shifts first. */
1a275226 3565 if (info.shift2 != NULL)
51c0c1d7 3566 {
1a275226
KH		 3567 for (; n > 1; n -= 2)
3568 output_asm_insn (info.shift2, operands);
51c0c1d7
JL		 3569 }
3570
3571 /* Now emit one bit shifts for any residual. */
1a275226
KH		 3572 for (; n > 0; n--)
3573 output_asm_insn (info.shift1, operands);
48837e29 3574 return "";
51c0c1d7 3575
48837e29
DE		 3576 case SHIFT_ROT_AND:
3577 {
3578 int m = GET_MODE_BITSIZE (mode) - n;
7798db98
KH		 3579 const int mask = (shift_type == SHIFT_ASHIFT
3580 ? ((1 << m) - 1) << n
3581 : (1 << m) - 1);
48837e29 3582 char insn_buf[200];
b5eaf9ba 3583
48837e29
DE		 3584 /* Not all possibilities of rotate are supported. They shouldn't
3585 be generated, but let's watch for 'em. */
35fb3d1f 3586 if (info.shift1 == 0)
48837e29 3587 abort ();
51c0c1d7
JL		 3588
3589 /* Emit two bit rotates first. */
1a275226 3590 if (info.shift2 != NULL)
51c0c1d7 3591 {
1a275226
KH		 3592 for (; m > 1; m -= 2)
3593 output_asm_insn (info.shift2, operands);
51c0c1d7
JL		 3594 }
3595
3596 /* Now single bit rotates for any residual. */
1a275226
KH		 3597 for (; m > 0; m--)
3598 output_asm_insn (info.shift1, operands);
51c0c1d7
JL		 3599
3600 /* Now mask off the high bits. */
ade53a50
KH		 3601 if (mode == QImode)
3602 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3603 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3604 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3605 else
3606 abort ();
3607
48837e29
DE		 3608 output_asm_insn (insn_buf, operands);
3609 return "";
3610 }
b5eaf9ba 3611
b5eaf9ba
KH		 3612 case SHIFT_LOOP:
3613 /* A loop to shift by a "large" constant value.
3614 If we have shift-by-2 insns, use them. */
35fb3d1f 3615 if (info.shift2 != NULL)
b5eaf9ba
KH		 3616 {
3617 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3618 names_big[REGNO (operands[4])]);
3619 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
35fb3d1f 3620 output_asm_insn (info.shift2, operands);
b5eaf9ba
KH		 3621 output_asm_insn ("add #0xff,%X4", operands);
3622 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3623 if (n % 2)
35fb3d1f 3624 output_asm_insn (info.shift1, operands);
b5eaf9ba
KH		 3625 }
3626 else
3627 {
3628 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3629 names_big[REGNO (operands[4])]);
3630 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
35fb3d1f 3631 output_asm_insn (info.shift1, operands);
b5eaf9ba
KH		 3632 output_asm_insn ("add #0xff,%X4", operands);
3633 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3634 }
51c0c1d7 3635 return "";
b5eaf9ba
KH		 3636
3637 default:
3638 abort ();
51c0c1d7 3639 }
07aae5c2 3640 }
07aae5c2 3641}
86855e8c 3642
e9eba255
KH		 3643/* Count the number of assembly instructions in a string TEMPLATE. */
3644
86855e8c 3645static unsigned int
cb713a8d 3646h8300_asm_insn_count (const char *template)
86855e8c
KH		 3647{
3648 unsigned int count = 1;
3649
3650 for (; *template; template++)
3651 if (*template == '\n')
3652 count++;
3653
3654 return count;
3655}
3656
e9eba255
KH		 3657/* Compute the length of a shift insn. */
3658
86855e8c 3659unsigned int
cb713a8d 3660compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
86855e8c
KH		 3661{
3662 rtx shift = operands[3];
3663 enum machine_mode mode = GET_MODE (shift);
3664 enum rtx_code code = GET_CODE (shift);
3665 enum shift_type shift_type;
3666 enum shift_mode shift_mode;
3667 struct shift_info info;
3668 unsigned int wlength = 0;
3669
3670 switch (mode)
3671 {
3672 case QImode:
3673 shift_mode = QIshift;
3674 break;
3675 case HImode:
3676 shift_mode = HIshift;
3677 break;
3678 case SImode:
3679 shift_mode = SIshift;
3680 break;
3681 default:
3682 abort ();
3683 }
3684
3685 switch (code)
3686 {
3687 case ASHIFTRT:
3688 shift_type = SHIFT_ASHIFTRT;
3689 break;
3690 case LSHIFTRT:
3691 shift_type = SHIFT_LSHIFTRT;
3692 break;
3693 case ASHIFT:
3694 shift_type = SHIFT_ASHIFT;
3695 break;
3696 default:
3697 abort ();
3698 }
3699
3700 if (GET_CODE (operands[2]) != CONST_INT)
3701 {
3702 /* Get the assembler code to do one shift. */
3703 get_shift_alg (shift_type, shift_mode, 1, &info);
3704
3705 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3706 }
3707 else
3708 {
3709 int n = INTVAL (operands[2]);
3710
3711 /* If the count is negative, make it 0. */
3712 if (n < 0)
3713 n = 0;
3714 /* If the count is too big, truncate it.
3715 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3716 do the intuitive thing. */
3717 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3718 n = GET_MODE_BITSIZE (mode);
3719
3720 get_shift_alg (shift_type, shift_mode, n, &info);
3721
3722 switch (info.alg)
3723 {
3724 case SHIFT_SPECIAL:
3725 wlength += h8300_asm_insn_count (info.special);
41c3eb5d
KH		 3726
3727 /* Every assembly instruction used in SHIFT_SPECIAL case
3728 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3729 see xor.l, we just pretend that xor.l counts as two insns
3730 so that the insn length will be computed correctly. */
3731 if (strstr (info.special, "xor.l") != NULL)
3732 wlength++;
3733
86855e8c
KH		 3734 /* Fall through. */
3735
3736 case SHIFT_INLINE:
3737 n = info.remainder;
3738
3739 if (info.shift2 != NULL)
3740 {
3741 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3742 n = n % 2;
3743 }
3744
3745 wlength += h8300_asm_insn_count (info.shift1) * n;
6b148bd9 3746
86855e8c
KH		 3747 return 2 * wlength;
3748
3749 case SHIFT_ROT_AND:
3750 {
3751 int m = GET_MODE_BITSIZE (mode) - n;
3752
3753 /* Not all possibilities of rotate are supported. They shouldn't
3754 be generated, but let's watch for 'em. */
3755 if (info.shift1 == 0)
3756 abort ();
3757
3758 if (info.shift2 != NULL)
3759 {
3760 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3761 m = m % 2;
3762 }
3763
3764 wlength += h8300_asm_insn_count (info.shift1) * m;
6b148bd9 3765
86855e8c
KH		 3766 /* Now mask off the high bits. */
3767 switch (mode)
3768 {
3769 case QImode:
3770 wlength += 1;
3771 break;
3772 case HImode:
3773 wlength += 2;
3774 break;
3775 case SImode:
3776 if (TARGET_H8300)
3777 abort ();
3778 wlength += 3;
3779 break;
3780 default:
3781 abort ();
3782 }
3783 return 2 * wlength;
3784 }
3785
3786 case SHIFT_LOOP:
3787 /* A loop to shift by a "large" constant value.
3788 If we have shift-by-2 insns, use them. */
3789 if (info.shift2 != NULL)
3790 {
3791 wlength += 3 + h8300_asm_insn_count (info.shift2);
3792 if (n % 2)
3793 wlength += h8300_asm_insn_count (info.shift1);
3794 }
3795 else
3796 {
3797 wlength += 3 + h8300_asm_insn_count (info.shift1);
3798 }
3799 return 2 * wlength;
3800
3801 default:
3802 abort ();
3803 }
3804 }
3805}
45ca2106 3806
e9eba255
KH		 3807/* Compute which flag bits are valid after a shift insn. */
3808
45ca2106 3809int
cb713a8d 3810compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
45ca2106
KH		 3811{
3812 rtx shift = operands[3];
3813 enum machine_mode mode = GET_MODE (shift);
3814 enum rtx_code code = GET_CODE (shift);
3815 enum shift_type shift_type;
3816 enum shift_mode shift_mode;
3817 struct shift_info info;
3818
3819 switch (mode)
3820 {
3821 case QImode:
3822 shift_mode = QIshift;
3823 break;
3824 case HImode:
3825 shift_mode = HIshift;
3826 break;
3827 case SImode:
3828 shift_mode = SIshift;
3829 break;
3830 default:
3831 abort ();
3832 }
3833
3834 switch (code)
3835 {
3836 case ASHIFTRT:
3837 shift_type = SHIFT_ASHIFTRT;
3838 break;
3839 case LSHIFTRT:
3840 shift_type = SHIFT_LSHIFTRT;
3841 break;
3842 case ASHIFT:
3843 shift_type = SHIFT_ASHIFT;
3844 break;
3845 default:
3846 abort ();
3847 }
3848
3849 if (GET_CODE (operands[2]) != CONST_INT)
3850 {
3851 /* This case must be taken care of by one of the two splitters
3852 that convert a variable shift into a loop. */
3853 abort ();
3854 }
3855 else
3856 {
3857 int n = INTVAL (operands[2]);
3858
3859 /* If the count is negative, make it 0. */
3860 if (n < 0)
3861 n = 0;
3862 /* If the count is too big, truncate it.
3863 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3864 do the intuitive thing. */
3865 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3866 n = GET_MODE_BITSIZE (mode);
3867
3868 get_shift_alg (shift_type, shift_mode, n, &info);
3869
3870 switch (info.alg)
3871 {
3872 case SHIFT_SPECIAL:
3873 if (info.remainder == 0)
3874 return info.cc_special;
3875
3876 /* Fall through. */
3877
3878 case SHIFT_INLINE:
3879 return info.cc_inline;
3880
3881 case SHIFT_ROT_AND:
3882 /* This case always ends with an and instruction. */
3883 return CC_SET_ZNV;
3884
3885 case SHIFT_LOOP:
3886 /* A loop to shift by a "large" constant value.
3887 If we have shift-by-2 insns, use them. */
3888 if (info.shift2 != NULL)
3889 {
3890 if (n % 2)
3891 return info.cc_inline;
3892 }
3893 return CC_CLOBBER;
3894
3895 default:
3896 abort ();
3897 }
3898 }
3899}
48837e29 3900\f
edd71f0f
KH		 3901/* A rotation by a non-constant will cause a loop to be generated, in
3902 which a rotation by one bit is used. A rotation by a constant,
3903 including the one in the loop, will be taken care of by
caf7f21a 3904 output_a_rotate () at the insn emit time. */
edd71f0f
KH		 3905
3906int
3d2e90d6 3907expand_a_rotate (rtx operands[])
edd71f0f
KH		 3908{
3909 rtx dst = operands[0];
3910 rtx src = operands[1];
3911 rtx rotate_amount = operands[2];
3912 enum machine_mode mode = GET_MODE (dst);
edd71f0f
KH		 3913
3914 /* We rotate in place. */
3915 emit_move_insn (dst, src);
3916
3917 if (GET_CODE (rotate_amount) != CONST_INT)
3918 {
3919 rtx counter = gen_reg_rtx (QImode);
3920 rtx start_label = gen_label_rtx ();
3921 rtx end_label = gen_label_rtx ();
3922
3923 /* If the rotate amount is less than or equal to 0,
3924 we go out of the loop. */
a556fd39 3925 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
d43e0b7d 3926 QImode, 0, end_label);
edd71f0f
KH		 3927
3928 /* Initialize the loop counter. */
3929 emit_move_insn (counter, rotate_amount);
3930
3931 emit_label (start_label);
3932
3933 /* Rotate by one bit. */
01ab5574
KH		 3934 switch (mode)
3935 {
3936 case QImode:
3937 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
3938 break;
3939 case HImode:
3940 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
3941 break;
3942 case SImode:
3943 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
3944 break;
3945 default:
3946 abort ();
3947 }
edd71f0f
KH		 3948
3949 /* Decrement the counter by 1. */
01ab5574 3950 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
edd71f0f 3951
9cd10576 3952 /* If the loop counter is nonzero, we go back to the beginning
edd71f0f 3953 of the loop. */
a556fd39 3954 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
d43e0b7d 3955 start_label);
edd71f0f
KH		 3956
3957 emit_label (end_label);
3958 }
3959 else
3960 {
3961 /* Rotate by AMOUNT bits. */
01ab5574
KH		 3962 switch (mode)
3963 {
3964 case QImode:
3965 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
3966 break;
3967 case HImode:
3968 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
3969 break;
3970 case SImode:
3971 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
3972 break;
3973 default:
3974 abort ();
3975 }
edd71f0f
KH		 3976 }
3977
3978 return 1;
3979}
3980
e9eba255 3981/* Output a rotate insn. */
edd71f0f
KH		 3982
3983const char *
caf7f21a 3984output_a_rotate (enum rtx_code code, rtx *operands)
edd71f0f
KH		 3985{
3986 rtx dst = operands[0];
3987 rtx rotate_amount = operands[2];
3988 enum shift_mode rotate_mode;
3989 enum shift_type rotate_type;
3990 const char *insn_buf;
3991 int bits;
3992 int amount;
3993 enum machine_mode mode = GET_MODE (dst);
3994
3995 if (GET_CODE (rotate_amount) != CONST_INT)
3996 abort ();
3997
3998 switch (mode)
3999 {
4000 case QImode:
4001 rotate_mode = QIshift;
4002 break;
4003 case HImode:
4004 rotate_mode = HIshift;
4005 break;
4006 case SImode:
4007 rotate_mode = SIshift;
4008 break;
4009 default:
4010 abort ();
4011 }
4012
4013 switch (code)
4014 {
4015 case ROTATERT:
4016 rotate_type = SHIFT_ASHIFT;
4017 break;
4018 case ROTATE:
4019 rotate_type = SHIFT_LSHIFTRT;
4020 break;
4021 default:
4022 abort ();
4023 }
4024
4025 amount = INTVAL (rotate_amount);
4026
4027 /* Clean up AMOUNT. */
4028 if (amount < 0)
4029 amount = 0;
4030 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4031 amount = GET_MODE_BITSIZE (mode);
4032
4033 /* Determine the faster direction. After this phase, amount will be
4034 at most a half of GET_MODE_BITSIZE (mode). */
e0c32c62 4035 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
edd71f0f
KH		 4036 {
4037 /* Flip the direction. */
4038 amount = GET_MODE_BITSIZE (mode) - amount;
4039 rotate_type =
4040 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4041 }
4042
4043 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4044 boost up the rotation. */
4045 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4046 || (mode == HImode && TARGET_H8300H && amount >= 6)
4047 || (mode == HImode && TARGET_H8300S && amount == 8)
4048 || (mode == SImode && TARGET_H8300H && amount >= 10)
4049 || (mode == SImode && TARGET_H8300S && amount >= 13))
4050 {
4051 switch (mode)
4052 {
4053 case HImode:
4054 /* This code works on any family. */
4055 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
4056 output_asm_insn (insn_buf, operands);
4057 break;
4058
4059 case SImode:
3db11b5c 4060 /* This code works on the H8/300H and H8S. */
edd71f0f
KH		 4061 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
4062 output_asm_insn (insn_buf, operands);
4063 break;
4064
4065 default:
4066 abort ();
4067 }
4068
4069 /* Adjust AMOUNT and flip the direction. */
4070 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4071 rotate_type =
4072 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4073 }
4074
01ab5574 4075 /* Output rotate insns. */
edd71f0f
KH		 4076 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
4077 {
4078 if (bits == 2)
4079 insn_buf = rotate_two[rotate_type][rotate_mode];
4080 else
4081 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2c54abce 4082
edd71f0f
KH		 4083 for (; amount >= bits; amount -= bits)
4084 output_asm_insn (insn_buf, operands);
4085 }
4086
4087 return "";
4088}
caf7f21a 4089
e9eba255
KH		 4090/* Compute the length of a rotate insn. */
4091
caf7f21a
KH		 4092unsigned int
4093compute_a_rotate_length (rtx *operands)
4094{
4095 rtx src = operands[1];
343fd2c7 4096 rtx amount_rtx = operands[2];
caf7f21a
KH		 4097 enum machine_mode mode = GET_MODE (src);
4098 int amount;
4099 unsigned int length = 0;
4100
343fd2c7
KH		 4101 if (GET_CODE (amount_rtx) != CONST_INT)
4102 abort ();
caf7f21a 4103
343fd2c7 4104 amount = INTVAL (amount_rtx);
caf7f21a
KH		 4105
4106 /* Clean up AMOUNT. */
4107 if (amount < 0)
4108 amount = 0;
4109 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4110 amount = GET_MODE_BITSIZE (mode);
4111
4112 /* Determine the faster direction. After this phase, amount
4113 will be at most a half of GET_MODE_BITSIZE (mode). */
4114 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4115 /* Flip the direction. */
4116 amount = GET_MODE_BITSIZE (mode) - amount;
4117
4118 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4119 boost up the rotation. */
4120 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4121 || (mode == HImode && TARGET_H8300H && amount >= 6)
4122 || (mode == HImode && TARGET_H8300S && amount == 8)
4123 || (mode == SImode && TARGET_H8300H && amount >= 10)
4124 || (mode == SImode && TARGET_H8300S && amount >= 13))
4125 {
4126 /* Adjust AMOUNT and flip the direction. */
4127 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4128 length += 6;
4129 }
4130
4131 /* We use 2-bit rotations on the H8S. */
4132 if (TARGET_H8300S)
4133 amount = amount / 2 + amount % 2;
4134
4135 /* The H8/300 uses three insns to rotate one bit, taking 6
4136 length. */
4137 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4138
4139 return length;
4140}
edd71f0f 4141\f
48837e29 4142/* Fix the operands of a gen_xxx so that it could become a bit
2c54abce 4143 operating insn. */
07aae5c2
SC		 4144
4145int
4093985c 4146fix_bit_operand (rtx *operands, enum rtx_code code)
07aae5c2 4147{
abc95ed3 4148 /* The bit_operand predicate accepts any memory during RTL generation, but
48837e29
DE		 4149 only 'U' memory afterwards, so if this is a MEM operand, we must force
4150 it to be valid for 'U' by reloading the address. */
07aae5c2 4151
4093985c
KH		 4152 if (code == AND
4153 ? single_zero_operand (operands[2], QImode)
4154 : single_one_operand (operands[2], QImode))
07aae5c2 4155 {
2e760b15
KH		 4156 /* OK to have a memory dest. */
4157 if (GET_CODE (operands[0]) == MEM
4158 && !EXTRA_CONSTRAINT (operands[0], 'U'))
48837e29 4159 {
2e760b15
KH		 4160 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4161 copy_to_mode_reg (Pmode,
4162 XEXP (operands[0], 0)));
4163 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4164 operands[0] = mem;
4165 }
48837e29 4166
2e760b15
KH		 4167 if (GET_CODE (operands[1]) == MEM
4168 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4169 {
4170 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4171 copy_to_mode_reg (Pmode,
4172 XEXP (operands[1], 0)));
4173 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4174 operands[1] = mem;
48837e29 4175 }
2e760b15 4176 return 0;
48837e29 4177 }
07aae5c2 4178
48837e29 4179 /* Dest and src op must be register. */
07aae5c2 4180
48837e29
DE		 4181 operands[1] = force_reg (QImode, operands[1]);
4182 {
4183 rtx res = gen_reg_rtx (QImode);
fd57a6e4 4184 switch (code)
a3579575
KH		 4185 {
4186 case AND:
4187 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
4188 break;
4189 case IOR:
4190 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
4191 break;
4192 case XOR:
4193 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
4194 break;
4195 default:
4196 abort ();
4197 }
4198 emit_insn (gen_movqi (operands[0], res));
48837e29
DE		 4199 }
4200 return 1;
07aae5c2 4201}
f5b65a56 4202
f5b65a56
JL		 4203/* Return nonzero if FUNC is an interrupt function as specified
4204 by the "interrupt" attribute. */
4205
4206static int
cb713a8d 4207h8300_interrupt_function_p (tree func)
f5b65a56
JL		 4208{
4209 tree a;
4210
4211 if (TREE_CODE (func) != FUNCTION_DECL)
4212 return 0;
4213
91d231cb 4214 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
f5b65a56
JL		 4215 return a != NULL_TREE;
4216}
4217
3cfa3702
KH		 4218/* Return nonzero if FUNC is a saveall function as specified by the
4219 "saveall" attribute. */
4220
4221static int
4222h8300_saveall_function_p (tree func)
4223{
4224 tree a;
4225
4226 if (TREE_CODE (func) != FUNCTION_DECL)
4227 return 0;
4228
4229 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
4230 return a != NULL_TREE;
4231}
4232
fabe72bb
JL		 4233/* Return nonzero if FUNC is an OS_Task function as specified
4234 by the "OS_Task" attribute. */
4235
4236static int
cb713a8d 4237h8300_os_task_function_p (tree func)
fabe72bb
JL		 4238{
4239 tree a;
4240
4241 if (TREE_CODE (func) != FUNCTION_DECL)
4242 return 0;
4243
91d231cb 4244 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
fabe72bb
JL		 4245 return a != NULL_TREE;
4246}
4247
4248/* Return nonzero if FUNC is a monitor function as specified
4249 by the "monitor" attribute. */
4250
4251static int
cb713a8d 4252h8300_monitor_function_p (tree func)
fabe72bb
JL		 4253{
4254 tree a;
4255
4256 if (TREE_CODE (func) != FUNCTION_DECL)
4257 return 0;
4258
91d231cb 4259 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
fabe72bb
JL		 4260 return a != NULL_TREE;
4261}
4262
f5b65a56
JL		 4263/* Return nonzero if FUNC is a function that should be called
4264 through the function vector. */
4265
4266int
cb713a8d 4267h8300_funcvec_function_p (tree func)
f5b65a56
JL		 4268{
4269 tree a;
4270
4271 if (TREE_CODE (func) != FUNCTION_DECL)
4272 return 0;
4273
91d231cb 4274 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
f5b65a56
JL		 4275 return a != NULL_TREE;
4276}
4277
887a8bd9 4278/* Return nonzero if DECL is a variable that's in the eight bit
15dc331e
JL		 4279 data area. */
4280
4281int
cb713a8d 4282h8300_eightbit_data_p (tree decl)
15dc331e
JL		 4283{
4284 tree a;
4285
4286 if (TREE_CODE (decl) != VAR_DECL)
4287 return 0;
4288
91d231cb 4289 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
15dc331e
JL		 4290 return a != NULL_TREE;
4291}
4292
887a8bd9
JL		 4293/* Return nonzero if DECL is a variable that's in the tiny
4294 data area. */
4295
4296int
cb713a8d 4297h8300_tiny_data_p (tree decl)
887a8bd9
JL		 4298{
4299 tree a;
4300
4301 if (TREE_CODE (decl) != VAR_DECL)
4302 return 0;
4303
91d231cb 4304 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
887a8bd9
JL		 4305 return a != NULL_TREE;
4306}
4307
3cfa3702
KH		 4308/* Generate an 'interrupt_handler' attribute for decls. We convert
4309 all the pragmas to corresponding attributes. */
2c1d2fcb
DD		 4310
4311static void
cb713a8d 4312h8300_insert_attributes (tree node, tree *attributes)
2c1d2fcb 4313{
3cfa3702
KH		 4314 if (TREE_CODE (node) == FUNCTION_DECL)
4315 {
4316 if (pragma_interrupt)
4317 {
4318 pragma_interrupt = 0;
2c1d2fcb 4319
3cfa3702
KH		 4320 /* Add an 'interrupt_handler' attribute. */
4321 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4322 NULL, *attributes);
4323 }
e392d367 4324
3cfa3702
KH		 4325 if (pragma_saveall)
4326 {
4327 pragma_saveall = 0;
4328
4329 /* Add an 'saveall' attribute. */
4330 *attributes = tree_cons (get_identifier ("saveall"),
4331 NULL, *attributes);
4332 }
4333 }
2c1d2fcb
DD		 4334}
4335
91d231cb 4336/* Supported attributes:
f5b65a56 4337
97c5ec1d 4338 interrupt_handler: output a prologue and epilogue suitable for an
f5b65a56
JL		 4339 interrupt handler.
4340
3cfa3702
KH		 4341 saveall: output a prologue and epilogue that saves and restores
4342 all registers except the stack pointer.
4343
97c5ec1d 4344 function_vector: This function should be called through the
887a8bd9
JL		 4345 function vector.
4346
4347 eightbit_data: This variable lives in the 8-bit data area and can
4348 be referenced with 8-bit absolute memory addresses.
4349
4350 tiny_data: This variable lives in the tiny data area and can be
4351 referenced with 16-bit absolute memory references. */
f5b65a56 4352
91d231cb 4353const struct attribute_spec h8300_attribute_table[] =
f5b65a56 4354{
91d231cb
JM		 4355 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4356 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3cfa3702 4357 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
91d231cb
JM		 4358 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4359 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4360 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4361 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4362 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4363 { NULL, 0, 0, false, false, false, NULL }
4364};
f5b65a56 4365
15dc331e 4366
91d231cb
JM		 4367/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4368 struct attribute_spec.handler. */
4369static tree
cb713a8d
KH		 4370h8300_handle_fndecl_attribute (tree *node, tree name,
4371 tree args ATTRIBUTE_UNUSED,
4372 int flags ATTRIBUTE_UNUSED,
4373 bool *no_add_attrs)
91d231cb
JM		 4374{
4375 if (TREE_CODE (*node) != FUNCTION_DECL)
4376 {
4377 warning ("`%s' attribute only applies to functions",
4378 IDENTIFIER_POINTER (name));
4379 *no_add_attrs = true;
4380 }
4381
4382 return NULL_TREE;
4383}
4384
4385/* Handle an "eightbit_data" attribute; arguments as in
4386 struct attribute_spec.handler. */
4387static tree
cb713a8d
KH		 4388h8300_handle_eightbit_data_attribute (tree *node, tree name,
4389 tree args ATTRIBUTE_UNUSED,
4390 int flags ATTRIBUTE_UNUSED,
4391 bool *no_add_attrs)
91d231cb
JM		 4392{
4393 tree decl = *node;
4394
4395 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
15dc331e 4396 {
64378c91 4397 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
91d231cb
JM		 4398 }
4399 else
4400 {
4401 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4402 *no_add_attrs = true;
887a8bd9
JL		 4403 }
4404
91d231cb
JM		 4405 return NULL_TREE;
4406}
4407
4408/* Handle an "tiny_data" attribute; arguments as in
4409 struct attribute_spec.handler. */
4410static tree
cb713a8d
KH		 4411h8300_handle_tiny_data_attribute (tree *node, tree name,
4412 tree args ATTRIBUTE_UNUSED,
4413 int flags ATTRIBUTE_UNUSED,
4414 bool *no_add_attrs)
91d231cb
JM		 4415{
4416 tree decl = *node;
4417
4418 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
887a8bd9 4419 {
64378c91 4420 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
91d231cb
JM		 4421 }
4422 else
4423 {
4424 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4425 *no_add_attrs = true;
15dc331e 4426 }
07e4d94e 4427
91d231cb 4428 return NULL_TREE;
f5b65a56
JL		 4429}
4430
dc66a1c4 4431/* Mark function vectors, and various small data objects. */
fb49053f
RH		 4432
4433static void
cb713a8d 4434h8300_encode_section_info (tree decl, rtx rtl, int first)
fb49053f 4435{
dc66a1c4
RH		 4436 int extra_flags = 0;
4437
c6a2438a 4438 default_encode_section_info (decl, rtl, first);
dc66a1c4 4439
fb49053f
RH		 4440 if (TREE_CODE (decl) == FUNCTION_DECL
4441 && h8300_funcvec_function_p (decl))
dc66a1c4 4442 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
fb49053f
RH		 4443 else if (TREE_CODE (decl) == VAR_DECL
4444 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4445 {
4446 if (h8300_eightbit_data_p (decl))
dc66a1c4 4447 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
fb49053f 4448 else if (first && h8300_tiny_data_p (decl))
dc66a1c4 4449 extra_flags = SYMBOL_FLAG_TINY_DATA;
fb49053f 4450 }
772c5265 4451
dc66a1c4 4452 if (extra_flags)
c6a2438a 4453 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
772c5265
RH		 4454}
4455
e9eba255
KH		 4456/* Output a single-bit extraction. */
4457
441d04c6 4458const char *
cb713a8d 4459output_simode_bld (int bild, rtx operands[])
bd93f126 4460{
6be580c7
KH		 4461 if (TARGET_H8300)
4462 {
4463 /* Clear the destination register. */
4464 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4465
4466 /* Now output the bit load or bit inverse load, and store it in
4467 the destination. */
4468 if (bild)
4469 output_asm_insn ("bild\t%Z2,%Y1", operands);
4470 else
4471 output_asm_insn ("bld\t%Z2,%Y1", operands);
bd93f126 4472
6be580c7
KH		 4473 output_asm_insn ("bst\t#0,%w0", operands);
4474 }
bd93f126 4475 else
6be580c7 4476 {
0eb933a0
KH		 4477 /* Determine if we can clear the destination first. */
4478 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4479 && REGNO (operands[0]) != REGNO (operands[1]));
4480
4481 if (clear_first)
4482 output_asm_insn ("sub.l\t%S0,%S0", operands);
4483
6be580c7
KH		 4484 /* Output the bit load or bit inverse load. */
4485 if (bild)
4486 output_asm_insn ("bild\t%Z2,%Y1", operands);
4487 else
4488 output_asm_insn ("bld\t%Z2,%Y1", operands);
4489
0eb933a0
KH		 4490 if (!clear_first)
4491 output_asm_insn ("xor.l\t%S0,%S0", operands);
4492
4493 /* Perform the bit store. */
802a9907 4494 output_asm_insn ("rotxl.l\t%S0", operands);
6be580c7 4495 }
bd93f126
JL		 4496
4497 /* All done. */
4498 return "";
4499}
e6219736 4500
ede75ee8 4501#ifndef OBJECT_FORMAT_ELF
7c262518 4502static void
cb713a8d 4503h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
7c262518
RH		 4504{
4505 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4506 fprintf (asm_out_file, "\t.section %s\n", name);
4507}
ede75ee8 4508#endif /* ! OBJECT_FORMAT_ELF */
803d56f5 4509
7c143ed2
KH		 4510/* Nonzero if X is a constant address suitable as an 8-bit absolute,
4511 which is a special case of the 'R' operand. */
4512
803d56f5 4513int
cb713a8d 4514h8300_eightbit_constant_address_p (rtx x)
803d56f5 4515{
ff482c8d 4516 /* The ranges of the 8-bit area. */
d2d199a3
KH		 4517 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4518 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
803d56f5
KH		 4519 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4520 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4521 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4522 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4523
4524 unsigned HOST_WIDE_INT addr;
4525
9675a91e 4526 /* We accept symbols declared with eightbit_data. */
dc66a1c4
RH		 4527 if (GET_CODE (x) == SYMBOL_REF)
4528 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
9675a91e 4529
803d56f5
KH		 4530 if (GET_CODE (x) != CONST_INT)
4531 return 0;
4532
4533 addr = INTVAL (x);
4534
4535 return (0
39ba95b5 4536 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
803d56f5
KH		 4537 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4538 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4539}
4540
7c143ed2
KH		 4541/* Nonzero if X is a constant address suitable as an 16-bit absolute
4542 on H8/300H and H8S. */
4543
803d56f5 4544int
cb713a8d 4545h8300_tiny_constant_address_p (rtx x)
803d56f5 4546{
3f7211f1 4547 /* The ranges of the 16-bit area. */
803d56f5
KH		 4548 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4549 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4550 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4551 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4552 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4553 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4554 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4555 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4556
4557 unsigned HOST_WIDE_INT addr;
4558
d6456562
KH		 4559 switch (GET_CODE (x))
4560 {
4561 case SYMBOL_REF:
a4bb41cc
KH		 4562 /* In the normal mode, any symbol fits in the 16-bit absolute
4563 address range. We also accept symbols declared with
4564 tiny_data. */
4565 return (TARGET_NORMAL_MODE
4566 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
56b8e164 4567
d6456562
KH		 4568 case CONST_INT:
4569 addr = INTVAL (x);
4570 return (TARGET_NORMAL_MODE
4571 || (TARGET_H8300H
4572 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4573 || (TARGET_H8300S
4574 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
803d56f5 4575
a4bb41cc
KH		 4576 case CONST:
4577 return TARGET_NORMAL_MODE;
4578
d6456562
KH		 4579 default:
4580 return 0;
4581 }
803d56f5 4582
803d56f5 4583}
9b98dc74 4584
e9eba255
KH		 4585/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
4586 locations that can be accessed as a 16-bit word. */
4587
9b98dc74 4588int
cb713a8d 4589byte_accesses_mergeable_p (rtx addr1, rtx addr2)
9b98dc74
KH		 4590{
4591 HOST_WIDE_INT offset1, offset2;
4592 rtx reg1, reg2;
4593
4594 if (REG_P (addr1))
4595 {
4596 reg1 = addr1;
4597 offset1 = 0;
4598 }
4599 else if (GET_CODE (addr1) == PLUS
4600 && REG_P (XEXP (addr1, 0))
4601 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4602 {
4603 reg1 = XEXP (addr1, 0);
4604 offset1 = INTVAL (XEXP (addr1, 1));
4605 }
4606 else
4607 return 0;
4608
4609 if (REG_P (addr2))
4610 {
4611 reg2 = addr2;
4612 offset2 = 0;
4613 }
4614 else if (GET_CODE (addr2) == PLUS
4615 && REG_P (XEXP (addr2, 0))
4616 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4617 {
4618 reg2 = XEXP (addr2, 0);
4619 offset2 = INTVAL (XEXP (addr2, 1));
4620 }
4621 else
4622 return 0;
4623
4624 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4625 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4626 && offset1 % 2 == 0
4627 && offset1 + 1 == offset2)
4628 return 1;
4629
4630 return 0;
4631}
02529902
KH		 4632
4633/* Return nonzero if we have the same comparison insn as I3 two insns
19cff4db 4634 before I3. I3 is assumed to be a comparison insn. */
02529902
KH		 4635
4636int
4637same_cmp_preceding_p (rtx i3)
4638{
4639 rtx i1, i2;
4640
4641 /* Make sure we have a sequence of three insns. */
4642 i2 = prev_nonnote_insn (i3);
4643 if (i2 == NULL_RTX)
4644 return 0;
4645 i1 = prev_nonnote_insn (i2);
4646 if (i1 == NULL_RTX)
4647 return 0;
4648
4649 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4650 && any_condjump_p (i2) && onlyjump_p (i2));
4651}
c87ec0ba 4652
c06d5c85
KH		 4653/* Return nonzero if we have the same comparison insn as I1 two insns
4654 after I1. I1 is assumed to be a comparison insn. */
4655
4656int
4657same_cmp_following_p (rtx i1)
4658{
4659 rtx i2, i3;
4660
4661 /* Make sure we have a sequence of three insns. */
4662 i2 = next_nonnote_insn (i1);
4663 if (i2 == NULL_RTX)
4664 return 0;
4665 i3 = next_nonnote_insn (i2);
4666 if (i3 == NULL_RTX)
4667 return 0;
4668
4669 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4670 && any_condjump_p (i2) && onlyjump_p (i2));
4671}
4672
a466bea3 4673/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
1ae58c30 4674 (or pops) N registers. OPERANDS are assumed to be an array of
a466bea3
KH		 4675 registers. */
4676
4677int
4678h8300_regs_ok_for_stm (int n, rtx operands[])
4679{
4680 switch (n)
4681 {
4682 case 2:
4683 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4684 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4685 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
4686 case 3:
4687 return ((REGNO (operands[0]) == 0
4688 && REGNO (operands[1]) == 1
4689 && REGNO (operands[2]) == 2)
4690 || (REGNO (operands[0]) == 4
4691 && REGNO (operands[1]) == 5
4692 && REGNO (operands[2]) == 6));
4693
4694 case 4:
4695 return (REGNO (operands[0]) == 0
4696 && REGNO (operands[1]) == 1
4697 && REGNO (operands[2]) == 2
4698 && REGNO (operands[3]) == 3);
4699 }
4700
4701 abort ();
4702}
4703
c87ec0ba
NY		 4704/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
4705
4706int
4707h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4708 unsigned int new_reg)
4709{
4710 /* Interrupt functions can only use registers that have already been
4711 saved by the prologue, even if they would normally be
4712 call-clobbered. */
4713
4714 if (h8300_current_function_interrupt_function_p ()
4715 && !regs_ever_live[new_reg])
4716 return 0;
4717
80e58519 4718 return 1;
c87ec0ba 4719}
d0022200
KH		 4720
4721/* Return nonzero if X is a legitimate constant. */
4722
4723int
4724h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
4725{
4726 return 1;
4727}
4728
4729/* Return nonzero if X is a REG or SUBREG suitable as a base register. */
4730
4731static int
4732h8300_rtx_ok_for_base_p (rtx x, int strict)
4733{
4734 /* Strip off SUBREG if any. */
4735 if (GET_CODE (x) == SUBREG)
4736 x = SUBREG_REG (x);
4737
4738 return (REG_P (x)
4739 && (strict
4740 ? REG_OK_FOR_BASE_STRICT_P (x)
4741 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
4742}
4743
4744/* Return nozero if X is a legitimate address. On the H8/300, a
4745 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
4746 CONSTANT_ADDRESS. */
4747
4748int
4749h8300_legitimate_address_p (rtx x, int strict)
4750{
4751 /* The register indirect addresses like @er0 is always valid. */
4752 if (h8300_rtx_ok_for_base_p (x, strict))
4753 return 1;
4754
4755 if (CONSTANT_ADDRESS_P (x))
4756 return 1;
4757
4758 if (GET_CODE (x) == PLUS
4759 && CONSTANT_ADDRESS_P (XEXP (x, 1))
4760 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
4761 return 1;
4762
4763 return 0;
4764}
07ee3b58
KH		 4765
4766/* Worker function for HARD_REGNO_NREGS.
4767
4768 We pretend the MAC register is 32bits -- we don't have any data
4769 types on the H8 series to handle more than 32bits. */
4770
4771int
4772h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
4773{
4774 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4775}
4776
4777/* Worker function for HARD_REGNO_MODE_OK. */
4778
4779int
4780h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
4781{
4782 if (TARGET_H8300)
4783 /* If an even reg, then anything goes. Otherwise the mode must be
4784 QI or HI. */
4785 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
4786 else
4787 /* MAC register can only be of SImode. Otherwise, anything
4788 goes. */
4789 return regno == MAC_REG ? mode == SImode : 1;
4790}
6e014ef3 4791\f
c15c90bb
ZW		 4792/* Perform target dependent optabs initialization. */
4793static void
4794h8300_init_libfuncs (void)
4795{
4796 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4797 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4798 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4799 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4800 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4801}
4802\f
e9eba255
KH		 4803/* Worker function for TARGET_RETURN_IN_MEMORY. */
4804
34bf1fe3
KH		 4805static bool
4806h8300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4807{
4808 return (TYPE_MODE (type) == BLKmode
4809 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
4810}
4811\f
6e014ef3
KH		 4812/* Initialize the GCC target structure. */
4813#undef TARGET_ATTRIBUTE_TABLE
4814#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4815
4816#undef TARGET_ASM_ALIGNED_HI_OP
4817#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4818
1bc7c5b6
ZW		 4819#undef TARGET_ASM_FILE_START
4820#define TARGET_ASM_FILE_START h8300_file_start
4821#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4822#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4823
6e014ef3
KH		 4824#undef TARGET_ASM_FILE_END
4825#define TARGET_ASM_FILE_END h8300_file_end
4826
4827#undef TARGET_ENCODE_SECTION_INFO
4828#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4829
4830#undef TARGET_INSERT_ATTRIBUTES
4831#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4832
4833#undef TARGET_RTX_COSTS
4834#define TARGET_RTX_COSTS h8300_rtx_costs
4835
c15c90bb
ZW		 4836#undef TARGET_INIT_LIBFUNCS
4837#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
4838
34bf1fe3
KH		 4839#undef TARGET_RETURN_IN_MEMORY
4840#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
4841
6e014ef3 4842struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git