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[thirdparty/kernel/stable-queue.git] / releases / 6.8.6 / drm-amd-display-increased-min_dcfclk_mhz-and-min_fcl.patch
CommitLineData
335f7cc0
SL
1From e0e410db0c791d8722264866500755c2bd36cd48 Mon Sep 17 00:00:00 2001
2From: Sasha Levin <sashal@kernel.org>
3Date: Tue, 16 Jan 2024 11:00:00 -0500
4Subject: drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz
5
6From: Sohaib Nadeem <sohaib.nadeem@amd.com>
7
8[ Upstream commit d46fb0068c54d3dc95ae8298299c4d9edb0fb7c1 ]
9
10[why]
11Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased
12to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware
13requirement will still be satisfied. Increasing min DCFCLK addresses
14underflow issues (underflow occurs when phantom pipe is turned on for some
15Sub-Viewport configs).
16
17[how]
18Increasing DCFCLK by raising the min_dcfclk_mhz
19
20Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
21Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
22Acked-by: Tom Chung <chiahsuan.chung@amd.com>
23Signed-off-by: Sohaib Nadeem <sohaib.nadeem@amd.com>
24Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
25Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
26Signed-off-by: Sasha Levin <sashal@kernel.org>
27---
28 drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
29 1 file changed, 1 insertion(+), 1 deletion(-)
30
31diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
32index a0a65e0991041..ba76dd4a2ce29 100644
33--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
34+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
35@@ -2760,7 +2760,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk
36 struct _vcs_dpi_voltage_scaling_st entry = {0};
37 struct clk_limit_table_entry max_clk_data = {0};
38
39- unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
40+ unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599;
41
42 static const unsigned int num_dcfclk_stas = 5;
43 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
44--
452.43.0
46