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hw/net/lan9118: Replace magic '2048' value by MIL_TXFIFO_SIZE definition
[thirdparty/qemu.git] / hw / net / lan9118.c
CommitLineData
2a424990
PB		 1/*
2 * SMSC LAN9118 Ethernet interface emulation
3 *
4 * Copyright (c) 2009 CodeSourcery, LLC.
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the GNU GPL v2
6b620ca3
PB		 8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
2a424990
PB		 11 */
12
e8d40465 13#include "qemu/osdep.h"
83c9f4ca 14#include "hw/sysbus.h"
d6454270 15#include "migration/vmstate.h"
1422e32d 16#include "net/net.h"
eedeaee7 17#include "net/eth.h"
64552b6b 18#include "hw/irq.h"
66b03dce 19#include "hw/net/lan9118.h"
83c9f4ca 20#include "hw/ptimer.h"
a27bd6c7 21#include "hw/qdev-properties.h"
3e80f690 22#include "qapi/error.h"
03dd024f 23#include "qemu/log.h"
0b8fa32f 24#include "qemu/module.h"
2a424990
PB		 25/* For crc32 */
26#include <zlib.h>
db1015e9 27#include "qom/object.h"
2a424990
PB		 28
29//#define DEBUG_LAN9118
30
31#ifdef DEBUG_LAN9118
32#define DPRINTF(fmt, ...) \
33do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
2a424990
PB		 34#else
35#define DPRINTF(fmt, ...) do {} while(0)
2a424990
PB		 36#endif
37
5cab6d5a
PM		 38/* The tx and rx fifo ports are a range of aliased 32-bit registers */
39#define RX_DATA_FIFO_PORT_FIRST 0x00
40#define RX_DATA_FIFO_PORT_LAST 0x1f
41#define TX_DATA_FIFO_PORT_FIRST 0x20
42#define TX_DATA_FIFO_PORT_LAST 0x3f
43
44#define RX_STATUS_FIFO_PORT 0x40
45#define RX_STATUS_FIFO_PEEK 0x44
46#define TX_STATUS_FIFO_PORT 0x48
47#define TX_STATUS_FIFO_PEEK 0x4c
48
2a424990
PB		 49#define CSR_ID_REV 0x50
50#define CSR_IRQ_CFG 0x54
51#define CSR_INT_STS 0x58
52#define CSR_INT_EN 0x5c
53#define CSR_BYTE_TEST 0x64
54#define CSR_FIFO_INT 0x68
55#define CSR_RX_CFG 0x6c
56#define CSR_TX_CFG 0x70
57#define CSR_HW_CFG 0x74
58#define CSR_RX_DP_CTRL 0x78
59#define CSR_RX_FIFO_INF 0x7c
60#define CSR_TX_FIFO_INF 0x80
61#define CSR_PMT_CTRL 0x84
62#define CSR_GPIO_CFG 0x88
209bf965
PB		 63#define CSR_GPT_CFG 0x8c
64#define CSR_GPT_CNT 0x90
2a424990
PB		 65#define CSR_WORD_SWAP 0x98
66#define CSR_FREE_RUN 0x9c
67#define CSR_RX_DROP 0xa0
68#define CSR_MAC_CSR_CMD 0xa4
69#define CSR_MAC_CSR_DATA 0xa8
70#define CSR_AFC_CFG 0xac
71#define CSR_E2P_CMD 0xb0
72#define CSR_E2P_DATA 0xb4
73
12fdd928
AB		 74#define E2P_CMD_MAC_ADDR_LOADED 0x100
75
2a424990 76/* IRQ_CFG */
209bf965 77#define IRQ_INT 0x00001000
2a424990
PB		 78#define IRQ_EN 0x00000100
79#define IRQ_POL 0x00000010
80#define IRQ_TYPE 0x00000001
81
82/* INT_STS/INT_EN */
83#define SW_INT 0x80000000
84#define TXSTOP_INT 0x02000000
85#define RXSTOP_INT 0x01000000
86#define RXDFH_INT 0x00800000
87#define TX_IOC_INT 0x00200000
88#define RXD_INT 0x00100000
89#define GPT_INT 0x00080000
90#define PHY_INT 0x00040000
91#define PME_INT 0x00020000
92#define TXSO_INT 0x00010000
93#define RWT_INT 0x00008000
94#define RXE_INT 0x00004000
95#define TXE_INT 0x00002000
96#define TDFU_INT 0x00000800
97#define TDFO_INT 0x00000400
98#define TDFA_INT 0x00000200
99#define TSFF_INT 0x00000100
100#define TSFL_INT 0x00000080
101#define RXDF_INT 0x00000040
102#define RDFL_INT 0x00000020
103#define RSFF_INT 0x00000010
104#define RSFL_INT 0x00000008
105#define GPIO2_INT 0x00000004
106#define GPIO1_INT 0x00000002
107#define GPIO0_INT 0x00000001
108#define RESERVED_INT 0x7c001000
109
110#define MAC_CR 1
111#define MAC_ADDRH 2
112#define MAC_ADDRL 3
113#define MAC_HASHH 4
114#define MAC_HASHL 5
115#define MAC_MII_ACC 6
116#define MAC_MII_DATA 7
117#define MAC_FLOW 8
118#define MAC_VLAN1 9 /* TODO */
119#define MAC_VLAN2 10 /* TODO */
120#define MAC_WUFF 11 /* TODO */
121#define MAC_WUCSR 12 /* TODO */
122
123#define MAC_CR_RXALL 0x80000000
124#define MAC_CR_RCVOWN 0x00800000
125#define MAC_CR_LOOPBK 0x00200000
126#define MAC_CR_FDPX 0x00100000
127#define MAC_CR_MCPAS 0x00080000
128#define MAC_CR_PRMS 0x00040000
129#define MAC_CR_INVFILT 0x00020000
130#define MAC_CR_PASSBAD 0x00010000
131#define MAC_CR_HO 0x00008000
132#define MAC_CR_HPFILT 0x00002000
133#define MAC_CR_LCOLL 0x00001000
134#define MAC_CR_BCAST 0x00000800
135#define MAC_CR_DISRTY 0x00000400
136#define MAC_CR_PADSTR 0x00000100
137#define MAC_CR_BOLMT 0x000000c0
138#define MAC_CR_DFCHK 0x00000020
139#define MAC_CR_TXEN 0x00000008
140#define MAC_CR_RXEN 0x00000004
141#define MAC_CR_RESERVED 0x7f404213
142
209bf965
PB		 143#define PHY_INT_ENERGYON 0x80
144#define PHY_INT_AUTONEG_COMPLETE 0x40
145#define PHY_INT_FAULT 0x20
146#define PHY_INT_DOWN 0x10
147#define PHY_INT_AUTONEG_LP 0x08
148#define PHY_INT_PARFAULT 0x04
149#define PHY_INT_AUTONEG_PAGE 0x02
150
151#define GPT_TIMER_EN 0x20000000
152
a4522346
PMD		 153/*
154 * The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit
155 * and a 128 Byte receive FIFO which is separate from the TX and RX FIFOs.
156 */
157#define MIL_TXFIFO_SIZE 2048
158
2a424990
PB		 159enum tx_state {
160 TX_IDLE,
161 TX_B,
162 TX_DATA
163};
164
165typedef struct {
b09da0c3
PM		 166 /* state is a tx_state but we can't put enums in VMStateDescriptions. */
167 uint32_t state;
2a424990
PB		 168 uint32_t cmd_a;
169 uint32_t cmd_b;
b09da0c3
PM		 170 int32_t buffer_size;
171 int32_t offset;
172 int32_t pad;
173 int32_t fifo_used;
174 int32_t len;
a4522346 175 uint8_t data[MIL_TXFIFO_SIZE];
2a424990
PB		 176} LAN9118Packet;
177
b09da0c3
PM		 178static const VMStateDescription vmstate_lan9118_packet = {
179 .name = "lan9118_packet",
180 .version_id = 1,
181 .minimum_version_id = 1,
1de81b42 182 .fields = (const VMStateField[]) {
b09da0c3
PM		 183 VMSTATE_UINT32(state, LAN9118Packet),
184 VMSTATE_UINT32(cmd_a, LAN9118Packet),
185 VMSTATE_UINT32(cmd_b, LAN9118Packet),
186 VMSTATE_INT32(buffer_size, LAN9118Packet),
187 VMSTATE_INT32(offset, LAN9118Packet),
188 VMSTATE_INT32(pad, LAN9118Packet),
189 VMSTATE_INT32(fifo_used, LAN9118Packet),
190 VMSTATE_INT32(len, LAN9118Packet),
a4522346 191 VMSTATE_UINT8_ARRAY(data, LAN9118Packet, MIL_TXFIFO_SIZE),
b09da0c3
PM		 192 VMSTATE_END_OF_LIST()
193 }
194};
195
8063396b 196OBJECT_DECLARE_SIMPLE_TYPE(lan9118_state, LAN9118)
3ff66d10 197
db1015e9 198struct lan9118_state {
3ff66d10
AF		 199 SysBusDevice parent_obj;
200
83b9f88c 201 NICState *nic;
2a424990
PB		 202 NICConf conf;
203 qemu_irq irq;
f0cdd7a9 204 MemoryRegion mmio;
209bf965 205 ptimer_state *timer;
2a424990
PB		 206
207 uint32_t irq_cfg;
208 uint32_t int_sts;
209 uint32_t int_en;
210 uint32_t fifo_int;
211 uint32_t rx_cfg;
212 uint32_t tx_cfg;
213 uint32_t hw_cfg;
214 uint32_t pmt_ctrl;
215 uint32_t gpio_cfg;
209bf965 216 uint32_t gpt_cfg;
2a424990
PB		 217 uint32_t word_swap;
218 uint32_t free_timer_start;
219 uint32_t mac_cmd;
220 uint32_t mac_data;
221 uint32_t afc_cfg;
222 uint32_t e2p_cmd;
223 uint32_t e2p_data;
224
225 uint32_t mac_cr;
226 uint32_t mac_hashh;
227 uint32_t mac_hashl;
228 uint32_t mac_mii_acc;
229 uint32_t mac_mii_data;
230 uint32_t mac_flow;
231
232 uint32_t phy_status;
233 uint32_t phy_control;
234 uint32_t phy_advertise;
209bf965
PB		 235 uint32_t phy_int;
236 uint32_t phy_int_mask;
2a424990 237
b09da0c3 238 int32_t eeprom_writable;
c46a3ea0 239 uint8_t eeprom[128];
2a424990 240
b09da0c3 241 int32_t tx_fifo_size;
2a424990
PB		 242 LAN9118Packet *txp;
243 LAN9118Packet tx_packet;
244
b09da0c3
PM		 245 int32_t tx_status_fifo_used;
246 int32_t tx_status_fifo_head;
2a424990
PB		 247 uint32_t tx_status_fifo[512];
248
b09da0c3
PM		 249 int32_t rx_status_fifo_size;
250 int32_t rx_status_fifo_used;
251 int32_t rx_status_fifo_head;
2a424990 252 uint32_t rx_status_fifo[896];
b09da0c3
PM		 253 int32_t rx_fifo_size;
254 int32_t rx_fifo_used;
255 int32_t rx_fifo_head;
2a424990 256 uint32_t rx_fifo[3360];
b09da0c3
PM		 257 int32_t rx_packet_size_head;
258 int32_t rx_packet_size_tail;
259 int32_t rx_packet_size[1024];
2a424990 260
b09da0c3
PM		 261 int32_t rxp_offset;
262 int32_t rxp_size;
263 int32_t rxp_pad;
1248f8d4
EV		 264
265 uint32_t write_word_prev_offset;
266 uint32_t write_word_n;
267 uint16_t write_word_l;
268 uint16_t write_word_h;
269 uint32_t read_word_prev_offset;
270 uint32_t read_word_n;
271 uint32_t read_long;
272
273 uint32_t mode_16bit;
db1015e9 274};
2a424990 275
b09da0c3
PM		 276static const VMStateDescription vmstate_lan9118 = {
277 .name = "lan9118",
1248f8d4 278 .version_id = 2,
b09da0c3 279 .minimum_version_id = 1,
1de81b42 280 .fields = (const VMStateField[]) {
b09da0c3
PM		 281 VMSTATE_PTIMER(timer, lan9118_state),
282 VMSTATE_UINT32(irq_cfg, lan9118_state),
283 VMSTATE_UINT32(int_sts, lan9118_state),
284 VMSTATE_UINT32(int_en, lan9118_state),
285 VMSTATE_UINT32(fifo_int, lan9118_state),
286 VMSTATE_UINT32(rx_cfg, lan9118_state),
287 VMSTATE_UINT32(tx_cfg, lan9118_state),
288 VMSTATE_UINT32(hw_cfg, lan9118_state),
289 VMSTATE_UINT32(pmt_ctrl, lan9118_state),
290 VMSTATE_UINT32(gpio_cfg, lan9118_state),
291 VMSTATE_UINT32(gpt_cfg, lan9118_state),
292 VMSTATE_UINT32(word_swap, lan9118_state),
293 VMSTATE_UINT32(free_timer_start, lan9118_state),
294 VMSTATE_UINT32(mac_cmd, lan9118_state),
295 VMSTATE_UINT32(mac_data, lan9118_state),
296 VMSTATE_UINT32(afc_cfg, lan9118_state),
297 VMSTATE_UINT32(e2p_cmd, lan9118_state),
298 VMSTATE_UINT32(e2p_data, lan9118_state),
299 VMSTATE_UINT32(mac_cr, lan9118_state),
300 VMSTATE_UINT32(mac_hashh, lan9118_state),
301 VMSTATE_UINT32(mac_hashl, lan9118_state),
302 VMSTATE_UINT32(mac_mii_acc, lan9118_state),
303 VMSTATE_UINT32(mac_mii_data, lan9118_state),
304 VMSTATE_UINT32(mac_flow, lan9118_state),
305 VMSTATE_UINT32(phy_status, lan9118_state),
306 VMSTATE_UINT32(phy_control, lan9118_state),
307 VMSTATE_UINT32(phy_advertise, lan9118_state),
308 VMSTATE_UINT32(phy_int, lan9118_state),
309 VMSTATE_UINT32(phy_int_mask, lan9118_state),
310 VMSTATE_INT32(eeprom_writable, lan9118_state),
311 VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
312 VMSTATE_INT32(tx_fifo_size, lan9118_state),
313 /* txp always points at tx_packet so need not be saved */
314 VMSTATE_STRUCT(tx_packet, lan9118_state, 0,
315 vmstate_lan9118_packet, LAN9118Packet),
316 VMSTATE_INT32(tx_status_fifo_used, lan9118_state),
317 VMSTATE_INT32(tx_status_fifo_head, lan9118_state),
318 VMSTATE_UINT32_ARRAY(tx_status_fifo, lan9118_state, 512),
319 VMSTATE_INT32(rx_status_fifo_size, lan9118_state),
320 VMSTATE_INT32(rx_status_fifo_used, lan9118_state),
321 VMSTATE_INT32(rx_status_fifo_head, lan9118_state),
322 VMSTATE_UINT32_ARRAY(rx_status_fifo, lan9118_state, 896),
323 VMSTATE_INT32(rx_fifo_size, lan9118_state),
324 VMSTATE_INT32(rx_fifo_used, lan9118_state),
325 VMSTATE_INT32(rx_fifo_head, lan9118_state),
326 VMSTATE_UINT32_ARRAY(rx_fifo, lan9118_state, 3360),
327 VMSTATE_INT32(rx_packet_size_head, lan9118_state),
328 VMSTATE_INT32(rx_packet_size_tail, lan9118_state),
329 VMSTATE_INT32_ARRAY(rx_packet_size, lan9118_state, 1024),
330 VMSTATE_INT32(rxp_offset, lan9118_state),
331 VMSTATE_INT32(rxp_size, lan9118_state),
332 VMSTATE_INT32(rxp_pad, lan9118_state),
1248f8d4
EV		 333 VMSTATE_UINT32_V(write_word_prev_offset, lan9118_state, 2),
334 VMSTATE_UINT32_V(write_word_n, lan9118_state, 2),
335 VMSTATE_UINT16_V(write_word_l, lan9118_state, 2),
336 VMSTATE_UINT16_V(write_word_h, lan9118_state, 2),
337 VMSTATE_UINT32_V(read_word_prev_offset, lan9118_state, 2),
338 VMSTATE_UINT32_V(read_word_n, lan9118_state, 2),
339 VMSTATE_UINT32_V(read_long, lan9118_state, 2),
340 VMSTATE_UINT32_V(mode_16bit, lan9118_state, 2),
b09da0c3
PM		 341 VMSTATE_END_OF_LIST()
342 }
343};
344
2a424990
PB		 345static void lan9118_update(lan9118_state *s)
346{
347 int level;
348
349 /* TODO: Implement FIFO level IRQs. */
350 level = (s->int_sts & s->int_en) != 0;
209bf965
PB		 351 if (level) {
352 s->irq_cfg |= IRQ_INT;
353 } else {
354 s->irq_cfg &= ~IRQ_INT;
355 }
2a424990
PB		 356 if ((s->irq_cfg & IRQ_EN) == 0) {
357 level = 0;
358 }
eb47d7c5
PM		 359 if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) {
360 /* Interrupt is active low unless we're configured as
361 * active-high polarity, push-pull type.
362 */
363 level = !level;
364 }
2a424990
PB		 365 qemu_set_irq(s->irq, level);
366}
367
368static void lan9118_mac_changed(lan9118_state *s)
369{
b356f76d 370 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
2a424990
PB		 371}
372
373static void lan9118_reload_eeprom(lan9118_state *s)
374{
375 int i;
376 if (s->eeprom[0] != 0xa5) {
12fdd928 377 s->e2p_cmd &= ~E2P_CMD_MAC_ADDR_LOADED;
2a424990
PB		 378 DPRINTF("MACADDR load failed\n");
379 return;
380 }
381 for (i = 0; i < 6; i++) {
382 s->conf.macaddr.a[i] = s->eeprom[i + 1];
383 }
12fdd928 384 s->e2p_cmd |= E2P_CMD_MAC_ADDR_LOADED;
2a424990
PB		 385 DPRINTF("MACADDR loaded from eeprom\n");
386 lan9118_mac_changed(s);
387}
388
209bf965
PB		 389static void phy_update_irq(lan9118_state *s)
390{
391 if (s->phy_int & s->phy_int_mask) {
392 s->int_sts |= PHY_INT;
393 } else {
394 s->int_sts &= ~PHY_INT;
395 }
396 lan9118_update(s);
397}
398
2a424990
PB		 399static void phy_update_link(lan9118_state *s)
400{
401 /* Autonegotiation status mirrors link status. */
b356f76d 402 if (qemu_get_queue(s->nic)->link_down) {
2a424990 403 s->phy_status &= ~0x0024;
209bf965 404 s->phy_int |= PHY_INT_DOWN;
2a424990
PB		 405 } else {
406 s->phy_status |= 0x0024;
209bf965
PB		 407 s->phy_int |= PHY_INT_ENERGYON;
408 s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
2a424990 409 }
209bf965 410 phy_update_irq(s);
2a424990
PB		 411}
412
4e68f7a0 413static void lan9118_set_link(NetClientState *nc)
2a424990 414{
cc1f0f45 415 phy_update_link(qemu_get_nic_opaque(nc));
2a424990
PB		 416}
417
418static void phy_reset(lan9118_state *s)
419{
209bf965 420 s->phy_status = 0x7809;
2a424990
PB		 421 s->phy_control = 0x3000;
422 s->phy_advertise = 0x01e1;
209bf965
PB		 423 s->phy_int_mask = 0;
424 s->phy_int = 0;
2a424990
PB		 425 phy_update_link(s);
426}
427
428static void lan9118_reset(DeviceState *d)
429{
3ff66d10
AF		 430 lan9118_state *s = LAN9118(d);
431
eb47d7c5 432 s->irq_cfg &= (IRQ_TYPE | IRQ_POL);
2a424990
PB		 433 s->int_sts = 0;
434 s->int_en = 0;
435 s->fifo_int = 0x48000000;
436 s->rx_cfg = 0;
437 s->tx_cfg = 0;
1248f8d4 438 s->hw_cfg = s->mode_16bit ? 0x00050000 : 0x00050004;
2a424990
PB		 439 s->pmt_ctrl &= 0x45;
440 s->gpio_cfg = 0;
441 s->txp->fifo_used = 0;
442 s->txp->state = TX_IDLE;
443 s->txp->cmd_a = 0xffffffffu;
444 s->txp->cmd_b = 0xffffffffu;
445 s->txp->len = 0;
446 s->txp->fifo_used = 0;
447 s->tx_fifo_size = 4608;
448 s->tx_status_fifo_used = 0;
449 s->rx_status_fifo_size = 704;
450 s->rx_fifo_size = 2640;
451 s->rx_fifo_used = 0;
452 s->rx_status_fifo_size = 176;
453 s->rx_status_fifo_used = 0;
454 s->rxp_offset = 0;
455 s->rxp_size = 0;
456 s->rxp_pad = 0;
457 s->rx_packet_size_tail = s->rx_packet_size_head;
458 s->rx_packet_size[s->rx_packet_size_head] = 0;
459 s->mac_cmd = 0;
460 s->mac_data = 0;
461 s->afc_cfg = 0;
462 s->e2p_cmd = 0;
463 s->e2p_data = 0;
bc72ad67 464 s->free_timer_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40;
2a424990 465
88e4bd67 466 ptimer_transaction_begin(s->timer);
209bf965
PB		 467 ptimer_stop(s->timer);
468 ptimer_set_count(s->timer, 0xffff);
88e4bd67 469 ptimer_transaction_commit(s->timer);
209bf965
PB		 470 s->gpt_cfg = 0xffff;
471
2a424990
PB		 472 s->mac_cr = MAC_CR_PRMS;
473 s->mac_hashh = 0;
474 s->mac_hashl = 0;
475 s->mac_mii_acc = 0;
476 s->mac_mii_data = 0;
477 s->mac_flow = 0;
478
1248f8d4
EV		 479 s->read_word_n = 0;
480 s->write_word_n = 0;
481
2a424990
PB		 482 phy_reset(s);
483
484 s->eeprom_writable = 0;
485 lan9118_reload_eeprom(s);
486}
487
2a424990
PB		 488static void rx_fifo_push(lan9118_state *s, uint32_t val)
489{
490 int fifo_pos;
491 fifo_pos = s->rx_fifo_head + s->rx_fifo_used;
492 if (fifo_pos >= s->rx_fifo_size)
493 fifo_pos -= s->rx_fifo_size;
494 s->rx_fifo[fifo_pos] = val;
495 s->rx_fifo_used++;
496}
497
498/* Return nonzero if the packet is accepted by the filter. */
499static int lan9118_filter(lan9118_state *s, const uint8_t *addr)
500{
501 int multicast;
502 uint32_t hash;
503
504 if (s->mac_cr & MAC_CR_PRMS) {
505 return 1;
506 }
507 if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff &&
508 addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) {
509 return (s->mac_cr & MAC_CR_BCAST) == 0;
510 }
511
512 multicast = addr[0] & 1;
513 if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
514 return 1;
515 }
516 if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0
517 : (s->mac_cr & MAC_CR_HO) == 0) {
518 /* Exact matching. */
519 hash = memcmp(addr, s->conf.macaddr.a, 6);
520 if (s->mac_cr & MAC_CR_INVFILT) {
521 return hash != 0;
522 } else {
523 return hash == 0;
524 }
525 } else {
526 /* Hash matching */
eedeaee7 527 hash = net_crc32(addr, ETH_ALEN) >> 26;
2a424990
PB		 528 if (hash & 0x20) {
529 return (s->mac_hashh >> (hash & 0x1f)) & 1;
530 } else {
531 return (s->mac_hashl >> (hash & 0x1f)) & 1;
532 }
533 }
534}
535
4e68f7a0 536static ssize_t lan9118_receive(NetClientState *nc, const uint8_t *buf,
2a424990
PB		 537 size_t size)
538{
cc1f0f45 539 lan9118_state *s = qemu_get_nic_opaque(nc);
2a424990
PB		 540 int fifo_len;
541 int offset;
542 int src_pos;
543 int n;
544 int filter;
545 uint32_t val;
546 uint32_t crc;
547 uint32_t status;
548
549 if ((s->mac_cr & MAC_CR_RXEN) == 0) {
550 return -1;
551 }
552
a4522346 553 if (size >= MIL_TXFIFO_SIZE || size < 14) {
2a424990
PB		 554 return -1;
555 }
556
557 /* TODO: Implement FIFO overflow notification. */
558 if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
559 return -1;
560 }
561
562 filter = lan9118_filter(s, buf);
563 if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) {
564 return size;
565 }
566
567 offset = (s->rx_cfg >> 8) & 0x1f;
568 n = offset & 3;
569 fifo_len = (size + n + 3) >> 2;
570 /* Add a word for the CRC. */
571 fifo_len++;
572 if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
573 return -1;
574 }
575
576 DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
577 (int)size, fifo_len, filter ? "pass" : "fail");
578 val = 0;
579 crc = bswap32(crc32(~0, buf, size));
580 for (src_pos = 0; src_pos < size; src_pos++) {
581 val = (val >> 8) | ((uint32_t)buf[src_pos] << 24);
582 n++;
583 if (n == 4) {
584 n = 0;
585 rx_fifo_push(s, val);
586 val = 0;
587 }
588 }
589 if (n) {
590 val >>= ((4 - n) * 8);
591 val |= crc << (n * 8);
592 rx_fifo_push(s, val);
593 val = crc >> ((4 - n) * 8);
594 rx_fifo_push(s, val);
595 } else {
596 rx_fifo_push(s, crc);
597 }
598 n = s->rx_status_fifo_head + s->rx_status_fifo_used;
599 if (n >= s->rx_status_fifo_size) {
600 n -= s->rx_status_fifo_size;
601 }
602 s->rx_packet_size[s->rx_packet_size_tail] = fifo_len;
603 s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023;
604 s->rx_status_fifo_used++;
605
606 status = (size + 4) << 16;
607 if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff &&
608 buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) {
609 status |= 0x00002000;
610 } else if (buf[0] & 1) {
611 status |= 0x00000400;
612 }
613 if (!filter) {
614 status |= 0x40000000;
615 }
616 s->rx_status_fifo[n] = status;
617
618 if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) {
619 s->int_sts |= RSFL_INT;
620 }
621 lan9118_update(s);
622
623 return size;
624}
625
626static uint32_t rx_fifo_pop(lan9118_state *s)
627{
628 int n;
629 uint32_t val;
630
631 if (s->rxp_size == 0 && s->rxp_pad == 0) {
632 s->rxp_size = s->rx_packet_size[s->rx_packet_size_head];
633 s->rx_packet_size[s->rx_packet_size_head] = 0;
634 if (s->rxp_size != 0) {
635 s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023;
636 s->rxp_offset = (s->rx_cfg >> 10) & 7;
637 n = s->rxp_offset + s->rxp_size;
638 switch (s->rx_cfg >> 30) {
639 case 1:
640 n = (-n) & 3;
641 break;
642 case 2:
643 n = (-n) & 7;
644 break;
645 default:
646 n = 0;
647 break;
648 }
649 s->rxp_pad = n;
650 DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
651 s->rxp_size, s->rxp_offset, s->rxp_pad);
652 }
653 }
654 if (s->rxp_offset > 0) {
655 s->rxp_offset--;
656 val = 0;
657 } else if (s->rxp_size > 0) {
658 s->rxp_size--;
659 val = s->rx_fifo[s->rx_fifo_head++];
660 if (s->rx_fifo_head >= s->rx_fifo_size) {
661 s->rx_fifo_head -= s->rx_fifo_size;
662 }
663 s->rx_fifo_used--;
664 } else if (s->rxp_pad > 0) {
665 s->rxp_pad--;
666 val = 0;
667 } else {
668 DPRINTF("RX underflow\n");
669 s->int_sts |= RXE_INT;
670 val = 0;
671 }
672 lan9118_update(s);
673 return val;
674}
675
676static void do_tx_packet(lan9118_state *s)
677{
678 int n;
679 uint32_t status;
680
681 /* FIXME: Honor TX disable, and allow queueing of packets. */
682 if (s->phy_control & 0x4000) {
683 /* This assumes the receive routine doesn't touch the VLANClient. */
37cee017 684 qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
2a424990 685 } else {
b356f76d 686 qemu_send_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
2a424990
PB		 687 }
688 s->txp->fifo_used = 0;
689
690 if (s->tx_status_fifo_used == 512) {
691 /* Status FIFO full */
692 return;
693 }
694 /* Add entry to status FIFO. */
695 status = s->txp->cmd_b & 0xffff0000u;
696 DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len);
697 n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
698 s->tx_status_fifo[n] = status;
699 s->tx_status_fifo_used++;
895a803c
LD		 700
701 /*
702 * Generate TSFL interrupt if TX FIFO level exceeds the level
703 * specified in the FIFO_INT TX Status Level field.
704 */
705 if (s->tx_status_fifo_used > ((s->fifo_int >> 16) & 0xff)) {
706 s->int_sts |= TSFL_INT;
707 }
2a424990
PB		 708 if (s->tx_status_fifo_used == 512) {
709 s->int_sts |= TSFF_INT;
710 /* TODO: Stop transmission. */
711 }
712}
713
714static uint32_t rx_status_fifo_pop(lan9118_state *s)
715{
716 uint32_t val;
717
718 val = s->rx_status_fifo[s->rx_status_fifo_head];
719 if (s->rx_status_fifo_used != 0) {
720 s->rx_status_fifo_used--;
721 s->rx_status_fifo_head++;
722 if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
723 s->rx_status_fifo_head -= s->rx_status_fifo_size;
724 }
725 /* ??? What value should be returned when the FIFO is empty? */
726 DPRINTF("RX status pop 0x%08x\n", val);
727 }
728 return val;
729}
730
731static uint32_t tx_status_fifo_pop(lan9118_state *s)
732{
733 uint32_t val;
734
735 val = s->tx_status_fifo[s->tx_status_fifo_head];
736 if (s->tx_status_fifo_used != 0) {
737 s->tx_status_fifo_used--;
738 s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511;
739 /* ??? What value should be returned when the FIFO is empty? */
740 }
741 return val;
742}
743
744static void tx_fifo_push(lan9118_state *s, uint32_t val)
745{
746 int n;
747
748 if (s->txp->fifo_used == s->tx_fifo_size) {
749 s->int_sts |= TDFO_INT;
750 return;
751 }
752 switch (s->txp->state) {
753 case TX_IDLE:
754 s->txp->cmd_a = val & 0x831f37ff;
755 s->txp->fifo_used++;
756 s->txp->state = TX_B;
2ad657e3
RF		 757 s->txp->buffer_size = extract32(s->txp->cmd_a, 0, 11);
758 s->txp->offset = extract32(s->txp->cmd_a, 16, 5);
2a424990
PB		 759 break;
760 case TX_B:
761 if (s->txp->cmd_a & 0x2000) {
762 /* First segment */
763 s->txp->cmd_b = val;
764 s->txp->fifo_used++;
2a424990
PB		 765 /* End alignment does not include command words. */
766 n = (s->txp->buffer_size + s->txp->offset + 3) >> 2;
767 switch ((n >> 24) & 3) {
768 case 1:
769 n = (-n) & 3;
770 break;
771 case 2:
772 n = (-n) & 7;
773 break;
774 default:
775 n = 0;
776 }
777 s->txp->pad = n;
778 s->txp->len = 0;
779 }
780 DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
781 s->txp->buffer_size, s->txp->offset, s->txp->pad,
782 s->txp->cmd_a);
783 s->txp->state = TX_DATA;
784 break;
785 case TX_DATA:
786 if (s->txp->offset >= 4) {
787 s->txp->offset -= 4;
788 break;
789 }
790 if (s->txp->buffer_size <= 0 && s->txp->pad != 0) {
791 s->txp->pad--;
792 } else {
c444dfab 793 n = MIN(4, s->txp->buffer_size + s->txp->offset);
2a424990
PB		 794 while (s->txp->offset) {
795 val >>= 8;
796 n--;
797 s->txp->offset--;
798 }
799 /* Documentation is somewhat unclear on the ordering of bytes
800 in FIFO words. Empirical results show it to be little-endian.
801 */
802 /* TODO: FIFO overflow checking. */
803 while (n--) {
804 s->txp->data[s->txp->len] = val & 0xff;
805 s->txp->len++;
806 val >>= 8;
807 s->txp->buffer_size--;
808 }
809 s->txp->fifo_used++;
810 }
811 if (s->txp->buffer_size <= 0 && s->txp->pad == 0) {
812 if (s->txp->cmd_a & 0x1000) {
813 do_tx_packet(s);
814 }
815 if (s->txp->cmd_a & 0x80000000) {
816 s->int_sts |= TX_IOC_INT;
817 }
818 s->txp->state = TX_IDLE;
819 }
820 break;
821 }
822}
823
824static uint32_t do_phy_read(lan9118_state *s, int reg)
825{
209bf965
PB		 826 uint32_t val;
827
2a424990
PB		 828 switch (reg) {
829 case 0: /* Basic Control */
830 return s->phy_control;
831 case 1: /* Basic Status */
832 return s->phy_status;
833 case 2: /* ID1 */
834 return 0x0007;
835 case 3: /* ID2 */
836 return 0xc0d1;
66a0a2cb 837 case 4: /* Auto-neg advertisement */
2a424990
PB		 838 return s->phy_advertise;
839 case 5: /* Auto-neg Link Partner Ability */
840 return 0x0f71;
841 case 6: /* Auto-neg Expansion */
842 return 1;
843 /* TODO 17, 18, 27, 29, 30, 31 */
209bf965
PB		 844 case 29: /* Interrupt source. */
845 val = s->phy_int;
846 s->phy_int = 0;
847 phy_update_irq(s);
848 return val;
849 case 30: /* Interrupt mask */
850 return s->phy_int_mask;
2a424990 851 default:
44c94cdb
QL		 852 qemu_log_mask(LOG_GUEST_ERROR,
853 "do_phy_read: PHY read reg %d\n", reg);
2a424990
PB		 854 return 0;
855 }
856}
857
858static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
859{
860 switch (reg) {
861 case 0: /* Basic Control */
862 if (val & 0x8000) {
863 phy_reset(s);
864 break;
865 }
866 s->phy_control = val & 0x7980;
4b71051e 867 /* Complete autonegotiation immediately. */
2a424990
PB		 868 if (val & 0x1000) {
869 s->phy_status |= 0x0020;
870 }
871 break;
66a0a2cb 872 case 4: /* Auto-neg advertisement */
2a424990
PB		 873 s->phy_advertise = (val & 0x2d7f) | 0x80;
874 break;
209bf965
PB		 875 /* TODO 17, 18, 27, 31 */
876 case 30: /* Interrupt mask */
877 s->phy_int_mask = val & 0xff;
878 phy_update_irq(s);
879 break;
2a424990 880 default:
44c94cdb
QL		 881 qemu_log_mask(LOG_GUEST_ERROR,
882 "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
2a424990
PB		 883 }
884}
885
886static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
887{
888 switch (reg) {
889 case MAC_CR:
890 if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) {
891 s->int_sts |= RXSTOP_INT;
892 }
893 s->mac_cr = val & ~MAC_CR_RESERVED;
894 DPRINTF("MAC_CR: %08x\n", val);
895 break;
896 case MAC_ADDRH:
897 s->conf.macaddr.a[4] = val & 0xff;
898 s->conf.macaddr.a[5] = (val >> 8) & 0xff;
899 lan9118_mac_changed(s);
900 break;
901 case MAC_ADDRL:
902 s->conf.macaddr.a[0] = val & 0xff;
903 s->conf.macaddr.a[1] = (val >> 8) & 0xff;
904 s->conf.macaddr.a[2] = (val >> 16) & 0xff;
905 s->conf.macaddr.a[3] = (val >> 24) & 0xff;
906 lan9118_mac_changed(s);
907 break;
908 case MAC_HASHH:
909 s->mac_hashh = val;
910 break;
911 case MAC_HASHL:
912 s->mac_hashl = val;
913 break;
914 case MAC_MII_ACC:
915 s->mac_mii_acc = val & 0xffc2;
916 if (val & 2) {
917 DPRINTF("PHY write %d = 0x%04x\n",
918 (val >> 6) & 0x1f, s->mac_mii_data);
919 do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
920 } else {
921 s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
922 DPRINTF("PHY read %d = 0x%04x\n",
923 (val >> 6) & 0x1f, s->mac_mii_data);
924 }
925 break;
926 case MAC_MII_DATA:
927 s->mac_mii_data = val & 0xffff;
928 break;
929 case MAC_FLOW:
930 s->mac_flow = val & 0xffff0000;
931 break;
a0313c00
AN		 932 case MAC_VLAN1:
933 /* Writing to this register changes a condition for
934 * FrameTooLong bit in rx_status. Since we do not set
935 * FrameTooLong anyway, just ignore write to this.
936 */
937 break;
2a424990 938 default:
52b4bb73
AB		 939 qemu_log_mask(LOG_GUEST_ERROR,
940 "lan9118: Unimplemented MAC register write: %d = 0x%x\n",
2a424990
PB		 941 s->mac_cmd & 0xf, val);
942 }
943}
944
945static uint32_t do_mac_read(lan9118_state *s, int reg)
946{
947 switch (reg) {
948 case MAC_CR:
949 return s->mac_cr;
950 case MAC_ADDRH:
951 return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
952 case MAC_ADDRL:
953 return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
954 | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
955 case MAC_HASHH:
956 return s->mac_hashh;
2a424990
PB		 957 case MAC_HASHL:
958 return s->mac_hashl;
2a424990
PB		 959 case MAC_MII_ACC:
960 return s->mac_mii_acc;
961 case MAC_MII_DATA:
962 return s->mac_mii_data;
963 case MAC_FLOW:
964 return s->mac_flow;
965 default:
52b4bb73
AB		 966 qemu_log_mask(LOG_GUEST_ERROR,
967 "lan9118: Unimplemented MAC register read: %d\n",
2a424990 968 s->mac_cmd & 0xf);
52b4bb73 969 return 0;
2a424990
PB		 970 }
971}
972
973static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr)
974{
12fdd928 975 s->e2p_cmd = (s->e2p_cmd & E2P_CMD_MAC_ADDR_LOADED) | (cmd << 28) | addr;
2a424990
PB		 976 switch (cmd) {
977 case 0:
978 s->e2p_data = s->eeprom[addr];
979 DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
980 break;
981 case 1:
982 s->eeprom_writable = 0;
983 DPRINTF("EEPROM Write Disable\n");
984 break;
985 case 2: /* EWEN */
986 s->eeprom_writable = 1;
987 DPRINTF("EEPROM Write Enable\n");
988 break;
989 case 3: /* WRITE */
990 if (s->eeprom_writable) {
991 s->eeprom[addr] &= s->e2p_data;
992 DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
993 } else {
994 DPRINTF("EEPROM Write %d (ignored)\n", addr);
995 }
996 break;
997 case 4: /* WRAL */
998 if (s->eeprom_writable) {
999 for (addr = 0; addr < 128; addr++) {
1000 s->eeprom[addr] &= s->e2p_data;
1001 }
1002 DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
1003 } else {
1004 DPRINTF("EEPROM Write All (ignored)\n");
1005 }
0e3b800e 1006 break;
2a424990
PB		 1007 case 5: /* ERASE */
1008 if (s->eeprom_writable) {
1009 s->eeprom[addr] = 0xff;
1010 DPRINTF("EEPROM Erase %d\n", addr);
1011 } else {
1012 DPRINTF("EEPROM Erase %d (ignored)\n", addr);
1013 }
1014 break;
1015 case 6: /* ERAL */
1016 if (s->eeprom_writable) {
1017 memset(s->eeprom, 0xff, 128);
1018 DPRINTF("EEPROM Erase All\n");
1019 } else {
1020 DPRINTF("EEPROM Erase All (ignored)\n");
1021 }
1022 break;
1023 case 7: /* RELOAD */
1024 lan9118_reload_eeprom(s);
1025 break;
1026 }
1027}
1028
209bf965
PB		 1029static void lan9118_tick(void *opaque)
1030{
1031 lan9118_state *s = (lan9118_state *)opaque;
1032 if (s->int_en & GPT_INT) {
1033 s->int_sts |= GPT_INT;
1034 }
1035 lan9118_update(s);
1036}
1037
a8170e5e 1038static void lan9118_writel(void *opaque, hwaddr offset,
f0cdd7a9 1039 uint64_t val, unsigned size)
2a424990
PB		 1040{
1041 lan9118_state *s = (lan9118_state *)opaque;
1042 offset &= 0xff;
1248f8d4 1043
2a424990 1044 //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
5cab6d5a
PM		 1045 if (offset >= TX_DATA_FIFO_PORT_FIRST &&
1046 offset <= TX_DATA_FIFO_PORT_LAST) {
2a424990
PB		 1047 /* TX FIFO */
1048 tx_fifo_push(s, val);
1049 return;
1050 }
1051 switch (offset) {
1052 case CSR_IRQ_CFG:
1053 /* TODO: Implement interrupt deassertion intervals. */
eb47d7c5
PM		 1054 val &= (IRQ_EN | IRQ_POL | IRQ_TYPE);
1055 s->irq_cfg = (s->irq_cfg & IRQ_INT) | val;
2a424990
PB		 1056 break;
1057 case CSR_INT_STS:
1058 s->int_sts &= ~val;
1059 break;
1060 case CSR_INT_EN:
1061 s->int_en = val & ~RESERVED_INT;
1062 s->int_sts |= val & SW_INT;
1063 break;
1064 case CSR_FIFO_INT:
1065 DPRINTF("FIFO INT levels %08x\n", val);
1066 s->fifo_int = val;
1067 break;
1068 case CSR_RX_CFG:
1069 if (val & 0x8000) {
1070 /* RX_DUMP */
1071 s->rx_fifo_used = 0;
1072 s->rx_status_fifo_used = 0;
1073 s->rx_packet_size_tail = s->rx_packet_size_head;
1074 s->rx_packet_size[s->rx_packet_size_head] = 0;
1075 }
1076 s->rx_cfg = val & 0xcfff1ff0;
1077 break;
1078 case CSR_TX_CFG:
1079 if (val & 0x8000) {
1080 s->tx_status_fifo_used = 0;
1081 }
1082 if (val & 0x4000) {
1083 s->txp->state = TX_IDLE;
1084 s->txp->fifo_used = 0;
1085 s->txp->cmd_a = 0xffffffff;
1086 }
1087 s->tx_cfg = val & 6;
1088 break;
1089 case CSR_HW_CFG:
1090 if (val & 1) {
1091 /* SRST */
3ff66d10 1092 lan9118_reset(DEVICE(s));
2a424990 1093 } else {
1248f8d4 1094 s->hw_cfg = (val & 0x003f300) | (s->hw_cfg & 0x4);
2a424990
PB		 1095 }
1096 break;
1097 case CSR_RX_DP_CTRL:
1098 if (val & 0x80000000) {
1099 /* Skip forward to next packet. */
1100 s->rxp_pad = 0;
1101 s->rxp_offset = 0;
1102 if (s->rxp_size == 0) {
1103 /* Pop a word to start the next packet. */
1104 rx_fifo_pop(s);
1105 s->rxp_pad = 0;
1106 s->rxp_offset = 0;
1107 }
1108 s->rx_fifo_head += s->rxp_size;
1109 if (s->rx_fifo_head >= s->rx_fifo_size) {
1110 s->rx_fifo_head -= s->rx_fifo_size;
1111 }
1112 }
1113 break;
1114 case CSR_PMT_CTRL:
1115 if (val & 0x400) {
1116 phy_reset(s);
1117 }
1118 s->pmt_ctrl &= ~0x34e;
1119 s->pmt_ctrl |= (val & 0x34e);
1120 break;
1121 case CSR_GPIO_CFG:
1122 /* Probably just enabling LEDs. */
1123 s->gpio_cfg = val & 0x7777071f;
1124 break;
209bf965
PB		 1125 case CSR_GPT_CFG:
1126 if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) {
88e4bd67 1127 ptimer_transaction_begin(s->timer);
209bf965
PB		 1128 if (val & GPT_TIMER_EN) {
1129 ptimer_set_count(s->timer, val & 0xffff);
1130 ptimer_run(s->timer, 0);
1131 } else {
1132 ptimer_stop(s->timer);
1133 ptimer_set_count(s->timer, 0xffff);
1134 }
88e4bd67 1135 ptimer_transaction_commit(s->timer);
209bf965
PB		 1136 }
1137 s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff);
1138 break;
2a424990
PB		 1139 case CSR_WORD_SWAP:
1140 /* Ignored because we're in 32-bit mode. */
1141 s->word_swap = val;
1142 break;
1143 case CSR_MAC_CSR_CMD:
1144 s->mac_cmd = val & 0x4000000f;
1145 if (val & 0x80000000) {
1146 if (val & 0x40000000) {
1147 s->mac_data = do_mac_read(s, val & 0xf);
1148 DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data);
1149 } else {
1150 DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data);
1151 do_mac_write(s, val & 0xf, s->mac_data);
1152 }
1153 }
1154 break;
1155 case CSR_MAC_CSR_DATA:
1156 s->mac_data = val;
1157 break;
1158 case CSR_AFC_CFG:
1159 s->afc_cfg = val & 0x00ffffff;
1160 break;
1161 case CSR_E2P_CMD:
c46a3ea0 1162 lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0x7f);
2a424990
PB		 1163 break;
1164 case CSR_E2P_DATA:
1165 s->e2p_data = val & 0xff;
1166 break;
1167
1168 default:
52b4bb73
AB		 1169 qemu_log_mask(LOG_GUEST_ERROR, "lan9118_write: Bad reg 0x%x = %x\n",
1170 (int)offset, (int)val);
2a424990
PB		 1171 break;
1172 }
1173 lan9118_update(s);
1174}
1175
a8170e5e 1176static void lan9118_writew(void *opaque, hwaddr offset,
1248f8d4
EV		 1177 uint32_t val)
1178{
1179 lan9118_state *s = (lan9118_state *)opaque;
1180 offset &= 0xff;
1181
1182 if (s->write_word_prev_offset != (offset & ~0x3)) {
1183 /* New offset, reset word counter */
1184 s->write_word_n = 0;
1185 s->write_word_prev_offset = offset & ~0x3;
1186 }
1187
1188 if (offset & 0x2) {
1189 s->write_word_h = val;
1190 } else {
1191 s->write_word_l = val;
1192 }
1193
1194 //DPRINTF("Writew reg 0x%02x = 0x%08x\n", (int)offset, val);
1195 s->write_word_n++;
1196 if (s->write_word_n == 2) {
1197 s->write_word_n = 0;
1198 lan9118_writel(s, offset & ~3, s->write_word_l +
1199 (s->write_word_h << 16), 4);
1200 }
1201}
1202
a8170e5e 1203static void lan9118_16bit_mode_write(void *opaque, hwaddr offset,
1248f8d4
EV		 1204 uint64_t val, unsigned size)
1205{
1206 switch (size) {
1207 case 2:
0ed8b6f6
BS		 1208 lan9118_writew(opaque, offset, (uint32_t)val);
1209 return;
1248f8d4 1210 case 4:
0ed8b6f6
BS		 1211 lan9118_writel(opaque, offset, val, size);
1212 return;
1248f8d4
EV		 1213 }
1214
44c94cdb
QL		 1215 qemu_log_mask(LOG_GUEST_ERROR,
1216 "lan9118_16bit_mode_write: Bad size 0x%x\n", size);
1248f8d4
EV		 1217}
1218
a8170e5e 1219static uint64_t lan9118_readl(void *opaque, hwaddr offset,
f0cdd7a9 1220 unsigned size)
2a424990
PB		 1221{
1222 lan9118_state *s = (lan9118_state *)opaque;
1223
1224 //DPRINTF("Read reg 0x%02x\n", (int)offset);
5cab6d5a 1225 if (offset <= RX_DATA_FIFO_PORT_LAST) {
2a424990
PB		 1226 /* RX FIFO */
1227 return rx_fifo_pop(s);
1228 }
1229 switch (offset) {
5cab6d5a 1230 case RX_STATUS_FIFO_PORT:
2a424990 1231 return rx_status_fifo_pop(s);
5cab6d5a 1232 case RX_STATUS_FIFO_PEEK:
e7e29fdb 1233 return s->rx_status_fifo[s->rx_status_fifo_head];
5cab6d5a 1234 case TX_STATUS_FIFO_PORT:
2a424990 1235 return tx_status_fifo_pop(s);
5cab6d5a 1236 case TX_STATUS_FIFO_PEEK:
2a424990
PB		 1237 return s->tx_status_fifo[s->tx_status_fifo_head];
1238 case CSR_ID_REV:
1239 return 0x01180001;
1240 case CSR_IRQ_CFG:
1241 return s->irq_cfg;
1242 case CSR_INT_STS:
1243 return s->int_sts;
1244 case CSR_INT_EN:
1245 return s->int_en;
1246 case CSR_BYTE_TEST:
1247 return 0x87654321;
1248 case CSR_FIFO_INT:
1249 return s->fifo_int;
1250 case CSR_RX_CFG:
1251 return s->rx_cfg;
1252 case CSR_TX_CFG:
1253 return s->tx_cfg;
1254 case CSR_HW_CFG:
1248f8d4 1255 return s->hw_cfg;
2a424990
PB		 1256 case CSR_RX_DP_CTRL:
1257 return 0;
1258 case CSR_RX_FIFO_INF:
1259 return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2);
1260 case CSR_TX_FIFO_INF:
1261 return (s->tx_status_fifo_used << 16)
1262 | (s->tx_fifo_size - s->txp->fifo_used);
1263 case CSR_PMT_CTRL:
1264 return s->pmt_ctrl;
1265 case CSR_GPIO_CFG:
1266 return s->gpio_cfg;
209bf965
PB		 1267 case CSR_GPT_CFG:
1268 return s->gpt_cfg;
1269 case CSR_GPT_CNT:
1270 return ptimer_get_count(s->timer);
2a424990
PB		 1271 case CSR_WORD_SWAP:
1272 return s->word_swap;
1273 case CSR_FREE_RUN:
bc72ad67 1274 return (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40) - s->free_timer_start;
2a424990
PB		 1275 case CSR_RX_DROP:
1276 /* TODO: Implement dropped frames counter. */
1277 return 0;
1278 case CSR_MAC_CSR_CMD:
1279 return s->mac_cmd;
1280 case CSR_MAC_CSR_DATA:
1281 return s->mac_data;
1282 case CSR_AFC_CFG:
1283 return s->afc_cfg;
1284 case CSR_E2P_CMD:
1285 return s->e2p_cmd;
1286 case CSR_E2P_DATA:
1287 return s->e2p_data;
1288 }
52b4bb73 1289 qemu_log_mask(LOG_GUEST_ERROR, "lan9118_read: Bad reg 0x%x\n", (int)offset);
2a424990
PB		 1290 return 0;
1291}
1292
a8170e5e 1293static uint32_t lan9118_readw(void *opaque, hwaddr offset)
1248f8d4
EV		 1294{
1295 lan9118_state *s = (lan9118_state *)opaque;
1296 uint32_t val;
1297
1298 if (s->read_word_prev_offset != (offset & ~0x3)) {
1299 /* New offset, reset word counter */
1300 s->read_word_n = 0;
1301 s->read_word_prev_offset = offset & ~0x3;
1302 }
1303
1304 s->read_word_n++;
1305 if (s->read_word_n == 1) {
1306 s->read_long = lan9118_readl(s, offset & ~3, 4);
1307 } else {
1308 s->read_word_n = 0;
1309 }
1310
1311 if (offset & 2) {
1312 val = s->read_long >> 16;
1313 } else {
1314 val = s->read_long & 0xFFFF;
1315 }
1316
1317 //DPRINTF("Readw reg 0x%02x, val 0x%x\n", (int)offset, val);
1318 return val;
1319}
1320
a8170e5e 1321static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset,
1248f8d4
EV		 1322 unsigned size)
1323{
1324 switch (size) {
1325 case 2:
1326 return lan9118_readw(opaque, offset);
1327 case 4:
1328 return lan9118_readl(opaque, offset, size);
1329 }
1330
44c94cdb
QL		 1331 qemu_log_mask(LOG_GUEST_ERROR,
1332 "lan9118_16bit_mode_read: Bad size 0x%x\n", size);
1248f8d4
EV		 1333 return 0;
1334}
1335
f0cdd7a9
PM		 1336static const MemoryRegionOps lan9118_mem_ops = {
1337 .read = lan9118_readl,
1338 .write = lan9118_writel,
1339 .endianness = DEVICE_NATIVE_ENDIAN,
2a424990
PB		 1340};
1341
1248f8d4
EV		 1342static const MemoryRegionOps lan9118_16bit_mem_ops = {
1343 .read = lan9118_16bit_mode_read,
1344 .write = lan9118_16bit_mode_write,
1345 .endianness = DEVICE_NATIVE_ENDIAN,
1346};
1347
83b9f88c 1348static NetClientInfo net_lan9118_info = {
f394b2e2 1349 .type = NET_CLIENT_DRIVER_NIC,
83b9f88c 1350 .size = sizeof(NICState),
83b9f88c 1351 .receive = lan9118_receive,
83b9f88c
MM		 1352 .link_status_changed = lan9118_set_link,
1353};
1354
f71b3367 1355static void lan9118_realize(DeviceState *dev, Error **errp)
2a424990 1356{
f71b3367 1357 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
3ff66d10 1358 lan9118_state *s = LAN9118(dev);
2a424990 1359 int i;
1248f8d4
EV		 1360 const MemoryRegionOps *mem_ops =
1361 s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
2a424990 1362
eedfac6f
PB		 1363 memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
1364 "lan9118-mmio", 0x100);
3ff66d10
AF		 1365 sysbus_init_mmio(sbd, &s->mmio);
1366 sysbus_init_irq(sbd, &s->irq);
2a424990
PB		 1367 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1368
83b9f88c 1369 s->nic = qemu_new_nic(&net_lan9118_info, &s->conf,
7d0fefdf
AO		 1370 object_get_typename(OBJECT(dev)), dev->id,
1371 &dev->mem_reentrancy_guard, s);
b356f76d 1372 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
2a424990
PB		 1373 s->eeprom[0] = 0xa5;
1374 for (i = 0; i < 6; i++) {
1375 s->eeprom[i + 1] = s->conf.macaddr.a[i];
1376 }
1377 s->pmt_ctrl = 1;
1378 s->txp = &s->tx_packet;
1379
9598c1bb 1380 s->timer = ptimer_init(lan9118_tick, s, PTIMER_POLICY_LEGACY);
88e4bd67 1381 ptimer_transaction_begin(s->timer);
209bf965
PB		 1382 ptimer_set_freq(s->timer, 10000);
1383 ptimer_set_limit(s->timer, 0xffff, 1);
88e4bd67 1384 ptimer_transaction_commit(s->timer);
2a424990
PB		 1385}
1386
999e12bb
AL		 1387static Property lan9118_properties[] = {
1388 DEFINE_NIC_PROPERTIES(lan9118_state, conf),
1248f8d4 1389 DEFINE_PROP_UINT32("mode_16bit", lan9118_state, mode_16bit, 0),
999e12bb
AL		 1390 DEFINE_PROP_END_OF_LIST(),
1391};
1392
1393static void lan9118_class_init(ObjectClass *klass, void *data)
1394{
39bffca2 1395 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 1396
39bffca2 1397 dc->reset = lan9118_reset;
4f67d30b 1398 device_class_set_props(dc, lan9118_properties);
39bffca2 1399 dc->vmsd = &vmstate_lan9118;
f71b3367 1400 dc->realize = lan9118_realize;
999e12bb
AL		 1401}
1402
8c43a6f0 1403static const TypeInfo lan9118_info = {
3ff66d10 1404 .name = TYPE_LAN9118,
39bffca2
AL		 1405 .parent = TYPE_SYS_BUS_DEVICE,
1406 .instance_size = sizeof(lan9118_state),
1407 .class_init = lan9118_class_init,
2a424990
PB		 1408};
1409
83f7d43a 1410static void lan9118_register_types(void)
2a424990 1411{
39bffca2 1412 type_register_static(&lan9118_info);
2a424990
PB		 1413}
1414
1415/* Legacy helper function. Should go away when machine config files are
1416 implemented. */
f138ed5e 1417void lan9118_init(uint32_t base, qemu_irq irq)
2a424990
PB		 1418{
1419 DeviceState *dev;
1420 SysBusDevice *s;
1421
3e80f690 1422 dev = qdev_new(TYPE_LAN9118);
f138ed5e 1423 qemu_configure_nic_device(dev, true, NULL);
1356b98d 1424 s = SYS_BUS_DEVICE(dev);
3c6ef471 1425 sysbus_realize_and_unref(s, &error_fatal);
2a424990
PB		 1426 sysbus_mmio_map(s, 0, base);
1427 sysbus_connect_irq(s, 0, irq);
1428}
1429
83f7d43a 1430type_init(lan9118_register_types)
Mirror of https://git.qemu.org/git/qemu.git