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MAINTAINERS: Add some missing ARM related header files
[thirdparty/qemu.git] / hw / sd / sdhci.c
CommitLineData
d7dfca08
IM		 1/*
2 * SD Association Host Standard Specification v2.0 controller emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
7 *
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
0430891c 25#include "qemu/osdep.h"
83c9f4ca 26#include "hw/hw.h"
fa1d36df 27#include "sysemu/block-backend.h"
d7dfca08
IM		 28#include "sysemu/blockdev.h"
29#include "sysemu/dma.h"
30#include "qemu/timer.h"
d7dfca08 31#include "qemu/bitops.h"
637d23be 32#include "sdhci-internal.h"
d7dfca08
IM		 33
34/* host controller debug messages */
35#ifndef SDHC_DEBUG
36#define SDHC_DEBUG 0
37#endif
38
7af0fc99
SPB		 39#define DPRINT_L1(fmt, args...) \
40 do { \
41 if (SDHC_DEBUG) { \
42 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
43 } \
44 } while (0)
45#define DPRINT_L2(fmt, args...) \
46 do { \
47 if (SDHC_DEBUG > 1) { \
48 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
49 } \
50 } while (0)
51#define ERRPRINT(fmt, args...) \
52 do { \
53 if (SDHC_DEBUG) { \
54 fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \
55 } \
56 } while (0)
d7dfca08 57
40bbc194
PM		 58#define TYPE_SDHCI_BUS "sdhci-bus"
59#define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
60
d7dfca08
IM		 61/* Default SD/MMC host controller features information, which will be
62 * presented in CAPABILITIES register of generic SD host controller at reset.
63 * If not stated otherwise:
64 * 0 - not supported, 1 - supported, other - prohibited.
65 */
66#define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */
67#define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */
68#define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */
69#define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */
70#define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */
71#define SDHC_CAPAB_SDMA 1ul /* SDMA support */
72#define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */
73#define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */
74#define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */
75/* Maximum host controller R/W buffers size
76 * Possible values: 512, 1024, 2048 bytes */
77#define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
78/* Maximum clock frequency for SDclock in MHz
79 * value in range 10-63 MHz, 0 - not defined */
c7ff8daa 80#define SDHC_CAPAB_BASECLKFREQ 52ul
d7dfca08
IM		 81#define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */
82/* Timeout clock frequency 1-63, 0 - not defined */
c7ff8daa 83#define SDHC_CAPAB_TOCLKFREQ 52ul
d7dfca08
IM		 84
85/* Now check all parameters and calculate CAPABILITIES REGISTER value */
86#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \
87 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \
88 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\
89 SDHC_CAPAB_TOUNIT > 1
90#error Capabilities features can have value 0 or 1 only!
91#endif
92
93#if SDHC_CAPAB_MAXBLOCKLENGTH == 512
94#define MAX_BLOCK_LENGTH 0ul
95#elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
96#define MAX_BLOCK_LENGTH 1ul
97#elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
98#define MAX_BLOCK_LENGTH 2ul
99#else
100#error Max host controller block size can have value 512, 1024 or 2048 only!
101#endif
102
103#if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
104 SDHC_CAPAB_BASECLKFREQ > 63
105#error SDclock frequency can have value in range 0, 10-63 only!
106#endif
107
108#if SDHC_CAPAB_TOCLKFREQ > 63
109#error Timeout clock frequency can have value in range 0-63 only!
110#endif
111
112#define SDHC_CAPAB_REG_DEFAULT \
113 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \
114 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \
115 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \
116 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \
117 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \
118 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
119 (SDHC_CAPAB_TOCLKFREQ))
120
121#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
122
123static uint8_t sdhci_slotint(SDHCIState *s)
124{
125 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
126 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) ||
127 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV));
128}
129
130static inline void sdhci_update_irq(SDHCIState *s)
131{
132 qemu_set_irq(s->irq, sdhci_slotint(s));
133}
134
135static void sdhci_raise_insertion_irq(void *opaque)
136{
137 SDHCIState *s = (SDHCIState *)opaque;
138
139 if (s->norintsts & SDHC_NIS_REMOVE) {
bc72ad67
AB		 140 timer_mod(s->insert_timer,
141 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 142 } else {
143 s->prnsts = 0x1ff0000;
144 if (s->norintstsen & SDHC_NISEN_INSERT) {
145 s->norintsts |= SDHC_NIS_INSERT;
146 }
147 sdhci_update_irq(s);
148 }
149}
150
40bbc194 151static void sdhci_set_inserted(DeviceState *dev, bool level)
d7dfca08 152{
40bbc194 153 SDHCIState *s = (SDHCIState *)dev;
d7dfca08
IM		 154 DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject");
155
156 if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
157 /* Give target some time to notice card ejection */
bc72ad67
AB		 158 timer_mod(s->insert_timer,
159 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 160 } else {
161 if (level) {
162 s->prnsts = 0x1ff0000;
163 if (s->norintstsen & SDHC_NISEN_INSERT) {
164 s->norintsts |= SDHC_NIS_INSERT;
165 }
166 } else {
167 s->prnsts = 0x1fa0000;
168 s->pwrcon &= ~SDHC_POWER_ON;
169 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN;
170 if (s->norintstsen & SDHC_NISEN_REMOVE) {
171 s->norintsts |= SDHC_NIS_REMOVE;
172 }
173 }
174 sdhci_update_irq(s);
175 }
176}
177
40bbc194 178static void sdhci_set_readonly(DeviceState *dev, bool level)
d7dfca08 179{
40bbc194 180 SDHCIState *s = (SDHCIState *)dev;
d7dfca08
IM		 181
182 if (level) {
183 s->prnsts &= ~SDHC_WRITE_PROTECT;
184 } else {
185 /* Write enabled */
186 s->prnsts |= SDHC_WRITE_PROTECT;
187 }
188}
189
190static void sdhci_reset(SDHCIState *s)
191{
40bbc194
PM		 192 DeviceState *dev = DEVICE(s);
193
bc72ad67
AB		 194 timer_del(s->insert_timer);
195 timer_del(s->transfer_timer);
d7dfca08
IM		 196 /* Set all registers to 0. Capabilities registers are not cleared
197 * and assumed to always preserve their value, given to them during
198 * initialization */
199 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
200
72369755 201 if (!s->noeject_quirk) {
40bbc194
PM		 202 /* Reset other state based on current card insertion/readonly status */
203 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
204 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
72369755 205 }
40bbc194 206
d7dfca08
IM		 207 s->data_count = 0;
208 s->stopped_state = sdhc_not_stopped;
209}
210
d368ba43 211static void sdhci_data_transfer(void *opaque);
d7dfca08
IM		 212
213static void sdhci_send_command(SDHCIState *s)
214{
215 SDRequest request;
216 uint8_t response[16];
217 int rlen;
218
219 s->errintsts = 0;
220 s->acmd12errsts = 0;
221 request.cmd = s->cmdreg >> 8;
222 request.arg = s->argument;
223 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg);
40bbc194 224 rlen = sdbus_do_command(&s->sdbus, &request, response);
d7dfca08
IM		 225
226 if (s->cmdreg & SDHC_CMD_RESPONSE) {
227 if (rlen == 4) {
228 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) |
229 (response[2] << 8) | response[3];
230 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
231 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]);
232 } else if (rlen == 16) {
233 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) |
234 (response[13] << 8) | response[14];
235 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) |
236 (response[9] << 8) | response[10];
237 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) |
238 (response[5] << 8) | response[6];
239 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
240 response[2];
241 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.."
242 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n",
243 s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]);
244 } else {
245 ERRPRINT("Timeout waiting for command response\n");
246 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
247 s->errintsts |= SDHC_EIS_CMDTIMEOUT;
248 s->norintsts |= SDHC_NIS_ERR;
249 }
250 }
251
252 if ((s->norintstsen & SDHC_NISEN_TRSCMP) &&
253 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
254 s->norintsts |= SDHC_NIS_TRSCMP;
255 }
d7dfca08
IM		 256 }
257
258 if (s->norintstsen & SDHC_NISEN_CMDCMP) {
259 s->norintsts |= SDHC_NIS_CMDCMP;
260 }
261
262 sdhci_update_irq(s);
263
264 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
656f416c 265 s->data_count = 0;
d368ba43 266 sdhci_data_transfer(s);
d7dfca08
IM		 267 }
268}
269
270static void sdhci_end_transfer(SDHCIState *s)
271{
272 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
273 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) {
274 SDRequest request;
275 uint8_t response[16];
276
277 request.cmd = 0x0C;
278 request.arg = 0;
279 DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg);
40bbc194 280 sdbus_do_command(&s->sdbus, &request, response);
d7dfca08
IM		 281 /* Auto CMD12 response goes to the upper Response register */
282 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) |
283 (response[2] << 8) | response[3];
284 }
285
286 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE |
287 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT |
288 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE);
289
290 if (s->norintstsen & SDHC_NISEN_TRSCMP) {
291 s->norintsts |= SDHC_NIS_TRSCMP;
292 }
293
294 sdhci_update_irq(s);
295}
296
297/*
298 * Programmed i/o data transfer
299 */
300
301/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
302static void sdhci_read_block_from_card(SDHCIState *s)
303{
304 int index = 0;
305
306 if ((s->trnmod & SDHC_TRNS_MULTI) &&
307 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
308 return;
309 }
310
311 for (index = 0; index < (s->blksize & 0x0fff); index++) {
40bbc194 312 s->fifo_buffer[index] = sdbus_read_data(&s->sdbus);
d7dfca08
IM		 313 }
314
315 /* New data now available for READ through Buffer Port Register */
316 s->prnsts |= SDHC_DATA_AVAILABLE;
317 if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
318 s->norintsts |= SDHC_NIS_RBUFRDY;
319 }
320
321 /* Clear DAT line active status if that was the last block */
322 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
323 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
324 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
325 }
326
327 /* If stop at block gap request was set and it's not the last block of
328 * data - generate Block Event interrupt */
329 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
330 s->blkcnt != 1) {
331 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
332 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
333 s->norintsts |= SDHC_EIS_BLKGAP;
334 }
335 }
336
337 sdhci_update_irq(s);
338}
339
340/* Read @size byte of data from host controller @s BUFFER DATA PORT register */
341static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
342{
343 uint32_t value = 0;
344 int i;
345
346 /* first check that a valid data exists in host controller input buffer */
347 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
348 ERRPRINT("Trying to read from empty buffer\n");
349 return 0;
350 }
351
352 for (i = 0; i < size; i++) {
353 value |= s->fifo_buffer[s->data_count] << i * 8;
354 s->data_count++;
355 /* check if we've read all valid data (blksize bytes) from buffer */
356 if ((s->data_count) >= (s->blksize & 0x0fff)) {
357 DPRINT_L2("All %u bytes of data have been read from input buffer\n",
358 s->data_count);
359 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
360 s->data_count = 0; /* next buff read must start at position [0] */
361
362 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
363 s->blkcnt--;
364 }
365
366 /* if that was the last block of data */
367 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
368 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) ||
369 /* stop at gap request */
370 (s->stopped_state == sdhc_gap_read &&
371 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
d368ba43 372 sdhci_end_transfer(s);
d7dfca08 373 } else { /* if there are more data, read next block from card */
d368ba43 374 sdhci_read_block_from_card(s);
d7dfca08
IM		 375 }
376 break;
377 }
378 }
379
380 return value;
381}
382
383/* Write data from host controller FIFO to card */
384static void sdhci_write_block_to_card(SDHCIState *s)
385{
386 int index = 0;
387
388 if (s->prnsts & SDHC_SPACE_AVAILABLE) {
389 if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
390 s->norintsts |= SDHC_NIS_WBUFRDY;
391 }
392 sdhci_update_irq(s);
393 return;
394 }
395
396 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
397 if (s->blkcnt == 0) {
398 return;
399 } else {
400 s->blkcnt--;
401 }
402 }
403
404 for (index = 0; index < (s->blksize & 0x0fff); index++) {
40bbc194 405 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]);
d7dfca08
IM		 406 }
407
408 /* Next data can be written through BUFFER DATORT register */
409 s->prnsts |= SDHC_SPACE_AVAILABLE;
d7dfca08
IM		 410
411 /* Finish transfer if that was the last block of data */
412 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
413 ((s->trnmod & SDHC_TRNS_MULTI) &&
414 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
d368ba43 415 sdhci_end_transfer(s);
dcdb4cd8
PC		 416 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
417 s->norintsts |= SDHC_NIS_WBUFRDY;
d7dfca08
IM		 418 }
419
420 /* Generate Block Gap Event if requested and if not the last block */
421 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
422 s->blkcnt > 0) {
423 s->prnsts &= ~SDHC_DOING_WRITE;
424 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
425 s->norintsts |= SDHC_EIS_BLKGAP;
426 }
d368ba43 427 sdhci_end_transfer(s);
d7dfca08
IM		 428 }
429
430 sdhci_update_irq(s);
431}
432
433/* Write @size bytes of @value data to host controller @s Buffer Data Port
434 * register */
435static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
436{
437 unsigned i;
438
439 /* Check that there is free space left in a buffer */
440 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
441 ERRPRINT("Can't write to data buffer: buffer full\n");
442 return;
443 }
444
445 for (i = 0; i < size; i++) {
446 s->fifo_buffer[s->data_count] = value & 0xFF;
447 s->data_count++;
448 value >>= 8;
449 if (s->data_count >= (s->blksize & 0x0fff)) {
450 DPRINT_L2("write buffer filled with %u bytes of data\n",
451 s->data_count);
452 s->data_count = 0;
453 s->prnsts &= ~SDHC_SPACE_AVAILABLE;
454 if (s->prnsts & SDHC_DOING_WRITE) {
d368ba43 455 sdhci_write_block_to_card(s);
d7dfca08
IM		 456 }
457 }
458 }
459}
460
461/*
462 * Single DMA data transfer
463 */
464
465/* Multi block SDMA transfer */
466static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
467{
468 bool page_aligned = false;
469 unsigned int n, begin;
470 const uint16_t block_size = s->blksize & 0x0fff;
471 uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12);
472 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
473
474 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
475 * possible stop at page boundary if initial address is not page aligned,
476 * allow them to work properly */
477 if ((s->sdmasysad % boundary_chk) == 0) {
478 page_aligned = true;
479 }
480
481 if (s->trnmod & SDHC_TRNS_READ) {
482 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
483 SDHC_DAT_LINE_ACTIVE;
484 while (s->blkcnt) {
485 if (s->data_count == 0) {
486 for (n = 0; n < block_size; n++) {
40bbc194 487 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
d7dfca08
IM		 488 }
489 }
490 begin = s->data_count;
491 if (((boundary_count + begin) < block_size) && page_aligned) {
492 s->data_count = boundary_count + begin;
493 boundary_count = 0;
494 } else {
495 s->data_count = block_size;
496 boundary_count -= block_size - begin;
497 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
498 s->blkcnt--;
499 }
500 }
df32fd1c 501 dma_memory_write(&address_space_memory, s->sdmasysad,
d7dfca08
IM		 502 &s->fifo_buffer[begin], s->data_count - begin);
503 s->sdmasysad += s->data_count - begin;
504 if (s->data_count == block_size) {
505 s->data_count = 0;
506 }
507 if (page_aligned && boundary_count == 0) {
508 break;
509 }
510 }
511 } else {
512 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT |
513 SDHC_DAT_LINE_ACTIVE;
514 while (s->blkcnt) {
515 begin = s->data_count;
516 if (((boundary_count + begin) < block_size) && page_aligned) {
517 s->data_count = boundary_count + begin;
518 boundary_count = 0;
519 } else {
520 s->data_count = block_size;
521 boundary_count -= block_size - begin;
522 }
df32fd1c 523 dma_memory_read(&address_space_memory, s->sdmasysad,
d7dfca08
IM		 524 &s->fifo_buffer[begin], s->data_count);
525 s->sdmasysad += s->data_count - begin;
526 if (s->data_count == block_size) {
527 for (n = 0; n < block_size; n++) {
40bbc194 528 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
d7dfca08
IM		 529 }
530 s->data_count = 0;
531 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
532 s->blkcnt--;
533 }
534 }
535 if (page_aligned && boundary_count == 0) {
536 break;
537 }
538 }
539 }
540
541 if (s->blkcnt == 0) {
d368ba43 542 sdhci_end_transfer(s);
d7dfca08
IM		 543 } else {
544 if (s->norintstsen & SDHC_NISEN_DMA) {
545 s->norintsts |= SDHC_NIS_DMA;
546 }
547 sdhci_update_irq(s);
548 }
549}
550
551/* single block SDMA transfer */
552
553static void sdhci_sdma_transfer_single_block(SDHCIState *s)
554{
555 int n;
556 uint32_t datacnt = s->blksize & 0x0fff;
557
558 if (s->trnmod & SDHC_TRNS_READ) {
559 for (n = 0; n < datacnt; n++) {
40bbc194 560 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
d7dfca08 561 }
df32fd1c 562 dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer,
d7dfca08
IM		 563 datacnt);
564 } else {
df32fd1c 565 dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer,
d7dfca08
IM		 566 datacnt);
567 for (n = 0; n < datacnt; n++) {
40bbc194 568 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
d7dfca08
IM		 569 }
570 }
571
572 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
573 s->blkcnt--;
574 }
575
d368ba43 576 sdhci_end_transfer(s);
d7dfca08
IM		 577}
578
579typedef struct ADMADescr {
580 hwaddr addr;
581 uint16_t length;
582 uint8_t attr;
583 uint8_t incr;
584} ADMADescr;
585
586static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
587{
588 uint32_t adma1 = 0;
589 uint64_t adma2 = 0;
590 hwaddr entry_addr = (hwaddr)s->admasysaddr;
591 switch (SDHC_DMA_TYPE(s->hostctl)) {
592 case SDHC_CTRL_ADMA2_32:
df32fd1c 593 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2,
d7dfca08
IM		 594 sizeof(adma2));
595 adma2 = le64_to_cpu(adma2);
596 /* The spec does not specify endianness of descriptor table.
597 * We currently assume that it is LE.
598 */
599 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
600 dscr->length = (uint16_t)extract64(adma2, 16, 16);
601 dscr->attr = (uint8_t)extract64(adma2, 0, 7);
602 dscr->incr = 8;
603 break;
604 case SDHC_CTRL_ADMA1_32:
df32fd1c 605 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1,
d7dfca08
IM		 606 sizeof(adma1));
607 adma1 = le32_to_cpu(adma1);
608 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
609 dscr->attr = (uint8_t)extract32(adma1, 0, 7);
610 dscr->incr = 4;
611 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
612 dscr->length = (uint16_t)extract32(adma1, 12, 16);
613 } else {
614 dscr->length = 4096;
615 }
616 break;
617 case SDHC_CTRL_ADMA2_64:
df32fd1c 618 dma_memory_read(&address_space_memory, entry_addr,
d7dfca08 619 (uint8_t *)(&dscr->attr), 1);
df32fd1c 620 dma_memory_read(&address_space_memory, entry_addr + 2,
d7dfca08
IM		 621 (uint8_t *)(&dscr->length), 2);
622 dscr->length = le16_to_cpu(dscr->length);
df32fd1c 623 dma_memory_read(&address_space_memory, entry_addr + 4,
d7dfca08
IM		 624 (uint8_t *)(&dscr->addr), 8);
625 dscr->attr = le64_to_cpu(dscr->attr);
626 dscr->attr &= 0xfffffff8;
627 dscr->incr = 12;
628 break;
629 }
630}
631
632/* Advanced DMA data transfer */
633
634static void sdhci_do_adma(SDHCIState *s)
635{
636 unsigned int n, begin, length;
637 const uint16_t block_size = s->blksize & 0x0fff;
638 ADMADescr dscr;
639 int i;
640
641 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
642 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
643
644 get_adma_description(s, &dscr);
645 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n",
646 dscr.addr, dscr.length, dscr.attr);
647
648 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
649 /* Indicate that error occurred in ST_FDS state */
650 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK;
651 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS;
652
653 /* Generate ADMA error interrupt */
654 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
655 s->errintsts |= SDHC_EIS_ADMAERR;
656 s->norintsts |= SDHC_NIS_ERR;
657 }
658
659 sdhci_update_irq(s);
660 return;
661 }
662
663 length = dscr.length ? dscr.length : 65536;
664
665 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
666 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
667
668 if (s->trnmod & SDHC_TRNS_READ) {
669 while (length) {
670 if (s->data_count == 0) {
671 for (n = 0; n < block_size; n++) {
40bbc194 672 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
d7dfca08
IM		 673 }
674 }
675 begin = s->data_count;
676 if ((length + begin) < block_size) {
677 s->data_count = length + begin;
678 length = 0;
679 } else {
680 s->data_count = block_size;
681 length -= block_size - begin;
682 }
df32fd1c 683 dma_memory_write(&address_space_memory, dscr.addr,
d7dfca08
IM		 684 &s->fifo_buffer[begin],
685 s->data_count - begin);
686 dscr.addr += s->data_count - begin;
687 if (s->data_count == block_size) {
688 s->data_count = 0;
689 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
690 s->blkcnt--;
691 if (s->blkcnt == 0) {
692 break;
693 }
694 }
695 }
696 }
697 } else {
698 while (length) {
699 begin = s->data_count;
700 if ((length + begin) < block_size) {
701 s->data_count = length + begin;
702 length = 0;
703 } else {
704 s->data_count = block_size;
705 length -= block_size - begin;
706 }
df32fd1c 707 dma_memory_read(&address_space_memory, dscr.addr,
9db11cef
PC		 708 &s->fifo_buffer[begin],
709 s->data_count - begin);
d7dfca08
IM		 710 dscr.addr += s->data_count - begin;
711 if (s->data_count == block_size) {
712 for (n = 0; n < block_size; n++) {
40bbc194 713 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
d7dfca08
IM		 714 }
715 s->data_count = 0;
716 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
717 s->blkcnt--;
718 if (s->blkcnt == 0) {
719 break;
720 }
721 }
722 }
723 }
724 }
725 s->admasysaddr += dscr.incr;
726 break;
727 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
728 s->admasysaddr = dscr.addr;
be9c5dde
SPB		 729 DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64 "\n",
730 s->admasysaddr);
d7dfca08
IM		 731 break;
732 default:
733 s->admasysaddr += dscr.incr;
734 break;
735 }
736
1d32c26f 737 if (dscr.attr & SDHC_ADMA_ATTR_INT) {
be9c5dde
SPB		 738 DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64 "\n",
739 s->admasysaddr);
1d32c26f
PC		 740 if (s->norintstsen & SDHC_NISEN_DMA) {
741 s->norintsts |= SDHC_NIS_DMA;
742 }
743
744 sdhci_update_irq(s);
745 }
746
d7dfca08
IM		 747 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
748 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
749 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
750 DPRINT_L2("ADMA transfer completed\n");
751 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
752 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
753 s->blkcnt != 0)) {
754 ERRPRINT("SD/MMC host ADMA length mismatch\n");
755 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
756 SDHC_ADMAERR_STATE_ST_TFR;
757 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
758 ERRPRINT("Set ADMA error flag\n");
759 s->errintsts |= SDHC_EIS_ADMAERR;
760 s->norintsts |= SDHC_NIS_ERR;
761 }
762
763 sdhci_update_irq(s);
764 }
d368ba43 765 sdhci_end_transfer(s);
d7dfca08
IM		 766 return;
767 }
768
d7dfca08
IM		 769 }
770
085d8134 771 /* we have unfinished business - reschedule to continue ADMA */
bc72ad67
AB		 772 timer_mod(s->transfer_timer,
773 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY);
d7dfca08
IM		 774}
775
776/* Perform data transfer according to controller configuration */
777
d368ba43 778static void sdhci_data_transfer(void *opaque)
d7dfca08 779{
d368ba43 780 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 781
782 if (s->trnmod & SDHC_TRNS_DMA) {
783 switch (SDHC_DMA_TYPE(s->hostctl)) {
784 case SDHC_CTRL_SDMA:
785 if ((s->trnmod & SDHC_TRNS_MULTI) &&
786 (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) {
787 break;
788 }
789
790 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
d368ba43 791 sdhci_sdma_transfer_single_block(s);
d7dfca08 792 } else {
d368ba43 793 sdhci_sdma_transfer_multi_blocks(s);
d7dfca08
IM		 794 }
795
796 break;
797 case SDHC_CTRL_ADMA1_32:
798 if (!(s->capareg & SDHC_CAN_DO_ADMA1)) {
799 ERRPRINT("ADMA1 not supported\n");
800 break;
801 }
802
d368ba43 803 sdhci_do_adma(s);
d7dfca08
IM		 804 break;
805 case SDHC_CTRL_ADMA2_32:
806 if (!(s->capareg & SDHC_CAN_DO_ADMA2)) {
807 ERRPRINT("ADMA2 not supported\n");
808 break;
809 }
810
d368ba43 811 sdhci_do_adma(s);
d7dfca08
IM		 812 break;
813 case SDHC_CTRL_ADMA2_64:
814 if (!(s->capareg & SDHC_CAN_DO_ADMA2) ||
815 !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) {
816 ERRPRINT("64 bit ADMA not supported\n");
817 break;
818 }
819
d368ba43 820 sdhci_do_adma(s);
d7dfca08
IM		 821 break;
822 default:
823 ERRPRINT("Unsupported DMA type\n");
824 break;
825 }
826 } else {
40bbc194 827 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) {
d7dfca08
IM		 828 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
829 SDHC_DAT_LINE_ACTIVE;
d368ba43 830 sdhci_read_block_from_card(s);
d7dfca08
IM		 831 } else {
832 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE |
833 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT;
d368ba43 834 sdhci_write_block_to_card(s);
d7dfca08
IM		 835 }
836 }
837}
838
839static bool sdhci_can_issue_command(SDHCIState *s)
840{
6890a695 841 if (!SDHC_CLOCK_IS_ON(s->clkcon) ||
d7dfca08
IM		 842 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) &&
843 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) ||
844 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY &&
845 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
846 return false;
847 }
848
849 return true;
850}
851
852/* The Buffer Data Port register must be accessed in sequential and
853 * continuous manner */
854static inline bool
855sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
856{
857 if ((s->data_count & 0x3) != byte_num) {
858 ERRPRINT("Non-sequential access to Buffer Data Port register"
859 "is prohibited\n");
860 return false;
861 }
862 return true;
863}
864
d368ba43 865static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
d7dfca08 866{
d368ba43 867 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 868 uint32_t ret = 0;
869
870 switch (offset & ~0x3) {
871 case SDHC_SYSAD:
872 ret = s->sdmasysad;
873 break;
874 case SDHC_BLKSIZE:
875 ret = s->blksize | (s->blkcnt << 16);
876 break;
877 case SDHC_ARGUMENT:
878 ret = s->argument;
879 break;
880 case SDHC_TRNMOD:
881 ret = s->trnmod | (s->cmdreg << 16);
882 break;
883 case SDHC_RSPREG0 ... SDHC_RSPREG3:
884 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2];
885 break;
886 case SDHC_BDATA:
887 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43
KC		 888 ret = sdhci_read_dataport(s, size);
889 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset,
677ff2ae 890 ret, ret);
d7dfca08
IM		 891 return ret;
892 }
893 break;
894 case SDHC_PRNSTS:
895 ret = s->prnsts;
896 break;
897 case SDHC_HOSTCTL:
898 ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) |
899 (s->wakcon << 24);
900 break;
901 case SDHC_CLKCON:
902 ret = s->clkcon | (s->timeoutcon << 16);
903 break;
904 case SDHC_NORINTSTS:
905 ret = s->norintsts | (s->errintsts << 16);
906 break;
907 case SDHC_NORINTSTSEN:
908 ret = s->norintstsen | (s->errintstsen << 16);
909 break;
910 case SDHC_NORINTSIGEN:
911 ret = s->norintsigen | (s->errintsigen << 16);
912 break;
913 case SDHC_ACMD12ERRSTS:
914 ret = s->acmd12errsts;
915 break;
916 case SDHC_CAPAREG:
917 ret = s->capareg;
918 break;
919 case SDHC_MAXCURR:
920 ret = s->maxcurr;
921 break;
922 case SDHC_ADMAERR:
923 ret = s->admaerr;
924 break;
925 case SDHC_ADMASYSADDR:
926 ret = (uint32_t)s->admasysaddr;
927 break;
928 case SDHC_ADMASYSADDR + 4:
929 ret = (uint32_t)(s->admasysaddr >> 32);
930 break;
931 case SDHC_SLOT_INT_STATUS:
932 ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s);
933 break;
934 default:
d368ba43 935 ERRPRINT("bad %ub read: addr[0x%04x]\n", size, (int)offset);
d7dfca08
IM		 936 break;
937 }
938
939 ret >>= (offset & 0x3) * 8;
940 ret &= (1ULL << (size * 8)) - 1;
d368ba43 941 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, ret, ret);
d7dfca08
IM		 942 return ret;
943}
944
945static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value)
946{
947 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
948 return;
949 }
950 s->blkgap = value & SDHC_STOP_AT_GAP_REQ;
951
952 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
953 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
954 if (s->stopped_state == sdhc_gap_read) {
955 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ;
d368ba43 956 sdhci_read_block_from_card(s);
d7dfca08
IM		 957 } else {
958 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE;
d368ba43 959 sdhci_write_block_to_card(s);
d7dfca08
IM		 960 }
961 s->stopped_state = sdhc_not_stopped;
962 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) {
963 if (s->prnsts & SDHC_DOING_READ) {
964 s->stopped_state = sdhc_gap_read;
965 } else if (s->prnsts & SDHC_DOING_WRITE) {
966 s->stopped_state = sdhc_gap_write;
967 }
968 }
969}
970
971static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
972{
973 switch (value) {
974 case SDHC_RESET_ALL:
d368ba43 975 sdhci_reset(s);
d7dfca08
IM		 976 break;
977 case SDHC_RESET_CMD:
978 s->prnsts &= ~SDHC_CMD_INHIBIT;
979 s->norintsts &= ~SDHC_NIS_CMDCMP;
980 break;
981 case SDHC_RESET_DATA:
982 s->data_count = 0;
983 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE |
984 SDHC_DOING_READ | SDHC_DOING_WRITE |
985 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE);
986 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ);
987 s->stopped_state = sdhc_not_stopped;
988 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY |
989 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP);
990 break;
991 }
992}
993
994static void
d368ba43 995sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
d7dfca08 996{
d368ba43 997 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 998 unsigned shift = 8 * (offset & 0x3);
999 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift);
d368ba43 1000 uint32_t value = val;
d7dfca08
IM		 1001 value <<= shift;
1002
1003 switch (offset & ~0x3) {
1004 case SDHC_SYSAD:
1005 s->sdmasysad = (s->sdmasysad & mask) | value;
1006 MASKED_WRITE(s->sdmasysad, mask, value);
1007 /* Writing to last byte of sdmasysad might trigger transfer */
1008 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&
1009 s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {
d368ba43 1010 sdhci_sdma_transfer_multi_blocks(s);
d7dfca08
IM		 1011 }
1012 break;
1013 case SDHC_BLKSIZE:
1014 if (!TRANSFERRING_DATA(s->prnsts)) {
1015 MASKED_WRITE(s->blksize, mask, value);
1016 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
1017 }
9201bb9a
AF		 1018
1019 /* Limit block size to the maximum buffer size */
1020 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) {
1021 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \
1022 "the maximum buffer 0x%x", __func__, s->blksize,
1023 s->buf_maxsz);
1024
1025 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz);
1026 }
1027
d7dfca08
IM		 1028 break;
1029 case SDHC_ARGUMENT:
1030 MASKED_WRITE(s->argument, mask, value);
1031 break;
1032 case SDHC_TRNMOD:
1033 /* DMA can be enabled only if it is supported as indicated by
1034 * capabilities register */
1035 if (!(s->capareg & SDHC_CAN_DO_DMA)) {
1036 value &= ~SDHC_TRNS_DMA;
1037 }
1038 MASKED_WRITE(s->trnmod, mask, value);
1039 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
1040
1041 /* Writing to the upper byte of CMDREG triggers SD command generation */
d368ba43 1042 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) {
d7dfca08
IM		 1043 break;
1044 }
1045
d368ba43 1046 sdhci_send_command(s);
d7dfca08
IM		 1047 break;
1048 case SDHC_BDATA:
1049 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43 1050 sdhci_write_dataport(s, value >> shift, size);
d7dfca08
IM		 1051 }
1052 break;
1053 case SDHC_HOSTCTL:
1054 if (!(mask & 0xFF0000)) {
1055 sdhci_blkgap_write(s, value >> 16);
1056 }
1057 MASKED_WRITE(s->hostctl, mask, value);
1058 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
1059 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
1060 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
1061 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
1062 s->pwrcon &= ~SDHC_POWER_ON;
1063 }
1064 break;
1065 case SDHC_CLKCON:
1066 if (!(mask & 0xFF000000)) {
1067 sdhci_reset_write(s, value >> 24);
1068 }
1069 MASKED_WRITE(s->clkcon, mask, value);
1070 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);
1071 if (s->clkcon & SDHC_CLOCK_INT_EN) {
1072 s->clkcon |= SDHC_CLOCK_INT_STABLE;
1073 } else {
1074 s->clkcon &= ~SDHC_CLOCK_INT_STABLE;
1075 }
1076 break;
1077 case SDHC_NORINTSTS:
1078 if (s->norintstsen & SDHC_NISEN_CARDINT) {
1079 value &= ~SDHC_NIS_CARDINT;
1080 }
1081 s->norintsts &= mask | ~value;
1082 s->errintsts &= (mask >> 16) | ~(value >> 16);
1083 if (s->errintsts) {
1084 s->norintsts |= SDHC_NIS_ERR;
1085 } else {
1086 s->norintsts &= ~SDHC_NIS_ERR;
1087 }
1088 sdhci_update_irq(s);
1089 break;
1090 case SDHC_NORINTSTSEN:
1091 MASKED_WRITE(s->norintstsen, mask, value);
1092 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);
1093 s->norintsts &= s->norintstsen;
1094 s->errintsts &= s->errintstsen;
1095 if (s->errintsts) {
1096 s->norintsts |= SDHC_NIS_ERR;
1097 } else {
1098 s->norintsts &= ~SDHC_NIS_ERR;
1099 }
1100 sdhci_update_irq(s);
1101 break;
1102 case SDHC_NORINTSIGEN:
1103 MASKED_WRITE(s->norintsigen, mask, value);
1104 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);
1105 sdhci_update_irq(s);
1106 break;
1107 case SDHC_ADMAERR:
1108 MASKED_WRITE(s->admaerr, mask, value);
1109 break;
1110 case SDHC_ADMASYSADDR:
1111 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
1112 (uint64_t)mask)) | (uint64_t)value;
1113 break;
1114 case SDHC_ADMASYSADDR + 4:
1115 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
1116 ((uint64_t)mask << 32))) | ((uint64_t)value << 32);
1117 break;
1118 case SDHC_FEAER:
1119 s->acmd12errsts |= value;
1120 s->errintsts |= (value >> 16) & s->errintstsen;
1121 if (s->acmd12errsts) {
1122 s->errintsts |= SDHC_EIS_CMD12ERR;
1123 }
1124 if (s->errintsts) {
1125 s->norintsts |= SDHC_NIS_ERR;
1126 }
1127 sdhci_update_irq(s);
1128 break;
1129 default:
1130 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n",
d368ba43 1131 size, (int)offset, value >> shift, value >> shift);
d7dfca08
IM		 1132 break;
1133 }
1134 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
d368ba43 1135 size, (int)offset, value >> shift, value >> shift);
d7dfca08
IM		 1136}
1137
1138static const MemoryRegionOps sdhci_mmio_ops = {
d368ba43
KC		 1139 .read = sdhci_read,
1140 .write = sdhci_write,
d7dfca08
IM		 1141 .valid = {
1142 .min_access_size = 1,
1143 .max_access_size = 4,
1144 .unaligned = false
1145 },
1146 .endianness = DEVICE_LITTLE_ENDIAN,
1147};
1148
1149static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
1150{
1151 switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) {
1152 case 0:
1153 return 512;
1154 case 1:
1155 return 1024;
1156 case 2:
1157 return 2048;
1158 default:
1159 hw_error("SDHC: unsupported value for maximum block size\n");
1160 return 0;
1161 }
1162}
1163
40bbc194 1164static void sdhci_initfn(SDHCIState *s)
d7dfca08 1165{
40bbc194
PM		 1166 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1167 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
d7dfca08 1168
bc72ad67 1169 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
d368ba43 1170 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
d7dfca08
IM		 1171}
1172
7302dcd6 1173static void sdhci_uninitfn(SDHCIState *s)
d7dfca08 1174{
bc72ad67
AB		 1175 timer_del(s->insert_timer);
1176 timer_free(s->insert_timer);
1177 timer_del(s->transfer_timer);
1178 timer_free(s->transfer_timer);
127a4e1a
AF		 1179 qemu_free_irq(s->eject_cb);
1180 qemu_free_irq(s->ro_cb);
d7dfca08 1181
012aef07
MA		 1182 g_free(s->fifo_buffer);
1183 s->fifo_buffer = NULL;
d7dfca08
IM		 1184}
1185
1186const VMStateDescription sdhci_vmstate = {
1187 .name = "sdhci",
1188 .version_id = 1,
1189 .minimum_version_id = 1,
35d08458 1190 .fields = (VMStateField[]) {
d7dfca08
IM		 1191 VMSTATE_UINT32(sdmasysad, SDHCIState),
1192 VMSTATE_UINT16(blksize, SDHCIState),
1193 VMSTATE_UINT16(blkcnt, SDHCIState),
1194 VMSTATE_UINT32(argument, SDHCIState),
1195 VMSTATE_UINT16(trnmod, SDHCIState),
1196 VMSTATE_UINT16(cmdreg, SDHCIState),
1197 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
1198 VMSTATE_UINT32(prnsts, SDHCIState),
1199 VMSTATE_UINT8(hostctl, SDHCIState),
1200 VMSTATE_UINT8(pwrcon, SDHCIState),
1201 VMSTATE_UINT8(blkgap, SDHCIState),
1202 VMSTATE_UINT8(wakcon, SDHCIState),
1203 VMSTATE_UINT16(clkcon, SDHCIState),
1204 VMSTATE_UINT8(timeoutcon, SDHCIState),
1205 VMSTATE_UINT8(admaerr, SDHCIState),
1206 VMSTATE_UINT16(norintsts, SDHCIState),
1207 VMSTATE_UINT16(errintsts, SDHCIState),
1208 VMSTATE_UINT16(norintstsen, SDHCIState),
1209 VMSTATE_UINT16(errintstsen, SDHCIState),
1210 VMSTATE_UINT16(norintsigen, SDHCIState),
1211 VMSTATE_UINT16(errintsigen, SDHCIState),
1212 VMSTATE_UINT16(acmd12errsts, SDHCIState),
1213 VMSTATE_UINT16(data_count, SDHCIState),
1214 VMSTATE_UINT64(admasysaddr, SDHCIState),
1215 VMSTATE_UINT8(stopped_state, SDHCIState),
1216 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, 0, buf_maxsz),
e720677e
PB		 1217 VMSTATE_TIMER_PTR(insert_timer, SDHCIState),
1218 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState),
d7dfca08
IM		 1219 VMSTATE_END_OF_LIST()
1220 }
1221};
1222
1223/* Capabilities registers provide information on supported features of this
1224 * specific host controller implementation */
5ec911c3 1225static Property sdhci_pci_properties[] = {
c7bcc85d 1226 DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
d7dfca08 1227 SDHC_CAPAB_REG_DEFAULT),
c7bcc85d 1228 DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
d7dfca08
IM		 1229 DEFINE_PROP_END_OF_LIST(),
1230};
1231
9af21dbe 1232static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
224d10ff
KC		 1233{
1234 SDHCIState *s = PCI_SDHCI(dev);
1235 dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */
1236 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
40bbc194 1237 sdhci_initfn(s);
224d10ff
KC		 1238 s->buf_maxsz = sdhci_get_fifolen(s);
1239 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1240 s->irq = pci_allocate_irq(dev);
1241 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
1242 SDHC_REGISTERS_MAP_SIZE);
1243 pci_register_bar(dev, 0, 0, &s->iomem);
224d10ff
KC		 1244}
1245
1246static void sdhci_pci_exit(PCIDevice *dev)
1247{
1248 SDHCIState *s = PCI_SDHCI(dev);
1249 sdhci_uninitfn(s);
1250}
1251
1252static void sdhci_pci_class_init(ObjectClass *klass, void *data)
1253{
1254 DeviceClass *dc = DEVICE_CLASS(klass);
1255 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1256
9af21dbe 1257 k->realize = sdhci_pci_realize;
224d10ff
KC		 1258 k->exit = sdhci_pci_exit;
1259 k->vendor_id = PCI_VENDOR_ID_REDHAT;
1260 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI;
1261 k->class_id = PCI_CLASS_SYSTEM_SDHCI;
1262 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1263 dc->vmsd = &sdhci_vmstate;
5ec911c3 1264 dc->props = sdhci_pci_properties;
224d10ff
KC		 1265}
1266
1267static const TypeInfo sdhci_pci_info = {
1268 .name = TYPE_PCI_SDHCI,
1269 .parent = TYPE_PCI_DEVICE,
1270 .instance_size = sizeof(SDHCIState),
1271 .class_init = sdhci_pci_class_init,
1272};
1273
5ec911c3
KC		 1274static Property sdhci_sysbus_properties[] = {
1275 DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
1276 SDHC_CAPAB_REG_DEFAULT),
1277 DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
72369755 1278 DEFINE_PROP_BOOL("noeject-quirk", SDHCIState, noeject_quirk, false),
5ec911c3
KC		 1279 DEFINE_PROP_END_OF_LIST(),
1280};
1281
7302dcd6
KC		 1282static void sdhci_sysbus_init(Object *obj)
1283{
1284 SDHCIState *s = SYSBUS_SDHCI(obj);
5ec911c3 1285
40bbc194 1286 sdhci_initfn(s);
7302dcd6
KC		 1287}
1288
1289static void sdhci_sysbus_finalize(Object *obj)
1290{
1291 SDHCIState *s = SYSBUS_SDHCI(obj);
1292 sdhci_uninitfn(s);
1293}
1294
1295static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
d7dfca08 1296{
7302dcd6 1297 SDHCIState *s = SYSBUS_SDHCI(dev);
d7dfca08
IM		 1298 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1299
1300 s->buf_maxsz = sdhci_get_fifolen(s);
1301 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1302 sysbus_init_irq(sbd, &s->irq);
29776739 1303 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
d7dfca08
IM		 1304 SDHC_REGISTERS_MAP_SIZE);
1305 sysbus_init_mmio(sbd, &s->iomem);
1306}
1307
7302dcd6 1308static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
d7dfca08
IM		 1309{
1310 DeviceClass *dc = DEVICE_CLASS(klass);
d7dfca08
IM		 1311
1312 dc->vmsd = &sdhci_vmstate;
5ec911c3 1313 dc->props = sdhci_sysbus_properties;
7302dcd6 1314 dc->realize = sdhci_sysbus_realize;
d7dfca08
IM		 1315}
1316
7302dcd6
KC		 1317static const TypeInfo sdhci_sysbus_info = {
1318 .name = TYPE_SYSBUS_SDHCI,
d7dfca08
IM		 1319 .parent = TYPE_SYS_BUS_DEVICE,
1320 .instance_size = sizeof(SDHCIState),
7302dcd6
KC		 1321 .instance_init = sdhci_sysbus_init,
1322 .instance_finalize = sdhci_sysbus_finalize,
1323 .class_init = sdhci_sysbus_class_init,
d7dfca08
IM		 1324};
1325
40bbc194
PM		 1326static void sdhci_bus_class_init(ObjectClass *klass, void *data)
1327{
1328 SDBusClass *sbc = SD_BUS_CLASS(klass);
1329
1330 sbc->set_inserted = sdhci_set_inserted;
1331 sbc->set_readonly = sdhci_set_readonly;
1332}
1333
1334static const TypeInfo sdhci_bus_info = {
1335 .name = TYPE_SDHCI_BUS,
1336 .parent = TYPE_SD_BUS,
1337 .instance_size = sizeof(SDBus),
1338 .class_init = sdhci_bus_class_init,
1339};
1340
d7dfca08
IM		 1341static void sdhci_register_types(void)
1342{
224d10ff 1343 type_register_static(&sdhci_pci_info);
7302dcd6 1344 type_register_static(&sdhci_sysbus_info);
40bbc194 1345 type_register_static(&sdhci_bus_info);
d7dfca08
IM		 1346}
1347
1348type_init(sdhci_register_types)
Mirror of https://git.qemu.org/git/qemu.git