[thirdparty/qemu.git] / hw / vt82c686.c

/*
 * VT82C686B south bridge support
 *
 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
 * This code is licensed under the GNU GPL v2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "hw/hw.h"
#include "hw/pc.h"
#include "hw/vt82c686.h"
#include "hw/i2c.h"
#include "hw/smbus.h"
#include "hw/pci/pci.h"
#include "hw/isa.h"
#include "hw/sysbus.h"
#include "hw/mips.h"
#include "hw/apm.h"
#include "hw/acpi.h"
#include "hw/pm_smbus.h"
#include "sysemu/sysemu.h"
#include "qemu/timer.h"
#include "exec/address-spaces.h"

//#define DEBUG_VT82C686B

#ifdef DEBUG_VT82C686B
#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
#else
#define DPRINTF(fmt, ...)
#endif

typedef struct SuperIOConfig
{
    uint8_t config[0xff];
    uint8_t index;
    uint8_t data;
} SuperIOConfig;

typedef struct VT82C686BState {
    PCIDevice dev;
    SuperIOConfig superio_conf;
} VT82C686BState;

static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
{
    int can_write;
    SuperIOConfig *superio_conf = opaque;

    DPRINTF("superio_ioport_writeb  address 0x%x  val 0x%x\n", addr, data);
    if (addr == 0x3f0) {
        superio_conf->index = data & 0xff;
    } else {
        /* 0x3f1 */
        switch (superio_conf->index) {
        case 0x00 ... 0xdf:
        case 0xe4:
        case 0xe5:
        case 0xe9 ... 0xed:
        case 0xf3:
        case 0xf5:
        case 0xf7:
        case 0xf9 ... 0xfb:
        case 0xfd ... 0xff:
            can_write = 0;
            break;
        default:
            can_write = 1;

            if (can_write) {
                switch (superio_conf->index) {
                case 0xe7:
                    if ((data & 0xff) != 0xfe) {
                        DPRINTF("chage uart 1 base. unsupported yet\n");
                    }
                    break;
                case 0xe8:
                    if ((data & 0xff) != 0xbe) {
                        DPRINTF("chage uart 2 base. unsupported yet\n");
                    }
                    break;

                default:
                    superio_conf->config[superio_conf->index] = data & 0xff;
                }
            }
        }
        superio_conf->config[superio_conf->index] = data & 0xff;
    }
}

static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
{
    SuperIOConfig *superio_conf = opaque;

    DPRINTF("superio_ioport_readb  address 0x%x\n", addr);
    return (superio_conf->config[superio_conf->index]);
}

static void vt82c686b_reset(void * opaque)
{
    PCIDevice *d = opaque;
    uint8_t *pci_conf = d->config;
    VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);

    pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
                 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);

    pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
    pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
    pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
    pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
    pci_conf[0x59] = 0x04;
    pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
    pci_conf[0x5f] = 0x04;
    pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */

    vt82c->superio_conf.config[0xe0] = 0x3c;
    vt82c->superio_conf.config[0xe2] = 0x03;
    vt82c->superio_conf.config[0xe3] = 0xfc;
    vt82c->superio_conf.config[0xe6] = 0xde;
    vt82c->superio_conf.config[0xe7] = 0xfe;
    vt82c->superio_conf.config[0xe8] = 0xbe;
}

/* write config pci function0 registers. PCI-ISA bridge */
static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
                                   uint32_t val, int len)
{
    VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);

    DPRINTF("vt82c686b_write_config  address 0x%x  val 0x%x len 0x%x\n",
           address, val, len);

    pci_default_write_config(d, address, val, len);
    if (address == 0x85) {  /* enable or disable super IO configure */
        if (val & 0x2) {
            /* floppy also uses 0x3f0 and 0x3f1.
             * But we do not emulate flopy,so just set it here. */
            isa_unassign_ioport(0x3f0, 2);
            register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
                                 &vt686->superio_conf);
            register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
                                  &vt686->superio_conf);
        } else {
            isa_unassign_ioport(0x3f0, 2);
        }
    }
}

#define ACPI_DBG_IO_ADDR  0xb044

typedef struct VT686PMState {
    PCIDevice dev;
    MemoryRegion io;
    ACPIREGS ar;
    APMState apm;
    PMSMBus smb;
    uint32_t smb_io_base;
} VT686PMState;

typedef struct VT686AC97State {
    PCIDevice dev;
} VT686AC97State;

typedef struct VT686MC97State {
    PCIDevice dev;
} VT686MC97State;

static void pm_update_sci(VT686PMState *s)
{
    int sci_level, pmsts;

    pmsts = acpi_pm1_evt_get_sts(&s->ar);
    sci_level = (((pmsts & s->ar.pm1.evt.en) &
                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
                   ACPI_BITMASK_TIMER_ENABLE)) != 0);
    qemu_set_irq(s->dev.irq[0], sci_level);
    /* schedule a timer interruption if needed */
    acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
                       !(pmsts & ACPI_BITMASK_TIMER_STATUS));
}

static void pm_tmr_timer(ACPIREGS *ar)
{
    VT686PMState *s = container_of(ar, VT686PMState, ar);
    pm_update_sci(s);
}

static void pm_io_space_update(VT686PMState *s)
{
    uint32_t pm_io_base;

    pm_io_base = pci_get_long(s->dev.config + 0x40);
    pm_io_base &= 0xffc0;

    memory_region_transaction_begin();
    memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
    memory_region_set_address(&s->io, pm_io_base);
    memory_region_transaction_commit();
}

static void pm_write_config(PCIDevice *d,
                            uint32_t address, uint32_t val, int len)
{
    DPRINTF("pm_write_config  address 0x%x  val 0x%x len 0x%x\n",
           address, val, len);
    pci_default_write_config(d, address, val, len);
}

static int vmstate_acpi_post_load(void *opaque, int version_id)
{
    VT686PMState *s = opaque;

    pm_io_space_update(s);
    return 0;
}

static const VMStateDescription vmstate_acpi = {
    .name = "vt82c686b_pm",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = vmstate_acpi_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, VT686PMState),
        VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
        VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
        VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
        VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
        VMSTATE_TIMER(ar.tmr.timer, VT686PMState),
        VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
        VMSTATE_END_OF_LIST()
    }
};

/*
 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
 * just register a PCI device now, functionalities will be implemented later.
 */

static int vt82c686b_ac97_initfn(PCIDevice *dev)
{
    VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
    uint8_t *pci_conf = s->dev.config;

    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
                 PCI_COMMAND_PARITY);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
                 PCI_STATUS_DEVSEL_MEDIUM);
    pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);

    return 0;
}

void vt82c686b_ac97_init(PCIBus *bus, int devfn)
{
    PCIDevice *dev;

    dev = pci_create(bus, devfn, "VT82C686B_AC97");
    qdev_init_nofail(&dev->qdev);
}

static void via_ac97_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = vt82c686b_ac97_initfn;
    k->vendor_id = PCI_VENDOR_ID_VIA;
    k->device_id = PCI_DEVICE_ID_VIA_AC97;
    k->revision = 0x50;
    k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
    dc->desc = "AC97";
}

static const TypeInfo via_ac97_info = {
    .name          = "VT82C686B_AC97",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(VT686AC97State),
    .class_init    = via_ac97_class_init,
};

static int vt82c686b_mc97_initfn(PCIDevice *dev)
{
    VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
    uint8_t *pci_conf = s->dev.config;

    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
                 PCI_COMMAND_VGA_PALETTE);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
    pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);

    return 0;
}

void vt82c686b_mc97_init(PCIBus *bus, int devfn)
{
    PCIDevice *dev;

    dev = pci_create(bus, devfn, "VT82C686B_MC97");
    qdev_init_nofail(&dev->qdev);
}

static void via_mc97_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = vt82c686b_mc97_initfn;
    k->vendor_id = PCI_VENDOR_ID_VIA;
    k->device_id = PCI_DEVICE_ID_VIA_MC97;
    k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
    k->revision = 0x30;
    dc->desc = "MC97";
}

static const TypeInfo via_mc97_info = {
    .name          = "VT82C686B_MC97",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(VT686MC97State),
    .class_init    = via_mc97_class_init,
};

/* vt82c686 pm init */
static int vt82c686b_pm_initfn(PCIDevice *dev)
{
    VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
    uint8_t *pci_conf;

    pci_conf = s->dev.config;
    pci_set_word(pci_conf + PCI_COMMAND, 0);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
                 PCI_STATUS_DEVSEL_MEDIUM);

    /* 0x48-0x4B is Power Management I/O Base */
    pci_set_long(pci_conf + 0x48, 0x00000001);

    /* SMB ports:0xeee0~0xeeef */
    s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
    pci_conf[0x90] = s->smb_io_base | 1;
    pci_conf[0x91] = s->smb_io_base >> 8;
    pci_conf[0xd2] = 0x90;
    pm_smbus_init(&s->dev.qdev, &s->smb);
    memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);

    apm_init(dev, &s->apm, NULL, s);

    memory_region_init(&s->io, "vt82c686-pm", 64);
    memory_region_set_enabled(&s->io, false);
    memory_region_add_subregion(get_system_io(), 0, &s->io);

    acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
    acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
    acpi_pm1_cnt_init(&s->ar, &s->io, 2);

    return 0;
}

i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq)
{
    PCIDevice *dev;
    VT686PMState *s;

    dev = pci_create(bus, devfn, "VT82C686B_PM");
    qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);

    s = DO_UPCAST(VT686PMState, dev, dev);

    qdev_init_nofail(&dev->qdev);

    return s->smb.smbus;
}

static Property via_pm_properties[] = {
    DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void via_pm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = vt82c686b_pm_initfn;
    k->config_write = pm_write_config;
    k->vendor_id = PCI_VENDOR_ID_VIA;
    k->device_id = PCI_DEVICE_ID_VIA_ACPI;
    k->class_id = PCI_CLASS_BRIDGE_OTHER;
    k->revision = 0x40;
    dc->desc = "PM";
    dc->vmsd = &vmstate_acpi;
    dc->props = via_pm_properties;
}

static const TypeInfo via_pm_info = {
    .name          = "VT82C686B_PM",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(VT686PMState),
    .class_init    = via_pm_class_init,
};

static const VMStateDescription vmstate_via = {
    .name = "vt82c686b",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, VT82C686BState),
        VMSTATE_END_OF_LIST()
    }
};

/* init the PCI-to-ISA bridge */
static int vt82c686b_initfn(PCIDevice *d)
{
    uint8_t *pci_conf;
    uint8_t *wmask;
    int i;

    isa_bus_new(&d->qdev, pci_address_space_io(d));

    pci_conf = d->config;
    pci_config_set_prog_interface(pci_conf, 0x0);

    wmask = d->wmask;
    for (i = 0x00; i < 0xff; i++) {
       if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
           wmask[i] = 0x00;
       }
    }

    qemu_register_reset(vt82c686b_reset, d);

    return 0;
}

ISABus *vt82c686b_init(PCIBus *bus, int devfn)
{
    PCIDevice *d;

    d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");

    return DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&d->qdev, "isa.0"));
}

static void via_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = vt82c686b_initfn;
    k->config_write = vt82c686b_write_config;
    k->vendor_id = PCI_VENDOR_ID_VIA;
    k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
    k->class_id = PCI_CLASS_BRIDGE_ISA;
    k->revision = 0x40;
    dc->desc = "ISA bridge";
    dc->no_user = 1;
    dc->vmsd = &vmstate_via;
}

static const TypeInfo via_info = {
    .name          = "VT82C686B",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(VT82C686BState),
    .class_init    = via_class_init,
};

static void vt82c686b_register_types(void)
{
    type_register_static(&via_ac97_info);
    type_register_static(&via_mc97_info);
    type_register_static(&via_pm_info);
    type_register_static(&via_info);
}

type_init(vt82c686b_register_types)
Commit	Line	Data
edf79e66 HC	1	/*
	2	* VT82C686B south bridge support
	3	*
	4	* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
	5	* Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
	6	* Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
	7	* This code is licensed under the GNU GPL v2.
6b620ca3 PB	8	*
	9	* Contributions after 2012-01-13 are licensed under the terms of the
	10	* GNU GPL, version 2 or (at your option) any later version.
edf79e66 HC	11	*/
edf79e66 HC	12
83c9f4ca PB	13	#include "hw/hw.h"
	14	#include "hw/pc.h"
	15	#include "hw/vt82c686.h"
	16	#include "hw/i2c.h"
	17	#include "hw/smbus.h"
	18	#include "hw/pci/pci.h"
	19	#include "hw/isa.h"
	20	#include "hw/sysbus.h"
	21	#include "hw/mips.h"
	22	#include "hw/apm.h"
	23	#include "hw/acpi.h"
	24	#include "hw/pm_smbus.h"
9c17d615	25	#include "sysemu/sysemu.h"
1de7afc9	26	#include "qemu/timer.h"
022c62cb	27	#include "exec/address-spaces.h"
edf79e66	28
edf79e66 HC	29	//#define DEBUG_VT82C686B
	30
	31	#ifdef DEBUG_VT82C686B
	32	#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
	33	#else
	34	#define DPRINTF(fmt, ...)
	35	#endif
	36
	37	typedef struct SuperIOConfig
	38	{
	39	uint8_t config[0xff];
	40	uint8_t index;
	41	uint8_t data;
	42	} SuperIOConfig;
	43
	44	typedef struct VT82C686BState {
	45	PCIDevice dev;
	46	SuperIOConfig superio_conf;
	47	} VT82C686BState;
	48
	49	static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
	50	{
	51	int can_write;
	52	SuperIOConfig *superio_conf = opaque;
	53
b2bedb21	54	DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
edf79e66 HC	55	if (addr == 0x3f0) {
	56	superio_conf->index = data & 0xff;
	57	} else {
	58	/* 0x3f1 */
	59	switch (superio_conf->index) {
	60	case 0x00 ... 0xdf:
	61	case 0xe4:
	62	case 0xe5:
	63	case 0xe9 ... 0xed:
	64	case 0xf3:
	65	case 0xf5:
	66	case 0xf7:
	67	case 0xf9 ... 0xfb:
	68	case 0xfd ... 0xff:
	69	can_write = 0;
	70	break;
	71	default:
	72	can_write = 1;
	73
	74	if (can_write) {
	75	switch (superio_conf->index) {
	76	case 0xe7:
	77	if ((data & 0xff) != 0xfe) {
b2bedb21	78	DPRINTF("chage uart 1 base. unsupported yet\n");
edf79e66 HC	79	}
	80	break;
	81	case 0xe8:
	82	if ((data & 0xff) != 0xbe) {
b2bedb21	83	DPRINTF("chage uart 2 base. unsupported yet\n");
edf79e66 HC	84	}
	85	break;
	86
	87	default:
	88	superio_conf->config[superio_conf->index] = data & 0xff;
	89	}
	90	}
	91	}
	92	superio_conf->config[superio_conf->index] = data & 0xff;
	93	}
	94	}
	95
	96	static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
	97	{
	98	SuperIOConfig *superio_conf = opaque;
	99
b2bedb21	100	DPRINTF("superio_ioport_readb address 0x%x\n", addr);
edf79e66 HC	101	return (superio_conf->config[superio_conf->index]);
	102	}
	103
	104	static void vt82c686b_reset(void * opaque)
	105	{
	106	PCIDevice *d = opaque;
	107	uint8_t *pci_conf = d->config;
	108	VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
	109
	110	pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
	111	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \|
	112	PCI_COMMAND_MASTER \| PCI_COMMAND_SPECIAL);
	113	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
	114
	115	pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
	116	pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
	117	pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
	118	pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
	119	pci_conf[0x59] = 0x04;
	120	pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
	121	pci_conf[0x5f] = 0x04;
	122	pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
	123
	124	vt82c->superio_conf.config[0xe0] = 0x3c;
	125	vt82c->superio_conf.config[0xe2] = 0x03;
	126	vt82c->superio_conf.config[0xe3] = 0xfc;
	127	vt82c->superio_conf.config[0xe6] = 0xde;
	128	vt82c->superio_conf.config[0xe7] = 0xfe;
	129	vt82c->superio_conf.config[0xe8] = 0xbe;
	130	}
	131
	132	/* write config pci function0 registers. PCI-ISA bridge */
	133	static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
	134	uint32_t val, int len)
	135	{
	136	VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
	137
b2bedb21	138	DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
edf79e66 HC	139	address, val, len);
	140
	141	pci_default_write_config(d, address, val, len);
	142	if (address == 0x85) { /* enable or disable super IO configure */
	143	if (val & 0x2) {
	144	/* floppy also uses 0x3f0 and 0x3f1.
	145	* But we do not emulate flopy,so just set it here. */
	146	isa_unassign_ioport(0x3f0, 2);
	147	register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
	148	&vt686->superio_conf);
	149	register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
	150	&vt686->superio_conf);
	151	} else {
	152	isa_unassign_ioport(0x3f0, 2);
	153	}
	154	}
	155	}
	156
	157	#define ACPI_DBG_IO_ADDR 0xb044
	158
	159	typedef struct VT686PMState {
	160	PCIDevice dev;
a2902821	161	MemoryRegion io;
355bf2e5	162	ACPIREGS ar;
edf79e66	163	APMState apm;
edf79e66 HC	164	PMSMBus smb;
	165	uint32_t smb_io_base;
	166	} VT686PMState;
	167
	168	typedef struct VT686AC97State {
	169	PCIDevice dev;
	170	} VT686AC97State;
	171
	172	typedef struct VT686MC97State {
	173	PCIDevice dev;
	174	} VT686MC97State;
	175
edf79e66 HC	176	static void pm_update_sci(VT686PMState *s)
	177	{
	178	int sci_level, pmsts;
edf79e66	179
2886be1b	180	pmsts = acpi_pm1_evt_get_sts(&s->ar);
355bf2e5	181	sci_level = (((pmsts & s->ar.pm1.evt.en) &
04dc308f IY	182	(ACPI_BITMASK_RT_CLOCK_ENABLE \|
	183	ACPI_BITMASK_POWER_BUTTON_ENABLE \|
	184	ACPI_BITMASK_GLOBAL_LOCK_ENABLE \|
	185	ACPI_BITMASK_TIMER_ENABLE)) != 0);
edf79e66 HC	186	qemu_set_irq(s->dev.irq[0], sci_level);
edf79e66 HC	187	/* schedule a timer interruption if needed */
355bf2e5	188	acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
a54d41a8	189	!(pmsts & ACPI_BITMASK_TIMER_STATUS));
edf79e66 HC	190	}
edf79e66 HC	191
355bf2e5	192	static void pm_tmr_timer(ACPIREGS *ar)
edf79e66	193	{
355bf2e5	194	VT686PMState *s = container_of(ar, VT686PMState, ar);
edf79e66 HC	195	pm_update_sci(s);
	196	}
	197
edf79e66 HC	198	static void pm_io_space_update(VT686PMState *s)
	199	{
	200	uint32_t pm_io_base;
	201
a2902821 GH	202	pm_io_base = pci_get_long(s->dev.config + 0x40);
a2902821 GH	203	pm_io_base &= 0xffc0;
edf79e66	204
a2902821 GH	205	memory_region_transaction_begin();
	206	memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
	207	memory_region_set_address(&s->io, pm_io_base);
	208	memory_region_transaction_commit();
edf79e66 HC	209	}
	210
	211	static void pm_write_config(PCIDevice *d,
	212	uint32_t address, uint32_t val, int len)
	213	{
b2bedb21	214	DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
edf79e66 HC	215	address, val, len);
	216	pci_default_write_config(d, address, val, len);
	217	}
	218
	219	static int vmstate_acpi_post_load(void *opaque, int version_id)
	220	{
	221	VT686PMState *s = opaque;
	222
	223	pm_io_space_update(s);
	224	return 0;
	225	}
	226
	227	static const VMStateDescription vmstate_acpi = {
	228	.name = "vt82c686b_pm",
	229	.version_id = 1,
	230	.minimum_version_id = 1,
	231	.minimum_version_id_old = 1,
	232	.post_load = vmstate_acpi_post_load,
	233	.fields = (VMStateField []) {
	234	VMSTATE_PCI_DEVICE(dev, VT686PMState),
355bf2e5 GH	235	VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
	236	VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
	237	VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
edf79e66	238	VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
355bf2e5 GH	239	VMSTATE_TIMER(ar.tmr.timer, VT686PMState),
355bf2e5 GH	240	VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
edf79e66 HC	241	VMSTATE_END_OF_LIST()
	242	}
	243	};
	244
	245	/*
	246	* TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
	247	* just register a PCI device now, functionalities will be implemented later.
	248	*/
	249
	250	static int vt82c686b_ac97_initfn(PCIDevice *dev)
	251	{
	252	VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
	253	uint8_t *pci_conf = s->dev.config;
	254
edf79e66 HC	255	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE \|
	256	PCI_COMMAND_PARITY);
	257	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST \|
	258	PCI_STATUS_DEVSEL_MEDIUM);
	259	pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
	260
	261	return 0;
	262	}
	263
	264	void vt82c686b_ac97_init(PCIBus *bus, int devfn)
	265	{
	266	PCIDevice *dev;
	267
	268	dev = pci_create(bus, devfn, "VT82C686B_AC97");
	269	qdev_init_nofail(&dev->qdev);
	270	}
	271
40021f08 AL	272	static void via_ac97_class_init(ObjectClass klass, void data)
40021f08 AL	273	{
39bffca2	274	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	275	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	276
	277	k->init = vt82c686b_ac97_initfn;
	278	k->vendor_id = PCI_VENDOR_ID_VIA;
	279	k->device_id = PCI_DEVICE_ID_VIA_AC97;
	280	k->revision = 0x50;
	281	k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
39bffca2	282	dc->desc = "AC97";
40021f08 AL	283	}
40021f08 AL	284
8c43a6f0	285	static const TypeInfo via_ac97_info = {
39bffca2 AL	286	.name = "VT82C686B_AC97",
	287	.parent = TYPE_PCI_DEVICE,
	288	.instance_size = sizeof(VT686AC97State),
	289	.class_init = via_ac97_class_init,
edf79e66 HC	290	};
edf79e66 HC	291
edf79e66 HC	292	static int vt82c686b_mc97_initfn(PCIDevice *dev)
	293	{
	294	VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
	295	uint8_t *pci_conf = s->dev.config;
	296
edf79e66 HC	297	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE \|
	298	PCI_COMMAND_VGA_PALETTE);
	299	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
	300	pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
	301
	302	return 0;
	303	}
	304
	305	void vt82c686b_mc97_init(PCIBus *bus, int devfn)
	306	{
	307	PCIDevice *dev;
	308
	309	dev = pci_create(bus, devfn, "VT82C686B_MC97");
	310	qdev_init_nofail(&dev->qdev);
	311	}
	312
40021f08 AL	313	static void via_mc97_class_init(ObjectClass klass, void data)
40021f08 AL	314	{
39bffca2	315	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	316	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	317
	318	k->init = vt82c686b_mc97_initfn;
	319	k->vendor_id = PCI_VENDOR_ID_VIA;
	320	k->device_id = PCI_DEVICE_ID_VIA_MC97;
	321	k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
	322	k->revision = 0x30;
39bffca2	323	dc->desc = "MC97";
40021f08 AL	324	}
40021f08 AL	325
8c43a6f0	326	static const TypeInfo via_mc97_info = {
39bffca2 AL	327	.name = "VT82C686B_MC97",
	328	.parent = TYPE_PCI_DEVICE,
	329	.instance_size = sizeof(VT686MC97State),
	330	.class_init = via_mc97_class_init,
edf79e66 HC	331	};
edf79e66 HC	332
edf79e66 HC	333	/* vt82c686 pm init */
	334	static int vt82c686b_pm_initfn(PCIDevice *dev)
	335	{
	336	VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
	337	uint8_t *pci_conf;
	338
	339	pci_conf = s->dev.config;
edf79e66 HC	340	pci_set_word(pci_conf + PCI_COMMAND, 0);
	341	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK \|
	342	PCI_STATUS_DEVSEL_MEDIUM);
	343
	344	/* 0x48-0x4B is Power Management I/O Base */
	345	pci_set_long(pci_conf + 0x48, 0x00000001);
	346
	347	/* SMB ports:0xeee0~0xeeef */
	348	s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
	349	pci_conf[0x90] = s->smb_io_base \| 1;
	350	pci_conf[0x91] = s->smb_io_base >> 8;
	351	pci_conf[0xd2] = 0x90;
798512e5 GH	352	pm_smbus_init(&s->dev.qdev, &s->smb);
798512e5 GH	353	memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
edf79e66	354
42d8a3cf	355	apm_init(dev, &s->apm, NULL, s);
edf79e66	356
a0f95659	357	memory_region_init(&s->io, "vt82c686-pm", 64);
a2902821 GH	358	memory_region_set_enabled(&s->io, false);
a2902821 GH	359	memory_region_add_subregion(get_system_io(), 0, &s->io);
edf79e66	360
77d58b1e	361	acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
b5a7c024	362	acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
560e6396	363	acpi_pm1_cnt_init(&s->ar, &s->io, 2);
edf79e66 HC	364
	365	return 0;
	366	}
	367
	368	i2c_bus vt82c686b_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
	369	qemu_irq sci_irq)
	370	{
	371	PCIDevice *dev;
	372	VT686PMState *s;
	373
	374	dev = pci_create(bus, devfn, "VT82C686B_PM");
	375	qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
	376
	377	s = DO_UPCAST(VT686PMState, dev, dev);
	378
	379	qdev_init_nofail(&dev->qdev);
	380
	381	return s->smb.smbus;
	382	}
	383
40021f08 AL	384	static Property via_pm_properties[] = {
	385	DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
	386	DEFINE_PROP_END_OF_LIST(),
	387	};
	388
	389	static void via_pm_class_init(ObjectClass klass, void data)
	390	{
39bffca2	391	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	392	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	393
	394	k->init = vt82c686b_pm_initfn;
	395	k->config_write = pm_write_config;
	396	k->vendor_id = PCI_VENDOR_ID_VIA;
	397	k->device_id = PCI_DEVICE_ID_VIA_ACPI;
	398	k->class_id = PCI_CLASS_BRIDGE_OTHER;
	399	k->revision = 0x40;
39bffca2 AL	400	dc->desc = "PM";
	401	dc->vmsd = &vmstate_acpi;
	402	dc->props = via_pm_properties;
40021f08 AL	403	}
40021f08 AL	404
8c43a6f0	405	static const TypeInfo via_pm_info = {
39bffca2 AL	406	.name = "VT82C686B_PM",
	407	.parent = TYPE_PCI_DEVICE,
	408	.instance_size = sizeof(VT686PMState),
	409	.class_init = via_pm_class_init,
edf79e66 HC	410	};
edf79e66 HC	411
edf79e66 HC	412	static const VMStateDescription vmstate_via = {
	413	.name = "vt82c686b",
	414	.version_id = 1,
	415	.minimum_version_id = 1,
	416	.minimum_version_id_old = 1,
	417	.fields = (VMStateField []) {
	418	VMSTATE_PCI_DEVICE(dev, VT82C686BState),
	419	VMSTATE_END_OF_LIST()
	420	}
	421	};
	422
	423	/* init the PCI-to-ISA bridge */
	424	static int vt82c686b_initfn(PCIDevice *d)
	425	{
	426	uint8_t *pci_conf;
	427	uint8_t *wmask;
	428	int i;
	429
c2d0d012	430	isa_bus_new(&d->qdev, pci_address_space_io(d));
edf79e66 HC	431
edf79e66 HC	432	pci_conf = d->config;
edf79e66	433	pci_config_set_prog_interface(pci_conf, 0x0);
edf79e66 HC	434
	435	wmask = d->wmask;
	436	for (i = 0x00; i < 0xff; i++) {
	437	if (i<=0x03 \|\| (i>=0x08 && i<=0x3f)) {
	438	wmask[i] = 0x00;
	439	}
	440	}
	441
	442	qemu_register_reset(vt82c686b_reset, d);
	443
	444	return 0;
	445	}
	446
c9940edb	447	ISABus vt82c686b_init(PCIBus bus, int devfn)
edf79e66 HC	448	{
	449	PCIDevice *d;
	450
aa5fb7b3	451	d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
edf79e66	452
c9940edb	453	return DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&d->qdev, "isa.0"));
edf79e66 HC	454	}
edf79e66 HC	455
40021f08 AL	456	static void via_class_init(ObjectClass klass, void data)
40021f08 AL	457	{
39bffca2	458	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	459	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	460
	461	k->init = vt82c686b_initfn;
	462	k->config_write = vt82c686b_write_config;
	463	k->vendor_id = PCI_VENDOR_ID_VIA;
	464	k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
	465	k->class_id = PCI_CLASS_BRIDGE_ISA;
	466	k->revision = 0x40;
39bffca2 AL	467	dc->desc = "ISA bridge";
	468	dc->no_user = 1;
	469	dc->vmsd = &vmstate_via;
40021f08 AL	470	}
40021f08 AL	471
8c43a6f0	472	static const TypeInfo via_info = {
39bffca2 AL	473	.name = "VT82C686B",
	474	.parent = TYPE_PCI_DEVICE,
	475	.instance_size = sizeof(VT82C686BState),
	476	.class_init = via_class_init,
edf79e66 HC	477	};
edf79e66 HC	478
83f7d43a	479	static void vt82c686b_register_types(void)
edf79e66	480	{
83f7d43a AF	481	type_register_static(&via_ac97_info);
	482	type_register_static(&via_mc97_info);
	483	type_register_static(&via_pm_info);
39bffca2	484	type_register_static(&via_info);
edf79e66	485	}
83f7d43a AF	486
83f7d43a AF	487	type_init(vt82c686b_register_types)