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use direct jump only for jumps in the same page - stop translation after mtsr[in]
[thirdparty/qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
3475187d
FB		 28 Optional alignment check
29 128-bit float
30 Tagged add/sub
bd497938 31*/
7a3f1944
FB		 32
33#include <stdarg.h>
34#include <stdlib.h>
35#include <stdio.h>
36#include <string.h>
37#include <inttypes.h>
38
39#include "cpu.h"
40#include "exec-all.h"
41#include "disas.h"
42
43#define DEBUG_DISAS
44
72cbca10
FB		 45#define DYNAMIC_PC 1 /* dynamic pc value */
46#define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
48
7a3f1944 49typedef struct DisasContext {
72cbca10
FB		 50 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 53 int is_br;
e8af50a3 54 int mem_idx;
cf495bcf 55 struct TranslationBlock *tb;
7a3f1944
FB		 56} DisasContext;
57
58static uint16_t *gen_opc_ptr;
59static uint32_t *gen_opparam_ptr;
60extern FILE *logfile;
61extern int loglevel;
62
63enum {
64#define DEF(s,n,copy_size) INDEX_op_ ## s,
65#include "opc.h"
66#undef DEF
cf495bcf 67 NB_OPS
7a3f1944
FB		 68};
69
70#include "gen-op.h"
71
3475187d 72// This function uses non-native bit order
7a3f1944
FB		 73#define GET_FIELD(X, FROM, TO) \
74 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
75
3475187d
FB		 76// This function uses the order in the manuals, i.e. bit 0 is 2^0
77#define GET_FIELD_SP(X, FROM, TO) \
78 GET_FIELD(X, 31 - (TO), 31 - (FROM))
79
80#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
81#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
82
83#ifdef TARGET_SPARC64
84#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
85#else
86#define DFPREG(r) (r)
87#endif
88
83469015
FB		 89#ifdef USE_DIRECT_JUMP
90#define TBPARAM(x)
91#else
92#define TBPARAM(x) (long)(x)
93#endif
94
3475187d
FB		 95static int sign_extend(int x, int len)
96{
97 len = 32 - len;
98 return (x << len) >> len;
99}
100
7a3f1944
FB		 101#define IS_IMM (insn & (1<<13))
102
cf495bcf 103static void disas_sparc_insn(DisasContext * dc);
7a3f1944 104
7a3f1944 105static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
cf495bcf
FB		 106 {
107 gen_op_movl_g0_T0,
108 gen_op_movl_g1_T0,
109 gen_op_movl_g2_T0,
110 gen_op_movl_g3_T0,
111 gen_op_movl_g4_T0,
112 gen_op_movl_g5_T0,
113 gen_op_movl_g6_T0,
114 gen_op_movl_g7_T0,
115 gen_op_movl_o0_T0,
116 gen_op_movl_o1_T0,
117 gen_op_movl_o2_T0,
118 gen_op_movl_o3_T0,
119 gen_op_movl_o4_T0,
120 gen_op_movl_o5_T0,
121 gen_op_movl_o6_T0,
122 gen_op_movl_o7_T0,
123 gen_op_movl_l0_T0,
124 gen_op_movl_l1_T0,
125 gen_op_movl_l2_T0,
126 gen_op_movl_l3_T0,
127 gen_op_movl_l4_T0,
128 gen_op_movl_l5_T0,
129 gen_op_movl_l6_T0,
130 gen_op_movl_l7_T0,
131 gen_op_movl_i0_T0,
132 gen_op_movl_i1_T0,
133 gen_op_movl_i2_T0,
134 gen_op_movl_i3_T0,
135 gen_op_movl_i4_T0,
136 gen_op_movl_i5_T0,
137 gen_op_movl_i6_T0,
138 gen_op_movl_i7_T0,
139 },
140 {
141 gen_op_movl_g0_T1,
142 gen_op_movl_g1_T1,
143 gen_op_movl_g2_T1,
144 gen_op_movl_g3_T1,
145 gen_op_movl_g4_T1,
146 gen_op_movl_g5_T1,
147 gen_op_movl_g6_T1,
148 gen_op_movl_g7_T1,
149 gen_op_movl_o0_T1,
150 gen_op_movl_o1_T1,
151 gen_op_movl_o2_T1,
152 gen_op_movl_o3_T1,
153 gen_op_movl_o4_T1,
154 gen_op_movl_o5_T1,
155 gen_op_movl_o6_T1,
156 gen_op_movl_o7_T1,
157 gen_op_movl_l0_T1,
158 gen_op_movl_l1_T1,
159 gen_op_movl_l2_T1,
160 gen_op_movl_l3_T1,
161 gen_op_movl_l4_T1,
162 gen_op_movl_l5_T1,
163 gen_op_movl_l6_T1,
164 gen_op_movl_l7_T1,
165 gen_op_movl_i0_T1,
166 gen_op_movl_i1_T1,
167 gen_op_movl_i2_T1,
168 gen_op_movl_i3_T1,
169 gen_op_movl_i4_T1,
170 gen_op_movl_i5_T1,
171 gen_op_movl_i6_T1,
172 gen_op_movl_i7_T1,
173 }
7a3f1944
FB		 174};
175
176static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
cf495bcf
FB		 177 {
178 gen_op_movl_T0_g0,
179 gen_op_movl_T0_g1,
180 gen_op_movl_T0_g2,
181 gen_op_movl_T0_g3,
182 gen_op_movl_T0_g4,
183 gen_op_movl_T0_g5,
184 gen_op_movl_T0_g6,
185 gen_op_movl_T0_g7,
186 gen_op_movl_T0_o0,
187 gen_op_movl_T0_o1,
188 gen_op_movl_T0_o2,
189 gen_op_movl_T0_o3,
190 gen_op_movl_T0_o4,
191 gen_op_movl_T0_o5,
192 gen_op_movl_T0_o6,
193 gen_op_movl_T0_o7,
194 gen_op_movl_T0_l0,
195 gen_op_movl_T0_l1,
196 gen_op_movl_T0_l2,
197 gen_op_movl_T0_l3,
198 gen_op_movl_T0_l4,
199 gen_op_movl_T0_l5,
200 gen_op_movl_T0_l6,
201 gen_op_movl_T0_l7,
202 gen_op_movl_T0_i0,
203 gen_op_movl_T0_i1,
204 gen_op_movl_T0_i2,
205 gen_op_movl_T0_i3,
206 gen_op_movl_T0_i4,
207 gen_op_movl_T0_i5,
208 gen_op_movl_T0_i6,
209 gen_op_movl_T0_i7,
210 },
211 {
212 gen_op_movl_T1_g0,
213 gen_op_movl_T1_g1,
214 gen_op_movl_T1_g2,
215 gen_op_movl_T1_g3,
216 gen_op_movl_T1_g4,
217 gen_op_movl_T1_g5,
218 gen_op_movl_T1_g6,
219 gen_op_movl_T1_g7,
220 gen_op_movl_T1_o0,
221 gen_op_movl_T1_o1,
222 gen_op_movl_T1_o2,
223 gen_op_movl_T1_o3,
224 gen_op_movl_T1_o4,
225 gen_op_movl_T1_o5,
226 gen_op_movl_T1_o6,
227 gen_op_movl_T1_o7,
228 gen_op_movl_T1_l0,
229 gen_op_movl_T1_l1,
230 gen_op_movl_T1_l2,
231 gen_op_movl_T1_l3,
232 gen_op_movl_T1_l4,
233 gen_op_movl_T1_l5,
234 gen_op_movl_T1_l6,
235 gen_op_movl_T1_l7,
236 gen_op_movl_T1_i0,
237 gen_op_movl_T1_i1,
238 gen_op_movl_T1_i2,
239 gen_op_movl_T1_i3,
240 gen_op_movl_T1_i4,
241 gen_op_movl_T1_i5,
242 gen_op_movl_T1_i6,
243 gen_op_movl_T1_i7,
244 },
245 {
246 gen_op_movl_T2_g0,
247 gen_op_movl_T2_g1,
248 gen_op_movl_T2_g2,
249 gen_op_movl_T2_g3,
250 gen_op_movl_T2_g4,
251 gen_op_movl_T2_g5,
252 gen_op_movl_T2_g6,
253 gen_op_movl_T2_g7,
254 gen_op_movl_T2_o0,
255 gen_op_movl_T2_o1,
256 gen_op_movl_T2_o2,
257 gen_op_movl_T2_o3,
258 gen_op_movl_T2_o4,
259 gen_op_movl_T2_o5,
260 gen_op_movl_T2_o6,
261 gen_op_movl_T2_o7,
262 gen_op_movl_T2_l0,
263 gen_op_movl_T2_l1,
264 gen_op_movl_T2_l2,
265 gen_op_movl_T2_l3,
266 gen_op_movl_T2_l4,
267 gen_op_movl_T2_l5,
268 gen_op_movl_T2_l6,
269 gen_op_movl_T2_l7,
270 gen_op_movl_T2_i0,
271 gen_op_movl_T2_i1,
272 gen_op_movl_T2_i2,
273 gen_op_movl_T2_i3,
274 gen_op_movl_T2_i4,
275 gen_op_movl_T2_i5,
276 gen_op_movl_T2_i6,
277 gen_op_movl_T2_i7,
278 }
7a3f1944
FB		 279};
280
281static GenOpFunc1 *gen_op_movl_TN_im[3] = {
cf495bcf
FB		 282 gen_op_movl_T0_im,
283 gen_op_movl_T1_im,
284 gen_op_movl_T2_im
7a3f1944
FB		 285};
286
3475187d
FB		 287// Sign extending version
288static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
289 gen_op_movl_T0_sim,
290 gen_op_movl_T1_sim,
291 gen_op_movl_T2_sim
292};
293
294#ifdef TARGET_SPARC64
295#define GEN32(func, NAME) \
296static GenOpFunc *NAME ## _table [64] = { \
297NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
298NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
299NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
300NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
301NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
302NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
303NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
304NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
305NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
306NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
307NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
308NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
309}; \
310static inline void func(int n) \
311{ \
312 NAME ## _table[n](); \
313}
314#else
e8af50a3
FB		 315#define GEN32(func, NAME) \
316static GenOpFunc *NAME ## _table [32] = { \
317NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
318NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
319NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
320NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
321NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
322NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
323NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
324NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
325}; \
326static inline void func(int n) \
327{ \
328 NAME ## _table[n](); \
329}
3475187d 330#endif
e8af50a3
FB		 331
332/* floating point registers moves */
333GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
334GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
e8af50a3
FB		 335GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
336GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
e8af50a3
FB		 337
338GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
339GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
e8af50a3
FB		 340GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
341GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 342
3475187d
FB		 343#ifdef TARGET_SPARC64
344// 'a' versions allowed to user depending on asi
345#if defined(CONFIG_USER_ONLY)
346#define supervisor(dc) 0
347#define gen_op_ldst(name) gen_op_##name##_raw()
348#define OP_LD_TABLE(width) \
349 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
350 { \
351 int asi, offset; \
352 \
353 if (IS_IMM) { \
354 offset = GET_FIELD(insn, 25, 31); \
355 if (is_ld) \
356 gen_op_ld_asi_reg(offset, size, sign); \
357 else \
358 gen_op_st_asi_reg(offset, size, sign); \
359 return; \
360 } \
361 asi = GET_FIELD(insn, 19, 26); \
362 switch (asi) { \
363 case 0x80: /* Primary address space */ \
364 gen_op_##width##_raw(); \
365 break; \
366 default: \
367 break; \
368 } \
369 }
370
371#else
372#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
373#define OP_LD_TABLE(width) \
374 static GenOpFunc *gen_op_##width[] = { \
375 &gen_op_##width##_user, \
376 &gen_op_##width##_kernel, \
377 }; \
378 \
379 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
380 { \
381 int asi, offset; \
382 \
383 if (IS_IMM) { \
384 offset = GET_FIELD(insn, 25, 31); \
385 if (is_ld) \
386 gen_op_ld_asi_reg(offset, size, sign); \
387 else \
388 gen_op_st_asi_reg(offset, size, sign); \
389 return; \
390 } \
391 asi = GET_FIELD(insn, 19, 26); \
392 if (is_ld) \
393 gen_op_ld_asi(asi, size, sign); \
394 else \
395 gen_op_st_asi(asi, size, sign); \
396 }
397
398#define supervisor(dc) (dc->mem_idx == 1)
399#endif
400#else
e8af50a3
FB		 401#if defined(CONFIG_USER_ONLY)
402#define gen_op_ldst(name) gen_op_##name##_raw()
0fa85d43 403#define OP_LD_TABLE(width)
e8af50a3
FB		 404#define supervisor(dc) 0
405#else
406#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
407#define OP_LD_TABLE(width) \
408static GenOpFunc *gen_op_##width[] = { \
409 &gen_op_##width##_user, \
410 &gen_op_##width##_kernel, \
411}; \
412 \
413static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
414{ \
415 int asi; \
416 \
417 asi = GET_FIELD(insn, 19, 26); \
418 switch (asi) { \
419 case 10: /* User data access */ \
420 gen_op_##width##_user(); \
421 break; \
422 case 11: /* Supervisor data access */ \
423 gen_op_##width##_kernel(); \
424 break; \
425 case 0x20 ... 0x2f: /* MMU passthrough */ \
426 if (is_ld) \
427 gen_op_ld_asi(asi, size, sign); \
428 else \
429 gen_op_st_asi(asi, size, sign); \
430 break; \
431 default: \
432 if (is_ld) \
433 gen_op_ld_asi(asi, size, sign); \
434 else \
435 gen_op_st_asi(asi, size, sign); \
436 break; \
437 } \
438}
439
440#define supervisor(dc) (dc->mem_idx == 1)
441#endif
3475187d 442#endif
e8af50a3
FB		 443
444OP_LD_TABLE(ld);
445OP_LD_TABLE(st);
446OP_LD_TABLE(ldub);
447OP_LD_TABLE(lduh);
448OP_LD_TABLE(ldsb);
449OP_LD_TABLE(ldsh);
450OP_LD_TABLE(stb);
451OP_LD_TABLE(sth);
452OP_LD_TABLE(std);
453OP_LD_TABLE(ldstub);
454OP_LD_TABLE(swap);
455OP_LD_TABLE(ldd);
456OP_LD_TABLE(stf);
457OP_LD_TABLE(stdf);
458OP_LD_TABLE(ldf);
459OP_LD_TABLE(lddf);
460
3475187d
FB		 461#ifdef TARGET_SPARC64
462OP_LD_TABLE(ldsw);
463OP_LD_TABLE(ldx);
464OP_LD_TABLE(stx);
465OP_LD_TABLE(cas);
466OP_LD_TABLE(casx);
467#endif
468
469static inline void gen_movl_imm_TN(int reg, uint32_t imm)
7a3f1944 470{
83469015 471 gen_op_movl_TN_im[reg](imm);
7a3f1944
FB		 472}
473
3475187d 474static inline void gen_movl_imm_T1(uint32_t val)
7a3f1944 475{
cf495bcf 476 gen_movl_imm_TN(1, val);
7a3f1944
FB		 477}
478
3475187d 479static inline void gen_movl_imm_T0(uint32_t val)
7a3f1944 480{
cf495bcf 481 gen_movl_imm_TN(0, val);
7a3f1944
FB		 482}
483
3475187d
FB		 484static inline void gen_movl_simm_TN(int reg, int32_t imm)
485{
486 gen_op_movl_TN_sim[reg](imm);
487}
488
489static inline void gen_movl_simm_T1(int32_t val)
490{
491 gen_movl_simm_TN(1, val);
492}
493
494static inline void gen_movl_simm_T0(int32_t val)
495{
496 gen_movl_simm_TN(0, val);
497}
498
cf495bcf 499static inline void gen_movl_reg_TN(int reg, int t)
7a3f1944 500{
cf495bcf
FB		 501 if (reg)
502 gen_op_movl_reg_TN[t][reg] ();
503 else
504 gen_movl_imm_TN(t, 0);
7a3f1944
FB		 505}
506
cf495bcf 507static inline void gen_movl_reg_T0(int reg)
7a3f1944 508{
cf495bcf 509 gen_movl_reg_TN(reg, 0);
7a3f1944
FB		 510}
511
cf495bcf 512static inline void gen_movl_reg_T1(int reg)
7a3f1944 513{
cf495bcf 514 gen_movl_reg_TN(reg, 1);
7a3f1944
FB		 515}
516
cf495bcf 517static inline void gen_movl_reg_T2(int reg)
7a3f1944 518{
cf495bcf 519 gen_movl_reg_TN(reg, 2);
7a3f1944
FB		 520}
521
cf495bcf 522static inline void gen_movl_TN_reg(int reg, int t)
7a3f1944 523{
cf495bcf
FB		 524 if (reg)
525 gen_op_movl_TN_reg[t][reg] ();
7a3f1944
FB		 526}
527
cf495bcf 528static inline void gen_movl_T0_reg(int reg)
7a3f1944 529{
cf495bcf 530 gen_movl_TN_reg(reg, 0);
7a3f1944
FB		 531}
532
cf495bcf 533static inline void gen_movl_T1_reg(int reg)
7a3f1944 534{
cf495bcf 535 gen_movl_TN_reg(reg, 1);
7a3f1944
FB		 536}
537
3475187d
FB		 538static inline void gen_jmp_im(target_ulong pc)
539{
540#ifdef TARGET_SPARC64
541 if (pc == (uint32_t)pc) {
542 gen_op_jmp_im(pc);
543 } else {
544 gen_op_jmp_im64(pc >> 32, pc);
545 }
546#else
547 gen_op_jmp_im(pc);
548#endif
549}
550
551static inline void gen_movl_npc_im(target_ulong npc)
552{
553#ifdef TARGET_SPARC64
554 if (npc == (uint32_t)npc) {
555 gen_op_movl_npc_im(npc);
556 } else {
557 gen_op_movq_npc_im64(npc >> 32, npc);
558 }
559#else
560 gen_op_movl_npc_im(npc);
561#endif
562}
563
83469015
FB		 564static inline void gen_branch2(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
565{
566 int l1;
567
568 l1 = gen_new_label();
569
570 gen_op_jz_T2_label(l1);
571
572 gen_op_goto_tb0(TBPARAM(tb));
573 gen_jmp_im(pc1);
574 gen_movl_npc_im(pc1 + 4);
575 gen_op_movl_T0_im((long)tb + 0);
576 gen_op_exit_tb();
577
578 gen_set_label(l1);
579 gen_op_goto_tb1(TBPARAM(tb));
580 gen_jmp_im(pc2);
581 gen_movl_npc_im(pc2 + 4);
582 gen_op_movl_T0_im((long)tb + 1);
583 gen_op_exit_tb();
584}
585
586static inline void gen_branch_a(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
587{
588 int l1;
589
590 l1 = gen_new_label();
591
592 gen_op_jz_T2_label(l1);
593
594 gen_op_goto_tb0(TBPARAM(tb));
595 gen_jmp_im(pc2);
596 gen_movl_npc_im(pc1);
597 gen_op_movl_T0_im((long)tb + 0);
598 gen_op_exit_tb();
599
600 gen_set_label(l1);
601 gen_op_goto_tb1(TBPARAM(tb));
602 gen_jmp_im(pc2 + 4);
603 gen_movl_npc_im(pc2 + 8);
604 gen_op_movl_T0_im((long)tb + 1);
605 gen_op_exit_tb();
606}
607
608static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
609{
610 gen_op_goto_tb0(TBPARAM(tb));
611 gen_jmp_im(pc);
612 gen_movl_npc_im(npc);
613 gen_op_movl_T0_im((long)tb + 0);
614 gen_op_exit_tb();
615}
616
617static inline void gen_generic_branch(DisasContext *dc, target_ulong npc1, target_ulong npc2)
618{
619 int l1, l2;
620
621 l1 = gen_new_label();
622 l2 = gen_new_label();
623 gen_op_jz_T2_label(l1);
624
625 gen_movl_npc_im(npc1);
626 gen_op_jmp_label(l2);
627
628 gen_set_label(l1);
629 gen_movl_npc_im(npc2);
630 gen_set_label(l2);
631}
632
633/* call this function before using T2 as it may have been set for a jump */
634static inline void flush_T2(DisasContext * dc)
635{
636 if (dc->npc == JUMP_PC) {
637 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
638 dc->npc = DYNAMIC_PC;
639 }
640}
641
72cbca10
FB		 642static inline void save_npc(DisasContext * dc)
643{
644 if (dc->npc == JUMP_PC) {
83469015 645 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 646 dc->npc = DYNAMIC_PC;
647 } else if (dc->npc != DYNAMIC_PC) {
3475187d 648 gen_movl_npc_im(dc->npc);
72cbca10
FB		 649 }
650}
651
652static inline void save_state(DisasContext * dc)
653{
3475187d 654 gen_jmp_im(dc->pc);
72cbca10
FB		 655 save_npc(dc);
656}
657
0bee699e
FB		 658static inline void gen_mov_pc_npc(DisasContext * dc)
659{
660 if (dc->npc == JUMP_PC) {
83469015 661 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
0bee699e
FB		 662 gen_op_mov_pc_npc();
663 dc->pc = DYNAMIC_PC;
664 } else if (dc->npc == DYNAMIC_PC) {
665 gen_op_mov_pc_npc();
666 dc->pc = DYNAMIC_PC;
667 } else {
668 dc->pc = dc->npc;
669 }
670}
671
3475187d
FB		 672static GenOpFunc * const gen_cond[2][16] = {
673 {
674 gen_op_eval_ba,
675 gen_op_eval_be,
676 gen_op_eval_ble,
677 gen_op_eval_bl,
678 gen_op_eval_bleu,
679 gen_op_eval_bcs,
680 gen_op_eval_bneg,
681 gen_op_eval_bvs,
682 gen_op_eval_bn,
683 gen_op_eval_bne,
684 gen_op_eval_bg,
685 gen_op_eval_bge,
686 gen_op_eval_bgu,
687 gen_op_eval_bcc,
688 gen_op_eval_bpos,
689 gen_op_eval_bvc,
690 },
691 {
692#ifdef TARGET_SPARC64
693 gen_op_eval_ba,
694 gen_op_eval_xbe,
695 gen_op_eval_xble,
696 gen_op_eval_xbl,
697 gen_op_eval_xbleu,
698 gen_op_eval_xbcs,
699 gen_op_eval_xbneg,
700 gen_op_eval_xbvs,
701 gen_op_eval_bn,
702 gen_op_eval_xbne,
703 gen_op_eval_xbg,
704 gen_op_eval_xbge,
705 gen_op_eval_xbgu,
706 gen_op_eval_xbcc,
707 gen_op_eval_xbpos,
708 gen_op_eval_xbvc,
709#endif
710 },
711};
712
713static GenOpFunc * const gen_fcond[4][16] = {
714 {
715 gen_op_eval_ba,
716 gen_op_eval_fbne,
717 gen_op_eval_fblg,
718 gen_op_eval_fbul,
719 gen_op_eval_fbl,
720 gen_op_eval_fbug,
721 gen_op_eval_fbg,
722 gen_op_eval_fbu,
723 gen_op_eval_bn,
724 gen_op_eval_fbe,
725 gen_op_eval_fbue,
726 gen_op_eval_fbge,
727 gen_op_eval_fbuge,
728 gen_op_eval_fble,
729 gen_op_eval_fbule,
730 gen_op_eval_fbo,
731 },
732#ifdef TARGET_SPARC64
733 {
734 gen_op_eval_ba,
735 gen_op_eval_fbne_fcc1,
736 gen_op_eval_fblg_fcc1,
737 gen_op_eval_fbul_fcc1,
738 gen_op_eval_fbl_fcc1,
739 gen_op_eval_fbug_fcc1,
740 gen_op_eval_fbg_fcc1,
741 gen_op_eval_fbu_fcc1,
742 gen_op_eval_bn,
743 gen_op_eval_fbe_fcc1,
744 gen_op_eval_fbue_fcc1,
745 gen_op_eval_fbge_fcc1,
746 gen_op_eval_fbuge_fcc1,
747 gen_op_eval_fble_fcc1,
748 gen_op_eval_fbule_fcc1,
749 gen_op_eval_fbo_fcc1,
750 },
751 {
752 gen_op_eval_ba,
753 gen_op_eval_fbne_fcc2,
754 gen_op_eval_fblg_fcc2,
755 gen_op_eval_fbul_fcc2,
756 gen_op_eval_fbl_fcc2,
757 gen_op_eval_fbug_fcc2,
758 gen_op_eval_fbg_fcc2,
759 gen_op_eval_fbu_fcc2,
760 gen_op_eval_bn,
761 gen_op_eval_fbe_fcc2,
762 gen_op_eval_fbue_fcc2,
763 gen_op_eval_fbge_fcc2,
764 gen_op_eval_fbuge_fcc2,
765 gen_op_eval_fble_fcc2,
766 gen_op_eval_fbule_fcc2,
767 gen_op_eval_fbo_fcc2,
768 },
769 {
770 gen_op_eval_ba,
771 gen_op_eval_fbne_fcc3,
772 gen_op_eval_fblg_fcc3,
773 gen_op_eval_fbul_fcc3,
774 gen_op_eval_fbl_fcc3,
775 gen_op_eval_fbug_fcc3,
776 gen_op_eval_fbg_fcc3,
777 gen_op_eval_fbu_fcc3,
778 gen_op_eval_bn,
779 gen_op_eval_fbe_fcc3,
780 gen_op_eval_fbue_fcc3,
781 gen_op_eval_fbge_fcc3,
782 gen_op_eval_fbuge_fcc3,
783 gen_op_eval_fble_fcc3,
784 gen_op_eval_fbule_fcc3,
785 gen_op_eval_fbo_fcc3,
786 },
787#else
788 {}, {}, {},
789#endif
790};
7a3f1944 791
3475187d
FB		 792#ifdef TARGET_SPARC64
793static void gen_cond_reg(int cond)
e8af50a3
FB		 794{
795 switch (cond) {
e8af50a3 796 case 0x1:
3475187d 797 gen_op_eval_brz();
e8af50a3
FB		 798 break;
799 case 0x2:
3475187d 800 gen_op_eval_brlez();
e8af50a3
FB		 801 break;
802 case 0x3:
3475187d 803 gen_op_eval_brlz();
e8af50a3
FB		 804 break;
805 case 0x5:
3475187d 806 gen_op_eval_brnz();
e8af50a3
FB		 807 break;
808 case 0x6:
3475187d 809 gen_op_eval_brgz();
e8af50a3
FB		 810 break;
811 default:
3475187d
FB		 812 case 0x7:
813 gen_op_eval_brgez();
e8af50a3
FB		 814 break;
815 }
816}
3475187d 817#endif
cf495bcf 818
0bee699e 819/* XXX: potentially incorrect if dynamic npc */
3475187d 820static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 821{
cf495bcf 822 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 823 target_ulong target = dc->pc + offset;
3475187d 824
cf495bcf
FB		 825 if (cond == 0x0) {
826 /* unconditional not taken */
827 if (a) {
0bee699e 828 dc->pc = dc->npc + 4;
cf495bcf
FB		 829 dc->npc = dc->pc + 4;
830 } else {
831 dc->pc = dc->npc;
832 dc->npc = dc->pc + 4;
833 }
834 } else if (cond == 0x8) {
835 /* unconditional taken */
836 if (a) {
72cbca10 837 dc->pc = target;
cf495bcf
FB		 838 dc->npc = dc->pc + 4;
839 } else {
840 dc->pc = dc->npc;
72cbca10 841 dc->npc = target;
cf495bcf
FB		 842 }
843 } else {
72cbca10 844 flush_T2(dc);
3475187d 845 gen_cond[cc][cond]();
cf495bcf 846 if (a) {
83469015 847 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
cf495bcf 848 dc->is_br = 1;
cf495bcf
FB		 849 } else {
850 dc->pc = dc->npc;
72cbca10
FB		 851 dc->jump_pc[0] = target;
852 dc->jump_pc[1] = dc->npc + 4;
853 dc->npc = JUMP_PC;
cf495bcf
FB		 854 }
855 }
7a3f1944
FB		 856}
857
0bee699e 858/* XXX: potentially incorrect if dynamic npc */
3475187d 859static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 860{
861 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 862 target_ulong target = dc->pc + offset;
863
e8af50a3
FB		 864 if (cond == 0x0) {
865 /* unconditional not taken */
866 if (a) {
867 dc->pc = dc->npc + 4;
868 dc->npc = dc->pc + 4;
869 } else {
870 dc->pc = dc->npc;
871 dc->npc = dc->pc + 4;
872 }
873 } else if (cond == 0x8) {
874 /* unconditional taken */
875 if (a) {
876 dc->pc = target;
877 dc->npc = dc->pc + 4;
878 } else {
879 dc->pc = dc->npc;
880 dc->npc = target;
881 }
882 } else {
883 flush_T2(dc);
3475187d 884 gen_fcond[cc][cond]();
e8af50a3 885 if (a) {
83469015 886 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
e8af50a3
FB		 887 dc->is_br = 1;
888 } else {
889 dc->pc = dc->npc;
890 dc->jump_pc[0] = target;
891 dc->jump_pc[1] = dc->npc + 4;
892 dc->npc = JUMP_PC;
893 }
894 }
895}
896
3475187d
FB		 897#ifdef TARGET_SPARC64
898/* XXX: potentially incorrect if dynamic npc */
899static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 900{
3475187d
FB		 901 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
902 target_ulong target = dc->pc + offset;
903
904 flush_T2(dc);
905 gen_cond_reg(cond);
906 if (a) {
83469015 907 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
3475187d
FB		 908 dc->is_br = 1;
909 } else {
910 dc->pc = dc->npc;
911 dc->jump_pc[0] = target;
912 dc->jump_pc[1] = dc->npc + 4;
913 dc->npc = JUMP_PC;
914 }
7a3f1944
FB		 915}
916
3475187d
FB		 917static GenOpFunc * const gen_fcmps[4] = {
918 gen_op_fcmps,
919 gen_op_fcmps_fcc1,
920 gen_op_fcmps_fcc2,
921 gen_op_fcmps_fcc3,
922};
923
924static GenOpFunc * const gen_fcmpd[4] = {
925 gen_op_fcmpd,
926 gen_op_fcmpd_fcc1,
927 gen_op_fcmpd_fcc2,
928 gen_op_fcmpd_fcc3,
929};
930#endif
931
0bee699e 932/* before an instruction, dc->pc must be static */
cf495bcf
FB		 933static void disas_sparc_insn(DisasContext * dc)
934{
935 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 936
0fa85d43 937 insn = ldl_code(dc->pc);
cf495bcf 938 opc = GET_FIELD(insn, 0, 1);
7a3f1944 939
cf495bcf
FB		 940 rd = GET_FIELD(insn, 2, 6);
941 switch (opc) {
942 case 0: /* branches/sethi */
943 {
944 unsigned int xop = GET_FIELD(insn, 7, 9);
af7bf89b 945 int32_t target;
cf495bcf 946 switch (xop) {
3475187d 947#ifdef TARGET_SPARC64
af7bf89b 948 case 0x1: /* V9 BPcc */
3475187d
FB		 949 {
950 int cc;
951
952 target = GET_FIELD_SP(insn, 0, 18);
953 target <<= 2;
954 target = sign_extend(target, 18);
955 cc = GET_FIELD_SP(insn, 20, 21);
956 if (cc == 0)
957 do_branch(dc, target, insn, 0);
958 else if (cc == 2)
959 do_branch(dc, target, insn, 1);
960 else
961 goto illegal_insn;
962 goto jmp_insn;
963 }
af7bf89b 964 case 0x3: /* V9 BPr */
3475187d
FB		 965 {
966 target = GET_FIELD_SP(insn, 0, 13) |
967 (GET_FIELD_SP(insn, 20, 21) >> 7);
968 target <<= 2;
969 target = sign_extend(target, 16);
970 rs1 = GET_FIELD(insn, 13, 17);
83469015 971 gen_movl_reg_T0(rs1);
3475187d
FB		 972 do_branch_reg(dc, target, insn);
973 goto jmp_insn;
974 }
af7bf89b 975 case 0x5: /* V9 FBPcc */
3475187d
FB		 976 {
977 int cc = GET_FIELD_SP(insn, 20, 21);
978#if !defined(CONFIG_USER_ONLY)
979 gen_op_trap_ifnofpu();
980#endif
981 target = GET_FIELD_SP(insn, 0, 18);
982 target <<= 2;
983 target = sign_extend(target, 19);
984 do_fbranch(dc, target, insn, cc);
985 goto jmp_insn;
986 }
987#endif
cf495bcf 988 case 0x2: /* BN+x */
7a3f1944 989 {
3475187d 990 target = GET_FIELD(insn, 10, 31);
cf495bcf
FB		 991 target <<= 2;
992 target = sign_extend(target, 22);
3475187d 993 do_branch(dc, target, insn, 0);
cf495bcf 994 goto jmp_insn;
7a3f1944 995 }
e8af50a3
FB		 996 case 0x6: /* FBN+x */
997 {
e80cfcfc
FB		 998#if !defined(CONFIG_USER_ONLY)
999 gen_op_trap_ifnofpu();
1000#endif
3475187d 1001 target = GET_FIELD(insn, 10, 31);
e8af50a3
FB		 1002 target <<= 2;
1003 target = sign_extend(target, 22);
3475187d 1004 do_fbranch(dc, target, insn, 0);
e8af50a3
FB		 1005 goto jmp_insn;
1006 }
cf495bcf 1007 case 0x4: /* SETHI */
e80cfcfc
FB		 1008#define OPTIM
1009#if defined(OPTIM)
1010 if (rd) { // nop
1011#endif
3475187d
FB		 1012 uint32_t value = GET_FIELD(insn, 10, 31);
1013 gen_movl_imm_T0(value << 10);
e80cfcfc
FB		 1014 gen_movl_T0_reg(rd);
1015#if defined(OPTIM)
1016 }
1017#endif
cf495bcf 1018 break;
3475187d
FB		 1019 case 0x0: /* UNIMPL */
1020 default:
1021 goto illegal_insn;
cf495bcf
FB		 1022 }
1023 break;
1024 }
af7bf89b 1025 break;
cf495bcf
FB		 1026 case 1:
1027 /*CALL*/ {
af7bf89b 1028 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1029
83469015
FB		 1030#ifdef TARGET_SPARC64
1031 if (dc->pc == (uint32_t)dc->pc) {
1032 gen_op_movl_T0_im(dc->pc);
1033 } else {
1034 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1035 }
1036#else
af7bf89b 1037 gen_op_movl_T0_im(dc->pc);
83469015 1038#endif
cf495bcf 1039 gen_movl_T0_reg(15);
af7bf89b 1040 target += dc->pc;
0bee699e 1041 gen_mov_pc_npc(dc);
72cbca10 1042 dc->npc = target;
cf495bcf
FB		 1043 }
1044 goto jmp_insn;
1045 case 2: /* FPU & Logical Operations */
1046 {
1047 unsigned int xop = GET_FIELD(insn, 7, 12);
1048 if (xop == 0x3a) { /* generate trap */
1049 int cond;
3475187d 1050
cf495bcf
FB		 1051 rs1 = GET_FIELD(insn, 13, 17);
1052 gen_movl_reg_T0(rs1);
1053 if (IS_IMM) {
e8af50a3 1054 rs2 = GET_FIELD(insn, 25, 31);
e80cfcfc 1055#if defined(OPTIM)
e8af50a3 1056 if (rs2 != 0) {
e80cfcfc 1057#endif
3475187d 1058 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1059 gen_op_add_T1_T0();
1060#if defined(OPTIM)
e8af50a3 1061 }
e80cfcfc 1062#endif
cf495bcf
FB		 1063 } else {
1064 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB		 1065#if defined(OPTIM)
1066 if (rs2 != 0) {
1067#endif
1068 gen_movl_reg_T1(rs2);
1069 gen_op_add_T1_T0();
1070#if defined(OPTIM)
1071 }
1072#endif
cf495bcf 1073 }
cf495bcf
FB		 1074 save_state(dc);
1075 cond = GET_FIELD(insn, 3, 6);
1076 if (cond == 0x8) {
1077 gen_op_trap_T0();
1078 dc->is_br = 1;
1079 goto jmp_insn;
af7bf89b 1080 } else if (cond != 0) {
3475187d
FB		 1081#ifdef TARGET_SPARC64
1082 /* V9 icc/xcc */
1083 int cc = GET_FIELD_SP(insn, 11, 12);
1084 if (cc == 0)
1085 gen_cond[0][cond]();
1086 else if (cc == 2)
1087 gen_cond[1][cond]();
1088 else
1089 goto illegal_insn;
1090#else
1091 gen_cond[0][cond]();
1092#endif
cf495bcf
FB		 1093 gen_op_trapcc_T0();
1094 }
1095 } else if (xop == 0x28) {
1096 rs1 = GET_FIELD(insn, 13, 17);
1097 switch(rs1) {
1098 case 0: /* rdy */
3475187d 1099 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB		 1100 gen_movl_T0_reg(rd);
1101 break;
af7bf89b 1102 case 15: /* stbar / V9 membar */
e8af50a3 1103 break; /* no effect? */
3475187d 1104#ifdef TARGET_SPARC64
af7bf89b 1105 case 0x2: /* V9 rdccr */
3475187d
FB		 1106 gen_op_rdccr();
1107 gen_movl_T0_reg(rd);
1108 break;
af7bf89b 1109 case 0x3: /* V9 rdasi */
3475187d
FB		 1110 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1111 gen_movl_T0_reg(rd);
1112 break;
af7bf89b 1113 case 0x4: /* V9 rdtick */
3475187d
FB		 1114 gen_op_rdtick();
1115 gen_movl_T0_reg(rd);
1116 break;
af7bf89b 1117 case 0x5: /* V9 rdpc */
3475187d
FB		 1118 gen_op_movl_T0_im(dc->pc);
1119 gen_movl_T0_reg(rd);
1120 break;
af7bf89b 1121 case 0x6: /* V9 rdfprs */
3475187d
FB		 1122 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1123 gen_movl_T0_reg(rd);
1124 break;
83469015
FB		 1125 case 0x17: /* Tick compare */
1126 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1127 gen_movl_T0_reg(rd);
1128 break;
1129 case 0x18: /* System tick */
1130 gen_op_rdtick(); // XXX
1131 gen_movl_T0_reg(rd);
1132 break;
1133 case 0x19: /* System tick compare */
1134 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1135 gen_movl_T0_reg(rd);
1136 break;
1137 case 0x10: /* Performance Control */
1138 case 0x11: /* Performance Instrumentation Counter */
1139 case 0x12: /* Dispatch Control */
1140 case 0x13: /* Graphics Status */
1141 case 0x14: /* Softint set, WO */
1142 case 0x15: /* Softint clear, WO */
1143 case 0x16: /* Softint write */
3475187d
FB		 1144#endif
1145 default:
cf495bcf
FB		 1146 goto illegal_insn;
1147 }
e8af50a3 1148#if !defined(CONFIG_USER_ONLY)
3475187d
FB		 1149#ifndef TARGET_SPARC64
1150 } else if (xop == 0x29) { /* rdpsr / V9 unimp */
e8af50a3
FB		 1151 if (!supervisor(dc))
1152 goto priv_insn;
1153 gen_op_rdpsr();
1154 gen_movl_T0_reg(rd);
1155 break;
3475187d
FB		 1156#endif
1157 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
e8af50a3
FB		 1158 if (!supervisor(dc))
1159 goto priv_insn;
3475187d
FB		 1160#ifdef TARGET_SPARC64
1161 rs1 = GET_FIELD(insn, 13, 17);
1162 switch (rs1) {
1163 case 0: // tpc
1164 gen_op_rdtpc();
1165 break;
1166 case 1: // tnpc
1167 gen_op_rdtnpc();
1168 break;
1169 case 2: // tstate
1170 gen_op_rdtstate();
1171 break;
1172 case 3: // tt
1173 gen_op_rdtt();
1174 break;
1175 case 4: // tick
1176 gen_op_rdtick();
1177 break;
1178 case 5: // tba
1179 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1180 break;
1181 case 6: // pstate
1182 gen_op_rdpstate();
1183 break;
1184 case 7: // tl
1185 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1186 break;
1187 case 8: // pil
1188 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1189 break;
1190 case 9: // cwp
1191 gen_op_rdcwp();
1192 break;
1193 case 10: // cansave
1194 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1195 break;
1196 case 11: // canrestore
1197 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1198 break;
1199 case 12: // cleanwin
1200 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1201 break;
1202 case 13: // otherwin
1203 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1204 break;
1205 case 14: // wstate
1206 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1207 break;
1208 case 31: // ver
1209 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1210 break;
1211 case 15: // fq
1212 default:
1213 goto illegal_insn;
1214 }
1215#else
1216 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1217#endif
e8af50a3
FB		 1218 gen_movl_T0_reg(rd);
1219 break;
3475187d
FB		 1220 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1221#ifdef TARGET_SPARC64
1222 gen_op_flushw();
1223#else
e8af50a3
FB		 1224 if (!supervisor(dc))
1225 goto priv_insn;
3475187d 1226 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 1227 gen_movl_T0_reg(rd);
3475187d 1228#endif
e8af50a3
FB		 1229 break;
1230#endif
e80cfcfc
FB		 1231 } else if (xop == 0x34) { /* FPU Operations */
1232#if !defined(CONFIG_USER_ONLY)
1233 gen_op_trap_ifnofpu();
1234#endif
e8af50a3
FB		 1235 rs1 = GET_FIELD(insn, 13, 17);
1236 rs2 = GET_FIELD(insn, 27, 31);
1237 xop = GET_FIELD(insn, 18, 26);
1238 switch (xop) {
1239 case 0x1: /* fmovs */
1240 gen_op_load_fpr_FT0(rs2);
1241 gen_op_store_FT0_fpr(rd);
1242 break;
1243 case 0x5: /* fnegs */
1244 gen_op_load_fpr_FT1(rs2);
1245 gen_op_fnegs();
1246 gen_op_store_FT0_fpr(rd);
1247 break;
1248 case 0x9: /* fabss */
1249 gen_op_load_fpr_FT1(rs2);
1250 gen_op_fabss();
1251 gen_op_store_FT0_fpr(rd);
1252 break;
1253 case 0x29: /* fsqrts */
1254 gen_op_load_fpr_FT1(rs2);
1255 gen_op_fsqrts();
1256 gen_op_store_FT0_fpr(rd);
1257 break;
1258 case 0x2a: /* fsqrtd */
3475187d 1259 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1260 gen_op_fsqrtd();
3475187d 1261 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1262 break;
e80cfcfc
FB		 1263 case 0x2b: /* fsqrtq */
1264 goto nfpu_insn;
e8af50a3
FB		 1265 case 0x41:
1266 gen_op_load_fpr_FT0(rs1);
1267 gen_op_load_fpr_FT1(rs2);
1268 gen_op_fadds();
1269 gen_op_store_FT0_fpr(rd);
1270 break;
1271 case 0x42:
3475187d
FB		 1272 gen_op_load_fpr_DT0(DFPREG(rs1));
1273 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1274 gen_op_faddd();
3475187d 1275 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1276 break;
e80cfcfc
FB		 1277 case 0x43: /* faddq */
1278 goto nfpu_insn;
e8af50a3
FB		 1279 case 0x45:
1280 gen_op_load_fpr_FT0(rs1);
1281 gen_op_load_fpr_FT1(rs2);
1282 gen_op_fsubs();
1283 gen_op_store_FT0_fpr(rd);
1284 break;
1285 case 0x46:
3475187d
FB		 1286 gen_op_load_fpr_DT0(DFPREG(rs1));
1287 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1288 gen_op_fsubd();
3475187d 1289 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1290 break;
e80cfcfc
FB		 1291 case 0x47: /* fsubq */
1292 goto nfpu_insn;
e8af50a3
FB		 1293 case 0x49:
1294 gen_op_load_fpr_FT0(rs1);
1295 gen_op_load_fpr_FT1(rs2);
1296 gen_op_fmuls();
1297 gen_op_store_FT0_fpr(rd);
1298 break;
1299 case 0x4a:
3475187d
FB		 1300 gen_op_load_fpr_DT0(DFPREG(rs1));
1301 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB		 1302 gen_op_fmuld();
1303 gen_op_store_DT0_fpr(rd);
1304 break;
e80cfcfc
FB		 1305 case 0x4b: /* fmulq */
1306 goto nfpu_insn;
e8af50a3
FB		 1307 case 0x4d:
1308 gen_op_load_fpr_FT0(rs1);
1309 gen_op_load_fpr_FT1(rs2);
1310 gen_op_fdivs();
1311 gen_op_store_FT0_fpr(rd);
1312 break;
1313 case 0x4e:
3475187d
FB		 1314 gen_op_load_fpr_DT0(DFPREG(rs1));
1315 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1316 gen_op_fdivd();
3475187d 1317 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1318 break;
e80cfcfc
FB		 1319 case 0x4f: /* fdivq */
1320 goto nfpu_insn;
e8af50a3
FB		 1321 case 0x69:
1322 gen_op_load_fpr_FT0(rs1);
1323 gen_op_load_fpr_FT1(rs2);
1324 gen_op_fsmuld();
3475187d 1325 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1326 break;
e80cfcfc
FB		 1327 case 0x6e: /* fdmulq */
1328 goto nfpu_insn;
e8af50a3
FB		 1329 case 0xc4:
1330 gen_op_load_fpr_FT1(rs2);
1331 gen_op_fitos();
1332 gen_op_store_FT0_fpr(rd);
1333 break;
1334 case 0xc6:
3475187d 1335 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB		 1336 gen_op_fdtos();
1337 gen_op_store_FT0_fpr(rd);
1338 break;
e80cfcfc
FB		 1339 case 0xc7: /* fqtos */
1340 goto nfpu_insn;
e8af50a3
FB		 1341 case 0xc8:
1342 gen_op_load_fpr_FT1(rs2);
1343 gen_op_fitod();
3475187d 1344 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3
FB		 1345 break;
1346 case 0xc9:
1347 gen_op_load_fpr_FT1(rs2);
1348 gen_op_fstod();
3475187d 1349 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1350 break;
e80cfcfc
FB		 1351 case 0xcb: /* fqtod */
1352 goto nfpu_insn;
1353 case 0xcc: /* fitoq */
1354 goto nfpu_insn;
1355 case 0xcd: /* fstoq */
1356 goto nfpu_insn;
1357 case 0xce: /* fdtoq */
1358 goto nfpu_insn;
e8af50a3
FB		 1359 case 0xd1:
1360 gen_op_load_fpr_FT1(rs2);
1361 gen_op_fstoi();
1362 gen_op_store_FT0_fpr(rd);
1363 break;
1364 case 0xd2:
1365 gen_op_load_fpr_DT1(rs2);
1366 gen_op_fdtoi();
1367 gen_op_store_FT0_fpr(rd);
1368 break;
e80cfcfc
FB		 1369 case 0xd3: /* fqtoi */
1370 goto nfpu_insn;
3475187d 1371#ifdef TARGET_SPARC64
af7bf89b 1372 case 0x2: /* V9 fmovd */
3475187d
FB		 1373 gen_op_load_fpr_DT0(DFPREG(rs2));
1374 gen_op_store_DT0_fpr(DFPREG(rd));
1375 break;
af7bf89b 1376 case 0x6: /* V9 fnegd */
3475187d
FB		 1377 gen_op_load_fpr_DT1(DFPREG(rs2));
1378 gen_op_fnegd();
1379 gen_op_store_DT0_fpr(DFPREG(rd));
1380 break;
af7bf89b 1381 case 0xa: /* V9 fabsd */
3475187d
FB		 1382 gen_op_load_fpr_DT1(DFPREG(rs2));
1383 gen_op_fabsd();
1384 gen_op_store_DT0_fpr(DFPREG(rd));
1385 break;
af7bf89b 1386 case 0x81: /* V9 fstox */
3475187d
FB		 1387 gen_op_load_fpr_FT1(rs2);
1388 gen_op_fstox();
1389 gen_op_store_DT0_fpr(DFPREG(rd));
1390 break;
af7bf89b 1391 case 0x82: /* V9 fdtox */
3475187d
FB		 1392 gen_op_load_fpr_DT1(DFPREG(rs2));
1393 gen_op_fdtox();
1394 gen_op_store_DT0_fpr(DFPREG(rd));
1395 break;
af7bf89b 1396 case 0x84: /* V9 fxtos */
3475187d
FB		 1397 gen_op_load_fpr_DT1(DFPREG(rs2));
1398 gen_op_fxtos();
1399 gen_op_store_FT0_fpr(rd);
1400 break;
af7bf89b 1401 case 0x88: /* V9 fxtod */
3475187d
FB		 1402 gen_op_load_fpr_DT1(DFPREG(rs2));
1403 gen_op_fxtod();
1404 gen_op_store_DT0_fpr(DFPREG(rd));
1405 break;
af7bf89b
FB		 1406 case 0x3: /* V9 fmovq */
1407 case 0x7: /* V9 fnegq */
1408 case 0xb: /* V9 fabsq */
1409 case 0x83: /* V9 fqtox */
1410 case 0x8c: /* V9 fxtoq */
3475187d
FB		 1411 goto nfpu_insn;
1412#endif
1413 default:
e8af50a3
FB		 1414 goto illegal_insn;
1415 }
e80cfcfc 1416 } else if (xop == 0x35) { /* FPU Operations */
3475187d
FB		 1417#ifdef TARGET_SPARC64
1418 int cond;
1419#endif
e80cfcfc
FB		 1420#if !defined(CONFIG_USER_ONLY)
1421 gen_op_trap_ifnofpu();
1422#endif
cf495bcf 1423 rs1 = GET_FIELD(insn, 13, 17);
e80cfcfc
FB		 1424 rs2 = GET_FIELD(insn, 27, 31);
1425 xop = GET_FIELD(insn, 18, 26);
3475187d
FB		 1426#ifdef TARGET_SPARC64
1427 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1428 cond = GET_FIELD_SP(insn, 14, 17);
1429 gen_op_load_fpr_FT0(rd);
1430 gen_op_load_fpr_FT1(rs2);
1431 rs1 = GET_FIELD(insn, 13, 17);
1432 gen_movl_reg_T0(rs1);
1433 flush_T2(dc);
1434 gen_cond_reg(cond);
1435 gen_op_fmovs_cc();
1436 gen_op_store_FT0_fpr(rd);
1437 break;
1438 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1439 cond = GET_FIELD_SP(insn, 14, 17);
1440 gen_op_load_fpr_DT0(rd);
1441 gen_op_load_fpr_DT1(rs2);
1442 flush_T2(dc);
1443 rs1 = GET_FIELD(insn, 13, 17);
1444 gen_movl_reg_T0(rs1);
1445 gen_cond_reg(cond);
1446 gen_op_fmovs_cc();
1447 gen_op_store_DT0_fpr(rd);
1448 break;
1449 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1450 goto nfpu_insn;
1451 }
1452#endif
e80cfcfc 1453 switch (xop) {
3475187d
FB		 1454#ifdef TARGET_SPARC64
1455 case 0x001: /* V9 fmovscc %fcc0 */
1456 cond = GET_FIELD_SP(insn, 14, 17);
1457 gen_op_load_fpr_FT0(rd);
1458 gen_op_load_fpr_FT1(rs2);
1459 flush_T2(dc);
1460 gen_fcond[0][cond]();
1461 gen_op_fmovs_cc();
1462 gen_op_store_FT0_fpr(rd);
1463 break;
1464 case 0x002: /* V9 fmovdcc %fcc0 */
1465 cond = GET_FIELD_SP(insn, 14, 17);
1466 gen_op_load_fpr_DT0(rd);
1467 gen_op_load_fpr_DT1(rs2);
1468 flush_T2(dc);
1469 gen_fcond[0][cond]();
1470 gen_op_fmovd_cc();
1471 gen_op_store_DT0_fpr(rd);
1472 break;
1473 case 0x003: /* V9 fmovqcc %fcc0 */
1474 goto nfpu_insn;
1475 case 0x041: /* V9 fmovscc %fcc1 */
1476 cond = GET_FIELD_SP(insn, 14, 17);
1477 gen_op_load_fpr_FT0(rd);
1478 gen_op_load_fpr_FT1(rs2);
1479 flush_T2(dc);
1480 gen_fcond[1][cond]();
1481 gen_op_fmovs_cc();
1482 gen_op_store_FT0_fpr(rd);
1483 break;
1484 case 0x042: /* V9 fmovdcc %fcc1 */
1485 cond = GET_FIELD_SP(insn, 14, 17);
1486 gen_op_load_fpr_DT0(rd);
1487 gen_op_load_fpr_DT1(rs2);
1488 flush_T2(dc);
1489 gen_fcond[1][cond]();
1490 gen_op_fmovd_cc();
1491 gen_op_store_DT0_fpr(rd);
1492 break;
1493 case 0x043: /* V9 fmovqcc %fcc1 */
1494 goto nfpu_insn;
1495 case 0x081: /* V9 fmovscc %fcc2 */
1496 cond = GET_FIELD_SP(insn, 14, 17);
1497 gen_op_load_fpr_FT0(rd);
1498 gen_op_load_fpr_FT1(rs2);
1499 flush_T2(dc);
1500 gen_fcond[2][cond]();
1501 gen_op_fmovs_cc();
1502 gen_op_store_FT0_fpr(rd);
1503 break;
1504 case 0x082: /* V9 fmovdcc %fcc2 */
1505 cond = GET_FIELD_SP(insn, 14, 17);
1506 gen_op_load_fpr_DT0(rd);
1507 gen_op_load_fpr_DT1(rs2);
1508 flush_T2(dc);
1509 gen_fcond[2][cond]();
1510 gen_op_fmovd_cc();
1511 gen_op_store_DT0_fpr(rd);
1512 break;
1513 case 0x083: /* V9 fmovqcc %fcc2 */
1514 goto nfpu_insn;
1515 case 0x0c1: /* V9 fmovscc %fcc3 */
1516 cond = GET_FIELD_SP(insn, 14, 17);
1517 gen_op_load_fpr_FT0(rd);
1518 gen_op_load_fpr_FT1(rs2);
1519 flush_T2(dc);
1520 gen_fcond[3][cond]();
1521 gen_op_fmovs_cc();
1522 gen_op_store_FT0_fpr(rd);
1523 break;
1524 case 0x0c2: /* V9 fmovdcc %fcc3 */
1525 cond = GET_FIELD_SP(insn, 14, 17);
1526 gen_op_load_fpr_DT0(rd);
1527 gen_op_load_fpr_DT1(rs2);
1528 flush_T2(dc);
1529 gen_fcond[3][cond]();
1530 gen_op_fmovd_cc();
1531 gen_op_store_DT0_fpr(rd);
1532 break;
1533 case 0x0c3: /* V9 fmovqcc %fcc3 */
1534 goto nfpu_insn;
1535 case 0x101: /* V9 fmovscc %icc */
1536 cond = GET_FIELD_SP(insn, 14, 17);
1537 gen_op_load_fpr_FT0(rd);
1538 gen_op_load_fpr_FT1(rs2);
1539 flush_T2(dc);
1540 gen_cond[0][cond]();
1541 gen_op_fmovs_cc();
1542 gen_op_store_FT0_fpr(rd);
1543 break;
1544 case 0x102: /* V9 fmovdcc %icc */
1545 cond = GET_FIELD_SP(insn, 14, 17);
1546 gen_op_load_fpr_DT0(rd);
1547 gen_op_load_fpr_DT1(rs2);
1548 flush_T2(dc);
1549 gen_cond[0][cond]();
1550 gen_op_fmovd_cc();
1551 gen_op_store_DT0_fpr(rd);
1552 break;
1553 case 0x103: /* V9 fmovqcc %icc */
1554 goto nfpu_insn;
1555 case 0x181: /* V9 fmovscc %xcc */
1556 cond = GET_FIELD_SP(insn, 14, 17);
1557 gen_op_load_fpr_FT0(rd);
1558 gen_op_load_fpr_FT1(rs2);
1559 flush_T2(dc);
1560 gen_cond[1][cond]();
1561 gen_op_fmovs_cc();
1562 gen_op_store_FT0_fpr(rd);
1563 break;
1564 case 0x182: /* V9 fmovdcc %xcc */
1565 cond = GET_FIELD_SP(insn, 14, 17);
1566 gen_op_load_fpr_DT0(rd);
1567 gen_op_load_fpr_DT1(rs2);
1568 flush_T2(dc);
1569 gen_cond[1][cond]();
1570 gen_op_fmovd_cc();
1571 gen_op_store_DT0_fpr(rd);
1572 break;
1573 case 0x183: /* V9 fmovqcc %xcc */
1574 goto nfpu_insn;
1575#endif
1576 case 0x51: /* V9 %fcc */
e80cfcfc
FB		 1577 gen_op_load_fpr_FT0(rs1);
1578 gen_op_load_fpr_FT1(rs2);
3475187d
FB		 1579#ifdef TARGET_SPARC64
1580 gen_fcmps[rd & 3]();
1581#else
e80cfcfc 1582 gen_op_fcmps();
3475187d 1583#endif
e80cfcfc 1584 break;
3475187d
FB		 1585 case 0x52: /* V9 %fcc */
1586 gen_op_load_fpr_DT0(DFPREG(rs1));
1587 gen_op_load_fpr_DT1(DFPREG(rs2));
1588#ifdef TARGET_SPARC64
1589 gen_fcmpd[rd & 3]();
1590#else
e80cfcfc 1591 gen_op_fcmpd();
3475187d 1592#endif
e80cfcfc
FB		 1593 break;
1594 case 0x53: /* fcmpq */
1595 goto nfpu_insn;
3475187d 1596 case 0x55: /* fcmpes, V9 %fcc */
e80cfcfc
FB		 1597 gen_op_load_fpr_FT0(rs1);
1598 gen_op_load_fpr_FT1(rs2);
3475187d
FB		 1599#ifdef TARGET_SPARC64
1600 gen_fcmps[rd & 3]();
1601#else
e80cfcfc 1602 gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */
3475187d 1603#endif
e80cfcfc 1604 break;
3475187d
FB		 1605 case 0x56: /* fcmped, V9 %fcc */
1606 gen_op_load_fpr_DT0(DFPREG(rs1));
1607 gen_op_load_fpr_DT1(DFPREG(rs2));
1608#ifdef TARGET_SPARC64
1609 gen_fcmpd[rd & 3]();
1610#else
e80cfcfc 1611 gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */
3475187d 1612#endif
e80cfcfc
FB		 1613 break;
1614 case 0x57: /* fcmpeq */
1615 goto nfpu_insn;
1616 default:
1617 goto illegal_insn;
1618 }
1619#if defined(OPTIM)
1620 } else if (xop == 0x2) {
1621 // clr/mov shortcut
1622
1623 rs1 = GET_FIELD(insn, 13, 17);
1624 if (rs1 == 0) {
1625 // or %g0, x, y -> mov T1, x; mov y, T1
1626 if (IS_IMM) { /* immediate */
1627 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1628 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1629 } else { /* register */
1630 rs2 = GET_FIELD(insn, 27, 31);
1631 gen_movl_reg_T1(rs2);
1632 }
1633 gen_movl_T1_reg(rd);
1634 } else {
1635 gen_movl_reg_T0(rs1);
1636 if (IS_IMM) { /* immediate */
1637 // or x, #0, y -> mov T1, x; mov y, T1
1638 rs2 = GET_FIELDs(insn, 19, 31);
1639 if (rs2 != 0) {
3475187d 1640 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1641 gen_op_or_T1_T0();
1642 }
1643 } else { /* register */
1644 // or x, %g0, y -> mov T1, x; mov y, T1
1645 rs2 = GET_FIELD(insn, 27, 31);
1646 if (rs2 != 0) {
1647 gen_movl_reg_T1(rs2);
1648 gen_op_or_T1_T0();
1649 }
1650 }
1651 gen_movl_T0_reg(rd);
1652 }
83469015
FB		 1653#endif
1654#ifdef TARGET_SPARC64
1655 } else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */
1656 rs1 = GET_FIELD(insn, 13, 17);
1657 gen_movl_reg_T0(rs1);
1658 if (IS_IMM) { /* immediate */
1659 rs2 = GET_FIELDs(insn, 20, 31);
1660 gen_movl_simm_T1(rs2);
1661 } else { /* register */
1662 rs2 = GET_FIELD(insn, 27, 31);
1663 gen_movl_reg_T1(rs2);
1664 }
1665 gen_op_sll();
1666 gen_movl_T0_reg(rd);
1667 } else if (xop == 0x26) { /* srl, V9 srlx */
1668 rs1 = GET_FIELD(insn, 13, 17);
1669 gen_movl_reg_T0(rs1);
1670 if (IS_IMM) { /* immediate */
1671 rs2 = GET_FIELDs(insn, 20, 31);
1672 gen_movl_simm_T1(rs2);
1673 } else { /* register */
1674 rs2 = GET_FIELD(insn, 27, 31);
1675 gen_movl_reg_T1(rs2);
1676 }
1677 if (insn & (1 << 12))
1678 gen_op_srlx();
1679 else
1680 gen_op_srl();
1681 gen_movl_T0_reg(rd);
1682 } else if (xop == 0x27) { /* sra, V9 srax */
1683 rs1 = GET_FIELD(insn, 13, 17);
1684 gen_movl_reg_T0(rs1);
1685 if (IS_IMM) { /* immediate */
1686 rs2 = GET_FIELDs(insn, 20, 31);
1687 gen_movl_simm_T1(rs2);
1688 } else { /* register */
1689 rs2 = GET_FIELD(insn, 27, 31);
1690 gen_movl_reg_T1(rs2);
1691 }
1692 if (insn & (1 << 12))
1693 gen_op_srax();
1694 else
1695 gen_op_sra();
1696 gen_movl_T0_reg(rd);
e80cfcfc
FB		 1697#endif
1698 } else if (xop < 0x38) {
1699 rs1 = GET_FIELD(insn, 13, 17);
1700 gen_movl_reg_T0(rs1);
1701 if (IS_IMM) { /* immediate */
cf495bcf 1702 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1703 gen_movl_simm_T1(rs2);
cf495bcf
FB		 1704 } else { /* register */
1705 rs2 = GET_FIELD(insn, 27, 31);
1706 gen_movl_reg_T1(rs2);
1707 }
1708 if (xop < 0x20) {
1709 switch (xop & ~0x10) {
1710 case 0x0:
1711 if (xop & 0x10)
1712 gen_op_add_T1_T0_cc();
1713 else
1714 gen_op_add_T1_T0();
1715 break;
1716 case 0x1:
1717 gen_op_and_T1_T0();
1718 if (xop & 0x10)
1719 gen_op_logic_T0_cc();
1720 break;
1721 case 0x2:
e80cfcfc
FB		 1722 gen_op_or_T1_T0();
1723 if (xop & 0x10)
1724 gen_op_logic_T0_cc();
1725 break;
cf495bcf
FB		 1726 case 0x3:
1727 gen_op_xor_T1_T0();
1728 if (xop & 0x10)
1729 gen_op_logic_T0_cc();
1730 break;
1731 case 0x4:
1732 if (xop & 0x10)
1733 gen_op_sub_T1_T0_cc();
1734 else
1735 gen_op_sub_T1_T0();
1736 break;
1737 case 0x5:
1738 gen_op_andn_T1_T0();
1739 if (xop & 0x10)
1740 gen_op_logic_T0_cc();
1741 break;
1742 case 0x6:
1743 gen_op_orn_T1_T0();
1744 if (xop & 0x10)
1745 gen_op_logic_T0_cc();
1746 break;
1747 case 0x7:
1748 gen_op_xnor_T1_T0();
1749 if (xop & 0x10)
1750 gen_op_logic_T0_cc();
1751 break;
1752 case 0x8:
cf495bcf 1753 if (xop & 0x10)
af7bf89b
FB		 1754 gen_op_addx_T1_T0_cc();
1755 else
1756 gen_op_addx_T1_T0();
cf495bcf
FB		 1757 break;
1758 case 0xa:
1759 gen_op_umul_T1_T0();
1760 if (xop & 0x10)
1761 gen_op_logic_T0_cc();
1762 break;
1763 case 0xb:
1764 gen_op_smul_T1_T0();
1765 if (xop & 0x10)
1766 gen_op_logic_T0_cc();
1767 break;
1768 case 0xc:
cf495bcf 1769 if (xop & 0x10)
af7bf89b
FB		 1770 gen_op_subx_T1_T0_cc();
1771 else
1772 gen_op_subx_T1_T0();
cf495bcf
FB		 1773 break;
1774 case 0xe:
1775 gen_op_udiv_T1_T0();
1776 if (xop & 0x10)
1777 gen_op_div_cc();
1778 break;
1779 case 0xf:
1780 gen_op_sdiv_T1_T0();
1781 if (xop & 0x10)
1782 gen_op_div_cc();
1783 break;
1784 default:
1785 goto illegal_insn;
1786 }
e80cfcfc 1787 gen_movl_T0_reg(rd);
cf495bcf
FB		 1788 } else {
1789 switch (xop) {
3475187d
FB		 1790#ifdef TARGET_SPARC64
1791 case 0x9: /* V9 mulx */
1792 gen_op_mulx_T1_T0();
1793 gen_movl_T0_reg(rd);
1794 break;
1795 case 0xd: /* V9 udivx */
1796 gen_op_udivx_T1_T0();
1797 gen_movl_T0_reg(rd);
1798 break;
1799#endif
e80cfcfc
FB		 1800 case 0x20: /* taddcc */
1801 case 0x21: /* tsubcc */
1802 case 0x22: /* taddcctv */
1803 case 0x23: /* tsubcctv */
1804 goto illegal_insn;
cf495bcf
FB		 1805 case 0x24: /* mulscc */
1806 gen_op_mulscc_T1_T0();
1807 gen_movl_T0_reg(rd);
1808 break;
83469015
FB		 1809#ifndef TARGET_SPARC64
1810 case 0x25: /* sll */
3475187d 1811 gen_op_sll();
cf495bcf
FB		 1812 gen_movl_T0_reg(rd);
1813 break;
83469015 1814 case 0x26: /* srl */
3475187d 1815 gen_op_srl();
cf495bcf
FB		 1816 gen_movl_T0_reg(rd);
1817 break;
83469015 1818 case 0x27: /* sra */
3475187d 1819 gen_op_sra();
cf495bcf
FB		 1820 gen_movl_T0_reg(rd);
1821 break;
83469015 1822#endif
cf495bcf
FB		 1823 case 0x30:
1824 {
cf495bcf 1825 switch(rd) {
3475187d
FB		 1826 case 0: /* wry */
1827 gen_op_xor_T1_T0();
1828 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 1829 break;
3475187d 1830#ifdef TARGET_SPARC64
af7bf89b 1831 case 0x2: /* V9 wrccr */
3475187d
FB		 1832 gen_op_wrccr();
1833 break;
af7bf89b 1834 case 0x3: /* V9 wrasi */
3475187d
FB		 1835 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1836 break;
af7bf89b 1837 case 0x6: /* V9 wrfprs */
3475187d
FB		 1838 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1839 break;
1840 case 0xf: /* V9 sir, nop if user */
1841#if !defined(CONFIG_USER_ONLY)
1842 if (supervisor(dc))
1843 gen_op_sir();
1844#endif
1845 break;
83469015
FB		 1846 case 0x17: /* Tick compare */
1847#if !defined(CONFIG_USER_ONLY)
1848 if (!supervisor(dc))
1849 goto illegal_insn;
1850#endif
1851 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
1852 break;
1853 case 0x18: /* System tick */
1854#if !defined(CONFIG_USER_ONLY)
1855 if (!supervisor(dc))
1856 goto illegal_insn;
1857#endif
1858 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1859 break;
1860 case 0x19: /* System tick compare */
1861#if !defined(CONFIG_USER_ONLY)
1862 if (!supervisor(dc))
1863 goto illegal_insn;
3475187d 1864#endif
83469015
FB		 1865 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1866 break;
1867
3475187d
FB		 1868 case 0x10: /* Performance Control */
1869 case 0x11: /* Performance Instrumentation Counter */
1870 case 0x12: /* Dispatch Control */
1871 case 0x13: /* Graphics Status */
1872 case 0x14: /* Softint set */
1873 case 0x15: /* Softint clear */
1874 case 0x16: /* Softint write */
83469015 1875#endif
3475187d 1876 default:
cf495bcf
FB		 1877 goto illegal_insn;
1878 }
1879 }
1880 break;
e8af50a3 1881#if !defined(CONFIG_USER_ONLY)
af7bf89b 1882 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3
FB		 1883 {
1884 if (!supervisor(dc))
1885 goto priv_insn;
3475187d
FB		 1886#ifdef TARGET_SPARC64
1887 switch (rd) {
1888 case 0:
1889 gen_op_saved();
1890 break;
1891 case 1:
1892 gen_op_restored();
1893 break;
1894 default:
1895 goto illegal_insn;
1896 }
1897#else
e8af50a3
FB		 1898 gen_op_xor_T1_T0();
1899 gen_op_wrpsr();
9e61bde5
FB		 1900 save_state(dc);
1901 gen_op_next_insn();
1902 gen_op_movl_T0_0();
1903 gen_op_exit_tb();
1904 dc->is_br = 1;
3475187d 1905#endif
e8af50a3
FB		 1906 }
1907 break;
af7bf89b 1908 case 0x32: /* wrwim, V9 wrpr */
e8af50a3
FB		 1909 {
1910 if (!supervisor(dc))
1911 goto priv_insn;
1912 gen_op_xor_T1_T0();
3475187d
FB		 1913#ifdef TARGET_SPARC64
1914 switch (rd) {
1915 case 0: // tpc
1916 gen_op_wrtpc();
1917 break;
1918 case 1: // tnpc
1919 gen_op_wrtnpc();
1920 break;
1921 case 2: // tstate
1922 gen_op_wrtstate();
1923 break;
1924 case 3: // tt
1925 gen_op_wrtt();
1926 break;
1927 case 4: // tick
1928 gen_op_wrtick();
1929 break;
1930 case 5: // tba
83469015 1931 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3475187d
FB		 1932 break;
1933 case 6: // pstate
1934 gen_op_wrpstate();
1935 break;
1936 case 7: // tl
1937 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
1938 break;
1939 case 8: // pil
1940 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
1941 break;
1942 case 9: // cwp
1943 gen_op_wrcwp();
1944 break;
1945 case 10: // cansave
1946 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
1947 break;
1948 case 11: // canrestore
1949 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
1950 break;
1951 case 12: // cleanwin
1952 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
1953 break;
1954 case 13: // otherwin
1955 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
1956 break;
1957 case 14: // wstate
1958 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
1959 break;
1960 default:
1961 goto illegal_insn;
1962 }
1963#else
1964 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
1965#endif
e8af50a3
FB		 1966 }
1967 break;
3475187d
FB		 1968#ifndef TARGET_SPARC64
1969 case 0x33: /* wrtbr, V9 unimp */
e8af50a3
FB		 1970 {
1971 if (!supervisor(dc))
1972 goto priv_insn;
1973 gen_op_xor_T1_T0();
3475187d 1974 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
e8af50a3
FB		 1975 }
1976 break;
1977#endif
3475187d
FB		 1978#endif
1979#ifdef TARGET_SPARC64
af7bf89b 1980 case 0x2c: /* V9 movcc */
3475187d
FB		 1981 {
1982 int cc = GET_FIELD_SP(insn, 11, 12);
1983 int cond = GET_FIELD_SP(insn, 14, 17);
1984 if (IS_IMM) { /* immediate */
1985 rs2 = GET_FIELD_SPs(insn, 0, 10);
1986 gen_movl_simm_T1(rs2);
1987 }
1988 else {
1989 rs2 = GET_FIELD_SP(insn, 0, 4);
1990 gen_movl_reg_T1(rs2);
1991 }
1992 gen_movl_reg_T0(rd);
1993 flush_T2(dc);
1994 if (insn & (1 << 18)) {
1995 if (cc == 0)
1996 gen_cond[0][cond]();
1997 else if (cc == 2)
1998 gen_cond[1][cond]();
1999 else
2000 goto illegal_insn;
2001 } else {
2002 gen_fcond[cc][cond]();
2003 }
2004 gen_op_mov_cc();
2005 gen_movl_T0_reg(rd);
2006 break;
2007 }
af7bf89b 2008 case 0x2d: /* V9 sdivx */
3475187d
FB		 2009 gen_op_sdivx_T1_T0();
2010 gen_movl_T0_reg(rd);
2011 break;
af7bf89b 2012 case 0x2e: /* V9 popc */
3475187d
FB		 2013 {
2014 if (IS_IMM) { /* immediate */
2015 rs2 = GET_FIELD_SPs(insn, 0, 12);
2016 gen_movl_simm_T1(rs2);
2017 // XXX optimize: popc(constant)
2018 }
2019 else {
2020 rs2 = GET_FIELD_SP(insn, 0, 4);
2021 gen_movl_reg_T1(rs2);
2022 }
2023 gen_op_popc();
2024 gen_movl_T0_reg(rd);
2025 }
af7bf89b 2026 case 0x2f: /* V9 movr */
3475187d
FB		 2027 {
2028 int cond = GET_FIELD_SP(insn, 10, 12);
2029 rs1 = GET_FIELD(insn, 13, 17);
2030 flush_T2(dc);
2031 gen_movl_reg_T0(rs1);
2032 gen_cond_reg(cond);
2033 if (IS_IMM) { /* immediate */
2034 rs2 = GET_FIELD_SPs(insn, 0, 10);
2035 gen_movl_simm_T1(rs2);
2036 }
2037 else {
2038 rs2 = GET_FIELD_SP(insn, 0, 4);
2039 gen_movl_reg_T1(rs2);
2040 }
2041 gen_movl_reg_T0(rd);
2042 gen_op_mov_cc();
2043 gen_movl_T0_reg(rd);
2044 break;
2045 }
2046 case 0x36: /* UltraSparc shutdown, VIS */
2047 {
2048 // XXX
2049 }
2050#endif
2051 default:
e80cfcfc
FB		 2052 goto illegal_insn;
2053 }
2054 }
3475187d
FB		 2055#ifdef TARGET_SPARC64
2056 } else if (xop == 0x39) { /* V9 return */
3475187d
FB		 2057 rs1 = GET_FIELD(insn, 13, 17);
2058 gen_movl_reg_T0(rs1);
2059 if (IS_IMM) { /* immediate */
2060 rs2 = GET_FIELDs(insn, 19, 31);
2061#if defined(OPTIM)
2062 if (rs2) {
2063#endif
2064 gen_movl_simm_T1(rs2);
2065 gen_op_add_T1_T0();
2066#if defined(OPTIM)
2067 }
2068#endif
2069 } else { /* register */
2070 rs2 = GET_FIELD(insn, 27, 31);
2071#if defined(OPTIM)
2072 if (rs2) {
2073#endif
2074 gen_movl_reg_T1(rs2);
2075 gen_op_add_T1_T0();
2076#if defined(OPTIM)
2077 }
2078#endif
2079 }
83469015 2080 gen_op_restore();
3475187d
FB		 2081 gen_mov_pc_npc(dc);
2082 gen_op_movl_npc_T0();
2083 dc->npc = DYNAMIC_PC;
2084 goto jmp_insn;
2085#endif
e80cfcfc
FB		 2086 } else {
2087 rs1 = GET_FIELD(insn, 13, 17);
2088 gen_movl_reg_T0(rs1);
2089 if (IS_IMM) { /* immediate */
2090 rs2 = GET_FIELDs(insn, 19, 31);
2091#if defined(OPTIM)
2092 if (rs2) {
e8af50a3 2093#endif
3475187d 2094 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 2095 gen_op_add_T1_T0();
2096#if defined(OPTIM)
2097 }
e8af50a3 2098#endif
e80cfcfc
FB		 2099 } else { /* register */
2100 rs2 = GET_FIELD(insn, 27, 31);
2101#if defined(OPTIM)
2102 if (rs2) {
2103#endif
2104 gen_movl_reg_T1(rs2);
2105 gen_op_add_T1_T0();
2106#if defined(OPTIM)
2107 }
e8af50a3 2108#endif
cf495bcf 2109 }
e80cfcfc
FB		 2110 switch (xop) {
2111 case 0x38: /* jmpl */
2112 {
e80cfcfc 2113 if (rd != 0) {
0bee699e
FB		 2114 gen_op_movl_T1_im(dc->pc);
2115 gen_movl_T1_reg(rd);
e80cfcfc 2116 }
0bee699e
FB		 2117 gen_mov_pc_npc(dc);
2118 gen_op_movl_npc_T0();
e80cfcfc
FB		 2119 dc->npc = DYNAMIC_PC;
2120 }
2121 goto jmp_insn;
3475187d 2122#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
af7bf89b 2123 case 0x39: /* rett, V9 return */
e80cfcfc
FB		 2124 {
2125 if (!supervisor(dc))
2126 goto priv_insn;
0bee699e 2127 gen_mov_pc_npc(dc);
e80cfcfc 2128 gen_op_movl_npc_T0();
0bee699e 2129 dc->npc = DYNAMIC_PC;
e80cfcfc
FB		 2130 gen_op_rett();
2131 }
0bee699e 2132 goto jmp_insn;
e80cfcfc
FB		 2133#endif
2134 case 0x3b: /* flush */
2135 gen_op_flush_T0();
2136 break;
2137 case 0x3c: /* save */
2138 save_state(dc);
2139 gen_op_save();
2140 gen_movl_T0_reg(rd);
2141 break;
2142 case 0x3d: /* restore */
2143 save_state(dc);
2144 gen_op_restore();
2145 gen_movl_T0_reg(rd);
2146 break;
3475187d 2147#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
af7bf89b 2148 case 0x3e: /* V9 done/retry */
3475187d
FB		 2149 {
2150 switch (rd) {
2151 case 0:
2152 if (!supervisor(dc))
2153 goto priv_insn;
83469015
FB		 2154 dc->npc = DYNAMIC_PC;
2155 dc->pc = DYNAMIC_PC;
3475187d 2156 gen_op_done();
83469015 2157 goto jmp_insn;
3475187d
FB		 2158 case 1:
2159 if (!supervisor(dc))
2160 goto priv_insn;
83469015
FB		 2161 dc->npc = DYNAMIC_PC;
2162 dc->pc = DYNAMIC_PC;
3475187d 2163 gen_op_retry();
83469015 2164 goto jmp_insn;
3475187d
FB		 2165 default:
2166 goto illegal_insn;
2167 }
2168 }
2169 break;
2170#endif
2171 default:
e80cfcfc
FB		 2172 goto illegal_insn;
2173 }
cf495bcf
FB		 2174 }
2175 break;
2176 }
af7bf89b 2177 break;
cf495bcf
FB		 2178 case 3: /* load/store instructions */
2179 {
2180 unsigned int xop = GET_FIELD(insn, 7, 12);
2181 rs1 = GET_FIELD(insn, 13, 17);
2182 gen_movl_reg_T0(rs1);
2183 if (IS_IMM) { /* immediate */
2184 rs2 = GET_FIELDs(insn, 19, 31);
e80cfcfc 2185#if defined(OPTIM)
e8af50a3 2186 if (rs2 != 0) {
e80cfcfc 2187#endif
3475187d 2188 gen_movl_simm_T1(rs2);
e8af50a3 2189 gen_op_add_T1_T0();
e80cfcfc 2190#if defined(OPTIM)
e8af50a3 2191 }
e80cfcfc 2192#endif
cf495bcf
FB		 2193 } else { /* register */
2194 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB		 2195#if defined(OPTIM)
2196 if (rs2 != 0) {
2197#endif
2198 gen_movl_reg_T1(rs2);
2199 gen_op_add_T1_T0();
2200#if defined(OPTIM)
2201 }
2202#endif
cf495bcf 2203 }
3475187d
FB		 2204 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \
2205 (xop > 0x17 && xop < 0x1d ) || \
2206 (xop > 0x2c && xop < 0x33) || xop == 0x1f) {
cf495bcf
FB		 2207 switch (xop) {
2208 case 0x0: /* load word */
e8af50a3 2209 gen_op_ldst(ld);
cf495bcf
FB		 2210 break;
2211 case 0x1: /* load unsigned byte */
e8af50a3 2212 gen_op_ldst(ldub);
cf495bcf
FB		 2213 break;
2214 case 0x2: /* load unsigned halfword */
e8af50a3 2215 gen_op_ldst(lduh);
cf495bcf
FB		 2216 break;
2217 case 0x3: /* load double word */
e8af50a3 2218 gen_op_ldst(ldd);
cf495bcf
FB		 2219 gen_movl_T0_reg(rd + 1);
2220 break;
2221 case 0x9: /* load signed byte */
e8af50a3 2222 gen_op_ldst(ldsb);
cf495bcf
FB		 2223 break;
2224 case 0xa: /* load signed halfword */
e8af50a3 2225 gen_op_ldst(ldsh);
cf495bcf
FB		 2226 break;
2227 case 0xd: /* ldstub -- XXX: should be atomically */
e8af50a3 2228 gen_op_ldst(ldstub);
cf495bcf
FB		 2229 break;
2230 case 0x0f: /* swap register with memory. Also atomically */
e80cfcfc 2231 gen_movl_reg_T1(rd);
e8af50a3
FB		 2232 gen_op_ldst(swap);
2233 break;
3475187d 2234#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 2235 case 0x10: /* load word alternate */
3475187d 2236#ifndef TARGET_SPARC64
e8af50a3
FB		 2237 if (!supervisor(dc))
2238 goto priv_insn;
3475187d 2239#endif
e8af50a3
FB		 2240 gen_op_lda(insn, 1, 4, 0);
2241 break;
2242 case 0x11: /* load unsigned byte alternate */
3475187d 2243#ifndef TARGET_SPARC64
e8af50a3
FB		 2244 if (!supervisor(dc))
2245 goto priv_insn;
3475187d 2246#endif
e8af50a3
FB		 2247 gen_op_lduba(insn, 1, 1, 0);
2248 break;
2249 case 0x12: /* load unsigned halfword alternate */
3475187d 2250#ifndef TARGET_SPARC64
e8af50a3
FB		 2251 if (!supervisor(dc))
2252 goto priv_insn;
3475187d 2253#endif
e8af50a3
FB		 2254 gen_op_lduha(insn, 1, 2, 0);
2255 break;
2256 case 0x13: /* load double word alternate */
3475187d 2257#ifndef TARGET_SPARC64
e8af50a3
FB		 2258 if (!supervisor(dc))
2259 goto priv_insn;
3475187d 2260#endif
e8af50a3
FB		 2261 gen_op_ldda(insn, 1, 8, 0);
2262 gen_movl_T0_reg(rd + 1);
2263 break;
2264 case 0x19: /* load signed byte alternate */
3475187d 2265#ifndef TARGET_SPARC64
e8af50a3
FB		 2266 if (!supervisor(dc))
2267 goto priv_insn;
3475187d 2268#endif
e8af50a3
FB		 2269 gen_op_ldsba(insn, 1, 1, 1);
2270 break;
2271 case 0x1a: /* load signed halfword alternate */
3475187d 2272#ifndef TARGET_SPARC64
e8af50a3
FB		 2273 if (!supervisor(dc))
2274 goto priv_insn;
3475187d 2275#endif
e8af50a3
FB		 2276 gen_op_ldsha(insn, 1, 2 ,1);
2277 break;
2278 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 2279#ifndef TARGET_SPARC64
e8af50a3
FB		 2280 if (!supervisor(dc))
2281 goto priv_insn;
3475187d 2282#endif
e8af50a3
FB		 2283 gen_op_ldstuba(insn, 1, 1, 0);
2284 break;
2285 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 2286#ifndef TARGET_SPARC64
e8af50a3
FB		 2287 if (!supervisor(dc))
2288 goto priv_insn;
3475187d 2289#endif
e80cfcfc 2290 gen_movl_reg_T1(rd);
e8af50a3 2291 gen_op_swapa(insn, 1, 4, 0);
cf495bcf 2292 break;
3475187d
FB		 2293
2294#ifndef TARGET_SPARC64
0fa85d43
FB		 2295 /* avoid warnings */
2296 (void) &gen_op_stfa;
2297 (void) &gen_op_stdfa;
2298 (void) &gen_op_ldfa;
2299 (void) &gen_op_lddfa;
3475187d
FB		 2300#else
2301#if !defined(CONFIG_USER_ONLY)
2302 (void) &gen_op_cas;
2303 (void) &gen_op_casx;
e80cfcfc 2304#endif
3475187d
FB		 2305#endif
2306#endif
2307#ifdef TARGET_SPARC64
af7bf89b 2308 case 0x08: /* V9 ldsw */
3475187d
FB		 2309 gen_op_ldst(ldsw);
2310 break;
af7bf89b 2311 case 0x0b: /* V9 ldx */
3475187d
FB		 2312 gen_op_ldst(ldx);
2313 break;
af7bf89b 2314 case 0x18: /* V9 ldswa */
3475187d
FB		 2315 gen_op_ldswa(insn, 1, 4, 1);
2316 break;
af7bf89b 2317 case 0x1b: /* V9 ldxa */
3475187d
FB		 2318 gen_op_ldxa(insn, 1, 8, 0);
2319 break;
2320 case 0x2d: /* V9 prefetch, no effect */
2321 goto skip_move;
af7bf89b 2322 case 0x30: /* V9 ldfa */
3475187d
FB		 2323 gen_op_ldfa(insn, 1, 8, 0); // XXX
2324 break;
af7bf89b 2325 case 0x33: /* V9 lddfa */
3475187d 2326 gen_op_lddfa(insn, 1, 8, 0); // XXX
af7bf89b 2327
3475187d
FB		 2328 break;
2329 case 0x3d: /* V9 prefetcha, no effect */
2330 goto skip_move;
af7bf89b 2331 case 0x32: /* V9 ldqfa */
3475187d
FB		 2332 goto nfpu_insn;
2333#endif
2334 default:
e80cfcfc 2335 goto illegal_insn;
7a3f1944 2336 }
cf495bcf 2337 gen_movl_T1_reg(rd);
3475187d
FB		 2338#ifdef TARGET_SPARC64
2339 skip_move: ;
2340#endif
e8af50a3 2341 } else if (xop >= 0x20 && xop < 0x24) {
3475187d 2342#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e80cfcfc
FB		 2343 gen_op_trap_ifnofpu();
2344#endif
e8af50a3
FB		 2345 switch (xop) {
2346 case 0x20: /* load fpreg */
2347 gen_op_ldst(ldf);
2348 gen_op_store_FT0_fpr(rd);
2349 break;
2350 case 0x21: /* load fsr */
9e61bde5 2351 gen_op_ldst(ldf);
e8af50a3
FB		 2352 gen_op_ldfsr();
2353 break;
af7bf89b
FB		 2354 case 0x22: /* load quad fpreg */
2355 goto nfpu_insn;
e8af50a3
FB		 2356 case 0x23: /* load double fpreg */
2357 gen_op_ldst(lddf);
3475187d 2358 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 2359 break;
e80cfcfc
FB		 2360 default:
2361 goto illegal_insn;
e8af50a3 2362 }
3475187d
FB		 2363 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
2364 xop == 0xe || xop == 0x1e) {
cf495bcf
FB		 2365 gen_movl_reg_T1(rd);
2366 switch (xop) {
2367 case 0x4:
e8af50a3 2368 gen_op_ldst(st);
cf495bcf
FB		 2369 break;
2370 case 0x5:
e8af50a3 2371 gen_op_ldst(stb);
cf495bcf
FB		 2372 break;
2373 case 0x6:
e8af50a3 2374 gen_op_ldst(sth);
cf495bcf
FB		 2375 break;
2376 case 0x7:
72cbca10 2377 flush_T2(dc);
cf495bcf 2378 gen_movl_reg_T2(rd + 1);
e8af50a3
FB		 2379 gen_op_ldst(std);
2380 break;
3475187d 2381#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 2382 case 0x14:
3475187d 2383#ifndef TARGET_SPARC64
e8af50a3
FB		 2384 if (!supervisor(dc))
2385 goto priv_insn;
3475187d 2386#endif
e8af50a3 2387 gen_op_sta(insn, 0, 4, 0);
d39c0b99 2388 break;
e8af50a3 2389 case 0x15:
3475187d 2390#ifndef TARGET_SPARC64
e8af50a3
FB		 2391 if (!supervisor(dc))
2392 goto priv_insn;
3475187d 2393#endif
e8af50a3 2394 gen_op_stba(insn, 0, 1, 0);
d39c0b99 2395 break;
e8af50a3 2396 case 0x16:
3475187d 2397#ifndef TARGET_SPARC64
e8af50a3
FB		 2398 if (!supervisor(dc))
2399 goto priv_insn;
3475187d 2400#endif
e8af50a3 2401 gen_op_stha(insn, 0, 2, 0);
d39c0b99 2402 break;
e8af50a3 2403 case 0x17:
3475187d 2404#ifndef TARGET_SPARC64
e8af50a3
FB		 2405 if (!supervisor(dc))
2406 goto priv_insn;
3475187d 2407#endif
e8af50a3
FB		 2408 flush_T2(dc);
2409 gen_movl_reg_T2(rd + 1);
2410 gen_op_stda(insn, 0, 8, 0);
d39c0b99 2411 break;
e80cfcfc 2412#endif
3475187d 2413#ifdef TARGET_SPARC64
af7bf89b 2414 case 0x0e: /* V9 stx */
3475187d
FB		 2415 gen_op_ldst(stx);
2416 break;
af7bf89b 2417 case 0x1e: /* V9 stxa */
3475187d
FB		 2418 gen_op_stxa(insn, 0, 8, 0); // XXX
2419 break;
2420#endif
2421 default:
e80cfcfc 2422 goto illegal_insn;
7a3f1944 2423 }
e8af50a3 2424 } else if (xop > 0x23 && xop < 0x28) {
e80cfcfc
FB		 2425#if !defined(CONFIG_USER_ONLY)
2426 gen_op_trap_ifnofpu();
2427#endif
e8af50a3
FB		 2428 switch (xop) {
2429 case 0x24:
2430 gen_op_load_fpr_FT0(rd);
2431 gen_op_ldst(stf);
2432 break;
af7bf89b 2433 case 0x25: /* stfsr, V9 stxfsr */
e8af50a3 2434 gen_op_stfsr();
9e61bde5 2435 gen_op_ldst(stf);
e8af50a3 2436 break;
af7bf89b
FB		 2437 case 0x26: /* stdfq */
2438 goto nfpu_insn;
e8af50a3 2439 case 0x27:
3475187d 2440 gen_op_load_fpr_DT0(DFPREG(rd));
e8af50a3
FB		 2441 gen_op_ldst(stdf);
2442 break;
e80cfcfc 2443 default:
3475187d
FB		 2444 goto illegal_insn;
2445 }
2446 } else if (xop > 0x33 && xop < 0x3f) {
2447#ifdef TARGET_SPARC64
2448 switch (xop) {
af7bf89b 2449 case 0x34: /* V9 stfa */
3475187d
FB		 2450 gen_op_stfa(insn, 0, 0, 0); // XXX
2451 break;
af7bf89b 2452 case 0x37: /* V9 stdfa */
3475187d
FB		 2453 gen_op_stdfa(insn, 0, 0, 0); // XXX
2454 break;
af7bf89b 2455 case 0x3c: /* V9 casa */
3475187d
FB		 2456 gen_op_casa(insn, 0, 4, 0); // XXX
2457 break;
af7bf89b 2458 case 0x3e: /* V9 casxa */
3475187d
FB		 2459 gen_op_casxa(insn, 0, 8, 0); // XXX
2460 break;
af7bf89b 2461 case 0x36: /* V9 stqfa */
3475187d
FB		 2462 goto nfpu_insn;
2463 default:
e80cfcfc 2464 goto illegal_insn;
e8af50a3 2465 }
3475187d 2466#else
e80cfcfc 2467 goto illegal_insn;
3475187d 2468#endif
e8af50a3 2469 }
e80cfcfc
FB		 2470 else
2471 goto illegal_insn;
7a3f1944 2472 }
af7bf89b 2473 break;
cf495bcf
FB		 2474 }
2475 /* default case for non jump instructions */
72cbca10
FB		 2476 if (dc->npc == DYNAMIC_PC) {
2477 dc->pc = DYNAMIC_PC;
2478 gen_op_next_insn();
2479 } else if (dc->npc == JUMP_PC) {
2480 /* we can do a static jump */
83469015 2481 gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 2482 dc->is_br = 1;
2483 } else {
cf495bcf
FB		 2484 dc->pc = dc->npc;
2485 dc->npc = dc->npc + 4;
cf495bcf 2486 }
e80cfcfc 2487 jmp_insn:
cf495bcf
FB		 2488 return;
2489 illegal_insn:
72cbca10 2490 save_state(dc);
cf495bcf
FB		 2491 gen_op_exception(TT_ILL_INSN);
2492 dc->is_br = 1;
e8af50a3 2493 return;
e80cfcfc 2494#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB		 2495 priv_insn:
2496 save_state(dc);
2497 gen_op_exception(TT_PRIV_INSN);
2498 dc->is_br = 1;
e80cfcfc
FB		 2499 return;
2500#endif
2501 nfpu_insn:
2502 save_state(dc);
2503 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
2504 dc->is_br = 1;
7a3f1944
FB		 2505}
2506
cf495bcf 2507static inline int gen_intermediate_code_internal(TranslationBlock * tb,
e8af50a3 2508 int spc, CPUSPARCState *env)
7a3f1944 2509{
72cbca10 2510 target_ulong pc_start, last_pc;
cf495bcf
FB		 2511 uint16_t *gen_opc_end;
2512 DisasContext dc1, *dc = &dc1;
e8af50a3 2513 int j, lj = -1;
cf495bcf
FB		 2514
2515 memset(dc, 0, sizeof(DisasContext));
cf495bcf 2516 dc->tb = tb;
72cbca10 2517 pc_start = tb->pc;
cf495bcf 2518 dc->pc = pc_start;
e80cfcfc 2519 last_pc = dc->pc;
72cbca10 2520 dc->npc = (target_ulong) tb->cs_base;
e8af50a3
FB		 2521#if defined(CONFIG_USER_ONLY)
2522 dc->mem_idx = 0;
2523#else
2524 dc->mem_idx = ((env->psrs) != 0);
2525#endif
cf495bcf
FB		 2526 gen_opc_ptr = gen_opc_buf;
2527 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2528 gen_opparam_ptr = gen_opparam_buf;
83469015 2529 nb_gen_labels = 0;
cf495bcf
FB		 2530
2531 do {
e8af50a3
FB		 2532 if (env->nb_breakpoints > 0) {
2533 for(j = 0; j < env->nb_breakpoints; j++) {
2534 if (env->breakpoints[j] == dc->pc) {
e80cfcfc
FB		 2535 if (dc->pc != pc_start)
2536 save_state(dc);
2537 gen_op_debug();
2538 gen_op_movl_T0_0();
2539 gen_op_exit_tb();
2540 dc->is_br = 1;
2541 goto exit_gen_loop;
e8af50a3
FB		 2542 }
2543 }
2544 }
2545 if (spc) {
2546 if (loglevel > 0)
2547 fprintf(logfile, "Search PC...\n");
2548 j = gen_opc_ptr - gen_opc_buf;
2549 if (lj < j) {
2550 lj++;
2551 while (lj < j)
2552 gen_opc_instr_start[lj++] = 0;
2553 gen_opc_pc[lj] = dc->pc;
2554 gen_opc_npc[lj] = dc->npc;
2555 gen_opc_instr_start[lj] = 1;
2556 }
2557 }
cf495bcf
FB		 2558 last_pc = dc->pc;
2559 disas_sparc_insn(dc);
3475187d 2560
cf495bcf
FB		 2561 if (dc->is_br)
2562 break;
2563 /* if the next PC is different, we abort now */
2564 if (dc->pc != (last_pc + 4))
2565 break;
d39c0b99
FB		 2566 /* if we reach a page boundary, we stop generation so that the
2567 PC of a TT_TFAULT exception is always in the right page */
2568 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
2569 break;
e80cfcfc
FB		 2570 /* if single step mode, we generate only one instruction and
2571 generate an exception */
2572 if (env->singlestep_enabled) {
3475187d 2573 gen_jmp_im(dc->pc);
e80cfcfc
FB		 2574 gen_op_movl_T0_0();
2575 gen_op_exit_tb();
2576 break;
2577 }
cf495bcf
FB		 2578 } while ((gen_opc_ptr < gen_opc_end) &&
2579 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 2580
2581 exit_gen_loop:
72cbca10
FB		 2582 if (!dc->is_br) {
2583 if (dc->pc != DYNAMIC_PC &&
2584 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
2585 /* static PC and NPC: we can use direct chaining */
83469015 2586 gen_branch(dc, (long)tb, dc->pc, dc->npc);
72cbca10
FB		 2587 } else {
2588 if (dc->pc != DYNAMIC_PC)
3475187d 2589 gen_jmp_im(dc->pc);
72cbca10
FB		 2590 save_npc(dc);
2591 gen_op_movl_T0_0();
2592 gen_op_exit_tb();
2593 }
2594 }
cf495bcf 2595 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 2596 if (spc) {
2597 j = gen_opc_ptr - gen_opc_buf;
2598 lj++;
2599 while (lj <= j)
2600 gen_opc_instr_start[lj++] = 0;
2601 tb->size = 0;
2602#if 0
2603 if (loglevel > 0) {
2604 page_dump(logfile);
2605 }
2606#endif
c3278b7b
FB		 2607 gen_opc_jump_pc[0] = dc->jump_pc[0];
2608 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 2609 } else {
e80cfcfc 2610 tb->size = last_pc + 4 - pc_start;
e8af50a3 2611 }
7a3f1944 2612#ifdef DEBUG_DISAS
e19e89a5 2613 if (loglevel & CPU_LOG_TB_IN_ASM) {
cf495bcf 2614 fprintf(logfile, "--------------\n");
0fa85d43
FB		 2615 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2616 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
cf495bcf 2617 fprintf(logfile, "\n");
e19e89a5
FB		 2618 if (loglevel & CPU_LOG_TB_OP) {
2619 fprintf(logfile, "OP:\n");
2620 dump_ops(gen_opc_buf, gen_opparam_buf);
2621 fprintf(logfile, "\n");
2622 }
cf495bcf 2623 }
7a3f1944 2624#endif
cf495bcf 2625 return 0;
7a3f1944
FB		 2626}
2627
cf495bcf 2628int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 2629{
e8af50a3 2630 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 2631}
2632
cf495bcf 2633int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 2634{
e8af50a3 2635 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 2636}
2637
e80cfcfc 2638extern int ram_size;
cf495bcf 2639
e80cfcfc
FB		 2640void cpu_reset(CPUSPARCState *env)
2641{
cf495bcf 2642 memset(env, 0, sizeof(*env));
bb05683b 2643 tlb_flush(env, 1);
cf495bcf
FB		 2644 env->cwp = 0;
2645 env->wim = 1;
2646 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 2647#if defined(CONFIG_USER_ONLY)
cf495bcf 2648 env->user_mode_only = 1;
e8af50a3 2649#else
e8af50a3 2650 env->psrs = 1;
0bee699e 2651 env->psrps = 1;
e80cfcfc 2652 env->gregs[1] = ram_size;
3475187d 2653#ifdef TARGET_SPARC64
83469015 2654 env->pstate = PS_PRIV;
3475187d 2655 env->version = GET_VER(env);
83469015 2656 env->pc = 0x1fff0000000ULL;
3475187d
FB		 2657#else
2658 env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
83469015 2659 env->pc = 0xffd00000;
3475187d 2660#endif
83469015 2661 env->npc = env->pc + 4;
e8af50a3 2662#endif
e80cfcfc
FB		 2663}
2664
2665CPUSPARCState *cpu_sparc_init(void)
2666{
2667 CPUSPARCState *env;
2668
2669 cpu_exec_init();
2670
2671 if (!(env = malloc(sizeof(CPUSPARCState))))
2672 return (NULL);
7496f526 2673 cpu_single_env = env;
e80cfcfc 2674 cpu_reset(env);
cf495bcf 2675 return (env);
7a3f1944
FB		 2676}
2677
2678#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
2679
7fe48483
FB		 2680void cpu_dump_state(CPUState *env, FILE *f,
2681 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2682 int flags)
7a3f1944 2683{
cf495bcf
FB		 2684 int i, x;
2685
af7bf89b 2686 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 2687 cpu_fprintf(f, "General Registers:\n");
cf495bcf 2688 for (i = 0; i < 4; i++)
af7bf89b 2689 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 2690 cpu_fprintf(f, "\n");
cf495bcf 2691 for (; i < 8; i++)
af7bf89b 2692 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 2693 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf
FB		 2694 for (x = 0; x < 3; x++) {
2695 for (i = 0; i < 4; i++)
af7bf89b 2696 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB		 2697 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
2698 env->regwptr[i + x * 8]);
7fe48483 2699 cpu_fprintf(f, "\n");
cf495bcf 2700 for (; i < 8; i++)
af7bf89b 2701 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB		 2702 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
2703 env->regwptr[i + x * 8]);
7fe48483 2704 cpu_fprintf(f, "\n");
cf495bcf 2705 }
7fe48483 2706 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 2707 for (i = 0; i < 32; i++) {
2708 if ((i & 3) == 0)
7fe48483
FB		 2709 cpu_fprintf(f, "%%f%02d:", i);
2710 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 2711 if ((i & 3) == 3)
7fe48483 2712 cpu_fprintf(f, "\n");
e8af50a3 2713 }
7fe48483 2714 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
cf495bcf
FB		 2715 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
2716 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
e8af50a3
FB		 2717 env->psrs?'S':'-', env->psrps?'P':'-',
2718 env->psret?'E':'-', env->wim);
3475187d 2719 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 2720}
edfcbd99 2721
e80cfcfc 2722#if defined(CONFIG_USER_ONLY)
d785e6be 2723target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB		 2724{
2725 return addr;
2726}
658138bc 2727
e80cfcfc 2728#else
af7bf89b
FB		 2729extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
2730 int *access_index, target_ulong address, int rw,
0fa85d43
FB		 2731 int is_user);
2732
d785e6be 2733target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 2734{
af7bf89b 2735 target_phys_addr_t phys_addr;
e80cfcfc
FB		 2736 int prot, access_index;
2737
2738 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
2739 return -1;
2740 return phys_addr;
2741}
2742#endif
2743
658138bc
FB		 2744void helper_flush(target_ulong addr)
2745{
2746 addr &= ~7;
2747 tb_invalidate_page_range(addr, addr + 8);
2748}
Mirror of https://git.qemu.org/git/qemu.git