[thirdparty/u-boot.git] / Bindings / firmware / xilinx / xlnx,zynqmp-firmware.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx firmware driver

maintainers:
  - Nava kishore Manne <nava.kishore.manne@amd.com>

description: The zynqmp-firmware node describes the interface to platform
  firmware. ZynqMP has an interface to communicate with secure firmware.
  Firmware driver provides an interface to firmware APIs. Interface APIs
  can be used by any driver to communicate to PMUFW(Platform Management Unit).
  These requests include clock management, pin control, device control,
  power management service, FPGA service and other platform management
  services.

properties:
  compatible:
    oneOf:
      - description: For implementations complying for Zynq Ultrascale+ MPSoC.
        const: xlnx,zynqmp-firmware

      - description: For implementations complying for Versal.
        const: xlnx,versal-firmware

  method:
    description: |
                 The method of calling the PM-API firmware layer.
                 Permitted values are.
                 - "smc" : SMC #0, following the SMCCC
                 - "hvc" : HVC #0, following the SMCCC

    $ref: /schemas/types.yaml#/definitions/string-array
    enum:
      - smc
      - hvc

  "#power-domain-cells":
    const: 1

  versal_fpga:
    $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
    description: Compatible of the FPGA device.
    type: object

  zynqmp-aes:
    $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
    description: The ZynqMP AES-GCM hardened cryptographic accelerator is
      used to encrypt or decrypt the data with provided key and initialization
      vector.
    type: object

  clock-controller:
    $ref: /schemas/clock/xlnx,versal-clk.yaml#
    description: The clock controller is a hardware block of Xilinx versal
      clock tree. It reads required input clock frequencies from the devicetree
      and acts as clock provider for all clock consumers of PS clocks.list of
      clock specifiers which are external input clocks to the given clock
      controller.
    type: object

required:
  - compatible

additionalProperties: false

examples:
  - |
    #include <dt-bindings/power/xlnx-zynqmp-power.h>
    firmware {
      zynqmp_firmware: zynqmp-firmware {
        #power-domain-cells = <1>;
        };
    };

    sata {
      power-domains = <&zynqmp_firmware PD_SATA>;
    };

    versal-firmware {
      compatible = "xlnx,versal-firmware";
      method = "smc";

      versal_fpga: versal_fpga {
        compatible = "xlnx,versal-fpga";
      };

      xlnx_aes: zynqmp-aes {
        compatible = "xlnx,zynqmp-aes";
      };

      versal_clk: clock-controller {
        #clock-cells = <1>;
        compatible = "xlnx,versal-clk";
        clocks = <&ref>, <&pl_alt_ref>;
        clock-names = "ref", "pl_alt_ref";
      };
    };

...
Commit	Line	Data
53633a89 TR	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Xilinx firmware driver
	8
	9	maintainers:
	10	- Nava kishore Manne <nava.kishore.manne@amd.com>
	11
	12	description: The zynqmp-firmware node describes the interface to platform
	13	firmware. ZynqMP has an interface to communicate with secure firmware.
	14	Firmware driver provides an interface to firmware APIs. Interface APIs
	15	can be used by any driver to communicate to PMUFW(Platform Management Unit).
	16	These requests include clock management, pin control, device control,
	17	power management service, FPGA service and other platform management
	18	services.
	19
	20	properties:
	21	compatible:
	22	oneOf:
	23	- description: For implementations complying for Zynq Ultrascale+ MPSoC.
	24	const: xlnx,zynqmp-firmware
	25
	26	- description: For implementations complying for Versal.
	27	const: xlnx,versal-firmware
	28
	29	method:
	30	description: \|
	31	The method of calling the PM-API firmware layer.
	32	Permitted values are.
	33	- "smc" : SMC #0, following the SMCCC
	34	- "hvc" : HVC #0, following the SMCCC
	35
	36	$ref: /schemas/types.yaml#/definitions/string-array
	37	enum:
	38	- smc
	39	- hvc
	40
	41	"#power-domain-cells":
	42	const: 1
	43
	44	versal_fpga:
	45	$ref: /schemas/fpga/xlnx,versal-fpga.yaml#
	46	description: Compatible of the FPGA device.
	47	type: object
	48
	49	zynqmp-aes:
	50	$ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
	51	description: The ZynqMP AES-GCM hardened cryptographic accelerator is
	52	used to encrypt or decrypt the data with provided key and initialization
	53	vector.
	54	type: object
	55
	56	clock-controller:
	57	$ref: /schemas/clock/xlnx,versal-clk.yaml#
	58	description: The clock controller is a hardware block of Xilinx versal
	59	clock tree. It reads required input clock frequencies from the devicetree
	60	and acts as clock provider for all clock consumers of PS clocks.list of
	61	clock specifiers which are external input clocks to the given clock
	62	controller.
	63	type: object
	64
65	required:
66	- compatible
67
68	additionalProperties: false
69
70	examples:
71	- \|
72	#include <dt-bindings/power/xlnx-zynqmp-power.h>
73	firmware {
74	zynqmp_firmware: zynqmp-firmware {
75	#power-domain-cells = <1>;
76	};
77	};
78
79	sata {
80	power-domains = <&zynqmp_firmware PD_SATA>;
81	};
82
83	versal-firmware {
84	compatible = "xlnx,versal-firmware";
85	method = "smc";
86
87	versal_fpga: versal_fpga {
88	compatible = "xlnx,versal-fpga";
89	};
90
91	xlnx_aes: zynqmp-aes {
92	compatible = "xlnx,zynqmp-aes";
93	};
94
95	versal_clk: clock-controller {
96	#clock-cells = <1>;
97	compatible = "xlnx,versal-clk";
93743d24 TR	98	clocks = <&ref>, <&pl_alt_ref>;
93743d24 TR	99	clock-names = "ref", "pl_alt_ref";
53633a89 TR	100	};
	101	};
	102
	103	...