[thirdparty/u-boot.git] / arch / arm / dts / imx93-11x11-evk-u-boot.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2022 NXP
 */

#include "imx93-u-boot.dtsi"

/ {
	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&wdog3>;
		bootph-pre-ram;
		bootph-some-ram;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

&{/soc@0} {
	bootph-all;
	bootph-pre-ram;
};

&lpi2c2 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <400000>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_lpi2c2>;
	pinctrl-1 = <&pinctrl_lpi2c2>;
	status = "okay";

	pmic@25 {
		compatible = "nxp,pca9451a";
		reg = <0x25>;
		interrupt-parent = <&pcal6524>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			buck1: BUCK1 {
				regulator-name = "BUCK1";
				regulator-min-microvolt = <650000>;
				regulator-max-microvolt = <2237500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck2: BUCK2 {
				regulator-name = "BUCK2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck4: BUCK4{
				regulator-name = "BUCK4";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5: BUCK5{
				regulator-name = "BUCK5";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6: BUCK6 {
				regulator-name = "BUCK6";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1: LDO1 {
				regulator-name = "LDO1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4: LDO4 {
				regulator-name = "LDO4";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5: LDO5 {
				regulator-name = "LDO5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};

	pcal6524: gpio@22 {
		compatible = "nxp,pcal6524";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pcal6524>;
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gpio3>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
	};

	adp5585gpio: gpio@34 {
		compatible = "adp5585";
		reg = <0x34>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&aips1 {
	bootph-pre-ram;
	bootph-all;
};

&aips2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&aips3 {
	bootph-pre-ram;
	bootph-some-ram;
};

&iomuxc {
	bootph-pre-ram;
	bootph-some-ram;

	pinctrl_lpi2c2: lpi2c2grp {
		fsl,pins = <
			MX93_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e
			MX93_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e
		>;
	};

	pinctrl_pcal6524: pcal6524grp {
		fsl,pins = <
			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
		>;
	};
};

&reg_usdhc2_vmmc {
	u-boot,off-on-delay-us = <20000>;
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_reg_usdhc2_vmmc {
	bootph-pre-ram;
};

&pinctrl_uart1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc2_gpio {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio3 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio4 {
	bootph-pre-ram;
	bootph-some-ram;
};

&lpuart1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&usdhc1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&usdhc2 {
	bootph-pre-ram;
	bootph-some-ram;
	fsl,signal-voltage-switch-extra-delay-ms = <8>;
};

&lpi2c2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
	bootph-pre-ram;
	bootph-some-ram;
};

&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_lpi2c2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&fec {
	phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <15>;
	phy-reset-post-delay = <100>;
};

&ethphy1 {
	reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
	reset-assert-us = <15000>;
	reset-deassert-us = <100000>;
};

&s4muap {
	bootph-pre-ram;
	bootph-some-ram;
	status = "okay";
};

&clk {
	bootph-all;
	bootph-pre-ram;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-rates;
	/delete-property/ assigned-clock-parents;
};

&osc_32k {
	bootph-all;
	bootph-pre-ram;
};

&osc_24m {
	bootph-all;
	bootph-pre-ram;
};

&clk_ext1 {
	bootph-all;
	bootph-pre-ram;
};
Commit	Line	Data
86a17970 PF	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2022 NXP
	4	*/
	5
bfbef0e8 MO	6	#include "imx93-u-boot.dtsi"
bfbef0e8 MO	7
86a17970 PF	8	/ {
	9	wdt-reboot {
	10	compatible = "wdt-reboot";
	11	wdt = <&wdog3>;
8c103c33	12	bootph-pre-ram;
fb2bdc4e	13	bootph-some-ram;
86a17970 PF	14	};
86a17970 PF	15
86a17970 PF	16	firmware {
	17	optee {
	18	compatible = "linaro,optee-tz";
	19	method = "smc";
	20	};
	21	};
	22	};
	23
	24	&{/soc@0} {
8c103c33 SG	25	bootph-all;
8c103c33 SG	26	bootph-pre-ram;
86a17970 PF	27	};
86a17970 PF	28
6bc68ed4 PF	29	&lpi2c2 {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32	clock-frequency = <400000>;
	33	pinctrl-names = "default", "sleep";
	34	pinctrl-0 = <&pinctrl_lpi2c2>;
	35	pinctrl-1 = <&pinctrl_lpi2c2>;
	36	status = "okay";
	37
	38	pmic@25 {
	39	compatible = "nxp,pca9451a";
	40	reg = <0x25>;
	41	interrupt-parent = <&pcal6524>;
	42	interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
	43
	44	regulators {
	45	buck1: BUCK1 {
	46	regulator-name = "BUCK1";
	47	regulator-min-microvolt = <650000>;
	48	regulator-max-microvolt = <2237500>;
	49	regulator-boot-on;
	50	regulator-always-on;
	51	regulator-ramp-delay = <3125>;
	52	};
	53
	54	buck2: BUCK2 {
	55	regulator-name = "BUCK2";
	56	regulator-min-microvolt = <600000>;
	57	regulator-max-microvolt = <2187500>;
	58	regulator-boot-on;
	59	regulator-always-on;
	60	regulator-ramp-delay = <3125>;
	61	};
	62
	63	buck4: BUCK4{
	64	regulator-name = "BUCK4";
	65	regulator-min-microvolt = <600000>;
	66	regulator-max-microvolt = <3400000>;
	67	regulator-boot-on;
	68	regulator-always-on;
	69	};
	70
	71	buck5: BUCK5{
	72	regulator-name = "BUCK5";
	73	regulator-min-microvolt = <600000>;
	74	regulator-max-microvolt = <3400000>;
	75	regulator-boot-on;
	76	regulator-always-on;
	77	};
	78
	79	buck6: BUCK6 {
	80	regulator-name = "BUCK6";
	81	regulator-min-microvolt = <600000>;
	82	regulator-max-microvolt = <3400000>;
	83	regulator-boot-on;
	84	regulator-always-on;
	85	};
	86
	87	ldo1: LDO1 {
	88	regulator-name = "LDO1";
	89	regulator-min-microvolt = <1600000>;
	90	regulator-max-microvolt = <3300000>;
	91	regulator-boot-on;
	92	regulator-always-on;
93	};
94
95	ldo4: LDO4 {
96	regulator-name = "LDO4";
97	regulator-min-microvolt = <800000>;
98	regulator-max-microvolt = <3300000>;
99	regulator-boot-on;
100	regulator-always-on;
101	};
102
103	ldo5: LDO5 {
104	regulator-name = "LDO5";
105	regulator-min-microvolt = <1800000>;
106	regulator-max-microvolt = <3300000>;
107	regulator-boot-on;
108	regulator-always-on;
109	};
110	};
111	};
112
113	pcal6524: gpio@22 {
114	compatible = "nxp,pcal6524";
115	pinctrl-names = "default";
116	pinctrl-0 = <&pinctrl_pcal6524>;
117	reg = <0x22>;
118	gpio-controller;
119	#gpio-cells = <2>;
120	interrupt-controller;
121	#interrupt-cells = <2>;
122	interrupt-parent = <&gpio3>;
123	interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
124	};
125
126	adp5585gpio: gpio@34 {
127	compatible = "adp5585";
128	reg = <0x34>;
129	gpio-controller;
130	#gpio-cells = <2>;
131	};
132	};
133
86a17970	134	&aips1 {
8c103c33 SG	135	bootph-pre-ram;
8c103c33 SG	136	bootph-all;
86a17970 PF	137	};
	138
	139	&aips2 {
8c103c33	140	bootph-pre-ram;
fb2bdc4e	141	bootph-some-ram;
86a17970 PF	142	};
	143
	144	&aips3 {
8c103c33	145	bootph-pre-ram;
fb2bdc4e	146	bootph-some-ram;
86a17970 PF	147	};
	148
	149	&iomuxc {
8c103c33	150	bootph-pre-ram;
fb2bdc4e	151	bootph-some-ram;
6bc68ed4 PF	152
	153	pinctrl_lpi2c2: lpi2c2grp {
	154	fsl,pins = <
	155	MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
	156	MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
	157	>;
	158	};
	159
	160	pinctrl_pcal6524: pcal6524grp {
	161	fsl,pins = <
	162	MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
	163	>;
	164	};
86a17970 PF	165	};
	166
	167	&reg_usdhc2_vmmc {
	168	u-boot,off-on-delay-us = <20000>;
8c103c33	169	bootph-pre-ram;
fb2bdc4e	170	bootph-some-ram;
86a17970 PF	171	};
	172
	173	&pinctrl_reg_usdhc2_vmmc {
8c103c33	174	bootph-pre-ram;
86a17970 PF	175	};
	176
	177	&pinctrl_uart1 {
8c103c33	178	bootph-pre-ram;
fb2bdc4e	179	bootph-some-ram;
86a17970 PF	180	};
	181
	182	&pinctrl_usdhc2_gpio {
8c103c33	183	bootph-pre-ram;
fb2bdc4e	184	bootph-some-ram;
86a17970 PF	185	};
	186
	187	&pinctrl_usdhc2 {
8c103c33	188	bootph-pre-ram;
fb2bdc4e	189	bootph-some-ram;
86a17970 PF	190	};
	191
	192	&gpio1 {
8c103c33	193	bootph-pre-ram;
fb2bdc4e	194	bootph-some-ram;
86a17970 PF	195	};
	196
	197	&gpio2 {
8c103c33	198	bootph-pre-ram;
fb2bdc4e	199	bootph-some-ram;
86a17970 PF	200	};
	201
	202	&gpio3 {
8c103c33	203	bootph-pre-ram;
fb2bdc4e	204	bootph-some-ram;
86a17970 PF	205	};
	206
	207	&gpio4 {
8c103c33	208	bootph-pre-ram;
fb2bdc4e	209	bootph-some-ram;
86a17970 PF	210	};
	211
	212	&lpuart1 {
8c103c33	213	bootph-pre-ram;
fb2bdc4e	214	bootph-some-ram;
86a17970 PF	215	};
	216
	217	&usdhc1 {
8c103c33	218	bootph-pre-ram;
fb2bdc4e	219	bootph-some-ram;
86a17970 PF	220	};
	221
	222	&usdhc2 {
8c103c33	223	bootph-pre-ram;
fb2bdc4e	224	bootph-some-ram;
86a17970 PF	225	fsl,signal-voltage-switch-extra-delay-ms = <8>;
	226	};
	227
	228	&lpi2c2 {
8c103c33	229	bootph-pre-ram;
fb2bdc4e	230	bootph-some-ram;
86a17970 PF	231	};
	232
	233	&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
8c103c33	234	bootph-pre-ram;
fb2bdc4e	235	bootph-some-ram;
86a17970 PF	236	};
	237
	238	&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
8c103c33	239	bootph-pre-ram;
fb2bdc4e	240	bootph-some-ram;
86a17970 PF	241	};
	242
	243	&pinctrl_lpi2c2 {
8c103c33	244	bootph-pre-ram;
fb2bdc4e	245	bootph-some-ram;
86a17970 PF	246	};
	247
	248	&fec {
	249	phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
	250	phy-reset-duration = <15>;
	251	phy-reset-post-delay = <100>;
	252	};
	253
86a17970 PF	254	&ethphy1 {
	255	reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
	256	reset-assert-us = <15000>;
	257	reset-deassert-us = <100000>;
	258	};
	259
86a17970	260	&s4muap {
8c103c33	261	bootph-pre-ram;
fb2bdc4e	262	bootph-some-ram;
86a17970 PF	263	status = "okay";
86a17970 PF	264	};
de2f7f54 SS	265
	266	&clk {
	267	bootph-all;
	268	bootph-pre-ram;
	269	/delete-property/ assigned-clocks;
	270	/delete-property/ assigned-clock-rates;
	271	/delete-property/ assigned-clock-parents;
	272	};
	273
	274	&osc_32k {
	275	bootph-all;
	276	bootph-pre-ram;
	277	};
	278
	279	&osc_24m {
	280	bootph-all;
	281	bootph-pre-ram;
	282	};
	283
	284	&clk_ext1 {
	285	bootph-all;
	286	bootph-pre-ram;
	287	};