[thirdparty/u-boot.git] / arch / arm / dts / k3-am654-icssg2.dtso

// SPDX-License-Identifier: GPL-2.0
/**
 * DT overlay for enabling ICSSG2 on AM654 EVM
 *
 * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/net/ti-dp83867.h>
#include "k3-pinctrl.h"

&{/} {
	aliases {
		ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
		ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
	};

	/* Ethernet node on PRU-ICSSG2 */
	icssg2_eth: icssg2-eth {
		compatible = "ti,am654-icssg-prueth";
		pinctrl-names = "default";
		pinctrl-0 = <&icssg2_rgmii_pins_default>;
		sram = <&msmc_ram>;
		ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
			<&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
		firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
				"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
				"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
				"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
				"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
				"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";

		ti,pruss-gp-mux-sel = <2>,      /* MII mode */
				      <2>,
				      <2>,
				      <2>,	/* MII mode */
				      <2>,
				      <2>;

		ti,mii-g-rt = <&icssg2_mii_g_rt>;
		ti,mii-rt = <&icssg2_mii_rt>;
		ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;

		interrupt-parent = <&icssg2_intc>;
		interrupts = <24 0 2>, <25 1 3>;
		interrupt-names = "tx_ts0", "tx_ts1";

		dmas = <&main_udmap 0xc300>, /* egress slice 0 */
		       <&main_udmap 0xc301>, /* egress slice 0 */
		       <&main_udmap 0xc302>, /* egress slice 0 */
		       <&main_udmap 0xc303>, /* egress slice 0 */
		       <&main_udmap 0xc304>, /* egress slice 1 */
		       <&main_udmap 0xc305>, /* egress slice 1 */
		       <&main_udmap 0xc306>, /* egress slice 1 */
		       <&main_udmap 0xc307>, /* egress slice 1 */
		       <&main_udmap 0x4300>, /* ingress slice 0 */
		       <&main_udmap 0x4301>; /* ingress slice 1 */

		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
			    "rx0", "rx1";
		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			icssg2_emac0: port@0 {
				reg = <0>;
				phy-handle = <&icssg2_phy0>;
				phy-mode = "rgmii-id";
				ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
				/* Filled in by bootloader */
				local-mac-address = [00 00 00 00 00 00];
			};
			icssg2_emac1: port@1 {
				reg = <1>;
				phy-handle = <&icssg2_phy1>;
				phy-mode = "rgmii-id";
				ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
				/* Filled in by bootloader */
				local-mac-address = [00 00 00 00 00 00];
			};
		};
	};
};

&main_pmx0 {

	icssg2_mdio_pins_default: icssg2-mdio-default-pins {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
			AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
		>;
	};

	icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
			AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
			AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
			AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
			AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
			AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
			AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
			AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
			AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
			AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
			AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
			AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */

			AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
			AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
			AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
			AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
			AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
			AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
			AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
			AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
			AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
			AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
			AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
			AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
		>;
	};
};

&icssg2_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&icssg2_mdio_pins_default>;
	#address-cells = <1>;
	#size-cells = <0>;

	icssg2_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};

	icssg2_phy1: ethernet-phy@3 {
		reg = <3>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};
};
Commit	Line	Data
a672d306 MDA	1	// SPDX-License-Identifier: GPL-2.0
	2	/**
	3	* DT overlay for enabling ICSSG2 on AM654 EVM
	4	*
	5	* Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
	6	*/
	7
	8	/dts-v1/;
	9	/plugin/;
	10
	11	#include <dt-bindings/net/ti-dp83867.h>
	12	#include "k3-pinctrl.h"
	13
	14	&{/} {
	15	aliases {
	16	ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
	17	ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
	18	};
	19
	20	/* Ethernet node on PRU-ICSSG2 */
	21	icssg2_eth: icssg2-eth {
	22	compatible = "ti,am654-icssg-prueth";
	23	pinctrl-names = "default";
	24	pinctrl-0 = <&icssg2_rgmii_pins_default>;
	25	sram = <&msmc_ram>;
	26	ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
	27	<&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
	28	firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
	29	"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
	30	"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
	31	"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
	32	"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
	33	"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
	34
	35	ti,pruss-gp-mux-sel = <2>, /* MII mode */
	36	<2>,
	37	<2>,
	38	<2>, /* MII mode */
	39	<2>,
	40	<2>;
	41
	42	ti,mii-g-rt = <&icssg2_mii_g_rt>;
	43	ti,mii-rt = <&icssg2_mii_rt>;
	44	ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
	45
	46	interrupt-parent = <&icssg2_intc>;
	47	interrupts = <24 0 2>, <25 1 3>;
	48	interrupt-names = "tx_ts0", "tx_ts1";
	49
	50	dmas = <&main_udmap 0xc300>, /* egress slice 0 */
	51	<&main_udmap 0xc301>, /* egress slice 0 */
	52	<&main_udmap 0xc302>, /* egress slice 0 */
	53	<&main_udmap 0xc303>, /* egress slice 0 */
	54	<&main_udmap 0xc304>, /* egress slice 1 */
	55	<&main_udmap 0xc305>, /* egress slice 1 */
	56	<&main_udmap 0xc306>, /* egress slice 1 */
	57	<&main_udmap 0xc307>, /* egress slice 1 */
	58	<&main_udmap 0x4300>, /* ingress slice 0 */
	59	<&main_udmap 0x4301>; /* ingress slice 1 */
	60
	61	dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
	62	"tx1-0", "tx1-1", "tx1-2", "tx1-3",
	63	"rx0", "rx1";
	64	ethernet-ports {
65	#address-cells = <1>;
66	#size-cells = <0>;
67	icssg2_emac0: port@0 {
68	reg = <0>;
69	phy-handle = <&icssg2_phy0>;
70	phy-mode = "rgmii-id";
71	ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
72	/* Filled in by bootloader */
73	local-mac-address = [00 00 00 00 00 00];
74	};
75	icssg2_emac1: port@1 {
76	reg = <1>;
77	phy-handle = <&icssg2_phy1>;
78	phy-mode = "rgmii-id";
79	ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
80	/* Filled in by bootloader */
81	local-mac-address = [00 00 00 00 00 00];
82	};
83	};
84	};
85	};
86
87	&main_pmx0 {
88
89	icssg2_mdio_pins_default: icssg2-mdio-default-pins {
90	pinctrl-single,pins = <
91	AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
92	AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
93	>;
94	};
95
96	icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
97	pinctrl-single,pins = <
98	AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
99	AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
100	AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
101	AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
102	AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
103	AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
104	AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
105	AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
106	AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
107	AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
108	AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
109	AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */
110
111	AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
112	AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
113	AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
114	AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
115	AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
116	AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
117	AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
118	AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
119	AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
120	AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
121	AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
122	AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
123	>;
124	};
125	};
126
127	&icssg2_mdio {
128	status = "okay";
129	pinctrl-names = "default";
130	pinctrl-0 = <&icssg2_mdio_pins_default>;
131	#address-cells = <1>;
132	#size-cells = <0>;
133
134	icssg2_phy0: ethernet-phy@0 {
135	reg = <0>;
136	ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
137	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
138	};
139
140	icssg2_phy1: ethernet-phy@3 {
141	reg = <3>;
142	ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
143	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
144	};
145	};