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7ce134b7 MZ |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Copyright 2019 Toradex | |
4 | */ | |
5 | ||
6 | #include <common.h> | |
9a3b4ceb | 7 | #include <cpu_func.h> |
5255932f | 8 | #include <init.h> |
401d1c4f | 9 | #include <asm/global_data.h> |
7ce134b7 MZ |
10 | |
11 | #include <asm/arch/clock.h> | |
12 | #include <asm/arch/imx8-pins.h> | |
13 | #include <asm/arch/iomux.h> | |
99ac6c76 | 14 | #include <firmware/imx/sci/sci.h> |
8d916e5c | 15 | #include <asm/arch/snvs_security_sc.h> |
7ce134b7 MZ |
16 | #include <asm/arch/sys_proto.h> |
17 | #include <asm/gpio.h> | |
18 | #include <asm/io.h> | |
9fb625ce | 19 | #include <env.h> |
7ce134b7 MZ |
20 | #include <errno.h> |
21 | #include <linux/libfdt.h> | |
22 | ||
23 | #include "../common/tdx-cfg-block.h" | |
24 | ||
25 | DECLARE_GLOBAL_DATA_PTR; | |
26 | ||
27 | #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ | |
28 | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ | |
29 | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ | |
30 | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) | |
31 | ||
32 | static iomux_cfg_t uart3_pads[] = { | |
33 | SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), | |
34 | SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), | |
35 | /* Transceiver FORCEOFF# signal, mux to use pull-up */ | |
36 | SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL), | |
37 | }; | |
38 | ||
39 | static void setup_iomux_uart(void) | |
40 | { | |
41 | imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); | |
42 | } | |
43 | ||
7689fc55 | 44 | static int is_imx8dx(void) |
89f7d08b | 45 | { |
7689fc55 | 46 | u32 val = 0; |
aa6e698a | 47 | int sc_err = sc_misc_otp_fuse_read(-1, 6, &val); |
89f7d08b | 48 | |
fdd529fa | 49 | if (!sc_err) { |
89f7d08b | 50 | /* DX has two A35 cores disabled */ |
7689fc55 | 51 | return (val & 0xf) != 0x0; |
89f7d08b | 52 | } |
7689fc55 MK |
53 | return false; |
54 | } | |
89f7d08b | 55 | |
7689fc55 MK |
56 | void board_mem_get_layout(u64 *phys_sdram_1_start, |
57 | u64 *phys_sdram_1_size, | |
58 | u64 *phys_sdram_2_start, | |
59 | u64 *phys_sdram_2_size) | |
60 | { | |
89f7d08b | 61 | *phys_sdram_1_start = PHYS_SDRAM_1; |
7689fc55 | 62 | if (is_imx8dx()) |
89f7d08b IO |
63 | /* Our DX based SKUs only have 1 GB RAM */ |
64 | *phys_sdram_1_size = SZ_1G; | |
65 | else | |
66 | *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; | |
67 | *phys_sdram_2_start = PHYS_SDRAM_2; | |
68 | *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; | |
69 | } | |
70 | ||
7ce134b7 MZ |
71 | int board_early_init_f(void) |
72 | { | |
73 | sc_pm_clock_rate_t rate; | |
aa6e698a | 74 | int err; |
7ce134b7 MZ |
75 | |
76 | /* | |
77 | * This works around that having only UART3 up the baudrate is 1.2M | |
78 | * instead of 115.2k. Set UART0 clock root to 80 MHz | |
79 | */ | |
80 | rate = 80000000; | |
81 | err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); | |
aa6e698a | 82 | if (err) |
7ce134b7 MZ |
83 | return 0; |
84 | ||
64b5f469 AG |
85 | /* Set UART3 clock root to 80 MHz and enable it */ |
86 | rate = SC_80MHZ; | |
87 | err = sc_pm_setup_uart(SC_R_UART_3, rate); | |
aa6e698a | 88 | if (err) |
7ce134b7 MZ |
89 | return 0; |
90 | ||
91 | setup_iomux_uart(); | |
92 | ||
93 | return 0; | |
94 | } | |
95 | ||
7ce134b7 MZ |
96 | #if IS_ENABLED(CONFIG_FEC_MXC) |
97 | #include <miiphy.h> | |
98 | ||
99 | int board_phy_config(struct phy_device *phydev) | |
100 | { | |
101 | if (phydev->drv->config) | |
102 | phydev->drv->config(phydev); | |
103 | ||
104 | return 0; | |
105 | } | |
106 | #endif | |
107 | ||
de666551 AC |
108 | static void select_dt_from_module_version(void) |
109 | { | |
110 | /* | |
111 | * The dtb filename is constructed from ${soc}-colibri-${fdt_board}.dtb. | |
112 | * Set soc depending on the used SoC. | |
113 | */ | |
114 | if (is_imx8dx()) | |
115 | env_set("soc", "imx8dx"); | |
116 | else | |
117 | env_set("soc", "imx8qxp"); | |
118 | } | |
119 | ||
7ce134b7 MZ |
120 | int board_init(void) |
121 | { | |
8d916e5c AC |
122 | if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) { |
123 | int ret = snvs_security_sc_init(); | |
124 | ||
125 | if (ret) | |
126 | return ret; | |
127 | } | |
128 | ||
7ce134b7 MZ |
129 | return 0; |
130 | } | |
131 | ||
7ce134b7 | 132 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
b75d8dc5 | 133 | int ft_board_setup(void *blob, struct bd_info *bd) |
7ce134b7 MZ |
134 | { |
135 | return ft_common_board_setup(blob, bd); | |
136 | } | |
137 | #endif | |
138 | ||
139 | int board_mmc_get_env_dev(int devno) | |
140 | { | |
141 | return devno; | |
142 | } | |
143 | ||
144 | int board_late_init(void) | |
145 | { | |
146 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
147 | /* TODO move to common */ | |
148 | env_set("board_name", "Colibri iMX8QXP"); | |
149 | env_set("board_rev", "v1.0"); | |
150 | #endif | |
151 | ||
ce38c643 AC |
152 | build_info(); |
153 | ||
de666551 AC |
154 | select_dt_from_module_version(); |
155 | ||
7ce134b7 MZ |
156 | return 0; |
157 | } |