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12b43d51 WD |
1 | /* |
2 | * (C) Copyright 2004 | |
3 | * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | #define CONFIG_MPC8220 1 | |
32 | #define CONFIG_SORCERY 1 /* Sorcery board */ | |
33 | ||
34 | /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to | |
35 | determine the CPU speed. */ | |
36 | #define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ | |
37 | #define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */ | |
38 | ||
39 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
40 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
41 | ||
42 | #define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ | |
43 | ||
44 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
45 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
46 | #endif | |
47 | ||
48 | /* | |
49 | * Serial console configuration | |
50 | */ | |
51 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC */ | |
52 | ||
53 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
54 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
55 | ||
7680c140 WD |
56 | /* PCI */ |
57 | #define CONFIG_PCI 1 | |
58 | #define CONFIG_PCI_PNP 1 | |
59 | ||
60 | #define CONFIG_PCI_MEM_BUS 0x80000000 | |
61 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
62 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
63 | ||
64 | #define CONFIG_PCI_IO_BUS 0x71000000 | |
65 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
66 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
67 | ||
68 | #define CONFIG_PCI_CFG_BUS 0x70000000 | |
69 | #define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS | |
70 | #define CONFIG_PCI_CFG_SIZE 0x01000000 | |
71 | ||
12b43d51 WD |
72 | /* |
73 | * Supported commands | |
74 | */ | |
75 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ | |
76 | CFG_CMD_BOOTD | \ | |
77 | CFG_CMD_CACHE | \ | |
78 | CFG_CMD_DHCP | \ | |
79 | CFG_CMD_DIAG | \ | |
80 | CFG_CMD_ELF | \ | |
81 | CFG_CMD_I2C | \ | |
82 | CFG_CMD_NET | \ | |
83 | CFG_CMD_NFS | \ | |
7680c140 | 84 | CFG_CMD_PCI | \ |
12b43d51 WD |
85 | CFG_CMD_PING | \ |
86 | CFG_CMD_REGINFO | \ | |
87 | CFG_CMD_SDRAM | \ | |
88 | CFG_CMD_SNTP | \ | |
89 | 0) | |
90 | ||
91 | /* CFG_CMD_MII | \ */ | |
12b43d51 WD |
92 | /* CFG_CMD_USB | \ */ |
93 | ||
94 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
95 | #include <cmd_confdefs.h> | |
96 | ||
97 | /* | |
98 | * Default Environment | |
99 | */ | |
100 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
101 | #define CONFIG_HOSTNAME sorcery | |
102 | ||
103 | #define CONFIG_PREBOOT "echo;" \ | |
104 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
105 | "echo" | |
106 | ||
107 | #undef CONFIG_BOOTARGS | |
108 | ||
109 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
110 | "netdev=eth0\0" \ | |
111 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
112 | "nfsroot=$serverip:$rootpath\0" \ | |
113 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
114 | "addip=setenv bootargs $bootargs " \ | |
115 | "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ | |
116 | ":$hostname:$netdev:off panic=1\0" \ | |
117 | "flash_nfs=run nfsargs addip;" \ | |
118 | "bootm $kernel_addr\0" \ | |
119 | "flash_self=run ramargs addip;" \ | |
120 | "bootm $kernel_addr $ramdisk_addr\0" \ | |
121 | "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \ | |
122 | "rootpath=/opt/eldk/ppc_82xx\0" \ | |
123 | "bootfile=/tftpboot/sorcery/uImage\0" \ | |
124 | "kernel_addr=FFE00000\0" \ | |
125 | "ramdisk_addr=FFB00000\0" \ | |
126 | "" | |
127 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
128 | ||
129 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
130 | ||
131 | #define CONFIG_NET_MULTI | |
7680c140 | 132 | #define CONFIG_EEPRO100 |
12b43d51 WD |
133 | |
134 | /* | |
135 | * I2C configuration | |
136 | */ | |
137 | #define CONFIG_HARD_I2C 1 | |
138 | #define CFG_I2C_MODULE 1 | |
139 | #define CFG_I2C_SPEED 100000 /* 100 kHz */ | |
140 | #define CFG_I2C_SLAVE 0x7F | |
141 | ||
142 | /* Use the HUSH parser */ | |
143 | #define CFG_HUSH_PARSER | |
144 | #ifdef CFG_HUSH_PARSER | |
145 | #define CFG_PROMPT_HUSH_PS2 "> " | |
146 | #endif | |
147 | ||
148 | /* | |
149 | * Flexbus Chipselect configuration | |
3c2b3d45 WD |
150 | * Beware: Some CS# seem to be mandatory (if these CS# are not set, |
151 | * board can hang-up in unpredictable place). | |
12b43d51 WD |
152 | * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS# |
153 | */ | |
154 | ||
155 | /* Flash */ | |
156 | #define CFG_CS0_BASE 0xf800 | |
157 | #define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */ | |
7680c140 | 158 | #define CFG_CS0_CTRL 0x001019c0 |
12b43d51 WD |
159 | |
160 | /* NVM */ | |
7680c140 WD |
161 | #define CFG_CS1_BASE 0xf7e8 |
162 | #define CFG_CS1_MASK 0x00040000 /* 256K */ | |
163 | #define CFG_CS1_CTRL 0x00101940 /* 8bit port size */ | |
12b43d51 WD |
164 | |
165 | /* Atlas2 + Gemini */ | |
7680c140 WD |
166 | #define CFG_CS2_BASE 0xf7e7 |
167 | #define CFG_CS2_MASK 0x00010000 /* 64K*/ | |
168 | #define CFG_CS2_CTRL 0x001011c0 /* 16bit port size */ | |
12b43d51 WD |
169 | |
170 | /* CAN Controller */ | |
7680c140 | 171 | #define CFG_CS3_BASE 0xf7e6 |
12b43d51 | 172 | #define CFG_CS3_MASK 0x00010000 /* 64K */ |
7680c140 | 173 | #define CFG_CS3_CTRL 0x00102140 /* 8Bit port size */ |
12b43d51 WD |
174 | |
175 | /* Foreign interface */ | |
7680c140 | 176 | #define CFG_CS4_BASE 0xf7e5 |
12b43d51 | 177 | #define CFG_CS4_MASK 0x00010000 /* 64K */ |
7680c140 | 178 | #define CFG_CS4_CTRL 0x00101dc0 /* 16bit port size */ |
12b43d51 | 179 | |
7680c140 WD |
180 | /* CPLD */ |
181 | #define CFG_CS5_BASE 0xf7e4 | |
182 | #define CFG_CS5_MASK 0x00010000 /* 64K */ | |
183 | #define CFG_CS5_CTRL 0x001000c0 /* 16bit port size */ | |
12b43d51 WD |
184 | |
185 | #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) | |
7680c140 | 186 | #define CFG_FLASH_BASE (CFG_FLASH0_BASE) |
12b43d51 | 187 | |
7680c140 WD |
188 | #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ |
189 | #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
12b43d51 WD |
190 | |
191 | #define CFG_FLASH_CFI_DRIVER | |
192 | #define CFG_FLASH_CFI | |
193 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ | |
194 | CFG_FLASH_BASE+0x04000000 } /* two banks */ | |
195 | ||
196 | /* | |
197 | * Environment settings | |
198 | */ | |
199 | #define CFG_ENV_IS_IN_FLASH 1 | |
7680c140 WD |
200 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000000 - 0x40000) |
201 | #define CFG_ENV_SIZE 0x4000 /* 16K */ | |
202 | #define CFG_ENV_SECT_SIZE 0x20000 | |
203 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + 0x20000) | |
204 | #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE | |
12b43d51 WD |
205 | |
206 | #define CONFIG_ENV_OVERWRITE 1 | |
207 | ||
208 | #if defined CFG_ENV_IS_IN_FLASH | |
209 | #undef CFG_ENV_IS_IN_NVRAM | |
210 | #undef CFG_ENV_IS_IN_EEPROM | |
211 | #elif defined CFG_ENV_IS_IN_NVRAM | |
212 | #undef CFG_ENV_IS_IN_FLASH | |
213 | #undef CFG_ENV_IS_IN_EEPROM | |
214 | #elif defined CFG_ENV_IS_IN_EEPROM | |
215 | #undef CFG_ENV_IS_IN_NVRAM | |
216 | #undef CFG_ENV_IS_IN_FLASH | |
217 | #endif | |
218 | ||
219 | /* | |
220 | * Memory map | |
221 | */ | |
222 | #define CFG_MBAR 0xF0000000 | |
223 | #define CFG_SDRAM_BASE 0x00000000 | |
224 | #define CFG_DEFAULT_MBAR 0x80000000 | |
225 | #define CFG_SRAM_BASE (CFG_MBAR + 0x20000) | |
226 | #define CFG_SRAM_SIZE 0x8000 | |
227 | ||
228 | /* Use SRAM until RAM will be available */ | |
229 | #define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) | |
230 | #define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ | |
231 | ||
232 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
233 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
234 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
235 | ||
236 | #define CFG_MONITOR_BASE TEXT_BASE | |
237 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
238 | # define CFG_RAMBOOT 1 | |
239 | #endif | |
240 | ||
241 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
242 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
243 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
244 | ||
245 | /* SDRAM configuration (for SPD) */ | |
246 | #define CFG_SDRAM_TOTAL_BANKS 1 | |
247 | #define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */ | |
248 | #define CFG_SDRAM_SPD_SIZE 0x100 | |
249 | #define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */ | |
250 | ||
7680c140 WD |
251 | /* SDRAM drive strength register (for SSTL_2 class II)*/ |
252 | #define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \ | |
253 | (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ | |
254 | (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \ | |
255 | (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \ | |
256 | (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT)) | |
257 | ||
12b43d51 WD |
258 | /* |
259 | * Ethernet configuration | |
260 | */ | |
261 | #define CONFIG_MPC8220_FEC 1 | |
262 | #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ | |
263 | #define CONFIG_PHY_ADDR 0x1F | |
264 | ||
265 | /* | |
266 | * Miscellaneous configurable options | |
267 | */ | |
268 | #define CFG_LONGHELP /* undef to save memory */ | |
269 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
270 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
271 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
272 | #else | |
273 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
274 | #endif | |
275 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
276 | #define CFG_MAXARGS 16 /* max number of command args */ | |
277 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
278 | ||
279 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
280 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
281 | ||
282 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
283 | ||
284 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
285 | ||
286 | /* | |
287 | * Various low-level settings | |
288 | */ | |
3c2b3d45 WD |
289 | #define CFG_HID0_INIT 0 |
290 | #define CFG_HID0_FINAL 0 | |
12b43d51 | 291 | |
7680c140 WD |
292 | /* |
293 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI | |
294 | #define CFG_HID0_FINAL HID0_ICE | |
295 | */ | |
296 | ||
12b43d51 | 297 | #endif /* __CONFIG_H */ |