[thirdparty/u-boot.git] / post / drivers / memory.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 */

#include <common.h>
#include <log.h>
#include <asm/global_data.h>

/* Memory test
 *
 * General observations:
 * o The recommended test sequence is to test the data lines: if they are
 *   broken, nothing else will work properly.  Then test the address
 *   lines.  Finally, test the cells in the memory now that the test
 *   program knows that the address and data lines work properly.
 *   This sequence also helps isolate and identify what is faulty.
 *
 * o For the address line test, it is a good idea to use the base
 *   address of the lowest memory location, which causes a '1' bit to
 *   walk through a field of zeros on the address lines and the highest
 *   memory location, which causes a '0' bit to walk through a field of
 *   '1's on the address line.
 *
 * o Floating buses can fool memory tests if the test routine writes
 *   a value and then reads it back immediately.  The problem is, the
 *   write will charge the residual capacitance on the data bus so the
 *   bus retains its state briefely.  When the test program reads the
 *   value back immediately, the capacitance of the bus can allow it
 *   to read back what was written, even though the memory circuitry
 *   is broken.  To avoid this, the test program should write a test
 *   pattern to the target location, write a different pattern elsewhere
 *   to charge the residual capacitance in a differnt manner, then read
 *   the target location back.
 *
 * o Always read the target location EXACTLY ONCE and save it in a local
 *   variable.  The problem with reading the target location more than
 *   once is that the second and subsequent reads may work properly,
 *   resulting in a failed test that tells the poor technician that
 *   "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
 *   doesn't help him one bit and causes puzzled phone calls.  Been there,
 *   done that.
 *
 * Data line test:
 * ---------------
 * This tests data lines for shorts and opens by forcing adjacent data
 * to opposite states. Because the data lines could be routed in an
 * arbitrary manner the must ensure test patterns ensure that every case
 * is tested. By using the following series of binary patterns every
 * combination of adjacent bits is test regardless of routing.
 *
 *     ...101010101010101010101010
 *     ...110011001100110011001100
 *     ...111100001111000011110000
 *     ...111111110000000011111111
 *
 * Carrying this out, gives us six hex patterns as follows:
 *
 *     0xaaaaaaaaaaaaaaaa
 *     0xcccccccccccccccc
 *     0xf0f0f0f0f0f0f0f0
 *     0xff00ff00ff00ff00
 *     0xffff0000ffff0000
 *     0xffffffff00000000
 *
 * To test for short and opens to other signals on our boards, we
 * simply test with the 1's complemnt of the paterns as well, resulting
 * in twelve patterns total.
 *
 * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
 * written to a different address in case the data lines are floating.
 * Thus, if a byte lane fails, you will see part of the special
 * pattern in that byte lane when the test runs.  For example, if the
 * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
 * (for the 'a' test pattern).
 *
 * Address line test:
 * ------------------
 *  This function performs a test to verify that all the address lines
 *  hooked up to the RAM work properly.  If there is an address line
 *  fault, it usually shows up as two different locations in the address
 *  map (related by the faulty address line) mapping to one physical
 *  memory storage location.  The artifact that shows up is writing to
 *  the first location "changes" the second location.
 *
 * To test all address lines, we start with the given base address and
 * xor the address with a '1' bit to flip one address line.  For each
 * test, we shift the '1' bit left to test the next address line.
 *
 * In the actual code, we start with address sizeof(ulong) since our
 * test pattern we use is a ulong and thus, if we tried to test lower
 * order address bits, it wouldn't work because our pattern would
 * overwrite itself.
 *
 * Example for a 4 bit address space with the base at 0000:
 *   0000 <- base
 *   0001 <- test 1
 *   0010 <- test 2
 *   0100 <- test 3
 *   1000 <- test 4
 * Example for a 4 bit address space with the base at 0010:
 *   0010 <- base
 *   0011 <- test 1
 *   0000 <- (below the base address, skipped)
 *   0110 <- test 2
 *   1010 <- test 3
 *
 * The test locations are successively tested to make sure that they are
 * not "mirrored" onto the base address due to a faulty address line.
 * Note that the base and each test location are related by one address
 * line flipped.  Note that the base address need not be all zeros.
 *
 * Memory tests 1-4:
 * -----------------
 * These tests verify RAM using sequential writes and reads
 * to/from RAM. There are several test cases that use different patterns to
 * verify RAM. Each test case fills a region of RAM with one pattern and
 * then reads the region back and compares its contents with the pattern.
 * The following patterns are used:
 *
 *  1a) zero pattern (0x00000000)
 *  1b) negative pattern (0xffffffff)
 *  1c) checkerboard pattern (0x55555555)
 *  1d) checkerboard pattern (0xaaaaaaaa)
 *  2)  bit-flip pattern ((1 << (offset % 32))
 *  3)  address pattern (offset)
 *  4)  address pattern (~offset)
 *
 * Being run in normal mode, the test verifies only small 4Kb
 * regions of RAM around each 1Mb boundary. For example, for 64Mb
 * RAM the following areas are verified: 0x00000000-0x00000800,
 * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
 * 0x04000000. If the test is run in slow-test mode, it verifies
 * the whole RAM.
 */

#include <post.h>
#include <watchdog.h>

#if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS)

DECLARE_GLOBAL_DATA_PTR;

/*
 * Define INJECT_*_ERRORS for testing error detection in the presence of
 * _good_ hardware.
 */
#undef  INJECT_DATA_ERRORS
#undef  INJECT_ADDRESS_ERRORS

#ifdef INJECT_DATA_ERRORS
#warning "Injecting data line errors for testing purposes"
#endif

#ifdef INJECT_ADDRESS_ERRORS
#warning "Injecting address line errors for testing purposes"
#endif


/*
 * This function performs a double word move from the data at
 * the source pointer to the location at the destination pointer.
 * This is helpful for testing memory on processors which have a 64 bit
 * wide data bus.
 *
 * On those PowerPC with FPU, use assembly and a floating point move:
 * this does a 64 bit move.
 *
 * For other processors, let the compiler generate the best code it can.
 */
static void move64(const unsigned long long *src, unsigned long long *dest)
{
	*dest = *src;
}

/*
 * This is 64 bit wide test patterns.  Note that they reside in ROM
 * (which presumably works) and the tests write them to RAM which may
 * not work.
 *
 * The "otherpattern" is written to drive the data bus to values other
 * than the test pattern.  This is for detecting floating bus lines.
 *
 */
const static unsigned long long pattern[] = {
	0xaaaaaaaaaaaaaaaaULL,
	0xccccccccccccccccULL,
	0xf0f0f0f0f0f0f0f0ULL,
	0xff00ff00ff00ff00ULL,
	0xffff0000ffff0000ULL,
	0xffffffff00000000ULL,
	0x00000000ffffffffULL,
	0x0000ffff0000ffffULL,
	0x00ff00ff00ff00ffULL,
	0x0f0f0f0f0f0f0f0fULL,
	0x3333333333333333ULL,
	0x5555555555555555ULL
};
const unsigned long long otherpattern = 0x0123456789abcdefULL;


static int memory_post_dataline(unsigned long long * pmem)
{
	unsigned long long temp64 = 0;
	int num_patterns = ARRAY_SIZE(pattern);
	int i;
	unsigned int hi, lo, pathi, patlo;
	int ret = 0;

	for ( i = 0; i < num_patterns; i++) {
		move64(&(pattern[i]), pmem++);
		/*
		 * Put a different pattern on the data lines: otherwise they
		 * may float long enough to read back what we wrote.
		 */
		move64(&otherpattern, pmem--);
		move64(pmem, &temp64);

#ifdef INJECT_DATA_ERRORS
		temp64 ^= 0x00008000;
#endif

		if (temp64 != pattern[i]){
			pathi = (pattern[i]>>32) & 0xffffffff;
			patlo = pattern[i] & 0xffffffff;

			hi = (temp64>>32) & 0xffffffff;
			lo = temp64 & 0xffffffff;

			post_log("Memory (data line) error at %08x, "
				  "wrote %08x%08x, read %08x%08x !\n",
					  pmem, pathi, patlo, hi, lo);
			ret = -1;
		}
	}
	return ret;
}

static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
{
	ulong *target;
	ulong *end;
	ulong readback;
	ulong xor;
	int   ret = 0;

	end = (ulong *)((ulong)base + size);	/* pointer arith! */
	xor = 0;
	for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
		target = (ulong *)((ulong)testaddr ^ xor);
		if((target >= base) && (target < end)) {
			*testaddr = ~*target;
			readback  = *target;

#ifdef INJECT_ADDRESS_ERRORS
			if(xor == 0x00008000) {
				readback = *testaddr;
			}
#endif
			if(readback == *testaddr) {
				post_log("Memory (address line) error at %08x<->%08x, "
					"XOR value %08x !\n",
					testaddr, target, xor);
				ret = -1;
			}
		}
	}
	return ret;
}

static int memory_post_test1(unsigned long start,
			      unsigned long size,
			      unsigned long val)
{
	unsigned long i;
	ulong *mem = (ulong *) start;
	ulong readback;
	int ret = 0;

	for (i = 0; i < size / sizeof (ulong); i++) {
		mem[i] = val;
		if (i % 1024 == 0)
			WATCHDOG_RESET();
	}

	for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
		readback = mem[i];
		if (readback != val) {
			post_log("Memory error at %08x, "
				  "wrote %08x, read %08x !\n",
					  mem + i, val, readback);

			ret = -1;
			break;
		}
		if (i % 1024 == 0)
			WATCHDOG_RESET();
	}

	return ret;
}

static int memory_post_test2(unsigned long start, unsigned long size)
{
	unsigned long i;
	ulong *mem = (ulong *) start;
	ulong readback;
	int ret = 0;

	for (i = 0; i < size / sizeof (ulong); i++) {
		mem[i] = 1 << (i % 32);
		if (i % 1024 == 0)
			WATCHDOG_RESET();
	}

	for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
		readback = mem[i];
		if (readback != (1 << (i % 32))) {
			post_log("Memory error at %08x, "
				  "wrote %08x, read %08x !\n",
					  mem + i, 1 << (i % 32), readback);

			ret = -1;
			break;
		}
		if (i % 1024 == 0)
			WATCHDOG_RESET();
	}

	return ret;
}

static int memory_post_test3(unsigned long start, unsigned long size)
{
	unsigned long i;
	ulong *mem = (ulong *) start;
	ulong readback;
	int ret = 0;

	for (i = 0; i < size / sizeof (ulong); i++) {
		mem[i] = i;
		if (i % 1024 == 0)
			WATCHDOG_RESET();
	}

	for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
		readback = mem[i];
		if (readback != i) {
			post_log("Memory error at %08x, "
				  "wrote %08x, read %08x !\n",
					  mem + i, i, readback);

			ret = -1;
			break;
		}
		if (i % 1024 == 0)
			WATCHDOG_RESET();
	}

	return ret;
}

static int memory_post_test4(unsigned long start, unsigned long size)
{
	unsigned long i;
	ulong *mem = (ulong *) start;
	ulong readback;
	int ret = 0;

	for (i = 0; i < size / sizeof (ulong); i++) {
		mem[i] = ~i;
		if (i % 1024 == 0)
			WATCHDOG_RESET();
	}

	for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
		readback = mem[i];
		if (readback != ~i) {
			post_log("Memory error at %08x, "
				  "wrote %08x, read %08x !\n",
					  mem + i, ~i, readback);

			ret = -1;
			break;
		}
		if (i % 1024 == 0)
			WATCHDOG_RESET();
	}

	return ret;
}

static int memory_post_test_lines(unsigned long start, unsigned long size)
{
	int ret = 0;

	ret = memory_post_dataline((unsigned long long *)start);
	WATCHDOG_RESET();
	if (!ret)
		ret = memory_post_addrline((ulong *)start, (ulong *)start,
				size);
	WATCHDOG_RESET();
	if (!ret)
		ret = memory_post_addrline((ulong *)(start+size-8),
				(ulong *)start, size);
	WATCHDOG_RESET();

	return ret;
}

static int memory_post_test_patterns(unsigned long start, unsigned long size)
{
	int ret = 0;

	ret = memory_post_test1(start, size, 0x00000000);
	WATCHDOG_RESET();
	if (!ret)
		ret = memory_post_test1(start, size, 0xffffffff);
	WATCHDOG_RESET();
	if (!ret)
		ret = memory_post_test1(start, size, 0x55555555);
	WATCHDOG_RESET();
	if (!ret)
		ret = memory_post_test1(start, size, 0xaaaaaaaa);
	WATCHDOG_RESET();
	if (!ret)
		ret = memory_post_test2(start, size);
	WATCHDOG_RESET();
	if (!ret)
		ret = memory_post_test3(start, size);
	WATCHDOG_RESET();
	if (!ret)
		ret = memory_post_test4(start, size);
	WATCHDOG_RESET();

	return ret;
}

static int memory_post_test_regions(unsigned long start, unsigned long size)
{
	unsigned long i;
	int ret = 0;

	for (i = 0; i < (size >> 20) && (!ret); i++) {
		if (!ret)
			ret = memory_post_test_patterns(start + (i << 20),
				0x800);
		if (!ret)
			ret = memory_post_test_patterns(start + (i << 20) +
				0xff800, 0x800);
	}

	return ret;
}

static int memory_post_tests(unsigned long start, unsigned long size)
{
	int ret = 0;

	ret = memory_post_test_lines(start, size);
	if (!ret)
		ret = memory_post_test_patterns(start, size);

	return ret;
}

/*
 * !! this is only valid, if you have contiguous memory banks !!
 */
__attribute__((weak))
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
	struct bd_info *bd = gd->bd;

	*vstart = CONFIG_SYS_SDRAM_BASE;
	*size = (gd->ram_size >= 256 << 20 ?
			256 << 20 : gd->ram_size) - (1 << 20);

	/* Limit area to be tested with the board info struct */
	if ((*vstart) + (*size) > (ulong)bd)
		*size = (ulong)bd - *vstart;

	return 0;
}

__attribute__((weak))
int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
	return 1;
}

__attribute__((weak))
int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
	return 0;
}

__attribute__((weak))
void arch_memory_failure_handle(void)
{
	return;
}

int memory_regions_post_test(int flags)
{
	int ret = 0;
	phys_addr_t phys_offset = 0;
	u32 memsize, vstart;

	arch_memory_test_prepare(&vstart, &memsize, &phys_offset);

	ret = memory_post_test_lines(vstart, memsize);
	if (!ret)
		ret = memory_post_test_regions(vstart, memsize);

	return ret;
}

int memory_post_test(int flags)
{
	int ret = 0;
	phys_addr_t phys_offset = 0;
	u32 memsize, vstart;

	arch_memory_test_prepare(&vstart, &memsize, &phys_offset);

	do {
		if (flags & POST_SLOWTEST) {
			ret = memory_post_tests(vstart, memsize);
		} else {			/* POST_NORMAL */
			ret = memory_post_test_regions(vstart, memsize);
		}
	} while (!ret &&
		!arch_memory_test_advance(&vstart, &memsize, &phys_offset));

	arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
	if (ret)
		arch_memory_failure_handle();

	return ret;
}

#endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
ad5bb451 WD	2	/*
	3	* (C) Copyright 2002
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ad5bb451 WD	5	*/
	6
	7	#include <common.h>
f7ae49fc	8	#include <log.h>
401d1c4f	9	#include <asm/global_data.h>
ad5bb451 WD	10
	11	/* Memory test
	12	*
	13	* General observations:
	14	* o The recommended test sequence is to test the data lines: if they are
	15	* broken, nothing else will work properly. Then test the address
	16	* lines. Finally, test the cells in the memory now that the test
	17	* program knows that the address and data lines work properly.
	18	* This sequence also helps isolate and identify what is faulty.
	19	*
	20	* o For the address line test, it is a good idea to use the base
	21	* address of the lowest memory location, which causes a '1' bit to
	22	* walk through a field of zeros on the address lines and the highest
	23	* memory location, which causes a '0' bit to walk through a field of
	24	* '1's on the address line.
	25	*
	26	* o Floating buses can fool memory tests if the test routine writes
	27	* a value and then reads it back immediately. The problem is, the
	28	* write will charge the residual capacitance on the data bus so the
	29	* bus retains its state briefely. When the test program reads the
	30	* value back immediately, the capacitance of the bus can allow it
	31	* to read back what was written, even though the memory circuitry
	32	* is broken. To avoid this, the test program should write a test
	33	* pattern to the target location, write a different pattern elsewhere
	34	* to charge the residual capacitance in a differnt manner, then read
	35	* the target location back.
	36	*
	37	* o Always read the target location EXACTLY ONCE and save it in a local
	38	* variable. The problem with reading the target location more than
	39	* once is that the second and subsequent reads may work properly,
	40	* resulting in a failed test that tells the poor technician that
	41	* "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
	42	* doesn't help him one bit and causes puzzled phone calls. Been there,
	43	* done that.
	44	*
	45	* Data line test:
	46	* ---------------
	47	* This tests data lines for shorts and opens by forcing adjacent data
	48	* to opposite states. Because the data lines could be routed in an
	49	* arbitrary manner the must ensure test patterns ensure that every case
	50	* is tested. By using the following series of binary patterns every
	51	* combination of adjacent bits is test regardless of routing.
	52	*
	53	* ...101010101010101010101010
	54	* ...110011001100110011001100
	55	* ...111100001111000011110000
	56	* ...111111110000000011111111
	57	*
	58	* Carrying this out, gives us six hex patterns as follows:
	59	*
	60	* 0xaaaaaaaaaaaaaaaa
	61	* 0xcccccccccccccccc
	62	* 0xf0f0f0f0f0f0f0f0
	63	* 0xff00ff00ff00ff00
	64	* 0xffff0000ffff0000
	65	* 0xffffffff00000000
	66	*
	67	* To test for short and opens to other signals on our boards, we
	68	* simply test with the 1's complemnt of the paterns as well, resulting
	69	* in twelve patterns total.
	70	*
	71	* After writing a test pattern. a special pattern 0x0123456789ABCDEF is
	72	* written to a different address in case the data lines are floating.
	73	* Thus, if a byte lane fails, you will see part of the special
74	* pattern in that byte lane when the test runs. For example, if the
75	* xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
76	* (for the 'a' test pattern).
77	*
78	* Address line test:
79	* ------------------
80	* This function performs a test to verify that all the address lines
81	* hooked up to the RAM work properly. If there is an address line
82	* fault, it usually shows up as two different locations in the address
83	* map (related by the faulty address line) mapping to one physical
84	* memory storage location. The artifact that shows up is writing to
85	* the first location "changes" the second location.
86	*
87	* To test all address lines, we start with the given base address and
88	* xor the address with a '1' bit to flip one address line. For each
89	* test, we shift the '1' bit left to test the next address line.
90	*
91	* In the actual code, we start with address sizeof(ulong) since our
92	* test pattern we use is a ulong and thus, if we tried to test lower
93	* order address bits, it wouldn't work because our pattern would
94	* overwrite itself.
95	*
96	* Example for a 4 bit address space with the base at 0000:
97	* 0000 <- base
98	* 0001 <- test 1
99	* 0010 <- test 2
100	* 0100 <- test 3
101	* 1000 <- test 4
102	* Example for a 4 bit address space with the base at 0010:
103	* 0010 <- base
104	* 0011 <- test 1
105	* 0000 <- (below the base address, skipped)
106	* 0110 <- test 2
107	* 1010 <- test 3
108	*
109	* The test locations are successively tested to make sure that they are
110	* not "mirrored" onto the base address due to a faulty address line.
111	* Note that the base and each test location are related by one address
112	* line flipped. Note that the base address need not be all zeros.
113	*
114	* Memory tests 1-4:
115	* -----------------
116	* These tests verify RAM using sequential writes and reads
117	* to/from RAM. There are several test cases that use different patterns to
118	* verify RAM. Each test case fills a region of RAM with one pattern and
119	* then reads the region back and compares its contents with the pattern.
120	* The following patterns are used:
121	*
122	* 1a) zero pattern (0x00000000)
123	* 1b) negative pattern (0xffffffff)
124	* 1c) checkerboard pattern (0x55555555)
125	* 1d) checkerboard pattern (0xaaaaaaaa)
126	* 2) bit-flip pattern ((1 << (offset % 32))
127	* 3) address pattern (offset)
128	* 4) address pattern (~offset)
129	*
130	* Being run in normal mode, the test verifies only small 4Kb
131	* regions of RAM around each 1Mb boundary. For example, for 64Mb
132	* RAM the following areas are verified: 0x00000000-0x00000800,
133	* 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
134	* 0x04000000. If the test is run in slow-test mode, it verifies
135	* the whole RAM.
136	*/
137
ad5bb451 WD	138	#include <post.h>
	139	#include <watchdog.h>
	140
8d3fcb5e	141	#if CONFIG_POST & (CONFIG_SYS_POST_MEMORY \| CONFIG_SYS_POST_MEM_REGIONS)
ad5bb451 WD	142
	143	DECLARE_GLOBAL_DATA_PTR;
	144
	145	/*
	146	* Define INJECT_*_ERRORS for testing error detection in the presence of
	147	* _good_ hardware.
	148	*/
	149	#undef INJECT_DATA_ERRORS
	150	#undef INJECT_ADDRESS_ERRORS
	151
	152	#ifdef INJECT_DATA_ERRORS
	153	#warning "Injecting data line errors for testing purposes"
	154	#endif
	155
	156	#ifdef INJECT_ADDRESS_ERRORS
	157	#warning "Injecting address line errors for testing purposes"
	158	#endif
	159
	160
	161	/*
	162	* This function performs a double word move from the data at
	163	* the source pointer to the location at the destination pointer.
	164	* This is helpful for testing memory on processors which have a 64 bit
	165	* wide data bus.
	166	*
	167	* On those PowerPC with FPU, use assembly and a floating point move:
	168	* this does a 64 bit move.
	169	*
	170	* For other processors, let the compiler generate the best code it can.
	171	*/
44b4dbed	172	static void move64(const unsigned long long src, unsigned long long dest)
ad5bb451	173	{
ad5bb451	174	dest = src;
ad5bb451 WD	175	}
	176
	177	/*
	178	* This is 64 bit wide test patterns. Note that they reside in ROM
	179	* (which presumably works) and the tests write them to RAM which may
	180	* not work.
	181	*
	182	* The "otherpattern" is written to drive the data bus to values other
	183	* than the test pattern. This is for detecting floating bus lines.
	184	*
	185	*/
	186	const static unsigned long long pattern[] = {
	187	0xaaaaaaaaaaaaaaaaULL,
	188	0xccccccccccccccccULL,
	189	0xf0f0f0f0f0f0f0f0ULL,
	190	0xff00ff00ff00ff00ULL,
	191	0xffff0000ffff0000ULL,
	192	0xffffffff00000000ULL,
	193	0x00000000ffffffffULL,
	194	0x0000ffff0000ffffULL,
	195	0x00ff00ff00ff00ffULL,
	196	0x0f0f0f0f0f0f0f0fULL,
	197	0x3333333333333333ULL,
	198	0x5555555555555555ULL
	199	};
	200	const unsigned long long otherpattern = 0x0123456789abcdefULL;
	201
	202
	203	static int memory_post_dataline(unsigned long long * pmem)
	204	{
	205	unsigned long long temp64 = 0;
d2397817	206	int num_patterns = ARRAY_SIZE(pattern);
ad5bb451 WD	207	int i;
	208	unsigned int hi, lo, pathi, patlo;
	209	int ret = 0;
	210
	211	for ( i = 0; i < num_patterns; i++) {
44b4dbed	212	move64(&(pattern[i]), pmem++);
ad5bb451 WD	213	/*
	214	* Put a different pattern on the data lines: otherwise they
	215	* may float long enough to read back what we wrote.
	216	*/
44b4dbed	217	move64(&otherpattern, pmem--);
ad5bb451 WD	218	move64(pmem, &temp64);
	219
	220	#ifdef INJECT_DATA_ERRORS
	221	temp64 ^= 0x00008000;
	222	#endif
	223
	224	if (temp64 != pattern[i]){
	225	pathi = (pattern[i]>>32) & 0xffffffff;
	226	patlo = pattern[i] & 0xffffffff;
	227
	228	hi = (temp64>>32) & 0xffffffff;
	229	lo = temp64 & 0xffffffff;
	230
e2ee3014	231	post_log("Memory (data line) error at %08x, "
ad5bb451 WD	232	"wrote %08x%08x, read %08x%08x !\n",
	233	pmem, pathi, patlo, hi, lo);
	234	ret = -1;
	235	}
	236	}
	237	return ret;
	238	}
	239
	240	static int memory_post_addrline(ulong testaddr, ulong base, ulong size)
	241	{
	242	ulong *target;
	243	ulong *end;
	244	ulong readback;
	245	ulong xor;
	246	int ret = 0;
	247
	248	end = (ulong )((ulong)base + size); / pointer arith! */
	249	xor = 0;
	250	for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
	251	target = (ulong *)((ulong)testaddr ^ xor);
	252	if((target >= base) && (target < end)) {
	253	testaddr = ~target;
	254	readback = *target;
	255
	256	#ifdef INJECT_ADDRESS_ERRORS
	257	if(xor == 0x00008000) {
	258	readback = *testaddr;
	259	}
	260	#endif
	261	if(readback == *testaddr) {
ca51d057	262	post_log("Memory (address line) error at %08x<->%08x, "
53677ef1	263	"XOR value %08x !\n",
ad5bb451 WD	264	testaddr, target, xor);
	265	ret = -1;
	266	}
	267	}
	268	}
	269	return ret;
	270	}
	271
ca51d057	272	static int memory_post_test1(unsigned long start,
ad5bb451 WD	273	unsigned long size,
	274	unsigned long val)
	275	{
	276	unsigned long i;
	277	ulong mem = (ulong ) start;
	278	ulong readback;
	279	int ret = 0;
	280
	281	for (i = 0; i < size / sizeof (ulong); i++) {
	282	mem[i] = val;
	283	if (i % 1024 == 0)
ca51d057	284	WATCHDOG_RESET();
ad5bb451 WD	285	}
ad5bb451 WD	286
ca51d057	287	for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
ad5bb451 WD	288	readback = mem[i];
ad5bb451 WD	289	if (readback != val) {
ca51d057	290	post_log("Memory error at %08x, "
ad5bb451 WD	291	"wrote %08x, read %08x !\n",
	292	mem + i, val, readback);
	293
	294	ret = -1;
	295	break;
	296	}
	297	if (i % 1024 == 0)
ca51d057	298	WATCHDOG_RESET();
ad5bb451 WD	299	}
	300
	301	return ret;
	302	}
	303
ca51d057	304	static int memory_post_test2(unsigned long start, unsigned long size)
ad5bb451 WD	305	{
	306	unsigned long i;
	307	ulong mem = (ulong ) start;
	308	ulong readback;
	309	int ret = 0;
	310
	311	for (i = 0; i < size / sizeof (ulong); i++) {
	312	mem[i] = 1 << (i % 32);
	313	if (i % 1024 == 0)
ca51d057	314	WATCHDOG_RESET();
ad5bb451 WD	315	}
ad5bb451 WD	316
ca51d057	317	for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
ad5bb451 WD	318	readback = mem[i];
ad5bb451 WD	319	if (readback != (1 << (i % 32))) {
ca51d057	320	post_log("Memory error at %08x, "
ad5bb451 WD	321	"wrote %08x, read %08x !\n",
	322	mem + i, 1 << (i % 32), readback);
	323
	324	ret = -1;
	325	break;
	326	}
	327	if (i % 1024 == 0)
ca51d057	328	WATCHDOG_RESET();
ad5bb451 WD	329	}
	330
	331	return ret;
	332	}
	333
ca51d057	334	static int memory_post_test3(unsigned long start, unsigned long size)
ad5bb451 WD	335	{
	336	unsigned long i;
	337	ulong mem = (ulong ) start;
	338	ulong readback;
	339	int ret = 0;
	340
	341	for (i = 0; i < size / sizeof (ulong); i++) {
	342	mem[i] = i;
	343	if (i % 1024 == 0)
ca51d057	344	WATCHDOG_RESET();
ad5bb451 WD	345	}
ad5bb451 WD	346
ca51d057	347	for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
ad5bb451 WD	348	readback = mem[i];
ad5bb451 WD	349	if (readback != i) {
ca51d057	350	post_log("Memory error at %08x, "
ad5bb451 WD	351	"wrote %08x, read %08x !\n",
	352	mem + i, i, readback);
	353
	354	ret = -1;
	355	break;
	356	}
	357	if (i % 1024 == 0)
ca51d057	358	WATCHDOG_RESET();
ad5bb451 WD	359	}
	360
	361	return ret;
	362	}
	363
ca51d057	364	static int memory_post_test4(unsigned long start, unsigned long size)
ad5bb451 WD	365	{
	366	unsigned long i;
	367	ulong mem = (ulong ) start;
	368	ulong readback;
	369	int ret = 0;
	370
	371	for (i = 0; i < size / sizeof (ulong); i++) {
	372	mem[i] = ~i;
	373	if (i % 1024 == 0)
ca51d057	374	WATCHDOG_RESET();
ad5bb451 WD	375	}
ad5bb451 WD	376
ca51d057	377	for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
ad5bb451 WD	378	readback = mem[i];
ad5bb451 WD	379	if (readback != ~i) {
ca51d057	380	post_log("Memory error at %08x, "
ad5bb451 WD	381	"wrote %08x, read %08x !\n",
	382	mem + i, ~i, readback);
	383
	384	ret = -1;
	385	break;
	386	}
	387	if (i % 1024 == 0)
ca51d057	388	WATCHDOG_RESET();
ad5bb451 WD	389	}
	390
	391	return ret;
	392	}
	393
8d3fcb5e	394	static int memory_post_test_lines(unsigned long start, unsigned long size)
ad5bb451 WD	395	{
	396	int ret = 0;
	397
8d3fcb5e	398	ret = memory_post_dataline((unsigned long long *)start);
ca51d057 VL	399	WATCHDOG_RESET();
	400	if (!ret)
	401	ret = memory_post_addrline((ulong )start, (ulong )start,
8d3fcb5e	402	size);
ca51d057 VL	403	WATCHDOG_RESET();
ca51d057 VL	404	if (!ret)
8d3fcb5e VL	405	ret = memory_post_addrline((ulong *)(start+size-8),
8d3fcb5e VL	406	(ulong *)start, size);
ca51d057	407	WATCHDOG_RESET();
8d3fcb5e VL	408
	409	return ret;
	410	}
	411
	412	static int memory_post_test_patterns(unsigned long start, unsigned long size)
	413	{
	414	int ret = 0;
	415
	416	ret = memory_post_test1(start, size, 0x00000000);
ca51d057 VL	417	WATCHDOG_RESET();
	418	if (!ret)
	419	ret = memory_post_test1(start, size, 0xffffffff);
	420	WATCHDOG_RESET();
	421	if (!ret)
	422	ret = memory_post_test1(start, size, 0x55555555);
	423	WATCHDOG_RESET();
	424	if (!ret)
	425	ret = memory_post_test1(start, size, 0xaaaaaaaa);
	426	WATCHDOG_RESET();
	427	if (!ret)
	428	ret = memory_post_test2(start, size);
	429	WATCHDOG_RESET();
	430	if (!ret)
	431	ret = memory_post_test3(start, size);
	432	WATCHDOG_RESET();
	433	if (!ret)
	434	ret = memory_post_test4(start, size);
	435	WATCHDOG_RESET();
ad5bb451 WD	436
	437	return ret;
	438	}
	439
8d3fcb5e VL	440	static int memory_post_test_regions(unsigned long start, unsigned long size)
	441	{
	442	unsigned long i;
	443	int ret = 0;
	444
	445	for (i = 0; i < (size >> 20) && (!ret); i++) {
	446	if (!ret)
7b5d61b5	447	ret = memory_post_test_patterns(start + (i << 20),
8d3fcb5e	448	0x800);
7b5d61b5 HS	449	if (!ret)
	450	ret = memory_post_test_patterns(start + (i << 20) +
	451	0xff800, 0x800);
8d3fcb5e VL	452	}
	453
	454	return ret;
	455	}
	456
	457	static int memory_post_tests(unsigned long start, unsigned long size)
	458	{
	459	int ret = 0;
	460
	461	ret = memory_post_test_lines(start, size);
	462	if (!ret)
	463	ret = memory_post_test_patterns(start, size);
	464
	465	return ret;
	466	}
	467
4204298d HS	468	/*
	469	* !! this is only valid, if you have contiguous memory banks !!
	470	*/
28417030 YS	471	__attribute__((weak))
28417030 YS	472	int arch_memory_test_prepare(u32 vstart, u32 size, phys_addr_t *phys_offset)
ad5bb451	473	{
b75d8dc5	474	struct bd_info *bd = gd->bd;
4204298d	475
28417030	476	*vstart = CONFIG_SYS_SDRAM_BASE;
4204298d HS	477	*size = (gd->ram_size >= 256 << 20 ?
4204298d HS	478	256 << 20 : gd->ram_size) - (1 << 20);
ad5bb451	479
9c02defc	480	/* Limit area to be tested with the board info struct */
28417030 YS	481	if ((vstart) + (size) > (ulong)bd)
	482	size = (ulong)bd - vstart;
	483
	484	return 0;
	485	}
ad5bb451	486
28417030 YS	487	__attribute__((weak))
	488	int arch_memory_test_advance(u32 vstart, u32 size, phys_addr_t *phys_offset)
	489	{
	490	return 1;
	491	}
ad5bb451	492
28417030 YS	493	__attribute__((weak))
	494	int arch_memory_test_cleanup(u32 vstart, u32 size, phys_addr_t *phys_offset)
	495	{
	496	return 0;
	497	}
ad5bb451	498
28417030 YS	499	__attribute__((weak))
	500	void arch_memory_failure_handle(void)
	501	{
	502	return;
	503	}
	504
8d3fcb5e VL	505	int memory_regions_post_test(int flags)
	506	{
	507	int ret = 0;
	508	phys_addr_t phys_offset = 0;
	509	u32 memsize, vstart;
	510
	511	arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
	512
	513	ret = memory_post_test_lines(vstart, memsize);
	514	if (!ret)
	515	ret = memory_post_test_regions(vstart, memsize);
	516
	517	return ret;
	518	}
	519
28417030 YS	520	int memory_post_test(int flags)
	521	{
	522	int ret = 0;
	523	phys_addr_t phys_offset = 0;
	524	u32 memsize, vstart;
	525
	526	arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
	527
	528	do {
	529	if (flags & POST_SLOWTEST) {
	530	ret = memory_post_tests(vstart, memsize);
	531	} else { /* POST_NORMAL */
8d3fcb5e	532	ret = memory_post_test_regions(vstart, memsize);
ad5bb451	533	}
28417030 YS	534	} while (!ret &&
	535	!arch_memory_test_advance(&vstart, &memsize, &phys_offset));
	536
	537	arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
	538	if (ret)
	539	arch_memory_failure_handle();
ad5bb451 WD	540
	541	return ret;
	542	}
	543
8d3fcb5e	544	#endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY\|CONFIG_SYS_POST_MEM_REGIONS) */