[thirdparty/u-boot.git] / src / arm / nxp / imx / imx27-eukrea-cpuimx27.dtsi

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 */

/dts-v1/;
#include "imx27.dtsi"

/ {
	model = "Eukrea CPUIMX27";
	compatible = "eukrea,cpuimx27", "fsl,imx27";

	memory@a0000000 {
		device_type = "memory";
		reg = <0xa0000000 0x04000000>;
	};

	clk14745600: clk-uart {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <14745600>;
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	status = "okay";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	rtc@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
	};
};

&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;
	status = "okay";
};

&owire {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_owire>;
	status = "okay";
};

&sdhci2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdhc2>;
	bus-width = <4>;
	non-removable;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	uart-has-rtscts;
	status = "okay";
};

&usbh2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh2>;
	dr_mode = "host";
	phy_type = "ulpi";
	disable-over-current;
	status = "okay";
};

&usbotg {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	dr_mode = "otg";
	phy_type = "ulpi";
	disable-over-current;
	status = "okay";
};

&weim {
	status = "okay";

	nor: flash@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0 0x00000000 0x04000000>;
		bank-width = <2>;
		linux,mtd-name = "physmap-flash.0";
		fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
	};

	uart8250@3,200000 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart8250_1>;
		compatible = "ns8250";
		clocks = <&clk14745600>;
		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
		interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
		reg = <3 0x200000 0x1000>;
		reg-shift = <1>;
		reg-io-width = <1>;
		no-loopback-test;
	};

	uart8250@3,400000 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart8250_2>;
		compatible = "ns8250";
		clocks = <&clk14745600>;
		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
		interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
		reg = <3 0x400000 0x1000>;
		reg-shift = <1>;
		reg-io-width = <1>;
		no-loopback-test;
	};

	uart8250@3,800000 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart8250_3>;
		compatible = "ns8250";
		clocks = <&clk14745600>;
		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
		interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
		reg = <3 0x800000 0x1000>;
		reg-shift = <1>;
		reg-io-width = <1>;
		no-loopback-test;
	};

	uart8250@3,1000000 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart8250_4>;
		compatible = "ns8250";
		clocks = <&clk14745600>;
		fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
		interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
		reg = <3 0x1000000 0x1000>;
		reg-shift = <1>;
		reg-io-width = <1>;
		no-loopback-test;
	};
};

&iomuxc {
	imx27-eukrea-cpuimx27 {
		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX27_PAD_SD3_CMD__FEC_TXD0		0x0
				MX27_PAD_SD3_CLK__FEC_TXD1		0x0
				MX27_PAD_ATA_DATA0__FEC_TXD2		0x0
				MX27_PAD_ATA_DATA1__FEC_TXD3		0x0
				MX27_PAD_ATA_DATA2__FEC_RX_ER		0x0
				MX27_PAD_ATA_DATA3__FEC_RXD1		0x0
				MX27_PAD_ATA_DATA4__FEC_RXD2		0x0
				MX27_PAD_ATA_DATA5__FEC_RXD3		0x0
				MX27_PAD_ATA_DATA6__FEC_MDIO		0x0
				MX27_PAD_ATA_DATA7__FEC_MDC		0x0
				MX27_PAD_ATA_DATA8__FEC_CRS		0x0
				MX27_PAD_ATA_DATA9__FEC_TX_CLK		0x0
				MX27_PAD_ATA_DATA10__FEC_RXD0		0x0
				MX27_PAD_ATA_DATA11__FEC_RX_DV		0x0
				MX27_PAD_ATA_DATA12__FEC_RX_CLK		0x0
				MX27_PAD_ATA_DATA13__FEC_COL		0x0
				MX27_PAD_ATA_DATA14__FEC_TX_ER		0x0
				MX27_PAD_ATA_DATA15__FEC_TX_EN		0x0
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX27_PAD_I2C_DATA__I2C_DATA		0x0
				MX27_PAD_I2C_CLK__I2C_CLK		0x0
			>;
		};

		pinctrl_nfc: nfcgrp {
			fsl,pins = <
				MX27_PAD_NFRB__NFRB			0x0
				MX27_PAD_NFCLE__NFCLE			0x0
				MX27_PAD_NFWP_B__NFWP_B			0x0
				MX27_PAD_NFCE_B__NFCE_B			0x0
				MX27_PAD_NFALE__NFALE			0x0
				MX27_PAD_NFRE_B__NFRE_B			0x0
				MX27_PAD_NFWE_B__NFWE_B			0x0
			>;
		};

		pinctrl_owire: owiregrp {
			fsl,pins = <
				MX27_PAD_RTCK__OWIRE			0x0
			>;
		};

		pinctrl_sdhc2: sdhc2grp {
			fsl,pins = <
				MX27_PAD_SD2_CLK__SD2_CLK		0x0
				MX27_PAD_SD2_CMD__SD2_CMD		0x0
				MX27_PAD_SD2_D0__SD2_D0			0x0
				MX27_PAD_SD2_D1__SD2_D1			0x0
				MX27_PAD_SD2_D2__SD2_D2			0x0
				MX27_PAD_SD2_D3__SD2_D3			0x0
			>;
		};

		pinctrl_uart4: uart4grp {
			fsl,pins = <
				MX27_PAD_USBH1_TXDM__UART4_TXD		0x0
				MX27_PAD_USBH1_RXDP__UART4_RXD		0x0
				MX27_PAD_USBH1_TXDP__UART4_CTS		0x0
				MX27_PAD_USBH1_FS__UART4_RTS		0x0
			>;
		};

		pinctrl_uart8250_1: uart82501grp {
			fsl,pins = <
				MX27_PAD_USB_PWR__GPIO2_23		0x0
			>;
		};

		pinctrl_uart8250_2: uart82502grp {
			fsl,pins = <
				MX27_PAD_USBH1_SUSP__GPIO2_22		0x0
			>;
		};

		pinctrl_uart8250_3: uart82503grp {
			fsl,pins = <
				MX27_PAD_USBH1_OE_B__GPIO2_27		0x0
			>;
		};

		pinctrl_uart8250_4: uart82504grp {
			fsl,pins = <
				MX27_PAD_USBH1_RXDM__GPIO2_30		0x0
			>;
		};

		pinctrl_usbh2: usbh2grp {
			fsl,pins = <
				MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
				MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
				MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
				MX27_PAD_USBH2_STP__USBH2_STP		0x0
				MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
				MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
				MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
				MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
				MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
				MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
				MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
				MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
				MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
				MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
				MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
			>;
		};
	};
};
Commit	Line	Data
53633a89 TR	1	// SPDX-License-Identifier: GPL-2.0-or-later
	2	/*
	3	* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
	4	*/
	5
	6	/dts-v1/;
	7	#include "imx27.dtsi"
	8
	9	/ {
	10	model = "Eukrea CPUIMX27";
	11	compatible = "eukrea,cpuimx27", "fsl,imx27";
	12
	13	memory@a0000000 {
	14	device_type = "memory";
	15	reg = <0xa0000000 0x04000000>;
	16	};
	17
	18	clk14745600: clk-uart {
	19	compatible = "fixed-clock";
	20	#clock-cells = <0>;
	21	clock-frequency = <14745600>;
	22	};
	23	};
	24
	25	&fec {
	26	pinctrl-names = "default";
	27	pinctrl-0 = <&pinctrl_fec>;
	28	status = "okay";
	29	};
	30
	31	&i2c1 {
	32	pinctrl-names = "default";
	33	pinctrl-0 = <&pinctrl_i2c1>;
	34	status = "okay";
	35
93743d24	36	rtc@51 {
53633a89 TR	37	compatible = "nxp,pcf8563";
	38	reg = <0x51>;
	39	};
	40	};
	41
	42	&nfc {
	43	pinctrl-names = "default";
	44	pinctrl-0 = <&pinctrl_nfc>;
	45	nand-bus-width = <8>;
	46	nand-ecc-mode = "hw";
	47	nand-on-flash-bbt;
	48	status = "okay";
	49	};
	50
	51	&owire {
	52	pinctrl-names = "default";
	53	pinctrl-0 = <&pinctrl_owire>;
	54	status = "okay";
	55	};
	56
	57	&sdhci2 {
	58	pinctrl-names = "default";
	59	pinctrl-0 = <&pinctrl_sdhc2>;
	60	bus-width = <4>;
	61	non-removable;
	62	status = "okay";
	63	};
	64
	65	&uart4 {
	66	pinctrl-names = "default";
	67	pinctrl-0 = <&pinctrl_uart4>;
	68	uart-has-rtscts;
	69	status = "okay";
	70	};
	71
	72	&usbh2 {
	73	pinctrl-names = "default";
	74	pinctrl-0 = <&pinctrl_usbh2>;
	75	dr_mode = "host";
	76	phy_type = "ulpi";
	77	disable-over-current;
	78	status = "okay";
	79	};
	80
	81	&usbotg {
	82	pinctrl-names = "default";
	83	pinctrl-0 = <&pinctrl_usbotg>;
	84	dr_mode = "otg";
	85	phy_type = "ulpi";
	86	disable-over-current;
	87	status = "okay";
	88	};
	89
	90	&weim {
	91	status = "okay";
	92
93743d24	93	nor: flash@0,0 {
53633a89 TR	94	#address-cells = <1>;
	95	#size-cells = <1>;
	96	compatible = "cfi-flash";
	97	reg = <0 0x00000000 0x04000000>;
	98	bank-width = <2>;
	99	linux,mtd-name = "physmap-flash.0";
	100	fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
	101	};
	102
	103	uart8250@3,200000 {
	104	pinctrl-names = "default";
	105	pinctrl-0 = <&pinctrl_uart8250_1>;
	106	compatible = "ns8250";
	107	clocks = <&clk14745600>;
	108	fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
	109	interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
	110	reg = <3 0x200000 0x1000>;
	111	reg-shift = <1>;
	112	reg-io-width = <1>;
	113	no-loopback-test;
	114	};
	115
	116	uart8250@3,400000 {
	117	pinctrl-names = "default";
	118	pinctrl-0 = <&pinctrl_uart8250_2>;
	119	compatible = "ns8250";
	120	clocks = <&clk14745600>;
	121	fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
	122	interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
	123	reg = <3 0x400000 0x1000>;
	124	reg-shift = <1>;
	125	reg-io-width = <1>;
	126	no-loopback-test;
	127	};
	128
	129	uart8250@3,800000 {
	130	pinctrl-names = "default";
	131	pinctrl-0 = <&pinctrl_uart8250_3>;
	132	compatible = "ns8250";
	133	clocks = <&clk14745600>;
	134	fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
	135	interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
	136	reg = <3 0x800000 0x1000>;
	137	reg-shift = <1>;
	138	reg-io-width = <1>;
	139	no-loopback-test;
	140	};
	141
	142	uart8250@3,1000000 {
	143	pinctrl-names = "default";
	144	pinctrl-0 = <&pinctrl_uart8250_4>;
	145	compatible = "ns8250";
	146	clocks = <&clk14745600>;
	147	fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
	148	interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
	149	reg = <3 0x1000000 0x1000>;
	150	reg-shift = <1>;
	151	reg-io-width = <1>;
	152	no-loopback-test;
	153	};
	154	};
	155
	156	&iomuxc {
	157	imx27-eukrea-cpuimx27 {
158	pinctrl_fec: fecgrp {
159	fsl,pins = <
160	MX27_PAD_SD3_CMD__FEC_TXD0 0x0
161	MX27_PAD_SD3_CLK__FEC_TXD1 0x0
162	MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
163	MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
164	MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
165	MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
166	MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
167	MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
168	MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
169	MX27_PAD_ATA_DATA7__FEC_MDC 0x0
170	MX27_PAD_ATA_DATA8__FEC_CRS 0x0
171	MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
172	MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
173	MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
174	MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
175	MX27_PAD_ATA_DATA13__FEC_COL 0x0
176	MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
177	MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
178	>;
179	};
180
181	pinctrl_i2c1: i2c1grp {
182	fsl,pins = <
183	MX27_PAD_I2C_DATA__I2C_DATA 0x0
184	MX27_PAD_I2C_CLK__I2C_CLK 0x0
185	>;
186	};
187
188	pinctrl_nfc: nfcgrp {
189	fsl,pins = <
190	MX27_PAD_NFRB__NFRB 0x0
191	MX27_PAD_NFCLE__NFCLE 0x0
192	MX27_PAD_NFWP_B__NFWP_B 0x0
193	MX27_PAD_NFCE_B__NFCE_B 0x0
194	MX27_PAD_NFALE__NFALE 0x0
195	MX27_PAD_NFRE_B__NFRE_B 0x0
196	MX27_PAD_NFWE_B__NFWE_B 0x0
197	>;
198	};
199
200	pinctrl_owire: owiregrp {
201	fsl,pins = <
202	MX27_PAD_RTCK__OWIRE 0x0
203	>;
204	};
205
206	pinctrl_sdhc2: sdhc2grp {
207	fsl,pins = <
208	MX27_PAD_SD2_CLK__SD2_CLK 0x0
209	MX27_PAD_SD2_CMD__SD2_CMD 0x0
210	MX27_PAD_SD2_D0__SD2_D0 0x0
211	MX27_PAD_SD2_D1__SD2_D1 0x0
212	MX27_PAD_SD2_D2__SD2_D2 0x0
213	MX27_PAD_SD2_D3__SD2_D3 0x0
214	>;
215	};
216
217	pinctrl_uart4: uart4grp {
218	fsl,pins = <
219	MX27_PAD_USBH1_TXDM__UART4_TXD 0x0
220	MX27_PAD_USBH1_RXDP__UART4_RXD 0x0
221	MX27_PAD_USBH1_TXDP__UART4_CTS 0x0
222	MX27_PAD_USBH1_FS__UART4_RTS 0x0
223	>;
224	};
225
226	pinctrl_uart8250_1: uart82501grp {
227	fsl,pins = <
228	MX27_PAD_USB_PWR__GPIO2_23 0x0
229	>;
230	};
231
232	pinctrl_uart8250_2: uart82502grp {
233	fsl,pins = <
234	MX27_PAD_USBH1_SUSP__GPIO2_22 0x0
235	>;
236	};
237
238	pinctrl_uart8250_3: uart82503grp {
239	fsl,pins = <
240	MX27_PAD_USBH1_OE_B__GPIO2_27 0x0
241	>;
242	};
243
244	pinctrl_uart8250_4: uart82504grp {
245	fsl,pins = <
246	MX27_PAD_USBH1_RXDM__GPIO2_30 0x0
247	>;
248	};
249
250	pinctrl_usbh2: usbh2grp {
251	fsl,pins = <
252	MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
253	MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
254	MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
255	MX27_PAD_USBH2_STP__USBH2_STP 0x0
256	MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
257	MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
258	MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
259	MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
260	MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
261	MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
262	MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
263	MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
264	>;
265	};
266
267	pinctrl_usbotg: usbotggrp {
268	fsl,pins = <
269	MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
270	MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
271	MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
272	MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
273	MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
274	MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
275	MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
276	MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
277	MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
278	MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
279	MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
280	MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
281	>;
282	};
283	};
284	};