RISC-V: Remove gather scale and offset handling.

With the recent vectorizer changes upstream the vectorizer can take care
of offset extension and scaling (and its proper costing) itself.
Thus, we can remove all related handling in expand_gather_scatter and
set the predicates in the gather/scatter expanders to what our
instructions actually support.

gcc/ChangeLog:

	* config/riscv/autovec.md: Use const_1_operand for scale and
	extend predicates.
	* config/riscv/riscv-v.cc (expand_gather_scatter): Remove scale
	and extension handling.

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 48de5efdde52f98db7e1c18c772bae4fa19a4744..4f0a1ce9c29856c3fe0a5b0b88add588ba270517 100644 (file)
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -55,8 +55,8 @@
   [(match_operand:RATIO64 0 "register_operand")
    (match_operand 1 "pmode_reg_or_0_operand")
    (match_operand:RATIO64I 2 "register_operand")
-   (match_operand 3 "<RATIO64:gs_extension>")
-   (match_operand 4 "<RATIO64:gs_scale>")
+   (match_operand 3 "const_1_operand")
+   (match_operand 4 "const_1_operand")
    (match_operand:<RATIO64:VM> 5 "vector_mask_operand")
    (match_operand 6 "maskload_else_operand")
    (match_operand 7 "autovec_length_operand")
@@ -71,8 +71,8 @@
   [(match_operand:RATIO32 0 "register_operand")
    (match_operand 1 "pmode_reg_or_0_operand")
    (match_operand:RATIO32I 2 "register_operand")
-   (match_operand 3 "<RATIO32:gs_extension>")
-   (match_operand 4 "<RATIO32:gs_scale>")
+   (match_operand 3 "const_1_operand")
+   (match_operand 4 "const_1_operand")
    (match_operand:<RATIO32:VM> 5 "vector_mask_operand")
    (match_operand 6 "maskload_else_operand")
    (match_operand 7 "autovec_length_operand")
@@ -87,8 +87,8 @@
   [(match_operand:RATIO16 0 "register_operand")
    (match_operand 1 "pmode_reg_or_0_operand")
    (match_operand:RATIO16I 2 "register_operand")
-   (match_operand 3 "<RATIO16:gs_extension>")
-   (match_operand 4 "<RATIO16:gs_scale>")
+   (match_operand 3 "const_1_operand")
+   (match_operand 4 "const_1_operand")
    (match_operand:<RATIO16:VM> 5 "vector_mask_operand")
    (match_operand 6 "maskload_else_operand")
    (match_operand 7 "autovec_length_operand")
@@ -103,8 +103,8 @@
   [(match_operand:RATIO8 0 "register_operand")
    (match_operand 1 "pmode_reg_or_0_operand")
    (match_operand:RATIO8I 2 "register_operand")
-   (match_operand 3 "<RATIO8:gs_extension>")
-   (match_operand 4 "<RATIO8:gs_scale>")
+   (match_operand 3 "const_1_operand")
+   (match_operand 4 "const_1_operand")
    (match_operand:<RATIO8:VM> 5 "vector_mask_operand")
    (match_operand 6 "maskload_else_operand")
    (match_operand 7 "autovec_length_operand")
@@ -119,8 +119,8 @@
   [(match_operand:RATIO4 0 "register_operand")
    (match_operand 1 "pmode_reg_or_0_operand")
    (match_operand:RATIO4I 2 "register_operand")
-   (match_operand 3 "<RATIO4:gs_extension>")
-   (match_operand 4 "<RATIO4:gs_scale>")
+   (match_operand 3 "const_1_operand")
+   (match_operand 4 "const_1_operand")
    (match_operand:<RATIO4:VM> 5 "vector_mask_operand")
    (match_operand 6 "maskload_else_operand")
    (match_operand 7 "autovec_length_operand")
@@ -135,8 +135,8 @@
   [(match_operand:RATIO2 0 "register_operand")
    (match_operand 1 "pmode_reg_or_0_operand")
    (match_operand:RATIO2I 2 "register_operand")
-   (match_operand 3 "<RATIO2:gs_extension>")
-   (match_operand 4 "<RATIO2:gs_scale>")
+   (match_operand 3 "const_1_operand")
+   (match_operand 4 "const_1_operand")
    (match_operand:<RATIO2:VM> 5 "vector_mask_operand")
    (match_operand 6 "maskload_else_operand")
    (match_operand 7 "autovec_length_operand")
@@ -155,8 +155,8 @@
   [(match_operand:RATIO1 0 "register_operand")
    (match_operand 1 "pmode_reg_or_0_operand")
    (match_operand:RATIO1 2 "register_operand")
-   (match_operand 3 "<gs_extension>")
-   (match_operand 4 "<gs_scale>")
+   (match_operand 3 "const_1_operand")
+   (match_operand 4 "const_1_operand")
    (match_operand:<VM> 5 "vector_mask_operand")
    (match_operand 6 "maskload_else_operand")
    (match_operand 7 "autovec_length_operand")
@@ -174,8 +174,8 @@
 (define_expand "mask_len_scatter_store<RATIO64:mode><RATIO64I:mode>"
   [(match_operand 0 "pmode_reg_or_0_operand")
    (match_operand:RATIO64I 1 "register_operand")
-   (match_operand 2 "<RATIO64:gs_extension>")
-   (match_operand 3 "<RATIO64:gs_scale>")
+   (match_operand 2 "const_1_operand")
+   (match_operand 3 "const_1_operand")
    (match_operand:RATIO64 4 "register_operand")
    (match_operand:<RATIO64:VM> 5 "vector_mask_operand")
    (match_operand 6 "autovec_length_operand")
@@ -189,8 +189,8 @@
 (define_expand "mask_len_scatter_store<RATIO32:mode><RATIO32I:mode>"
   [(match_operand 0 "pmode_reg_or_0_operand")
    (match_operand:RATIO32I 1 "register_operand")
-   (match_operand 2 "<RATIO32:gs_extension>")
-   (match_operand 3 "<RATIO32:gs_scale>")
+   (match_operand 2 "const_1_operand")
+   (match_operand 3 "const_1_operand")
    (match_operand:RATIO32 4 "register_operand")
    (match_operand:<RATIO32:VM> 5 "vector_mask_operand")
    (match_operand 6 "autovec_length_operand")
@@ -204,8 +204,8 @@
 (define_expand "mask_len_scatter_store<RATIO16:mode><RATIO16I:mode>"
   [(match_operand 0 "pmode_reg_or_0_operand")
    (match_operand:RATIO16I 1 "register_operand")
-   (match_operand 2 "<RATIO16:gs_extension>")
-   (match_operand 3 "<RATIO16:gs_scale>")
+   (match_operand 2 "const_1_operand")
+   (match_operand 3 "const_1_operand")
    (match_operand:RATIO16 4 "register_operand")
    (match_operand:<RATIO16:VM> 5 "vector_mask_operand")
    (match_operand 6 "autovec_length_operand")
@@ -219,8 +219,8 @@
 (define_expand "mask_len_scatter_store<RATIO8:mode><RATIO8I:mode>"
   [(match_operand 0 "pmode_reg_or_0_operand")
    (match_operand:RATIO8I 1 "register_operand")
-   (match_operand 2 "<RATIO8:gs_extension>")
-   (match_operand 3 "<RATIO8:gs_scale>")
+   (match_operand 2 "const_1_operand")
+   (match_operand 3 "const_1_operand")
    (match_operand:RATIO8 4 "register_operand")
    (match_operand:<RATIO8:VM> 5 "vector_mask_operand")
    (match_operand 6 "autovec_length_operand")
@@ -234,8 +234,8 @@
 (define_expand "mask_len_scatter_store<RATIO4:mode><RATIO4I:mode>"
   [(match_operand 0 "pmode_reg_or_0_operand")
    (match_operand:RATIO4I 1 "register_operand")
-   (match_operand 2 "<RATIO4:gs_extension>")
-   (match_operand 3 "<RATIO4:gs_scale>")
+   (match_operand 2 "const_1_operand")
+   (match_operand 3 "const_1_operand")
    (match_operand:RATIO4 4 "register_operand")
    (match_operand:<RATIO4:VM> 5 "vector_mask_operand")
    (match_operand 6 "autovec_length_operand")
@@ -249,8 +249,8 @@
 (define_expand "mask_len_scatter_store<RATIO2:mode><RATIO2I:mode>"
   [(match_operand 0 "pmode_reg_or_0_operand")
    (match_operand:RATIO2I 1 "register_operand")
-   (match_operand 2 "<RATIO2:gs_extension>")
-   (match_operand 3 "<RATIO2:gs_scale>")
+   (match_operand 2 "const_1_operand")
+   (match_operand 3 "const_1_operand")
    (match_operand:RATIO2 4 "register_operand")
    (match_operand:<RATIO2:VM> 5 "vector_mask_operand")
    (match_operand 6 "autovec_length_operand")
@@ -268,8 +268,8 @@
 (define_expand "mask_len_scatter_store<mode><mode>"
   [(match_operand 0 "pmode_reg_or_0_operand")
    (match_operand:RATIO1 1 "register_operand")
-   (match_operand 2 "<gs_extension>")
-   (match_operand 3 "<gs_scale>")
+   (match_operand 2 "const_1_operand")
+   (match_operand 3 "const_1_operand")
    (match_operand:RATIO1 4 "register_operand")
    (match_operand:<VM> 5 "vector_mask_operand")
    (match_operand 6 "autovec_length_operand")

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 707924db6a370ec670c3755cf0d2d90b40218044..658c6327cc5cff8c8eea566ee3fd6c4e20b33d3e 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -4747,8 +4747,6 @@ void
 expand_gather_scatter (rtx *ops, bool is_load)
 {
   rtx ptr, vec_offset, vec_reg;
-  bool zero_extend_p;
-  int shift;
   rtx mask = ops[5];
   rtx len = ops[6];
   if (is_load)
@@ -4758,78 +4756,18 @@ expand_gather_scatter (rtx *ops, bool is_load)
       vec_reg = ops[0];
       ptr = ops[1];
       vec_offset = ops[2];
-      zero_extend_p = INTVAL (ops[3]);
-      shift = exact_log2 (INTVAL (ops[4]));
     }
   else
     {
       vec_reg = ops[4];
       ptr = ops[0];
       vec_offset = ops[1];
-      zero_extend_p = INTVAL (ops[2]);
-      shift = exact_log2 (INTVAL (ops[3]));
     }
 
   machine_mode vec_mode = GET_MODE (vec_reg);
   machine_mode idx_mode = GET_MODE (vec_offset);
-  scalar_mode inner_idx_mode = GET_MODE_INNER (idx_mode);
-  unsigned inner_offsize = GET_MODE_BITSIZE (inner_idx_mode);
-  poly_int64 nunits = GET_MODE_NUNITS (vec_mode);
   bool is_vlmax = is_vlmax_len_p (vec_mode, len);
 
-  bool use_widening_shift = false;
-
-  /* Extend the offset element to address width.  */
-  if (inner_offsize < BITS_PER_WORD)
-    {
-      use_widening_shift = TARGET_ZVBB && zero_extend_p && shift == 1;
-      /* 7.2. Vector Load/Store Addressing Modes.
-        If the vector offset elements are narrower than XLEN, they are
-        zero-extended to XLEN before adding to the ptr effective address. If
-        the vector offset elements are wider than XLEN, the least-significant
-        XLEN bits are used in the address calculation. An implementation must
-        raise an illegal instruction exception if the EEW is not supported for
-        offset elements.
-
-        RVV spec only refers to the shift == 0 case.  */
-      if (!zero_extend_p || shift)
-       {
-         if (zero_extend_p)
-           inner_idx_mode
-             = int_mode_for_size (inner_offsize * 2, 0).require ();
-         else
-           inner_idx_mode = int_mode_for_size (BITS_PER_WORD, 0).require ();
-         machine_mode new_idx_mode
-           = get_vector_mode (inner_idx_mode, nunits).require ();
-         if (!use_widening_shift)
-           {
-             rtx tmp = gen_reg_rtx (new_idx_mode);
-             emit_insn (gen_extend_insn (tmp, vec_offset, new_idx_mode, idx_mode,
-                                         zero_extend_p ? true : false));
-             vec_offset = tmp;
-           }
-         idx_mode = new_idx_mode;
-       }
-    }
-
-  if (shift)
-    {
-      rtx tmp;
-      if (!use_widening_shift)
-       tmp = expand_binop (idx_mode, ashl_optab, vec_offset,
-                           gen_int_mode (shift, Pmode), NULL_RTX, 0,
-                           OPTAB_DIRECT);
-      else
-       {
-         tmp = gen_reg_rtx (idx_mode);
-         insn_code icode = code_for_pred_vwsll_scalar (idx_mode);
-         rtx ops[] = {tmp, vec_offset, const1_rtx};
-         emit_vlmax_insn (icode, BINARY_OP, ops);
-       }
-
-      vec_offset = tmp;
-    }
-
   insn_code icode = prepare_gather_scatter (vec_mode, idx_mode, is_load);
   if (is_vlmax)
     {