RISC-V: Add test for vec_duplicate + vwmaccu.vv combine with GR2VR cost 0, 1 and 15

Add asm dump check and run test for vec_duplicate + vwmaccu.vv
combine to vwmacc.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vwmaccu.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Add test helper
	macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmaccu-run-1-u64.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index be4d23c2f437e3ff8dabc1b2bf2f43c3b2b9debb..1a48afa2788fba310b181faba68253232af4d019 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -11,6 +11,7 @@
 TEST_BINARY_VX_UNSIGNED_0(T)
 TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 2 } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 56dd314a7e168238a81e3c030ed01bf37f94d3b9..2b00614d2f4c386d1422ddbcb21d0078864d8e70 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -11,6 +11,7 @@
 TEST_BINARY_VX_UNSIGNED_0(T)
 TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 2 } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 685f5f631ef505d7b74728a439e64ab1838f7d4f..8cbf47e2eb415d903cae6afba7258b99e38ccb33 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -11,6 +11,7 @@
 TEST_BINARY_VX_UNSIGNED_0(T)
 TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -37,3 +38,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vwmulu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vwaddu.wx} 1 } } */
 /* { dg-final { scan-assembler-times {vwsubu.wx} 1 } } */
+/* { dg-final { scan-assembler-times {vwmaccu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 391c59f502a1231ec90ec7f190db6cd36d246c62..9aa9029d3d03261159aacdc7c0fc59975f030359 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -11,6 +11,7 @@
 TEST_BINARY_VX_UNSIGNED_0(T)
 TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 2bcb6a136ff8915730837fab9a22f7044014d714..2ffd850fa9f042b750d238d357a730492d8b18db 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -11,6 +11,7 @@
 TEST_BINARY_VX_UNSIGNED_0(T)
 TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 0aa6a212c1e564ff6b9734cc77cb9c4a21468244..8bb5c50413ae021da0b1be021c9f6cc219818a98 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -11,6 +11,7 @@
 TEST_BINARY_VX_UNSIGNED_0(T)
 TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 48e095f63ff1abf091b79dc927de7487edcc0198..9f5351615ddad89fa75bbf4a0be4a3e4dffcc113 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -11,6 +11,7 @@
 TEST_BINARY_VX_UNSIGNED_0(T)
 TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 761ce5d1a56e00c3bfb9e2a1b781f132d6f9abe4..069efefa7fa7ad853b290fac2307cdfb2ad40a73 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -11,6 +11,7 @@
 TEST_BINARY_VX_UNSIGNED_0(T)
 TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 1eebec94a6db184eedc5be3354c8857bbcca6422..04332ff70b57b5637fc2f17f4e534d35362cc30c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -11,6 +11,7 @@
 TEST_BINARY_VX_UNSIGNED_0(T)
 TEST_TERNARY_VX_UNSIGNED_0(T)
 TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmulu.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.wx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmaccu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmaccu-run-1-u64.c
new file mode 100644 (file)
index 0000000..c058141
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmaccu-run-1-u64.c
@@ -0,0 +1,18 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_widen.h"
+#include "vx_widen_data.h"
+
+#define WT        uint64_t
+#define NT        uint32_t
+#define NAME      wmacc
+#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME)
+#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME)
+
+DEF_VX_WIDEN_TERNARY_CASE_0_WRAP(WT, NT, +, *, NAME)
+
+#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \
+  RUN_VX_WIDEN_TERNARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N)
+
+#include "vx_widen_vx_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
index 5be5f2d456e15e1bf1529f637af18a7f39aa1f9a..cd73a1b5f4817e827c80af20984ca562b28c72c0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
@@ -45,6 +45,24 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_1 (WT * restrict vd,   \
 #define RUN_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \
   RUN_VX_WIDEN_BINARY_CASE_1(WT, NT, NAME, vd, vs2, rs1, n)
 
+#define DEF_VX_WIDEN_TERNARY_CASE_0(WT, NT, OP1, OP2, NAME)             \
+void                                                                    \
+test_vx_widen_ternary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd,  \
+                                                   NT * restrict vs2,  \
+                                                   NT rs1,             \
+                                                   unsigned n)         \
+{                                                                       \
+  for (unsigned i = 0; i < n; i++)                                      \
+    vd[i] = vd[i] OP1 (WT)vs2[i] OP2 (WT)rs1;                           \
+}
+
+#define DEF_VX_WIDEN_TERNARY_CASE_0_WRAP(WT, NT, OP1, OP2, NAME) \
+  DEF_VX_WIDEN_TERNARY_CASE_0(WT, NT, OP1, OP2, NAME)
+#define RUN_VX_WIDEN_TERNARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n) \
+  test_vx_widen_ternary_##NAME##_##WT##_##NT##_case_0(vd, vs2, rs1, n)
+#define RUN_VX_WIDEN_TERNARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \
+  RUN_VX_WIDEN_TERNARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n)
+
 #define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT)     \
   DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) \
   DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) \
@@ -52,4 +70,7 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_1 (WT * restrict vd,   \
   DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, +, add) \
   DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, -, sub) \
 
+#define TEST_WIDEN_TERNARY_VX_UNSIGNED(WT, NT)     \
+  DEF_VX_WIDEN_TERNARY_CASE_0_WRAP(WT, NT, +, *, wmadd)
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
index af7d8358ad90a124eb1e0d981268a3161850e59e..9b2460f6b26b3c9e695d3639cca17b5d54dcbd61 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
@@ -59,6 +59,7 @@
 DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add)
 DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, sub)
 DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, mul)
+DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, wmacc)
 
 #define DEF_BINARY_WIDEN_STRUCT_1(WT, NT, NAME)            \
   DEF_BINARY_WIDEN_STRUCT_1_TYPE_WRAP(WT, NT, NAME)        \
@@ -269,4 +270,57 @@ DEF_BINARY_WIDEN_STRUCT_1_DECL_WRAP(uint64_t, uint32_t, sub)[] = {
   },
 };
 
+DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, wmacc)[] = {
+  {
+    /* vs2 NT */
+    {
+               3,          3,          3,          3,
+               7,          7,          7,          7,
+               9,          9,          9,          9,
+               5,          5,          5,          5,
+    },
+    /* rs1 NT */
+    1,
+    /* expect WT */
+    {
+               4,          4,          4,          4,
+               9,          9,          9,          9,
+              17,         17,         17,         17,
+               5,          5,          5,          5,
+    },
+    /* vd WT */
+    {
+               1,          1,          1,          1,
+               2,          2,          2,          2,
+               8,          8,          8,          8,
+               0,          0,          0,          0,
+    },
+  },
+  {
+    /* vs2 NT */
+    {
+      4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull,
+      4294967294ull, 4294967294ull, 4294967294ull, 4294967294ull,
+      4294967293ull, 4294967293ull, 4294967293ull, 4294967293ull,
+      4294967292ull, 4294967292ull, 4294967292ull, 4294967292ull,
+    },
+    /* rs1 NT */
+    2,
+    /* expect WT */
+    {
+      8589934591ull, 8589934591ull, 8589934591ull, 8589934591ull,
+      8589934590ull, 8589934590ull, 8589934590ull, 8589934590ull,
+      8589934589ull, 8589934589ull, 8589934589ull, 8589934589ull,
+      8589934584ull, 8589934584ull, 8589934584ull, 8589934584ull,
+    },
+    /* vd WT */
+    {
+               1,          1,          1,          1,
+               2,          2,          2,          2,
+               3,          3,          3,          3,
+               0,          0,          0,          0,
+    },
+  },
+};
+
 #endif