[thirdparty/u-boot.git] / Bindings / display / msm / qcom,sm8150-mdss.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8150 Display MDSS

maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

description:
  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS are mentioned for SM8150 target.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,sm8150-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display hf axi clock
      - description: Display sf axi clock
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: bus
      - const: nrt_bus
      - const: core

  iommus:
    maxItems: 1

  interconnects:
    maxItems: 2

  interconnect-names:
    maxItems: 2

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sm8150-dpu

  "^dsi@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        items:
          - const: qcom,sm8150-dsi-ctrl
          - const: qcom,mdss-dsi-ctrl

  "^phy@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: qcom,dsi-phy-7nm-8150

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sm8150.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@ae00000 {
        compatible = "qcom,sm8150-mdss";
        reg = <0x0ae00000 0x1000>;
        reg-names = "mdss";

        interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
                        <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
        interconnect-names = "mdp0-mem", "mdp1-mem";

        power-domains = <&dispcc MDSS_GDSC>;

        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&gcc GCC_DISP_SF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
        clock-names = "iface", "bus", "nrt_bus", "core";

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        iommus = <&apps_smmu 0x800 0x420>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        display-controller@ae01000 {
            compatible = "qcom,sm8150-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "iface", "bus", "core", "vsync";

            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            assigned-clock-rates = <19200000>;

            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmhpd SM8150_MMCX>;

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dpu_intf2_out: endpoint {
                        remote-endpoint = <&dsi1_in>;
                    };
                };
            };

            mdp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-171428571 {
                    opp-hz = /bits/ 64 <171428571>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-300000000 {
                    opp-hz = /bits/ 64 <300000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-345000000 {
                    opp-hz = /bits/ 64 <345000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-460000000 {
                    opp-hz = /bits/ 64 <460000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };

        dsi@ae94000 {
            compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
            reg = <0x0ae94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";

            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd SM8150_MMCX>;

            phys = <&dsi0_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };

            dsi_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-187500000 {
                    opp-hz = /bits/ 64 <187500000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-300000000 {
                    opp-hz = /bits/ 64 <300000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-358000000 {
                    opp-hz = /bits/ 64 <358000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };
            };
        };

        dsi0_phy: phy@ae94400 {
            compatible = "qcom,dsi-phy-7nm-8150";
            reg = <0x0ae94400 0x200>,
                  <0x0ae94600 0x280>,
                  <0x0ae94900 0x260>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";
            vdds-supply = <&vreg_dsi_phy>;
        };

        dsi@ae96000 {
            compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
            reg = <0x0ae96000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <5>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";

            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd SM8150_MMCX>;

            phys = <&dsi1_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi1_in: endpoint {
                        remote-endpoint = <&dpu_intf2_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi1_out: endpoint {
                    };
                };
            };
        };

        dsi1_phy: phy@ae96400 {
            compatible = "qcom,dsi-phy-7nm-8150";
            reg = <0x0ae96400 0x200>,
                  <0x0ae96600 0x280>,
                  <0x0ae96900 0x260>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";
            vdds-supply = <&vreg_dsi_phy>;
        };
    };
...
Commit	Line	Data
53633a89 TR	1	# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm SM8150 Display MDSS
	8
	9	maintainers:
	10	- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
	11
	12	description:
	13	Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
	14	sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
	15	bindings of MDSS are mentioned for SM8150 target.
	16
	17	$ref: /schemas/display/msm/mdss-common.yaml#
	18
	19	properties:
	20	compatible:
	21	items:
	22	- const: qcom,sm8150-mdss
	23
	24	clocks:
	25	items:
	26	- description: Display AHB clock from gcc
	27	- description: Display hf axi clock
	28	- description: Display sf axi clock
	29	- description: Display core clock
	30
	31	clock-names:
	32	items:
	33	- const: iface
	34	- const: bus
	35	- const: nrt_bus
	36	- const: core
	37
	38	iommus:
	39	maxItems: 1
	40
	41	interconnects:
	42	maxItems: 2
	43
	44	interconnect-names:
	45	maxItems: 2
	46
	47	patternProperties:
	48	"^display-controller@[0-9a-f]+$":
	49	type: object
	50	additionalProperties: true
	51
	52	properties:
	53	compatible:
	54	const: qcom,sm8150-dpu
	55
	56	"^dsi@[0-9a-f]+$":
	57	type: object
	58	additionalProperties: true
	59
	60	properties:
	61	compatible:
	62	items:
	63	- const: qcom,sm8150-dsi-ctrl
	64	- const: qcom,mdss-dsi-ctrl
65
66	"^phy@[0-9a-f]+$":
67	type: object
68	additionalProperties: true
69
70	properties:
71	compatible:
93743d24	72	const: qcom,dsi-phy-7nm-8150
53633a89 TR	73
	74	unevaluatedProperties: false
	75
	76	examples:
	77	- \|
	78	#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
	79	#include <dt-bindings/clock/qcom,gcc-sm8150.h>
	80	#include <dt-bindings/clock/qcom,rpmh.h>
	81	#include <dt-bindings/interrupt-controller/arm-gic.h>
	82	#include <dt-bindings/interconnect/qcom,sm8150.h>
	83	#include <dt-bindings/power/qcom-rpmpd.h>
	84
	85	display-subsystem@ae00000 {
	86	compatible = "qcom,sm8150-mdss";
	87	reg = <0x0ae00000 0x1000>;
	88	reg-names = "mdss";
	89
	90	interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
	91	<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
	92	interconnect-names = "mdp0-mem", "mdp1-mem";
	93
	94	power-domains = <&dispcc MDSS_GDSC>;
	95
	96	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	97	<&gcc GCC_DISP_HF_AXI_CLK>,
	98	<&gcc GCC_DISP_SF_AXI_CLK>,
	99	<&dispcc DISP_CC_MDSS_MDP_CLK>;
	100	clock-names = "iface", "bus", "nrt_bus", "core";
	101
	102	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	103	interrupt-controller;
	104	#interrupt-cells = <1>;
	105
	106	iommus = <&apps_smmu 0x800 0x420>;
	107
	108	#address-cells = <1>;
	109	#size-cells = <1>;
	110	ranges;
	111
	112	display-controller@ae01000 {
	113	compatible = "qcom,sm8150-dpu";
	114	reg = <0x0ae01000 0x8f000>,
	115	<0x0aeb0000 0x2008>;
	116	reg-names = "mdp", "vbif";
	117
	118	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	119	<&gcc GCC_DISP_HF_AXI_CLK>,
	120	<&dispcc DISP_CC_MDSS_MDP_CLK>,
	121	<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
	122	clock-names = "iface", "bus", "core", "vsync";
	123
	124	assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
	125	assigned-clock-rates = <19200000>;
	126
	127	operating-points-v2 = <&mdp_opp_table>;
	128	power-domains = <&rpmhpd SM8150_MMCX>;
	129
	130	interrupt-parent = <&mdss>;
	131	interrupts = <0>;
	132
	133	ports {
	134	#address-cells = <1>;
	135	#size-cells = <0>;
	136
137	port@0 {
138	reg = <0>;
139	dpu_intf1_out: endpoint {
140	remote-endpoint = <&dsi0_in>;
141	};
142	};
143
144	port@1 {
145	reg = <1>;
146	dpu_intf2_out: endpoint {
147	remote-endpoint = <&dsi1_in>;
148	};
149	};
150	};
151
152	mdp_opp_table: opp-table {
153	compatible = "operating-points-v2";
154
155	opp-171428571 {
156	opp-hz = /bits/ 64 <171428571>;
157	required-opps = <&rpmhpd_opp_low_svs>;
158	};
159
160	opp-300000000 {
161	opp-hz = /bits/ 64 <300000000>;
162	required-opps = <&rpmhpd_opp_svs>;
163	};
164
165	opp-345000000 {
166	opp-hz = /bits/ 64 <345000000>;
167	required-opps = <&rpmhpd_opp_svs_l1>;
168	};
169
170	opp-460000000 {
171	opp-hz = /bits/ 64 <460000000>;
172	required-opps = <&rpmhpd_opp_nom>;
173	};
174	};
175	};
176
177	dsi@ae94000 {
178	compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
179	reg = <0x0ae94000 0x400>;
180	reg-names = "dsi_ctrl";
181
182	interrupt-parent = <&mdss>;
183	interrupts = <4>;
184
185	clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
186	<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
187	<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
188	<&dispcc DISP_CC_MDSS_ESC0_CLK>,
189	<&dispcc DISP_CC_MDSS_AHB_CLK>,
190	<&gcc GCC_DISP_HF_AXI_CLK>;
191	clock-names = "byte",
192	"byte_intf",
193	"pixel",
194	"core",
195	"iface",
196	"bus";
197
198	assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
199	<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
200	assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
201
202	operating-points-v2 = <&dsi_opp_table>;
203	power-domains = <&rpmhpd SM8150_MMCX>;
204
205	phys = <&dsi0_phy>;
206	phy-names = "dsi";
207
208	#address-cells = <1>;
209	#size-cells = <0>;
210
211	ports {
212	#address-cells = <1>;
213	#size-cells = <0>;
214
215	port@0 {
216	reg = <0>;
217	dsi0_in: endpoint {
218	remote-endpoint = <&dpu_intf1_out>;
219	};
220	};
221
222	port@1 {
223	reg = <1>;
224	dsi0_out: endpoint {
225	};
226	};
227	};
228
229	dsi_opp_table: opp-table {
230	compatible = "operating-points-v2";
231
232	opp-187500000 {
233	opp-hz = /bits/ 64 <187500000>;
234	required-opps = <&rpmhpd_opp_low_svs>;
235	};
236
237	opp-300000000 {
238	opp-hz = /bits/ 64 <300000000>;
239	required-opps = <&rpmhpd_opp_svs>;
240	};
241
242	opp-358000000 {
243	opp-hz = /bits/ 64 <358000000>;
244	required-opps = <&rpmhpd_opp_svs_l1>;
245	};
246	};
247	};
248
249	dsi0_phy: phy@ae94400 {
93743d24	250	compatible = "qcom,dsi-phy-7nm-8150";
53633a89 TR	251	reg = <0x0ae94400 0x200>,
	252	<0x0ae94600 0x280>,
	253	<0x0ae94900 0x260>;
	254	reg-names = "dsi_phy",
	255	"dsi_phy_lane",
	256	"dsi_pll";
	257
	258	#clock-cells = <1>;
	259	#phy-cells = <0>;
	260
	261	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	262	<&rpmhcc RPMH_CXO_CLK>;
	263	clock-names = "iface", "ref";
	264	vdds-supply = <&vreg_dsi_phy>;
	265	};
	266
	267	dsi@ae96000 {
	268	compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
	269	reg = <0x0ae96000 0x400>;
	270	reg-names = "dsi_ctrl";
	271
	272	interrupt-parent = <&mdss>;
	273	interrupts = <5>;
	274
	275	clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
	276	<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
	277	<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
	278	<&dispcc DISP_CC_MDSS_ESC1_CLK>,
	279	<&dispcc DISP_CC_MDSS_AHB_CLK>,
	280	<&gcc GCC_DISP_HF_AXI_CLK>;
	281	clock-names = "byte",
	282	"byte_intf",
	283	"pixel",
	284	"core",
	285	"iface",
	286	"bus";
	287
	288	assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
	289	<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
	290	assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
	291
	292	operating-points-v2 = <&dsi_opp_table>;
	293	power-domains = <&rpmhpd SM8150_MMCX>;
	294
	295	phys = <&dsi1_phy>;
	296	phy-names = "dsi";
	297
	298	#address-cells = <1>;
	299	#size-cells = <0>;
	300
	301	ports {
	302	#address-cells = <1>;
	303	#size-cells = <0>;
	304
	305	port@0 {
	306	reg = <0>;
	307	dsi1_in: endpoint {
	308	remote-endpoint = <&dpu_intf2_out>;
	309	};
	310	};
	311
	312	port@1 {
	313	reg = <1>;
	314	dsi1_out: endpoint {
315	};
316	};
317	};
318	};
319
320	dsi1_phy: phy@ae96400 {
93743d24	321	compatible = "qcom,dsi-phy-7nm-8150";
53633a89 TR	322	reg = <0x0ae96400 0x200>,
	323	<0x0ae96600 0x280>,
	324	<0x0ae96900 0x260>;
	325	reg-names = "dsi_phy",
	326	"dsi_phy_lane",
	327	"dsi_pll";
	328
	329	#clock-cells = <1>;
	330	#phy-cells = <0>;
	331
	332	clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	333	<&rpmhcc RPMH_CXO_CLK>;
	334	clock-names = "iface", "ref";
	335	vdds-supply = <&vreg_dsi_phy>;
	336	};
	337	};
	338	...