projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 53633a89 TR |
1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | # Copyright (C) 2020 Texas Instruments Incorporated | |
| 3 | # Author: Peter Ujfalusi <peter.ujfalusi@ti.com> | |
| 4 | %YAML 1.2 | |
| 5 | --- | |
| 6 | $id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml# | |
| 7 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 8 | ||
| 9 | title: Texas Instruments K3 DMSS PKTDMA | |
| 10 | ||
| 11 | maintainers: | |
| 12 | - Peter Ujfalusi <peter.ujfalusi@gmail.com> | |
| 13 | ||
| 14 | description: | | |
| 15 | The Packet DMA (PKTDMA) is intended to perform similar functions as the packet | |
| 16 | mode channels of K3 UDMA-P. | |
| 17 | PKTDMA only includes Split channels to service PSI-L based peripherals. | |
| 18 | ||
| 19 | The peripherals can be PSI-L native or legacy, non PSI-L native peripherals | |
| 20 | with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the | |
| 21 | legacy peripheral. | |
| 22 | ||
| 23 | PDMAs can be configured via PKTDMA split channel's peer registers to match | |
| 24 | with the configuration of the legacy peripheral. | |
| 25 | ||
| 26 | allOf: | |
| 27 | - $ref: /schemas/dma/dma-controller.yaml# | |
| 28 | - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# | |
| 29 | ||
| 30 | properties: | |
| 31 | compatible: | |
| 32 | const: ti,am64-dmss-pktdma | |
| 33 | ||
| 34 | "#dma-cells": | |
| 35 | const: 2 | |
| 36 | description: | | |
| 37 | The first cell is the PSI-L thread ID of the remote (to PKTDMA) end. | |
| 38 | Valid ranges for thread ID depends on the data movement direction: | |
| 39 | for source thread IDs (rx): 0 - 0x7fff | |
| 40 | for destination thread IDs (tx): 0x8000 - 0xffff | |
| 41 | ||
| 42 | Please refer to the device documentation for the PSI-L thread map and also | |
| 43 | the PSI-L peripheral chapter for the correct thread ID. | |
| 44 | ||
| 45 | The second cell is the ASEL value for the channel | |
| 46 | ||
| 47 | reg: | |
| 93743d24 TR |
48 | minItems: 4 |
| 49 | items: | |
| 50 | - description: Packet DMA Control /Status Registers region | |
| 51 | - description: RX Channel Realtime Registers region | |
| 52 | - description: TX Channel Realtime Registers region | |
| 53 | - description: Ring Realtime Registers region | |
| 54 | - description: Ring Configuration Registers region | |
| 55 | - description: TX Configuration Registers region | |
| 56 | - description: RX Configuration Registers region | |
| 57 | - description: RX Flow Configuration Registers region | |
| 53633a89 TR |
58 | |
| 59 | reg-names: | |
| 93743d24 | 60 | minItems: 4 |
| 53633a89 TR |
61 | items: |
| 62 | - const: gcfg | |
| 63 | - const: rchanrt | |
| 64 | - const: tchanrt | |
| 65 | - const: ringrt | |
| 93743d24 TR |
66 | - const: ring |
| 67 | - const: tchan | |
| 68 | - const: rchan | |
| 69 | - const: rflow | |
| 53633a89 TR |
70 | |
| 71 | msi-parent: true | |
| 72 | ||
| 73 | ti,sci-rm-range-tchan: | |
| 74 | $ref: /schemas/types.yaml#/definitions/uint32-array | |
| 75 | description: | | |
| 76 | Array of PKTDMA split tx channel resource subtypes for resource allocation | |
| 77 | for this host | |
| 78 | minItems: 1 | |
| 79 | # Should be enough | |
| 80 | maxItems: 255 | |
| 81 | items: | |
| 82 | maximum: 0x3f | |
| 83 | ||
| 84 | ti,sci-rm-range-tflow: | |
| 85 | $ref: /schemas/types.yaml#/definitions/uint32-array | |
| 86 | description: | | |
| 87 | Array of PKTDMA split tx flow resource subtypes for resource allocation | |
| 88 | for this host | |
| 89 | minItems: 1 | |
| 90 | # Should be enough | |
| 91 | maxItems: 255 | |
| 92 | items: | |
| 93 | maximum: 0x3f | |
| 94 | ||
| 95 | ti,sci-rm-range-rchan: | |
| 96 | $ref: /schemas/types.yaml#/definitions/uint32-array | |
| 97 | description: | | |
| 98 | Array of PKTDMA split rx channel resource subtypes for resource allocation | |
| 99 | for this host | |
| 100 | minItems: 1 | |
| 101 | # Should be enough | |
| 102 | maxItems: 255 | |
| 103 | items: | |
| 104 | maximum: 0x3f | |
| 105 | ||
| 106 | ti,sci-rm-range-rflow: | |
| 107 | $ref: /schemas/types.yaml#/definitions/uint32-array | |
| 108 | description: | | |
| 109 | Array of PKTDMA split rx flow resource subtypes for resource allocation | |
| 110 | for this host | |
| 111 | minItems: 1 | |
| 112 | # Should be enough | |
| 113 | maxItems: 255 | |
| 114 | items: | |
| 115 | maximum: 0x3f | |
| 116 | ||
| 117 | required: | |
| 118 | - compatible | |
| 119 | - "#dma-cells" | |
| 120 | - reg | |
| 121 | - reg-names | |
| 122 | - msi-parent | |
| 123 | - ti,sci | |
| 124 | - ti,sci-dev-id | |
| 125 | - ti,sci-rm-range-tchan | |
| 126 | - ti,sci-rm-range-tflow | |
| 127 | - ti,sci-rm-range-rchan | |
| 128 | - ti,sci-rm-range-rflow | |
| 129 | ||
| 130 | unevaluatedProperties: false | |
| 131 | ||
| 132 | examples: | |
| 133 | - |+ | |
| 134 | cbass_main { | |
| 135 | #address-cells = <2>; | |
| 136 | #size-cells = <2>; | |
| 137 | ||
| 138 | main_dmss { | |
| 139 | compatible = "simple-mfd"; | |
| 140 | #address-cells = <2>; | |
| 141 | #size-cells = <2>; | |
| 142 | dma-ranges; | |
| 143 | ranges; | |
| 144 | ||
| 145 | ti,sci-dev-id = <25>; | |
| 146 | ||
| 147 | main_pktdma: dma-controller@485c0000 { | |
| 148 | compatible = "ti,am64-dmss-pktdma"; | |
| 149 | ||
| 150 | reg = <0x0 0x485c0000 0x0 0x100>, | |
| 151 | <0x0 0x4a800000 0x0 0x20000>, | |
| 152 | <0x0 0x4aa00000 0x0 0x40000>, | |
| 93743d24 TR |
153 | <0x0 0x4b800000 0x0 0x400000>, |
| 154 | <0x0 0x485e0000 0x0 0x20000>, | |
| 155 | <0x0 0x484a0000 0x0 0x4000>, | |
| 156 | <0x0 0x484c0000 0x0 0x2000>, | |
| 157 | <0x0 0x48430000 0x0 0x4000>; | |
| 158 | reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", | |
| 159 | "ring", "tchan", "rchan", "rflow"; | |
| 160 | ||
| 53633a89 TR |
161 | msi-parent = <&inta_main_dmss>; |
| 162 | #dma-cells = <2>; | |
| 163 | ||
| 164 | ti,sci = <&dmsc>; | |
| 165 | ti,sci-dev-id = <30>; | |
| 166 | ||
| 167 | ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ | |
| 168 | <0x24>, /* CPSW_TX_CHAN */ | |
| 169 | <0x25>, /* SAUL_TX_0_CHAN */ | |
| 170 | <0x26>, /* SAUL_TX_1_CHAN */ | |
| 171 | <0x27>, /* ICSSG_0_TX_CHAN */ | |
| 172 | <0x28>; /* ICSSG_1_TX_CHAN */ | |
| 173 | ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ | |
| 174 | <0x11>, /* RING_CPSW_TX_CHAN */ | |
| 175 | <0x12>, /* RING_SAUL_TX_0_CHAN */ | |
| 176 | <0x13>, /* RING_SAUL_TX_1_CHAN */ | |
| 177 | <0x14>, /* RING_ICSSG_0_TX_CHAN */ | |
| 178 | <0x15>; /* RING_ICSSG_1_TX_CHAN */ | |
| 179 | ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ | |
| 180 | <0x2b>, /* CPSW_RX_CHAN */ | |
| 181 | <0x2d>, /* SAUL_RX_0_CHAN */ | |
| 182 | <0x2f>, /* SAUL_RX_1_CHAN */ | |
| 183 | <0x31>, /* SAUL_RX_2_CHAN */ | |
| 184 | <0x33>, /* SAUL_RX_3_CHAN */ | |
| 185 | <0x35>, /* ICSSG_0_RX_CHAN */ | |
| 186 | <0x37>; /* ICSSG_1_RX_CHAN */ | |
| 187 | ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ | |
| 188 | <0x2c>, /* FLOW_CPSW_RX_CHAN */ | |
| 189 | <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ | |
| 190 | <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ | |
| 191 | <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ | |
| 192 | <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ | |
| 193 | }; | |
| 194 | }; | |
| 195 | }; |