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53633a89 TR |
1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: Analog Devices AD2S90 Resolver-to-Digital Converter | |
8 | ||
9 | maintainers: | |
10 | - Matheus Tavares <matheus.bernardino@usp.br> | |
11 | ||
12 | description: | | |
13 | Datasheet: https://www.analog.com/en/products/ad2s90.html | |
14 | ||
15 | properties: | |
16 | compatible: | |
17 | const: adi,ad2s90 | |
18 | ||
19 | reg: | |
20 | maxItems: 1 | |
21 | ||
22 | spi-max-frequency: | |
23 | maximum: 830000 | |
24 | description: | | |
25 | Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns | |
26 | delay is expected between the application of a logic LO to CS and the | |
27 | application of SCLK, as also specified. And since the delay is not | |
28 | implemented in the spi code, to satisfy it, SCLK's period should be at | |
29 | most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives | |
30 | roughly 830000Hz. | |
31 | ||
32 | spi-cpol: true | |
33 | ||
34 | spi-cpha: true | |
35 | ||
36 | required: | |
37 | - compatible | |
38 | - reg | |
39 | ||
40 | dependencies: | |
41 | spi-cpol: [ spi-cpha ] | |
42 | spi-cpha: [ spi-cpol ] | |
43 | ||
44 | allOf: | |
45 | - $ref: /schemas/spi/spi-peripheral-props.yaml# | |
46 | ||
47 | unevaluatedProperties: false | |
48 | ||
49 | examples: | |
50 | - | | |
51 | spi { | |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
54 | ||
55 | resolver@0 { | |
56 | compatible = "adi,ad2s90"; | |
57 | reg = <0>; | |
58 | spi-max-frequency = <830000>; | |
59 | spi-cpol; | |
60 | spi-cpha; | |
61 | }; | |
62 | }; | |
63 | ... |