projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 53633a89 TR |
1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 | |
| 3 | --- | |
| 4 | $id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml# | |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| 6 | ||
| 7 | title: Qualcom MPM Interrupt Controller | |
| 8 | ||
| 9 | maintainers: | |
| 10 | - Shawn Guo <shawn.guo@linaro.org> | |
| 11 | ||
| 12 | description: | |
| 13 | Qualcomm Technologies Inc. SoCs based on the RPM architecture have a | |
| 14 | MSM Power Manager (MPM) that is in always-on domain. In addition to managing | |
| 15 | resources during sleep, the hardware also has an interrupt controller that | |
| 16 | monitors the interrupts when the system is asleep, wakes up the APSS when | |
| 17 | one of these interrupts occur and replays it to GIC interrupt controller | |
| 18 | after GIC becomes operational. | |
| 19 | ||
| 20 | allOf: | |
| 21 | - $ref: /schemas/interrupt-controller.yaml# | |
| 22 | ||
| 23 | properties: | |
| 24 | compatible: | |
| 25 | items: | |
| 26 | - const: qcom,mpm | |
| 27 | ||
| 28 | reg: | |
| 29 | maxItems: 1 | |
| 30 | description: | |
| 31 | Specifies the base address and size of vMPM registers in RPM MSG RAM. | |
| 93743d24 TR |
32 | deprecated: true |
| 33 | ||
| 34 | qcom,rpm-msg-ram: | |
| 35 | $ref: /schemas/types.yaml#/definitions/phandle | |
| 36 | description: | |
| 37 | Phandle to the APSS MPM slice of the RPM Message RAM | |
| 53633a89 TR |
38 | |
| 39 | interrupts: | |
| 40 | maxItems: 1 | |
| 41 | description: | |
| 42 | Specify the IRQ used by RPM to wakeup APSS. | |
| 43 | ||
| 44 | mboxes: | |
| 45 | maxItems: 1 | |
| 46 | description: | |
| 47 | Specify the mailbox used to notify RPM for writing vMPM registers. | |
| 48 | ||
| 49 | interrupt-controller: true | |
| 50 | ||
| 51 | '#interrupt-cells': | |
| 52 | const: 2 | |
| 53 | description: | |
| 54 | The first cell is the MPM pin number for the interrupt, and the second | |
| 55 | is the trigger type. | |
| 56 | ||
| 57 | qcom,mpm-pin-count: | |
| 58 | description: | |
| 59 | Specify the total MPM pin count that a SoC supports. | |
| 60 | $ref: /schemas/types.yaml#/definitions/uint32 | |
| 61 | ||
| 62 | qcom,mpm-pin-map: | |
| 63 | description: | |
| 64 | A set of MPM pin numbers and the corresponding GIC SPIs. | |
| 65 | $ref: /schemas/types.yaml#/definitions/uint32-matrix | |
| 66 | items: | |
| 67 | items: | |
| 68 | - description: MPM pin number | |
| 69 | - description: GIC SPI number for the MPM pin | |
| 70 | ||
| 71 | '#power-domain-cells': | |
| 72 | const: 0 | |
| 73 | ||
| 74 | required: | |
| 75 | - compatible | |
| 53633a89 TR |
76 | - interrupts |
| 77 | - mboxes | |
| 78 | - interrupt-controller | |
| 79 | - '#interrupt-cells' | |
| 80 | - qcom,mpm-pin-count | |
| 81 | - qcom,mpm-pin-map | |
| 93743d24 | 82 | - qcom,rpm-msg-ram |
| 53633a89 TR |
83 | |
| 84 | additionalProperties: false | |
| 85 | ||
| 86 | examples: | |
| 87 | - | | |
| 88 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 93743d24 TR |
89 | |
| 90 | remoteproc-rpm { | |
| 91 | compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; | |
| 92 | ||
| 93 | glink-edge { | |
| 94 | compatible = "qcom,glink-rpm"; | |
| 95 | ||
| 96 | interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; | |
| 97 | qcom,rpm-msg-ram = <&rpm_msg_ram>; | |
| 98 | mboxes = <&apcs_glb 0>; | |
| 99 | }; | |
| 100 | ||
| 101 | mpm: interrupt-controller { | |
| 102 | compatible = "qcom,mpm"; | |
| 103 | qcom,rpm-msg-ram = <&apss_mpm>; | |
| 104 | interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; | |
| 105 | mboxes = <&apcs_glb 1>; | |
| 106 | interrupt-controller; | |
| 107 | #interrupt-cells = <2>; | |
| 108 | interrupt-parent = <&intc>; | |
| 109 | qcom,mpm-pin-count = <96>; | |
| 110 | qcom,mpm-pin-map = <2 275>, | |
| 111 | <5 296>, | |
| 112 | <12 422>, | |
| 113 | <24 79>, | |
| 114 | <86 183>, | |
| 115 | <91 260>; | |
| 116 | #power-domain-cells = <0>; | |
| 117 | }; | |
| 53633a89 | 118 | }; |