projects / thirdparty / kernel / stable.git / blame
| Commit | Line | Data |
|---|---|---|
| 871b4560 LP |
1 | Renesas R-Car LVDS Encoder |
| 2 | ========================== | |
| 3 | ||
| 4 | These DT bindings describe the LVDS encoder embedded in the Renesas R-Car | |
| 5 | Gen2, R-Car Gen3 and RZ/G SoCs. | |
| 6 | ||
| 7 | Required properties: | |
| 8 | ||
| 9 | - compatible : Shall contain one of | |
| 10 | - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders | |
| 8a2fe6c0 | 11 | - "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders |
| 1cac4f26 | 12 | - "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders |
| 871b4560 LP |
13 | - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders |
| 14 | - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders | |
| 15 | - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders | |
| 16 | - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders | |
| 17 | - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders | |
| 828ff2ad | 18 | - "renesas,r8a77965-lvds" for R8A77965 (R-Car M3-N) compatible LVDS encoders |
| 15c12c17 | 19 | - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders |
| ab77eb4c | 20 | - "renesas,r8a77980-lvds" for R8A77980 (R-Car V3H) compatible LVDS encoders |
| f9c32db1 | 21 | - "renesas,r8a77990-lvds" for R8A77990 (R-Car E3) compatible LVDS encoders |
| 77f59f89 | 22 | - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders |
| 871b4560 LP |
23 | |
| 24 | - reg: Base address and length for the memory-mapped registers | |
| 9734a700 LP |
25 | - clocks: A list of phandles + clock-specifier pairs, one for each entry in |
| 26 | the clock-names property. | |
| 27 | - clock-names: Name of the clocks. This property is model-dependent. | |
| 28 | - The functional clock, which mandatory for all models, shall be listed | |
| 29 | first, and shall be named "fck". | |
| 1cac4f26 | 30 | - On R8A77990, R8A77995 and R8A774C0, the LVDS encoder can use the EXTAL or |
| 9734a700 LP |
31 | DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be |
| 32 | named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN | |
| 33 | numerical index. | |
| 34 | - When the clocks property only contains the functional clock, the | |
| 35 | clock-names property may be omitted. | |
| 871b4560 LP |
36 | - resets: A phandle + reset specifier for the module reset |
| 37 | ||
| 38 | Required nodes: | |
| 39 | ||
| 40 | The LVDS encoder has two video ports. Their connections are modelled using the | |
| 41 | OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. | |
| 42 | ||
| 43 | - Video port 0 corresponds to the parallel RGB input | |
| 44 | - Video port 1 corresponds to the LVDS output | |
| 45 | ||
| 46 | Each port shall have a single endpoint. | |
| 47 | ||
| 48 | ||
| 49 | Example: | |
| 50 | ||
| 51 | lvds0: lvds@feb90000 { | |
| 52 | compatible = "renesas,r8a7790-lvds"; | |
| 53 | reg = <0 0xfeb90000 0 0x1c>; | |
| 54 | clocks = <&cpg CPG_MOD 726>; | |
| 55 | resets = <&cpg 726>; | |
| 56 | ||
| 57 | ports { | |
| 58 | #address-cells = <1>; | |
| 59 | #size-cells = <0>; | |
| 60 | ||
| 61 | port@0 { | |
| 62 | reg = <0>; | |
| 63 | lvds0_in: endpoint { | |
| 64 | remote-endpoint = <&du_out_lvds0>; | |
| 65 | }; | |
| 66 | }; | |
| 67 | port@1 { | |
| 68 | reg = <1>; | |
| 69 | lvds0_out: endpoint { | |
| 70 | }; | |
| 71 | }; | |
| 72 | }; | |
| 73 | }; |