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720ad00e TR |
1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
2 | %YAML 1.2 | |
3 | --- | |
4 | $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# | |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | |
6 | ||
7 | title: NVIDIA Tegra186 (and later) SoC Memory Controller | |
8 | ||
9 | maintainers: | |
10 | - Jon Hunter <jonathanh@nvidia.com> | |
11 | - Thierry Reding <thierry.reding@gmail.com> | |
12 | ||
13 | description: | | |
14 | The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split | |
15 | into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC | |
16 | handles memory requests for 40-bit virtual addresses from internal clients | |
17 | and arbitrates among them to allocate memory bandwidth. | |
18 | ||
19 | Up to 15 GiB of physical memory can be supported. Security features such as | |
20 | encryption of traffic to and from DRAM via general security apertures are | |
21 | available for video and other secure applications, as well as DRAM ECC for | |
22 | automotive safety applications (single bit error correction and double bit | |
23 | error detection). | |
24 | ||
25 | properties: | |
26 | $nodename: | |
27 | pattern: "^memory-controller@[0-9a-f]+$" | |
28 | ||
29 | compatible: | |
30 | items: | |
31 | - enum: | |
32 | - nvidia,tegra186-mc | |
33 | - nvidia,tegra194-mc | |
34 | ||
35 | reg: | |
36 | maxItems: 1 | |
37 | ||
38 | interrupts: | |
39 | maxItems: 1 | |
40 | ||
41 | "#address-cells": | |
42 | const: 2 | |
43 | ||
44 | "#size-cells": | |
45 | const: 2 | |
46 | ||
47 | ranges: true | |
48 | ||
49 | dma-ranges: true | |
50 | ||
51 | patternProperties: | |
52 | "^external-memory-controller@[0-9a-f]+$": | |
53 | description: | |
54 | The bulk of the work involved in controlling the external memory | |
55 | controller on NVIDIA Tegra186 and later is performed on the BPMP. This | |
56 | coprocessor exposes the EMC clock that is used to set the frequency at | |
57 | which the external memory is clocked and a remote procedure call that | |
58 | can be used to obtain the set of available frequencies. | |
59 | type: object | |
60 | properties: | |
61 | compatible: | |
62 | items: | |
63 | - enum: | |
64 | - nvidia,tegra186-emc | |
65 | - nvidia,tegra194-emc | |
66 | ||
67 | reg: | |
68 | maxItems: 1 | |
69 | ||
70 | interrupts: | |
71 | maxItems: 1 | |
72 | ||
73 | clocks: | |
74 | items: | |
75 | - description: external memory clock | |
76 | ||
77 | clock-names: | |
78 | items: | |
79 | - const: emc | |
80 | ||
81 | nvidia,bpmp: | |
82 | $ref: /schemas/types.yaml#/definitions/phandle | |
83 | description: | |
84 | phandle of the node representing the BPMP | |
85 | ||
86 | required: | |
87 | - compatible | |
88 | - reg | |
89 | - interrupts | |
90 | - "#address-cells" | |
91 | - "#size-cells" | |
92 | ||
93 | additionalProperties: false | |
94 | ||
95 | examples: | |
96 | - | | |
97 | #include <dt-bindings/clock/tegra186-clock.h> | |
98 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
99 | ||
f88d59fc | 100 | bus { |
720ad00e TR |
101 | #address-cells = <2>; |
102 | #size-cells = <2>; | |
103 | ||
f88d59fc RH |
104 | memory-controller@2c00000 { |
105 | compatible = "nvidia,tegra186-mc"; | |
106 | reg = <0x0 0x02c00000 0x0 0xb0000>; | |
107 | interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; | |
108 | ||
109 | #address-cells = <2>; | |
110 | #size-cells = <2>; | |
111 | ||
112 | ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; | |
720ad00e | 113 | |
f88d59fc RH |
114 | /* |
115 | * Memory clients have access to all 40 bits that the memory | |
116 | * controller can address. | |
117 | */ | |
118 | dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; | |
720ad00e | 119 | |
f88d59fc RH |
120 | external-memory-controller@2c60000 { |
121 | compatible = "nvidia,tegra186-emc"; | |
122 | reg = <0x0 0x02c60000 0x0 0x50000>; | |
123 | interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; | |
124 | clocks = <&bpmp TEGRA186_CLK_EMC>; | |
125 | clock-names = "emc"; | |
720ad00e | 126 | |
f88d59fc RH |
127 | nvidia,bpmp = <&bpmp>; |
128 | }; | |
720ad00e TR |
129 | }; |
130 | }; | |
131 | ||
132 | bpmp: bpmp { | |
133 | compatible = "nvidia,tegra186-bpmp"; | |
134 | #clock-cells = <1>; | |
135 | }; |