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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
67482f57 AB |
2 | /* |
3 | * Copyright (C) 2017 Synopsys, Inc. All rights reserved. | |
67482f57 AB |
4 | */ |
5 | /dts-v1/; | |
6 | ||
7 | #include "skeleton.dtsi" | |
ada8affd | 8 | #include "dt-bindings/clock/snps,hsdk-cgu.h" |
67482f57 AB |
9 | |
10 | / { | |
c3dcd508 AB |
11 | model = "snps,hsdk"; |
12 | ||
67482f57 AB |
13 | #address-cells = <1>; |
14 | #size-cells = <1>; | |
15 | ||
16 | aliases { | |
17 | console = &uart0; | |
f770b3ee | 18 | spi0 = &spi0; |
67482f57 AB |
19 | }; |
20 | ||
21 | cpu_card { | |
22 | core_clk: core_clk { | |
23 | #clock-cells = <0>; | |
24 | compatible = "fixed-clock"; | |
13e57722 | 25 | clock-frequency = <500000000>; |
67482f57 AB |
26 | u-boot,dm-pre-reloc; |
27 | }; | |
28 | }; | |
29 | ||
ada8affd EP |
30 | clk-fmeas { |
31 | clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>, | |
32 | <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>, | |
33 | <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>, | |
34 | <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>, | |
35 | <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>, | |
36 | <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>, | |
37 | <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>, | |
38 | <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>, | |
39 | <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>, | |
40 | <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>, | |
41 | <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>, | |
42 | <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>, | |
43 | <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>; | |
44 | clock-names = "cpu-pll", "sys-pll", | |
45 | "tun-pll", "ddr-clk", | |
46 | "cpu-clk", "hdmi-pll", | |
47 | "tun-clk", "hdmi-clk", | |
48 | "apb-clk", "axi-clk", | |
49 | "eth-clk", "usb-clk", | |
50 | "sdio-clk", "hdmi-sys-clk", | |
51 | "gfx-core-clk", "gfx-dma-clk", | |
52 | "gfx-cfg-clk", "dmac-core-clk", | |
53 | "dmac-cfg-clk", "sdio-ref-clk", | |
54 | "spi-clk", "i2c-clk", | |
55 | "uart-clk", "ebi-clk", | |
56 | "rom-clk", "pwm-clk"; | |
57 | }; | |
58 | ||
7897f4e5 EP |
59 | cgu_clk: cgu-clk@f0000000 { |
60 | compatible = "snps,hsdk-cgu-clock"; | |
61 | reg = <0xf0000000 0x10>, <0xf00014B8 0x4>; | |
62 | #clock-cells = <1>; | |
63 | }; | |
64 | ||
67482f57 AB |
65 | uart0: serial0@f0005000 { |
66 | compatible = "snps,dw-apb-uart"; | |
67 | reg = <0xf0005000 0x1000>; | |
68 | reg-shift = <2>; | |
69 | reg-io-width = <4>; | |
70 | }; | |
71 | ||
72 | ethernet@f0008000 { | |
73 | #interrupt-cells = <1>; | |
74 | compatible = "altr,socfpga-stmmac"; | |
75 | reg = <0xf0008000 0x2000>; | |
76 | phy-mode = "gmii"; | |
77 | }; | |
78 | ||
79 | ehci@0xf0040000 { | |
80 | compatible = "generic-ehci"; | |
81 | reg = <0xf0040000 0x100>; | |
82 | }; | |
83 | ||
84 | ohci@0xf0060000 { | |
85 | compatible = "generic-ohci"; | |
86 | reg = <0xf0060000 0x100>; | |
87 | }; | |
f770b3ee | 88 | |
54858311 EP |
89 | mmcclk_ciu: mmcclk-ciu { |
90 | compatible = "fixed-clock"; | |
91 | /* | |
92 | * DW sdio controller has external ciu clock divider | |
93 | * controlled via register in SDIO IP. Due to its | |
94 | * unexpected default value (it should divide by 1 | |
95 | * but it divides by 8) SDIO IP uses wrong clock and | |
96 | * works unstable (see STAR 9001204800) | |
97 | * We switched to the minimum possible value of the | |
98 | * divisor (div-by-2) in HSDK platform code. | |
99 | * So default mmcclk ciu clock is 50000000 Hz. | |
100 | */ | |
101 | clock-frequency = <50000000>; | |
102 | #clock-cells = <0>; | |
103 | }; | |
104 | ||
105 | mmc: mmc0@f000a000 { | |
106 | compatible = "snps,dw-mshc"; | |
107 | reg = <0xf000a000 0x400>; | |
108 | bus-width = <4>; | |
109 | fifo-depth = <256>; | |
110 | clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>; | |
111 | clock-names = "biu", "ciu"; | |
112 | max-frequency = <25000000>; | |
113 | }; | |
114 | ||
f770b3ee EP |
115 | spi0: spi@f0020000 { |
116 | compatible = "snps,dw-apb-ssi"; | |
117 | reg = <0xf0020000 0x1000>; | |
118 | #address-cells = <1>; | |
119 | #size-cells = <0>; | |
120 | spi-max-frequency = <4000000>; | |
121 | clocks = <&cgu_clk CLK_SYS_SPI_REF>; | |
122 | clock-names = "spi_clk"; | |
123 | cs-gpio = <&cs_gpio 0>; | |
124 | spi_flash@0 { | |
ffd4c7c2 | 125 | compatible = "jedec,spi-nor"; |
f770b3ee EP |
126 | reg = <0>; |
127 | spi-max-frequency = <4000000>; | |
128 | }; | |
129 | }; | |
130 | ||
131 | cs_gpio: gpio@f00014b0 { | |
fe3eb7a8 | 132 | compatible = "snps,creg-gpio"; |
f770b3ee EP |
133 | reg = <0xf00014b0 0x4>; |
134 | gpio-controller; | |
135 | #gpio-cells = <1>; | |
136 | gpio-bank-name = "hsdk-spi-cs"; | |
137 | gpio-count = <1>; | |
fe3eb7a8 EP |
138 | gpio-first-shift = <0>; |
139 | gpio-bit-per-line = <2>; | |
140 | gpio-activate-val = <2>; | |
141 | gpio-deactivate-val = <3>; | |
142 | gpio-default-val = <1>; | |
f770b3ee | 143 | }; |
67482f57 | 144 | }; |