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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
c121c506 VG |
2 | /* |
3 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
c121c506 VG |
4 | */ |
5 | ||
6 | #include <linux/seq_file.h> | |
7 | #include <linux/fs.h> | |
8 | #include <linux/delay.h> | |
9 | #include <linux/root_dev.h> | |
7f35144c | 10 | #include <linux/clk.h> |
92b03314 | 11 | #include <linux/clocksource.h> |
c121c506 VG |
12 | #include <linux/console.h> |
13 | #include <linux/module.h> | |
43900edf | 14 | #include <linux/sizes.h> |
c121c506 | 15 | #include <linux/cpu.h> |
3b00b042 | 16 | #include <linux/of_clk.h> |
999159a5 | 17 | #include <linux/of_fdt.h> |
1ce0b585 | 18 | #include <linux/of.h> |
1ec9db10 | 19 | #include <linux/cache.h> |
e262e32d | 20 | #include <uapi/linux/mount.h> |
999159a5 | 21 | #include <asm/sections.h> |
c121c506 | 22 | #include <asm/arcregs.h> |
240c84b1 | 23 | #include <asm/asserts.h> |
c121c506 | 24 | #include <asm/tlb.h> |
c121c506 VG |
25 | #include <asm/setup.h> |
26 | #include <asm/page.h> | |
27 | #include <asm/irq.h> | |
854a0d95 | 28 | #include <asm/unwind.h> |
03a6d28c | 29 | #include <asm/mach_desc.h> |
619f3018 | 30 | #include <asm/smp.h> |
4827d0cf | 31 | #include <asm/dsp-impl.h> |
c121c506 VG |
32 | |
33 | #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) | |
34 | ||
4255b07f VG |
35 | unsigned int intr_to_DE_cnt; |
36 | ||
59ed9413 VG |
37 | /* Part of U-boot ABI: see head.S */ |
38 | int __initdata uboot_tag; | |
edb64bca | 39 | int __initdata uboot_magic; |
59ed9413 VG |
40 | char __initdata *uboot_arg; |
41 | ||
880beb88 | 42 | const struct machine_desc *machine_desc; |
c121c506 VG |
43 | |
44 | struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ | |
45 | ||
46 | struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; | |
47 | ||
00a4ae65 VG |
48 | static const struct id_to_str arc_legacy_rel[] = { |
49 | /* ID.ARCVER, Release */ | |
73e284d2 | 50 | #ifdef CONFIG_ISA_ARCOMPACT |
00a4ae65 VG |
51 | { 0x34, "R4.10"}, |
52 | { 0x35, "R4.11"}, | |
73e284d2 | 53 | #else |
00a4ae65 VG |
54 | { 0x51, "R2.0" }, |
55 | { 0x52, "R2.1" }, | |
56 | { 0x53, "R3.0" }, | |
73e284d2 | 57 | #endif |
00a4ae65 | 58 | { 0x00, NULL } |
d975cbc8 VG |
59 | }; |
60 | ||
00a4ae65 VG |
61 | static const struct id_to_str arc_cpu_rel[] = { |
62 | /* UARCH.MAJOR, Release */ | |
63 | { 0, "R3.10a"}, | |
64 | { 1, "R3.50a"}, | |
65 | { 0xFF, NULL } | |
73e284d2 VG |
66 | }; |
67 | ||
a150b085 VG |
68 | static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) |
69 | { | |
70 | if (is_isa_arcompact()) { | |
71 | struct bcr_iccm_arcompact iccm; | |
72 | struct bcr_dccm_arcompact dccm; | |
73 | ||
74 | READ_BCR(ARC_REG_ICCM_BUILD, iccm); | |
75 | if (iccm.ver) { | |
76 | cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ | |
77 | cpu->iccm.base_addr = iccm.base << 16; | |
78 | } | |
79 | ||
80 | READ_BCR(ARC_REG_DCCM_BUILD, dccm); | |
81 | if (dccm.ver) { | |
82 | unsigned long base; | |
83 | cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ | |
84 | ||
85 | base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); | |
86 | cpu->dccm.base_addr = base & ~0xF; | |
87 | } | |
88 | } else { | |
89 | struct bcr_iccm_arcv2 iccm; | |
90 | struct bcr_dccm_arcv2 dccm; | |
91 | unsigned long region; | |
92 | ||
93 | READ_BCR(ARC_REG_ICCM_BUILD, iccm); | |
94 | if (iccm.ver) { | |
95 | cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ | |
96 | if (iccm.sz00 == 0xF && iccm.sz01 > 0) | |
97 | cpu->iccm.sz <<= iccm.sz01; | |
98 | ||
99 | region = read_aux_reg(ARC_REG_AUX_ICCM); | |
100 | cpu->iccm.base_addr = region & 0xF0000000; | |
101 | } | |
102 | ||
103 | READ_BCR(ARC_REG_DCCM_BUILD, dccm); | |
104 | if (dccm.ver) { | |
105 | cpu->dccm.sz = 256 << dccm.sz0; | |
106 | if (dccm.sz0 == 0xF && dccm.sz1 > 0) | |
107 | cpu->dccm.sz <<= dccm.sz1; | |
108 | ||
109 | region = read_aux_reg(ARC_REG_AUX_DCCM); | |
110 | cpu->dccm.base_addr = region & 0xF0000000; | |
111 | } | |
112 | } | |
113 | } | |
114 | ||
00a4ae65 VG |
115 | static void decode_arc_core(struct cpuinfo_arc *cpu) |
116 | { | |
117 | struct bcr_uarch_build_arcv2 uarch; | |
118 | const struct id_to_str *tbl; | |
119 | ||
120 | /* | |
121 | * Up until (including) the first core4 release (0x54) things were | |
122 | * simple: AUX IDENTITY.ARCVER was sufficient to identify arc family | |
123 | * and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue) | |
124 | */ | |
125 | ||
126 | if (cpu->core.family < 0x54) { /* includes arc700 */ | |
127 | ||
128 | for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) { | |
129 | if (cpu->core.family == tbl->id) { | |
130 | cpu->release = tbl->str; | |
131 | break; | |
132 | } | |
133 | } | |
134 | ||
135 | if (is_isa_arcompact()) | |
136 | cpu->name = "ARC700"; | |
137 | else if (tbl->str) | |
138 | cpu->name = "HS38"; | |
139 | else | |
140 | cpu->name = cpu->release = "Unknown"; | |
141 | ||
142 | return; | |
143 | } | |
144 | ||
145 | /* | |
146 | * However the subsequent HS release (same 0x54) allow HS38 or HS48 | |
147 | * configurations and encode this info in a different BCR. | |
148 | * The BCR was introduced in 0x54 so can't be read unconditionally. | |
149 | */ | |
150 | ||
151 | READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch); | |
152 | ||
153 | if (uarch.prod == 4) { | |
154 | cpu->name = "HS48"; | |
155 | cpu->extn.dual = 1; | |
156 | ||
157 | } else { | |
158 | cpu->name = "HS38"; | |
159 | } | |
160 | ||
161 | for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) { | |
162 | if (uarch.maj == tbl->id) { | |
163 | cpu->release = tbl->str; | |
164 | break; | |
165 | } | |
166 | } | |
167 | } | |
168 | ||
8e457d6a | 169 | static void read_arc_build_cfg_regs(void) |
c121c506 | 170 | { |
b89bd1f4 | 171 | struct bcr_timer timer; |
56372082 | 172 | struct bcr_generic bcr; |
af617428 | 173 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; |
010a8c98 | 174 | struct bcr_isa_arcv2 isa; |
7dd380c3 | 175 | struct bcr_actionpoint ap; |
73e284d2 | 176 | |
af617428 VG |
177 | FIX_PTR(cpu); |
178 | ||
179 | READ_BCR(AUX_IDENTITY, cpu->core); | |
00a4ae65 | 180 | decode_arc_core(cpu); |
73e284d2 | 181 | |
b89bd1f4 VG |
182 | READ_BCR(ARC_REG_TIMERS_BCR, timer); |
183 | cpu->extn.timer0 = timer.t0; | |
184 | cpu->extn.timer1 = timer.t1; | |
185 | cpu->extn.rtc = timer.rtc; | |
186 | ||
af617428 | 187 | cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); |
af617428 | 188 | |
56372082 | 189 | READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); |
af617428 | 190 | |
a150b085 VG |
191 | /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ |
192 | read_decode_ccm_bcr(cpu); | |
193 | ||
c121c506 VG |
194 | read_decode_mmu_bcr(); |
195 | read_decode_cache_bcr(); | |
af617428 | 196 | |
1f6ccfff | 197 | if (is_isa_arcompact()) { |
56372082 VG |
198 | struct bcr_fp_arcompact sp, dp; |
199 | struct bcr_bpu_arcompact bpu; | |
200 | ||
201 | READ_BCR(ARC_REG_FP_BCR, sp); | |
202 | READ_BCR(ARC_REG_DPFP_BCR, dp); | |
203 | cpu->extn.fpu_sp = sp.ver ? 1 : 0; | |
204 | cpu->extn.fpu_dp = dp.ver ? 1 : 0; | |
205 | ||
206 | READ_BCR(ARC_REG_BPU_BCR, bpu); | |
207 | cpu->bpu.ver = bpu.ver; | |
208 | cpu->bpu.full = bpu.fam ? 1 : 0; | |
209 | if (bpu.ent) { | |
210 | cpu->bpu.num_cache = 256 << (bpu.ent - 1); | |
211 | cpu->bpu.num_pred = 256 << (bpu.ent - 1); | |
212 | } | |
1f6ccfff VG |
213 | } else { |
214 | struct bcr_fp_arcv2 spdp; | |
215 | struct bcr_bpu_arcv2 bpu; | |
216 | ||
217 | READ_BCR(ARC_REG_FP_V2_BCR, spdp); | |
218 | cpu->extn.fpu_sp = spdp.sp ? 1 : 0; | |
219 | cpu->extn.fpu_dp = spdp.dp ? 1 : 0; | |
220 | ||
221 | READ_BCR(ARC_REG_BPU_BCR, bpu); | |
222 | cpu->bpu.ver = bpu.ver; | |
223 | cpu->bpu.full = bpu.ft; | |
224 | cpu->bpu.num_cache = 256 << bpu.bce; | |
225 | cpu->bpu.num_pred = 2048 << bpu.pte; | |
97e98132 | 226 | cpu->bpu.ret_stk = 4 << bpu.rse; |
dea82520 | 227 | |
00a4ae65 VG |
228 | /* if dual issue hardware, is it enabled ? */ |
229 | if (cpu->extn.dual) { | |
230 | unsigned int exec_ctrl; | |
7b2e932f | 231 | |
00a4ae65 VG |
232 | READ_BCR(AUX_EXEC_CTRL, exec_ctrl); |
233 | cpu->extn.dual_enb = !(exec_ctrl & 1); | |
dea82520 | 234 | } |
56372082 VG |
235 | } |
236 | ||
7dd380c3 VG |
237 | READ_BCR(ARC_REG_AP_BCR, ap); |
238 | if (ap.ver) { | |
239 | cpu->extn.ap_num = 2 << ap.num; | |
cdf92962 | 240 | cpu->extn.ap_full = !ap.min; |
7dd380c3 | 241 | } |
56372082 VG |
242 | |
243 | READ_BCR(ARC_REG_SMART_BCR, bcr); | |
244 | cpu->extn.smart = bcr.ver ? 1 : 0; | |
245 | ||
a44ec8bd VG |
246 | READ_BCR(ARC_REG_RTT_BCR, bcr); |
247 | cpu->extn.rtt = bcr.ver ? 1 : 0; | |
248 | ||
010a8c98 VG |
249 | READ_BCR(ARC_REG_ISA_CFG_BCR, isa); |
250 | ||
73e284d2 VG |
251 | /* some hacks for lack of feature BCR info in old ARC700 cores */ |
252 | if (is_isa_arcompact()) { | |
010a8c98 | 253 | if (!isa.ver) /* ISA BCR absent, use Kconfig info */ |
73e284d2 | 254 | cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); |
010a8c98 VG |
255 | else { |
256 | /* ARC700_BUILD only has 2 bits of isa info */ | |
257 | struct bcr_generic bcr = *(struct bcr_generic *)&isa; | |
258 | cpu->isa.atomic = bcr.info & 1; | |
259 | } | |
af617428 | 260 | |
73e284d2 | 261 | cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); |
d975cbc8 VG |
262 | |
263 | /* there's no direct way to distinguish 750 vs. 770 */ | |
264 | if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3)) | |
265 | cpu->name = "ARC750"; | |
010a8c98 VG |
266 | } else { |
267 | cpu->isa = isa; | |
73e284d2 VG |
268 | } |
269 | } | |
56372082 | 270 | |
8e457d6a | 271 | static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) |
af617428 | 272 | { |
af617428 VG |
273 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; |
274 | struct bcr_identity *core = &cpu->core; | |
85d6adcb | 275 | char mpy_opt[16]; |
76551468 | 276 | int n = 0; |
56372082 | 277 | |
af617428 VG |
278 | FIX_PTR(cpu); |
279 | ||
280 | n += scnprintf(buf + n, len - n, | |
56372082 VG |
281 | "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", |
282 | core->family, core->cpu_id, core->chip_id); | |
af617428 | 283 | |
dea82520 | 284 | n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n", |
00a4ae65 | 285 | cpu_id, cpu->name, cpu->release, |
73e284d2 | 286 | is_isa_arcompact() ? "ARCompact" : "ARCv2", |
dea82520 | 287 | IS_AVAIL1(cpu->isa.be, "[Big-Endian]"), |
f3156851 | 288 | IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue ")); |
af617428 | 289 | |
04421420 | 290 | n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ", |
b89bd1f4 VG |
291 | IS_AVAIL1(cpu->extn.timer0, "Timer0 "), |
292 | IS_AVAIL1(cpu->extn.timer1, "Timer1 "), | |
04421420 VG |
293 | IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), |
294 | IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT)); | |
af617428 | 295 | |
85d6adcb VG |
296 | if (cpu->extn_mpy.ver) { |
297 | if (is_isa_arcompact()) { | |
298 | scnprintf(mpy_opt, 16, "mpy"); | |
299 | } else { | |
300 | ||
301 | int opt = 2; /* stock MPY/MPYH */ | |
302 | ||
303 | if (cpu->extn_mpy.dsp) /* OPT 7-9 */ | |
304 | opt = cpu->extn_mpy.dsp + 6; | |
305 | ||
306 | scnprintf(mpy_opt, 16, "mpy[opt %d] ", opt); | |
307 | } | |
308 | } | |
309 | ||
310 | n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", | |
76551468 EP |
311 | IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), |
312 | IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), | |
85d6adcb VG |
313 | IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS), |
314 | IS_AVAIL1(cpu->extn_mpy.ver, mpy_opt), | |
315 | IS_AVAIL1(cpu->isa.div_rem, "div_rem ")); | |
316 | ||
85d6adcb | 317 | if (cpu->bpu.ver) { |
56372082 | 318 | n += scnprintf(buf + n, len - n, |
97e98132 | 319 | "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d", |
56372082 VG |
320 | IS_AVAIL1(cpu->bpu.full, "full"), |
321 | IS_AVAIL1(!cpu->bpu.full, "partial"), | |
97e98132 | 322 | cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk); |
af617428 | 323 | |
85d6adcb VG |
324 | if (is_isa_arcv2()) { |
325 | struct bcr_lpb lpb; | |
f3156851 | 326 | |
85d6adcb VG |
327 | READ_BCR(ARC_REG_LPB_BUILD, lpb); |
328 | if (lpb.ver) { | |
329 | unsigned int ctl; | |
330 | ctl = read_aux_reg(ARC_REG_LPB_CTRL); | |
f3156851 | 331 | |
85d6adcb VG |
332 | n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s", |
333 | lpb.entries, | |
334 | IS_DISABLED_RUN(!ctl)); | |
335 | } | |
f3156851 | 336 | } |
85d6adcb | 337 | n += scnprintf(buf + n, len - n, "\n"); |
f3156851 VG |
338 | } |
339 | ||
56372082 VG |
340 | return buf; |
341 | } | |
af617428 | 342 | |
8e457d6a | 343 | static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) |
af617428 VG |
344 | { |
345 | int n = 0; | |
346 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; | |
347 | ||
348 | FIX_PTR(cpu); | |
af617428 | 349 | |
711c1f26 | 350 | n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base); |
56372082 VG |
351 | |
352 | if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) | |
353 | n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", | |
354 | IS_AVAIL1(cpu->extn.fpu_sp, "SP "), | |
355 | IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); | |
356 | ||
7dd380c3 VG |
357 | if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) { |
358 | n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s", | |
56372082 VG |
359 | IS_AVAIL1(cpu->extn.smart, "smaRT "), |
360 | IS_AVAIL1(cpu->extn.rtt, "RTT ")); | |
7dd380c3 VG |
361 | if (cpu->extn.ap_num) { |
362 | n += scnprintf(buf + n, len - n, "ActionPoint %d/%s", | |
363 | cpu->extn.ap_num, | |
364 | cpu->extn.ap_full ? "full":"min"); | |
365 | } | |
366 | n += scnprintf(buf + n, len - n, "\n"); | |
367 | } | |
56372082 VG |
368 | |
369 | if (cpu->dccm.sz || cpu->iccm.sz) | |
370 | n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", | |
371 | cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), | |
af617428 VG |
372 | cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); |
373 | ||
f3156851 VG |
374 | if (is_isa_arcv2()) { |
375 | ||
376 | /* Error Protection: ECC/Parity */ | |
377 | struct bcr_erp erp; | |
378 | READ_BCR(ARC_REG_ERP_BUILD, erp); | |
379 | ||
380 | if (erp.ver) { | |
381 | struct ctl_erp ctl; | |
382 | READ_BCR(ARC_REG_ERP_CTRL, ctl); | |
383 | ||
384 | /* inverted bits: 0 means enabled */ | |
385 | n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n", | |
386 | IS_AVAIL3(erp.ic, !ctl.dpi, "IC "), | |
387 | IS_AVAIL3(erp.dc, !ctl.dpd, "DC "), | |
388 | IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU ")); | |
389 | } | |
390 | } | |
391 | ||
af617428 VG |
392 | return buf; |
393 | } | |
394 | ||
240c84b1 EP |
395 | void chk_opt_strict(char *opt_name, bool hw_exists, bool opt_ena) |
396 | { | |
397 | if (hw_exists && !opt_ena) | |
398 | pr_warn(" ! Enable %s for working apps\n", opt_name); | |
399 | else if (!hw_exists && opt_ena) | |
400 | panic("Disable %s, hardware NOT present\n", opt_name); | |
401 | } | |
402 | ||
f09d3174 EP |
403 | void chk_opt_weak(char *opt_name, bool hw_exists, bool opt_ena) |
404 | { | |
405 | if (!hw_exists && opt_ena) | |
406 | panic("Disable %s, hardware NOT present\n", opt_name); | |
407 | } | |
408 | ||
c4b9856b | 409 | static void arc_chk_core_config(void) |
8b5850f8 | 410 | { |
8b5850f8 | 411 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; |
240c84b1 | 412 | int present = 0; |
8b5850f8 | 413 | |
b89bd1f4 | 414 | if (!cpu->extn.timer0) |
56372082 VG |
415 | panic("Timer0 is not present!\n"); |
416 | ||
b89bd1f4 | 417 | if (!cpu->extn.timer1) |
56372082 VG |
418 | panic("Timer1 is not present!\n"); |
419 | ||
8b5850f8 VG |
420 | #ifdef CONFIG_ARC_HAS_DCCM |
421 | /* | |
422 | * DCCM can be arbit placed in hardware. | |
423 | * Make sure it's placement/sz matches what Linux is built with | |
424 | */ | |
425 | if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) | |
426 | panic("Linux built with incorrect DCCM Base address\n"); | |
427 | ||
43900edf | 428 | if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz) |
8b5850f8 VG |
429 | panic("Linux built with incorrect DCCM Size\n"); |
430 | #endif | |
431 | ||
432 | #ifdef CONFIG_ARC_HAS_ICCM | |
43900edf | 433 | if (CONFIG_ARC_ICCM_SZ * SZ_1K != cpu->iccm.sz) |
8b5850f8 VG |
434 | panic("Linux built with incorrect ICCM Size\n"); |
435 | #endif | |
8b5850f8 | 436 | |
c4b9856b VG |
437 | /* |
438 | * FP hardware/software config sanity | |
3d5e8012 | 439 | * -If hardware present, kernel needs to save/restore FPU state |
c4b9856b | 440 | * -If not, it will crash trying to save/restore the non-existant regs |
c4b9856b | 441 | */ |
af617428 | 442 | |
3d5e8012 | 443 | if (is_isa_arcompact()) { |
3d5e8012 VG |
444 | /* only DPDP checked since SP has no arch visible regs */ |
445 | present = cpu->extn.fpu_dp; | |
240c84b1 | 446 | CHK_OPT_STRICT(CONFIG_ARC_FPU_SAVE_RESTORE, present); |
3d5e8012 | 447 | } else { |
3d5e8012 VG |
448 | /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */ |
449 | present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp; | |
240c84b1 | 450 | CHK_OPT_STRICT(CONFIG_ARC_HAS_ACCL_REGS, present); |
4827d0cf EP |
451 | |
452 | dsp_config_check(); | |
3d5e8012 | 453 | } |
c121c506 VG |
454 | } |
455 | ||
456 | /* | |
457 | * Initialize and setup the processor core | |
458 | * This is called by all the CPUs thus should not do special case stuff | |
459 | * such as only for boot CPU etc | |
460 | */ | |
461 | ||
ce759956 | 462 | void setup_processor(void) |
c121c506 | 463 | { |
af617428 VG |
464 | char str[512]; |
465 | int cpu_id = smp_processor_id(); | |
466 | ||
c121c506 VG |
467 | read_arc_build_cfg_regs(); |
468 | arc_init_IRQ(); | |
af617428 | 469 | |
18ee4bec | 470 | pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); |
af617428 | 471 | |
c121c506 VG |
472 | arc_mmu_init(); |
473 | arc_cache_init(); | |
af617428 | 474 | |
18ee4bec NC |
475 | pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); |
476 | pr_info("%s", arc_platform_smp_cpuinfo()); | |
af617428 | 477 | |
c4b9856b | 478 | arc_chk_core_config(); |
c121c506 VG |
479 | } |
480 | ||
a66f2e57 | 481 | static inline bool uboot_arg_invalid(unsigned long addr) |
59ed9413 | 482 | { |
a66f2e57 EP |
483 | /* |
484 | * Check that it is a untranslated address (although MMU is not enabled | |
485 | * yet, it being a high address ensures this is not by fluke) | |
486 | */ | |
487 | if (addr < PAGE_OFFSET) | |
488 | return true; | |
489 | ||
490 | /* Check that address doesn't clobber resident kernel image */ | |
491 | return addr >= (unsigned long)_stext && addr <= (unsigned long)_end; | |
59ed9413 VG |
492 | } |
493 | ||
a66f2e57 EP |
494 | #define IGNORE_ARGS "Ignore U-boot args: " |
495 | ||
496 | /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */ | |
497 | #define UBOOT_TAG_NONE 0 | |
498 | #define UBOOT_TAG_CMDLINE 1 | |
499 | #define UBOOT_TAG_DTB 2 | |
edb64bca EP |
500 | /* We always pass 0 as magic from U-boot */ |
501 | #define UBOOT_MAGIC_VALUE 0 | |
a66f2e57 EP |
502 | |
503 | void __init handle_uboot_args(void) | |
c121c506 | 504 | { |
a66f2e57 EP |
505 | bool use_embedded_dtb = true; |
506 | bool append_cmdline = false; | |
507 | ||
a66f2e57 EP |
508 | /* check that we know this tag */ |
509 | if (uboot_tag != UBOOT_TAG_NONE && | |
510 | uboot_tag != UBOOT_TAG_CMDLINE && | |
511 | uboot_tag != UBOOT_TAG_DTB) { | |
512 | pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag); | |
513 | goto ignore_uboot_args; | |
514 | } | |
515 | ||
edb64bca EP |
516 | if (uboot_magic != UBOOT_MAGIC_VALUE) { |
517 | pr_warn(IGNORE_ARGS "non zero uboot magic\n"); | |
518 | goto ignore_uboot_args; | |
519 | } | |
520 | ||
a66f2e57 EP |
521 | if (uboot_tag != UBOOT_TAG_NONE && |
522 | uboot_arg_invalid((unsigned long)uboot_arg)) { | |
523 | pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg); | |
524 | goto ignore_uboot_args; | |
525 | } | |
526 | ||
527 | /* see if U-boot passed an external Device Tree blob */ | |
528 | if (uboot_tag == UBOOT_TAG_DTB) { | |
529 | machine_desc = setup_machine_fdt((void *)uboot_arg); | |
e57d339a | 530 | |
a66f2e57 EP |
531 | /* external Device Tree blob is invalid - use embedded one */ |
532 | use_embedded_dtb = !machine_desc; | |
533 | } | |
534 | ||
535 | if (uboot_tag == UBOOT_TAG_CMDLINE) | |
536 | append_cmdline = true; | |
537 | ||
538 | ignore_uboot_args: | |
a66f2e57 EP |
539 | |
540 | if (use_embedded_dtb) { | |
59ed9413 VG |
541 | machine_desc = setup_machine_fdt(__dtb_start); |
542 | if (!machine_desc) | |
543 | panic("Embedded DT invalid\n"); | |
a66f2e57 | 544 | } |
59ed9413 | 545 | |
a66f2e57 EP |
546 | /* |
547 | * NOTE: @boot_command_line is populated by setup_machine_fdt() so this | |
548 | * append processing can only happen after. | |
549 | */ | |
550 | if (append_cmdline) { | |
551 | /* Ensure a whitespace between the 2 cmdlines */ | |
552 | strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); | |
553 | strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE); | |
e57d339a | 554 | } |
a66f2e57 EP |
555 | } |
556 | ||
557 | void __init setup_arch(char **cmdline_p) | |
558 | { | |
559 | handle_uboot_args(); | |
c121c506 VG |
560 | |
561 | /* Save unparsed command line copy for /proc/cmdline */ | |
9593a933 | 562 | *cmdline_p = boot_command_line; |
999159a5 | 563 | |
c121c506 VG |
564 | /* To force early parsing of things like mem=xxx */ |
565 | parse_early_param(); | |
566 | ||
567 | /* Platform/board specific: e.g. early console registration */ | |
03a6d28c VG |
568 | if (machine_desc->init_early) |
569 | machine_desc->init_early(); | |
c121c506 | 570 | |
41195d23 | 571 | smp_init_cpus(); |
e55af4da VG |
572 | |
573 | setup_processor(); | |
c121c506 VG |
574 | setup_arch_memory(); |
575 | ||
eab6a08c | 576 | /* copy flat DT out of .init and then unflatten it */ |
1efc959e | 577 | unflatten_and_copy_device_tree(); |
999159a5 | 578 | |
c121c506 VG |
579 | /* Can be issue if someone passes cmd line arg "ro" |
580 | * But that is unlikely so keeping it as it is | |
581 | */ | |
582 | root_mountflags &= ~MS_RDONLY; | |
583 | ||
854a0d95 | 584 | arc_unwind_init(); |
c121c506 VG |
585 | } |
586 | ||
92b03314 VG |
587 | /* |
588 | * Called from start_kernel() - boot CPU only | |
589 | */ | |
590 | void __init time_init(void) | |
591 | { | |
592 | of_clk_init(NULL); | |
ba5d08c0 | 593 | timer_probe(); |
92b03314 VG |
594 | } |
595 | ||
03a6d28c VG |
596 | static int __init customize_machine(void) |
597 | { | |
03a6d28c VG |
598 | if (machine_desc->init_machine) |
599 | machine_desc->init_machine(); | |
600 | ||
601 | return 0; | |
602 | } | |
603 | arch_initcall(customize_machine); | |
604 | ||
605 | static int __init init_late_machine(void) | |
606 | { | |
607 | if (machine_desc->init_late) | |
608 | machine_desc->init_late(); | |
609 | ||
610 | return 0; | |
611 | } | |
612 | late_initcall(init_late_machine); | |
c121c506 VG |
613 | /* |
614 | * Get CPU information for use by the procfs. | |
615 | */ | |
616 | ||
617 | #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c))) | |
618 | #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p)) | |
619 | ||
620 | static int show_cpuinfo(struct seq_file *m, void *v) | |
621 | { | |
622 | char *str; | |
623 | int cpu_id = ptr_to_cpu(v); | |
7f35144c VZ |
624 | struct device *cpu_dev = get_cpu_device(cpu_id); |
625 | struct clk *cpu_clk; | |
626 | unsigned long freq = 0; | |
c121c506 | 627 | |
4c86231c VG |
628 | if (!cpu_online(cpu_id)) { |
629 | seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); | |
630 | goto done; | |
631 | } | |
632 | ||
0ee931c4 | 633 | str = (char *)__get_free_page(GFP_KERNEL); |
c121c506 VG |
634 | if (!str) |
635 | goto done; | |
636 | ||
af617428 | 637 | seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
c121c506 | 638 | |
7f35144c VZ |
639 | cpu_clk = clk_get(cpu_dev, NULL); |
640 | if (IS_ERR(cpu_clk)) { | |
641 | seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n", | |
642 | cpu_id); | |
643 | } else { | |
644 | freq = clk_get_rate(cpu_clk); | |
645 | } | |
20c7dbbd | 646 | if (freq) |
7f35144c | 647 | seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n", |
20c7dbbd AB |
648 | freq / 1000000, (freq / 10000) % 100); |
649 | ||
56372082 | 650 | seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", |
c121c506 VG |
651 | loops_per_jiffy / (500000 / HZ), |
652 | (loops_per_jiffy / (5000 / HZ)) % 100); | |
653 | ||
af617428 | 654 | seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 655 | seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 656 | seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 657 | seq_printf(m, arc_platform_smp_cpuinfo()); |
af617428 | 658 | |
c121c506 VG |
659 | free_page((unsigned long)str); |
660 | done: | |
4c86231c | 661 | seq_printf(m, "\n"); |
c121c506 VG |
662 | |
663 | return 0; | |
664 | } | |
665 | ||
666 | static void *c_start(struct seq_file *m, loff_t *pos) | |
667 | { | |
668 | /* | |
669 | * Callback returns cpu-id to iterator for show routine, NULL to stop. | |
670 | * However since NULL is also a valid cpu-id (0), we use a round-about | |
671 | * way to pass it w/o having to kmalloc/free a 2 byte string. | |
672 | * Encode cpu-id as 0xFFcccc, which is decoded by show routine. | |
673 | */ | |
3da43104 | 674 | return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL; |
c121c506 VG |
675 | } |
676 | ||
677 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
678 | { | |
679 | ++*pos; | |
680 | return c_start(m, pos); | |
681 | } | |
682 | ||
683 | static void c_stop(struct seq_file *m, void *v) | |
684 | { | |
685 | } | |
686 | ||
687 | const struct seq_operations cpuinfo_op = { | |
688 | .start = c_start, | |
689 | .next = c_next, | |
690 | .stop = c_stop, | |
691 | .show = show_cpuinfo | |
692 | }; | |
693 | ||
694 | static DEFINE_PER_CPU(struct cpu, cpu_topology); | |
695 | ||
696 | static int __init topology_init(void) | |
697 | { | |
698 | int cpu; | |
699 | ||
700 | for_each_present_cpu(cpu) | |
701 | register_cpu(&per_cpu(cpu_topology, cpu), cpu); | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
706 | subsys_initcall(topology_init); |