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Commit | Line | Data |
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b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | config ARM |
3 | bool | |
4 | default y | |
942fa985 | 5 | select ARCH_32BIT_OFF_T |
fed240d9 | 6 | select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND |
aef0f78e | 7 | select ARCH_HAS_BINFMT_FLAT |
ee31bb05 | 8 | select ARCH_HAS_CPU_FINALIZE_INIT if MMU |
2792d84e | 9 | select ARCH_HAS_CURRENT_STACK_POINTER |
c7780ab5 | 10 | select ARCH_HAS_DEBUG_VIRTUAL if MMU |
419e2f18 | 11 | select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE |
2b68f6ca | 12 | select ARCH_HAS_ELF_RANDOMIZE |
ee333554 | 13 | select ARCH_HAS_FORTIFY_SOURCE |
d8ae8a37 | 14 | select ARCH_HAS_KEEPINITRD |
75851720 | 15 | select ARCH_HAS_KCOV |
e69244d2 | 16 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
0ebeea8c | 17 | select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE |
3010a5ea | 18 | select ARCH_HAS_PTE_SPECIAL if ARM_LPAE |
347cb6af | 19 | select ARCH_HAS_SETUP_DMA_OPS |
75851720 | 20 | select ARCH_HAS_SET_MEMORY |
9fbed16c | 21 | select ARCH_STACKWALK |
ad21fc4f LA |
22 | select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL |
23 | select ARCH_HAS_STRICT_MODULE_RWX if MMU | |
ae626eb9 CH |
24 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
25 | select ARCH_HAS_SYNC_DMA_FOR_CPU | |
dc2acded | 26 | select ARCH_HAS_TEARDOWN_DMA_OPS if MMU |
3d06770e | 27 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
9aaf9bb7 | 28 | select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K |
957e3fac | 29 | select ARCH_HAS_GCOV_PROFILE_ALL |
5e545df3 | 30 | select ARCH_KEEP_MEMBLOCK |
d539fee9 | 31 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
d7018848 | 32 | select ARCH_MIGHT_HAVE_PC_PARPORT |
ad21fc4f LA |
33 | select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX |
34 | select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 | |
4badad35 | 35 | select ARCH_SUPPORTS_ATOMIC_RMW |
855f9a8e | 36 | select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE |
017f161a | 37 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 38 | select ARCH_USE_CMPXCHG_LOCKREF |
dce44566 | 39 | select ARCH_USE_MEMTEST |
dba79c3d | 40 | select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU |
07431506 | 41 | select ARCH_WANT_GENERAL_HUGETLB |
b1b3f49c | 42 | select ARCH_WANT_IPC_PARSE_VERSION |
59612b24 | 43 | select ARCH_WANT_LD_ORPHAN_WARN |
bdd15a28 | 44 | select BINFMT_FLAT_ARGVP_ENVP_ON_STACK |
10916706 | 45 | select BUILDTIME_TABLE_SORT if MMU |
6fd09c9a | 46 | select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) |
171b3f0d | 47 | select CLONE_BACKWARDS |
f00790aa | 48 | select CPU_PM if SUSPEND || CPU_IDLE |
dce5c9e3 | 49 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
ff4c25f2 | 50 | select DMA_DECLARE_COHERENT |
31b089bb | 51 | select DMA_GLOBAL_POOL if !MMU |
2f9237d4 | 52 | select DMA_OPS |
f5ff79fd | 53 | select DMA_NONCOHERENT_MMAP if MMU |
b01aec9b BP |
54 | select EDAC_SUPPORT |
55 | select EDAC_ATOMIC_SCRUB | |
36d0fd21 | 56 | select GENERIC_ALLOCATOR |
2ef7a295 | 57 | select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY |
f00790aa | 58 | select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI |
b1b3f49c | 59 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
56afcd3d | 60 | select GENERIC_IRQ_IPI if SMP |
ea2d9a96 | 61 | select GENERIC_CPU_AUTOPROBE |
2937367b | 62 | select GENERIC_EARLY_IOREMAP |
171b3f0d | 63 | select GENERIC_IDLE_POLL_SETUP |
234a0f20 | 64 | select GENERIC_IRQ_MULTI_HANDLER |
b1b3f49c RK |
65 | select GENERIC_IRQ_PROBE |
66 | select GENERIC_IRQ_SHOW | |
7c07005e | 67 | select GENERIC_IRQ_SHOW_LEVEL |
914ee966 | 68 | select GENERIC_LIB_DEVMEM_IS_ALLOWED |
b1b3f49c | 69 | select GENERIC_PCI_IOMAP |
38ff87f7 | 70 | select GENERIC_SCHED_CLOCK |
b1b3f49c | 71 | select GENERIC_SMP_IDLE_THREAD |
b1b3f49c | 72 | select HARDIRQS_SW_RESEND |
fcbfe812 | 73 | select HAS_IOPORT |
f00790aa | 74 | select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT |
0b7857db | 75 | select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 |
437682ee | 76 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
75969686 | 77 | select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL |
437682ee | 78 | select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU |
42101571 | 79 | select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL |
565cbaad | 80 | select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN |
e0c25d95 | 81 | select HAVE_ARCH_MMAP_RND_BITS if MMU |
4f5b0c17 | 82 | select HAVE_ARCH_PFN_VALID |
282a181b | 83 | select HAVE_ARCH_SECCOMP |
f00790aa | 84 | select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT |
08626a60 | 85 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
0693bf68 | 86 | select HAVE_ARCH_TRACEHOOK |
e8003bf6 | 87 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE |
b329f95d | 88 | select HAVE_ARM_SMCCC if CPU_V7 |
39c13c20 | 89 | select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 |
24a9c541 | 90 | select HAVE_CONTEXT_TRACKING_USER |
b1b3f49c | 91 | select HAVE_C_RECORDMCOUNT |
4ed308c4 | 92 | select HAVE_BUILDTIME_MCOUNT_SORT |
bc420c6c | 93 | select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL |
b1b3f49c | 94 | select HAVE_DMA_CONTIGUOUS if MMU |
f00790aa | 95 | select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
620176f3 | 96 | select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE |
dce5c9e3 | 97 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
5f56a5df | 98 | select HAVE_EXIT_THREAD |
67a929e0 | 99 | select HAVE_FAST_GUP if ARM_LPAE |
f00790aa | 100 | select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL |
aaa4dd1b | 101 | select HAVE_FUNCTION_ERROR_INJECTION |
41918ec8 | 102 | select HAVE_FUNCTION_GRAPH_TRACER |
d6800ca7 | 103 | select HAVE_FUNCTION_TRACER if !XIP_KERNEL |
6b90bd4b | 104 | select HAVE_GCC_PLUGINS |
f00790aa | 105 | select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) |
87c46b6c | 106 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 107 | select HAVE_KERNEL_GZIP |
f9b493ac | 108 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 109 | select HAVE_KERNEL_LZMA |
b1b3f49c | 110 | select HAVE_KERNEL_LZO |
a7f464f3 | 111 | select HAVE_KERNEL_XZ |
cb1293e2 | 112 | select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M |
f00790aa | 113 | select HAVE_KRETPROBES if HAVE_KPROBES |
7d485f64 | 114 | select HAVE_MOD_ARCH_SPECIFIC |
42a0bb3f | 115 | select HAVE_NMI |
0dc016db | 116 | select HAVE_OPTPROBES if !THUMB2_KERNEL |
47723de8 | 117 | select HAVE_PCI if MMU |
7ada189f | 118 | select HAVE_PERF_EVENTS |
49863894 WD |
119 | select HAVE_PERF_REGS |
120 | select HAVE_PERF_USER_STACK_DUMP | |
ff2e6d72 | 121 | select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE |
e513f8bf | 122 | select HAVE_REGS_AND_STACK_ACCESS_API |
9800b9dc | 123 | select HAVE_RSEQ |
d148eac0 | 124 | select HAVE_STACKPROTECTOR |
b1b3f49c | 125 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 126 | select HAVE_UID16 |
31c1fc81 | 127 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
5490e769 | 128 | select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU |
da0ec6f7 | 129 | select IRQ_FORCED_THREADING |
8b35ca3e | 130 | select LOCK_MM_AND_FIND_VMA |
171b3f0d | 131 | select MODULES_USE_ELF_REL |
f616ab59 | 132 | select NEED_DMA_MAP_STATE |
aa7d5f18 | 133 | select OF_EARLY_FLATTREE if OF |
171b3f0d RK |
134 | select OLD_SIGACTION |
135 | select OLD_SIGSUSPEND3 | |
6fd09c9a | 136 | select PCI_DOMAINS_GENERIC if PCI |
20f1b79d | 137 | select PCI_SYSCALL if PCI |
b1b3f49c RK |
138 | select PERF_USE_VMALLOC |
139 | select RTC_LIB | |
6fd09c9a | 140 | select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) |
b1b3f49c | 141 | select SYS_SUPPORTS_APM_EMULATION |
9c46929e | 142 | select THREAD_INFO_IN_TASK |
6fd09c9a | 143 | select TIMER_OF if OF |
d6905849 | 144 | select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS |
4aae683f | 145 | select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M |
6fd09c9a | 146 | select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) |
171b3f0d RK |
147 | # Above selects are sorted alphabetically; please add new ones |
148 | # according to that. Thanks. | |
1da177e4 LT |
149 | help |
150 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 151 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 152 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 153 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
154 | Europe. There is an ARM Linux project with a web page at |
155 | <http://www.arm.linux.org.uk/>. | |
156 | ||
d6905849 AB |
157 | config ARM_HAS_GROUP_RELOCS |
158 | def_bool y | |
159 | depends on !LD_IS_LLD || LLD_VERSION >= 140000 | |
160 | depends on !COMPILE_TEST | |
161 | help | |
162 | Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group | |
163 | relocations, which have been around for a long time, but were not | |
164 | supported in LLD until version 14. The combined range is -/+ 256 MiB, | |
165 | which is usually sufficient, but not for allyesconfig, so we disable | |
166 | this feature when doing compile testing. | |
167 | ||
4ce63fcd | 168 | config ARM_DMA_USE_IOMMU |
4ce63fcd | 169 | bool |
b1b3f49c | 170 | select NEED_SG_DMA_LENGTH |
4ce63fcd | 171 | |
60460abf SWK |
172 | if ARM_DMA_USE_IOMMU |
173 | ||
174 | config ARM_DMA_IOMMU_ALIGNMENT | |
175 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
176 | range 4 9 | |
177 | default 8 | |
178 | help | |
179 | DMA mapping framework by default aligns all buffers to the smallest | |
180 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
181 | size. This works well for buffers up to a few hundreds kilobytes, but | |
182 | for larger buffers it just a waste of address space. Drivers which has | |
183 | relatively small addressing window (like 64Mib) might run out of | |
184 | virtual space with just a few allocations. | |
185 | ||
186 | With this parameter you can specify the maximum PAGE_SIZE order for | |
187 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
188 | specified order. The order is expressed as a power of two multiplied | |
189 | by the PAGE_SIZE. | |
190 | ||
191 | endif | |
192 | ||
75e7153a RB |
193 | config SYS_SUPPORTS_APM_EMULATION |
194 | bool | |
195 | ||
bc581770 LW |
196 | config HAVE_TCM |
197 | bool | |
198 | select GENERIC_ALLOCATOR | |
199 | ||
e119bfff RK |
200 | config HAVE_PROC_CPU |
201 | bool | |
202 | ||
ce816fa8 | 203 | config NO_IOPORT_MAP |
5ea81769 | 204 | bool |
5ea81769 | 205 | |
1da177e4 LT |
206 | config SBUS |
207 | bool | |
208 | ||
f16fb1ec RK |
209 | config STACKTRACE_SUPPORT |
210 | bool | |
211 | default y | |
212 | ||
213 | config LOCKDEP_SUPPORT | |
214 | bool | |
215 | default y | |
216 | ||
f0d1b0b3 DH |
217 | config ARCH_HAS_ILOG2_U32 |
218 | bool | |
f0d1b0b3 DH |
219 | |
220 | config ARCH_HAS_ILOG2_U64 | |
221 | bool | |
f0d1b0b3 | 222 | |
4a1b5733 EV |
223 | config ARCH_HAS_BANDGAP |
224 | bool | |
225 | ||
a5f4c561 SA |
226 | config FIX_EARLYCON_MEM |
227 | def_bool y if MMU | |
228 | ||
b89c3b16 AM |
229 | config GENERIC_HWEIGHT |
230 | bool | |
231 | default y | |
232 | ||
1da177e4 LT |
233 | config GENERIC_CALIBRATE_DELAY |
234 | bool | |
235 | default y | |
236 | ||
a08b6b79 AV |
237 | config ARCH_MAY_HAVE_PC_FDC |
238 | bool | |
239 | ||
c7edc9e3 DL |
240 | config ARCH_SUPPORTS_UPROBES |
241 | def_bool y | |
242 | ||
1da177e4 LT |
243 | config GENERIC_ISA_DMA |
244 | bool | |
245 | ||
1da177e4 LT |
246 | config FIQ |
247 | bool | |
248 | ||
034d2f5a AV |
249 | config ARCH_MTD_XIP |
250 | bool | |
251 | ||
dc21af99 | 252 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
253 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
254 | default y | |
5408445b | 255 | depends on MMU |
dc21af99 | 256 | help |
111e9a5c RK |
257 | Patch phys-to-virt and virt-to-phys translation functions at |
258 | boot and module load time according to the position of the | |
259 | kernel in system memory. | |
dc21af99 | 260 | |
111e9a5c | 261 | This can only be used with non-XIP MMU kernels where the base |
9443076e | 262 | of physical memory is at a 2 MiB boundary. |
dc21af99 | 263 | |
c1becedc RK |
264 | Only disable this option if you know that you do not require |
265 | this feature (eg, building a kernel for a single machine) and | |
266 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 267 | |
c334bc15 RH |
268 | config NEED_MACH_IO_H |
269 | bool | |
270 | help | |
271 | Select this when mach/io.h is required to provide special | |
272 | definitions for this platform. The need for mach/io.h should | |
273 | be avoided when possible. | |
274 | ||
0cdc8b92 | 275 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
276 | bool |
277 | help | |
0cdc8b92 NP |
278 | Select this when mach/memory.h is required to provide special |
279 | definitions for this platform. The need for mach/memory.h should | |
280 | be avoided when possible. | |
dc21af99 | 281 | |
1b9f95f8 | 282 | config PHYS_OFFSET |
974c0724 | 283 | hex "Physical address of main memory" if MMU |
92481c7d | 284 | depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR |
974c0724 | 285 | default DRAM_BASE if !MMU |
06954b6a | 286 | default 0x00000000 if ARCH_FOOTBRIDGE |
c6f54a9b | 287 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC |
b91a69d1 | 288 | default 0xa0000000 if ARCH_PXA |
c6e77bb6 AB |
289 | default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 |
290 | default 0 | |
111e9a5c | 291 | help |
1b9f95f8 NP |
292 | Please provide the physical address corresponding to the |
293 | location of main memory in your system. | |
cada3c08 | 294 | |
87e040b6 SG |
295 | config GENERIC_BUG |
296 | def_bool y | |
297 | depends on BUG | |
298 | ||
1bcad26e KS |
299 | config PGTABLE_LEVELS |
300 | int | |
301 | default 3 if ARM_LPAE | |
302 | default 2 | |
303 | ||
1da177e4 LT |
304 | menu "System Type" |
305 | ||
3c427975 HC |
306 | config MMU |
307 | bool "MMU-based Paged Memory Management Support" | |
308 | default y | |
309 | help | |
310 | Select if you want MMU-based virtualised addressing space | |
311 | support by paged memory management. If unsure, say 'Y'. | |
312 | ||
2f618d5e AB |
313 | config ARM_SINGLE_ARMV7M |
314 | def_bool !MMU | |
315 | select ARM_NVIC | |
2f618d5e AB |
316 | select CPU_V7M |
317 | select NO_IOPORT_MAP | |
2f618d5e | 318 | |
e0c25d95 DC |
319 | config ARCH_MMAP_RND_BITS_MIN |
320 | default 8 | |
321 | ||
322 | config ARCH_MMAP_RND_BITS_MAX | |
323 | default 14 if PAGE_OFFSET=0x40000000 | |
324 | default 15 if PAGE_OFFSET=0x80000000 | |
325 | default 16 | |
326 | ||
387798b3 | 327 | config ARCH_MULTIPLATFORM |
84fc8636 AB |
328 | bool "Require kernel to be portable to multiple machines" if EXPERT |
329 | depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) | |
330 | default y | |
1da177e4 | 331 | help |
84fc8636 AB |
332 | In general, all Arm machines can be supported in a single |
333 | kernel image, covering either Armv4/v5 or Armv6/v7. | |
1da177e4 | 334 | |
84fc8636 AB |
335 | However, some configuration options require hardcoding machine |
336 | specific physical addresses or enable errata workarounds that may | |
337 | break other machines. | |
1da177e4 | 338 | |
84fc8636 AB |
339 | Selecting N here allows using those options, including |
340 | DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. | |
1da177e4 | 341 | |
6fd09c9a AB |
342 | menu "Platform selection" |
343 | depends on MMU | |
387798b3 RH |
344 | |
345 | comment "CPU Core family selection" | |
346 | ||
f8afae40 | 347 | config ARCH_MULTI_V4 |
6fd09c9a | 348 | bool "ARMv4 based platforms (FA526, StrongARM)" |
f8afae40 | 349 | depends on !ARCH_MULTI_V6_V7 |
5eb6e280 NC |
350 | # https://github.com/llvm/llvm-project/issues/50764 |
351 | depends on !LD_IS_LLD || LLD_VERSION >= 160000 | |
f8afae40 | 352 | select ARCH_MULTI_V4_V5 |
6fd09c9a | 353 | select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) |
f8afae40 | 354 | |
387798b3 RH |
355 | config ARCH_MULTI_V4T |
356 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 357 | depends on !ARCH_MULTI_V6_V7 |
5eb6e280 NC |
358 | # https://github.com/llvm/llvm-project/issues/50764 |
359 | depends on !LD_IS_LLD || LLD_VERSION >= 160000 | |
b1b3f49c | 360 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
361 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
362 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
363 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
364 | |
365 | config ARCH_MULTI_V5 | |
366 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 367 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 368 | select ARCH_MULTI_V4_V5 |
12567bbd | 369 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
24e860fb AB |
370 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
371 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
372 | |
373 | config ARCH_MULTI_V4_V5 | |
374 | bool | |
375 | ||
376 | config ARCH_MULTI_V6 | |
8dda05cc | 377 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 378 | select ARCH_MULTI_V6_V7 |
42f4754a | 379 | select CPU_V6K |
387798b3 RH |
380 | |
381 | config ARCH_MULTI_V7 | |
8dda05cc | 382 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
383 | default y |
384 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 385 | select CPU_V7 |
90bc8ac7 | 386 | select HAVE_SMP |
387798b3 RH |
387 | |
388 | config ARCH_MULTI_V6_V7 | |
389 | bool | |
9352b05b | 390 | select MIGHT_HAVE_CACHE_L2X0 |
387798b3 RH |
391 | |
392 | config ARCH_MULTI_CPU_AUTO | |
393 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
394 | select ARCH_MULTI_V5 | |
395 | ||
396 | endmenu | |
397 | ||
05e2a3de | 398 | config ARCH_VIRT |
e3246542 MY |
399 | bool "Dummy Virtual Machine" |
400 | depends on ARCH_MULTI_V7 | |
4b8b5f25 | 401 | select ARM_AMBA |
05e2a3de | 402 | select ARM_GIC |
3ee80364 | 403 | select ARM_GIC_V2M if PCI |
0b28f1db | 404 | select ARM_GIC_V3 |
bb29cecb | 405 | select ARM_GIC_V3_ITS if PCI |
05e2a3de | 406 | select ARM_PSCI |
4b8b5f25 | 407 | select HAVE_ARM_ARCH_TIMER |
05e2a3de | 408 | |
2cf1c348 JC |
409 | config ARCH_AIROHA |
410 | bool "Airoha SoC Support" | |
411 | depends on ARCH_MULTI_V7 | |
412 | select ARM_AMBA | |
413 | select ARM_GIC | |
414 | select ARM_GIC_V3 | |
415 | select ARM_PSCI | |
416 | select HAVE_ARM_ARCH_TIMER | |
2cf1c348 JC |
417 | help |
418 | Support for Airoha EN7523 SoCs | |
419 | ||
ccf50e23 RK |
420 | # |
421 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
422 | # Kconfigs may be included either alphabetically (according to the | |
423 | # plat- suffix) or along side the corresponding mach-* source. | |
424 | # | |
6bb8536c AF |
425 | source "arch/arm/mach-actions/Kconfig" |
426 | ||
445d9b30 TZ |
427 | source "arch/arm/mach-alpine/Kconfig" |
428 | ||
590b460c LP |
429 | source "arch/arm/mach-artpec/Kconfig" |
430 | ||
d9bfc86d OR |
431 | source "arch/arm/mach-asm9260/Kconfig" |
432 | ||
a66c51f9 AB |
433 | source "arch/arm/mach-aspeed/Kconfig" |
434 | ||
95b8f20f RK |
435 | source "arch/arm/mach-at91/Kconfig" |
436 | ||
1d22924e AB |
437 | source "arch/arm/mach-axxia/Kconfig" |
438 | ||
8ac49e04 CD |
439 | source "arch/arm/mach-bcm/Kconfig" |
440 | ||
1c37fa10 SH |
441 | source "arch/arm/mach-berlin/Kconfig" |
442 | ||
1da177e4 LT |
443 | source "arch/arm/mach-clps711x/Kconfig" |
444 | ||
95b8f20f RK |
445 | source "arch/arm/mach-davinci/Kconfig" |
446 | ||
df8d742e BS |
447 | source "arch/arm/mach-digicolor/Kconfig" |
448 | ||
95b8f20f RK |
449 | source "arch/arm/mach-dove/Kconfig" |
450 | ||
e7736d47 LB |
451 | source "arch/arm/mach-ep93xx/Kconfig" |
452 | ||
a66c51f9 | 453 | source "arch/arm/mach-exynos/Kconfig" |
a66c51f9 | 454 | |
1da177e4 LT |
455 | source "arch/arm/mach-footbridge/Kconfig" |
456 | ||
59d3a193 PZ |
457 | source "arch/arm/mach-gemini/Kconfig" |
458 | ||
387798b3 RH |
459 | source "arch/arm/mach-highbank/Kconfig" |
460 | ||
389ee0c2 HZ |
461 | source "arch/arm/mach-hisi/Kconfig" |
462 | ||
11d89440 NH |
463 | source "arch/arm/mach-hpe/Kconfig" |
464 | ||
a66c51f9 AB |
465 | source "arch/arm/mach-imx/Kconfig" |
466 | ||
1da177e4 LT |
467 | source "arch/arm/mach-ixp4xx/Kconfig" |
468 | ||
828989ad SS |
469 | source "arch/arm/mach-keystone/Kconfig" |
470 | ||
75bf1bd7 | 471 | source "arch/arm/mach-lpc32xx/Kconfig" |
95b8f20f | 472 | |
a66c51f9 AB |
473 | source "arch/arm/mach-mediatek/Kconfig" |
474 | ||
3b8f5030 CC |
475 | source "arch/arm/mach-meson/Kconfig" |
476 | ||
9fb29c73 ST |
477 | source "arch/arm/mach-milbeaut/Kconfig" |
478 | ||
a66c51f9 | 479 | source "arch/arm/mach-mmp/Kconfig" |
17723fd3 | 480 | |
a66c51f9 | 481 | source "arch/arm/mach-moxart/Kconfig" |
8c2ed9bc | 482 | |
312b62b6 DP |
483 | source "arch/arm/mach-mstar/Kconfig" |
484 | ||
794d15b2 SS |
485 | source "arch/arm/mach-mv78xx0/Kconfig" |
486 | ||
a66c51f9 | 487 | source "arch/arm/mach-mvebu/Kconfig" |
f682a218 | 488 | |
1d3f33d5 SG |
489 | source "arch/arm/mach-mxs/Kconfig" |
490 | ||
95b8f20f | 491 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 492 | |
7bffa14c BH |
493 | source "arch/arm/mach-npcm/Kconfig" |
494 | ||
9851ca57 DT |
495 | source "arch/arm/mach-nspire/Kconfig" |
496 | ||
d48af15e | 497 | source "arch/arm/mach-omap1/Kconfig" |
1da177e4 | 498 | |
1dbae815 TL |
499 | source "arch/arm/mach-omap2/Kconfig" |
500 | ||
9dd0b194 | 501 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 502 | |
95b8f20f | 503 | source "arch/arm/mach-pxa/Kconfig" |
585cf175 | 504 | |
8fc1b0f8 KG |
505 | source "arch/arm/mach-qcom/Kconfig" |
506 | ||
78e3dbc1 AF |
507 | source "arch/arm/mach-rda/Kconfig" |
508 | ||
86aeee4d AF |
509 | source "arch/arm/mach-realtek/Kconfig" |
510 | ||
6fd09c9a AB |
511 | source "arch/arm/mach-rpc/Kconfig" |
512 | ||
d63dc051 HS |
513 | source "arch/arm/mach-rockchip/Kconfig" |
514 | ||
71b9114d | 515 | source "arch/arm/mach-s3c/Kconfig" |
a66c51f9 AB |
516 | |
517 | source "arch/arm/mach-s5pv210/Kconfig" | |
518 | ||
95b8f20f | 519 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 520 | |
a66c51f9 AB |
521 | source "arch/arm/mach-shmobile/Kconfig" |
522 | ||
387798b3 RH |
523 | source "arch/arm/mach-socfpga/Kconfig" |
524 | ||
a7ed099f | 525 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 526 | |
65ebcc11 SK |
527 | source "arch/arm/mach-sti/Kconfig" |
528 | ||
bcb84fb4 AT |
529 | source "arch/arm/mach-stm32/Kconfig" |
530 | ||
0aa94eea QJ |
531 | source "arch/arm/mach-sunplus/Kconfig" |
532 | ||
3b52634f MR |
533 | source "arch/arm/mach-sunxi/Kconfig" |
534 | ||
c5f80065 EG |
535 | source "arch/arm/mach-tegra/Kconfig" |
536 | ||
ba56a987 MY |
537 | source "arch/arm/mach-uniphier/Kconfig" |
538 | ||
95b8f20f | 539 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
540 | |
541 | source "arch/arm/mach-versatile/Kconfig" | |
542 | ||
6f35f9a9 TP |
543 | source "arch/arm/mach-vt8500/Kconfig" |
544 | ||
9a45eb69 JC |
545 | source "arch/arm/mach-zynq/Kconfig" |
546 | ||
499f1640 | 547 | # ARMv7-M architecture |
499f1640 SA |
548 | config ARCH_LPC18XX |
549 | bool "NXP LPC18xx/LPC43xx" | |
550 | depends on ARM_SINGLE_ARMV7M | |
551 | select ARCH_HAS_RESET_CONTROLLER | |
552 | select ARM_AMBA | |
553 | select CLKSRC_LPC32XX | |
554 | select PINCTRL | |
555 | help | |
556 | Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 | |
557 | high performance microcontrollers. | |
558 | ||
1847119d | 559 | config ARCH_MPS2 |
17bd274e | 560 | bool "ARM MPS2 platform" |
1847119d VM |
561 | depends on ARM_SINGLE_ARMV7M |
562 | select ARM_AMBA | |
563 | select CLKSRC_MPS2 | |
564 | help | |
565 | Support for Cortex-M Prototyping System (or V2M-MPS2) which comes | |
566 | with a range of available cores like Cortex-M3/M4/M7. | |
567 | ||
568 | Please, note that depends which Application Note is used memory map | |
569 | for the platform may vary, so adjustment of RAM base might be needed. | |
570 | ||
1da177e4 LT |
571 | # Definitions to make life easier |
572 | config ARCH_ACORN | |
573 | bool | |
574 | ||
69b02f6a LB |
575 | config PLAT_ORION |
576 | bool | |
bfe45e0b | 577 | select CLKSRC_MMIO |
dc7ad3b3 | 578 | select GENERIC_IRQ_CHIP |
278b45b0 | 579 | select IRQ_DOMAIN |
69b02f6a | 580 | |
abcda1dc TP |
581 | config PLAT_ORION_LEGACY |
582 | bool | |
583 | select PLAT_ORION | |
584 | ||
f4b8b319 RK |
585 | config PLAT_VERSATILE |
586 | bool | |
587 | ||
8636a1f9 | 588 | source "arch/arm/mm/Kconfig" |
1da177e4 | 589 | |
afe4b25e | 590 | config IWMMXT |
d93003e8 SH |
591 | bool "Enable iWMMXt support" |
592 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B | |
593 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B | |
afe4b25e LB |
594 | help |
595 | Enable support for iWMMXt context switching at run time if | |
596 | running on a CPU that supports it. | |
597 | ||
3b93e7b0 HC |
598 | if !MMU |
599 | source "arch/arm/Kconfig-nommu" | |
600 | endif | |
601 | ||
3e0a07f8 GC |
602 | config PJ4B_ERRATA_4742 |
603 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
604 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
605 | default y | |
606 | help | |
607 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
608 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
609 | the retiring WFI/WFE instructions and the newly issued subsequent | |
610 | instructions. This sensitivity can result in a CPU hang scenario. | |
611 | Workaround: | |
612 | The software must insert either a Data Synchronization Barrier (DSB) | |
613 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
614 | instruction | |
615 | ||
f0c4b8d6 WD |
616 | config ARM_ERRATA_326103 |
617 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
618 | depends on CPU_V6 | |
619 | help | |
620 | Executing a SWP instruction to read-only memory does not set bit 11 | |
621 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
622 | treat the access as a read, preventing a COW from occurring and | |
623 | causing the faulting task to livelock. | |
624 | ||
9cba3ccc CM |
625 | config ARM_ERRATA_411920 |
626 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 627 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
628 | help |
629 | Invalidation of the Instruction Cache operation can | |
630 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
631 | It does not affect the MPCore. This option enables the ARM Ltd. | |
632 | recommended workaround. | |
633 | ||
7ce236fc CM |
634 | config ARM_ERRATA_430973 |
635 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
636 | depends on CPU_V7 | |
637 | help | |
638 | This option enables the workaround for the 430973 Cortex-A8 | |
79403cda | 639 | r1p* erratum. If a code sequence containing an ARM/Thumb |
7ce236fc CM |
640 | interworking branch is replaced with another code sequence at the |
641 | same virtual address, whether due to self-modifying code or virtual | |
642 | to physical address re-mapping, Cortex-A8 does not recover from the | |
643 | stale interworking branch prediction. This results in Cortex-A8 | |
644 | executing the new code sequence in the incorrect ARM or Thumb state. | |
645 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
646 | and also flushes the branch target cache at every context switch. | |
647 | Note that setting specific bits in the ACTLR register may not be | |
648 | available in non-secure mode. | |
649 | ||
855c551f CM |
650 | config ARM_ERRATA_458693 |
651 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
652 | depends on CPU_V7 | |
62e4d357 | 653 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
654 | help |
655 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
656 | erratum. For very specific sequences of memory operations, it is | |
657 | possible for a hazard condition intended for a cache line to instead | |
658 | be incorrectly associated with a different cache line. This false | |
659 | hazard might then cause a processor deadlock. The workaround enables | |
660 | the L1 caching of the NEON accesses and disables the PLD instruction | |
661 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
368ccecd SR |
662 | register may not be available in non-secure mode and thus is not |
663 | available on a multiplatform kernel. This should be applied by the | |
664 | bootloader instead. | |
855c551f | 665 | |
0516e464 CM |
666 | config ARM_ERRATA_460075 |
667 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
668 | depends on CPU_V7 | |
62e4d357 | 669 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
670 | help |
671 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
672 | erratum. Any asynchronous access to the L2 cache may encounter a | |
673 | situation in which recent store transactions to the L2 cache are lost | |
674 | and overwritten with stale memory contents from external memory. The | |
675 | workaround disables the write-allocate mode for the L2 cache via the | |
676 | ACTLR register. Note that setting specific bits in the ACTLR register | |
368ccecd SR |
677 | may not be available in non-secure mode and thus is not available on |
678 | a multiplatform kernel. This should be applied by the bootloader | |
679 | instead. | |
0516e464 | 680 | |
9f05027c WD |
681 | config ARM_ERRATA_742230 |
682 | bool "ARM errata: DMB operation may be faulty" | |
683 | depends on CPU_V7 && SMP | |
62e4d357 | 684 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
685 | help |
686 | This option enables the workaround for the 742230 Cortex-A9 | |
687 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
688 | between two write operations may not ensure the correct visibility | |
689 | ordering of the two writes. This workaround sets a specific bit in | |
690 | the diagnostic register of the Cortex-A9 which causes the DMB | |
691 | instruction to behave as a DSB, ensuring the correct behaviour of | |
368ccecd SR |
692 | the two writes. Note that setting specific bits in the diagnostics |
693 | register may not be available in non-secure mode and thus is not | |
694 | available on a multiplatform kernel. This should be applied by the | |
695 | bootloader instead. | |
9f05027c | 696 | |
a672e99b WD |
697 | config ARM_ERRATA_742231 |
698 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
699 | depends on CPU_V7 && SMP | |
62e4d357 | 700 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
701 | help |
702 | This option enables the workaround for the 742231 Cortex-A9 | |
703 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
704 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
705 | accessing some data located in the same cache line, may get corrupted | |
706 | data due to bad handling of the address hazard when the line gets | |
707 | replaced from one of the CPUs at the same time as another CPU is | |
708 | accessing it. This workaround sets specific bits in the diagnostic | |
709 | register of the Cortex-A9 which reduces the linefill issuing | |
368ccecd SR |
710 | capabilities of the processor. Note that setting specific bits in the |
711 | diagnostics register may not be available in non-secure mode and thus | |
712 | is not available on a multiplatform kernel. This should be applied by | |
713 | the bootloader instead. | |
a672e99b | 714 | |
69155794 JM |
715 | config ARM_ERRATA_643719 |
716 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
717 | depends on CPU_V7 && SMP | |
e5a5de44 | 718 | default y |
69155794 JM |
719 | help |
720 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
721 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
722 | register returns zero when it should return one. The workaround | |
723 | corrects this value, ensuring cache maintenance operations which use | |
724 | it behave as intended and avoiding data corruption. | |
725 | ||
cdf357f1 WD |
726 | config ARM_ERRATA_720789 |
727 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 728 | depends on CPU_V7 |
cdf357f1 WD |
729 | help |
730 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
731 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
732 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
733 | As a consequence of this erratum, some TLB entries which should be | |
734 | invalidated are not, resulting in an incoherency in the system page | |
735 | tables. The workaround changes the TLB flushing routines to invalidate | |
736 | entries regardless of the ASID. | |
475d92fc WD |
737 | |
738 | config ARM_ERRATA_743622 | |
739 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
740 | depends on CPU_V7 | |
62e4d357 | 741 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
742 | help |
743 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 744 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
745 | optimisation in the Cortex-A9 Store Buffer may lead to data |
746 | corruption. This workaround sets a specific bit in the diagnostic | |
747 | register of the Cortex-A9 which disables the Store Buffer | |
748 | optimisation, preventing the defect from occurring. This has no | |
749 | visible impact on the overall performance or power consumption of the | |
368ccecd SR |
750 | processor. Note that setting specific bits in the diagnostics register |
751 | may not be available in non-secure mode and thus is not available on a | |
752 | multiplatform kernel. This should be applied by the bootloader instead. | |
475d92fc | 753 | |
9a27c27c WD |
754 | config ARM_ERRATA_751472 |
755 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 756 | depends on CPU_V7 |
62e4d357 | 757 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
758 | help |
759 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
760 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
761 | completion of a following broadcasted operation if the second | |
762 | operation is received by a CPU before the ICIALLUIS has completed, | |
763 | potentially leading to corrupted entries in the cache or TLB. | |
368ccecd SR |
764 | Note that setting specific bits in the diagnostics register may |
765 | not be available in non-secure mode and thus is not available on | |
766 | a multiplatform kernel. This should be applied by the bootloader | |
767 | instead. | |
9a27c27c | 768 | |
fcbdc5fe WD |
769 | config ARM_ERRATA_754322 |
770 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
771 | depends on CPU_V7 | |
772 | help | |
773 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
774 | r3p*) erratum. A speculative memory access may cause a page table walk | |
775 | which starts prior to an ASID switch but completes afterwards. This | |
776 | can populate the micro-TLB with a stale entry which may be hit with | |
777 | the new ASID. This workaround places two dsb instructions in the mm | |
778 | switching code so that no page table walks can cross the ASID switch. | |
779 | ||
5dab26af WD |
780 | config ARM_ERRATA_754327 |
781 | bool "ARM errata: no automatic Store Buffer drain" | |
782 | depends on CPU_V7 && SMP | |
783 | help | |
784 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
785 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
786 | mechanism and therefore a livelock may occur if an external agent | |
787 | continuously polls a memory location waiting to observe an update. | |
788 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
789 | written polling loops from denying visibility of updates to memory. | |
790 | ||
145e10e1 CM |
791 | config ARM_ERRATA_364296 |
792 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 793 | depends on CPU_V6 |
145e10e1 CM |
794 | help |
795 | This options enables the workaround for the 364296 ARM1136 | |
796 | r0p2 erratum (possible cache data corruption with | |
797 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
798 | the auxiliary control register and the FI bit in the control | |
799 | register, thus disabling hit-under-miss without putting the | |
800 | processor into full low interrupt latency mode. ARM11MPCore | |
801 | is not affected. | |
802 | ||
f630c1bd WD |
803 | config ARM_ERRATA_764369 |
804 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
805 | depends on CPU_V7 && SMP | |
806 | help | |
807 | This option enables the workaround for erratum 764369 | |
808 | affecting Cortex-A9 MPCore with two or more processors (all | |
809 | current revisions). Under certain timing circumstances, a data | |
810 | cache line maintenance operation by MVA targeting an Inner | |
811 | Shareable memory region may fail to proceed up to either the | |
812 | Point of Coherency or to the Point of Unification of the | |
813 | system. This workaround adds a DSB instruction before the | |
814 | relevant cache maintenance functions and sets a specific bit | |
815 | in the diagnostic control register of the SCU. | |
816 | ||
8294fec1 NH |
817 | config ARM_ERRATA_764319 |
818 | bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" | |
819 | depends on CPU_V7 | |
820 | help | |
821 | This option enables the workaround for the 764319 Cortex A-9 erratum. | |
822 | CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an | |
823 | unexpected Undefined Instruction exception when the DBGSWENABLE | |
824 | external pin is set to 0, even when the CP14 accesses are performed | |
825 | from a privileged mode. This work around catches the exception in a | |
826 | way the kernel does not stop execution. | |
827 | ||
7253b85c SH |
828 | config ARM_ERRATA_775420 |
829 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
830 | depends on CPU_V7 | |
831 | help | |
832 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
cb73737e | 833 | r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance |
7253b85c SH |
834 | operation aborts with MMU exception, it might cause the processor |
835 | to deadlock. This workaround puts DSB before executing ISB if | |
836 | an abort may occur on cache maintenance. | |
837 | ||
93dc6887 CM |
838 | config ARM_ERRATA_798181 |
839 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
840 | depends on CPU_V7 && SMP | |
841 | help | |
842 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
843 | adequately shooting down all use of the old entries. This | |
844 | option enables the Linux kernel workaround for this erratum | |
845 | which sends an IPI to the CPUs that are running the same ASID | |
846 | as the one being invalidated. | |
847 | ||
84b6504f WD |
848 | config ARM_ERRATA_773022 |
849 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
850 | depends on CPU_V7 | |
851 | help | |
852 | This option enables the workaround for the 773022 Cortex-A15 | |
853 | (up to r0p4) erratum. In certain rare sequences of code, the | |
854 | loop buffer may deliver incorrect instructions. This | |
855 | workaround disables the loop buffer to avoid the erratum. | |
856 | ||
62c0f4a5 DA |
857 | config ARM_ERRATA_818325_852422 |
858 | bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" | |
859 | depends on CPU_V7 | |
860 | help | |
861 | This option enables the workaround for: | |
862 | - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM | |
863 | instruction might deadlock. Fixed in r0p1. | |
864 | - Cortex-A12 852422: Execution of a sequence of instructions might | |
865 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
866 | any Cortex-A12 cores yet. | |
867 | This workaround for all both errata involves setting bit[12] of the | |
868 | Feature Register. This bit disables an optimisation applied to a | |
869 | sequence of 2 instructions that use opposing condition codes. | |
870 | ||
416bcf21 DA |
871 | config ARM_ERRATA_821420 |
872 | bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" | |
873 | depends on CPU_V7 | |
874 | help | |
875 | This option enables the workaround for the 821420 Cortex-A12 | |
876 | (all revs) erratum. In very rare timing conditions, a sequence | |
877 | of VMOV to Core registers instructions, for which the second | |
878 | one is in the shadow of a branch or abort, can lead to a | |
879 | deadlock when the VMOV instructions are issued out-of-order. | |
880 | ||
9f6f9354 DA |
881 | config ARM_ERRATA_825619 |
882 | bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" | |
883 | depends on CPU_V7 | |
884 | help | |
885 | This option enables the workaround for the 825619 Cortex-A12 | |
886 | (all revs) erratum. Within rare timing constraints, executing a | |
887 | DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable | |
888 | and Device/Strongly-Ordered loads and stores might cause deadlock | |
889 | ||
304009a1 DA |
890 | config ARM_ERRATA_857271 |
891 | bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" | |
892 | depends on CPU_V7 | |
893 | help | |
894 | This option enables the workaround for the 857271 Cortex-A12 | |
895 | (all revs) erratum. Under very rare timing conditions, the CPU might | |
896 | hang. The workaround is expected to have a < 1% performance impact. | |
897 | ||
9f6f9354 DA |
898 | config ARM_ERRATA_852421 |
899 | bool "ARM errata: A17: DMB ST might fail to create order between stores" | |
900 | depends on CPU_V7 | |
901 | help | |
902 | This option enables the workaround for the 852421 Cortex-A17 | |
903 | (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, | |
904 | execution of a DMB ST instruction might fail to properly order | |
905 | stores from GroupA and stores from GroupB. | |
906 | ||
62c0f4a5 DA |
907 | config ARM_ERRATA_852423 |
908 | bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" | |
909 | depends on CPU_V7 | |
910 | help | |
911 | This option enables the workaround for: | |
912 | - Cortex-A17 852423: Execution of a sequence of instructions might | |
913 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
914 | any Cortex-A17 cores yet. | |
915 | This is identical to Cortex-A12 erratum 852422. It is a separate | |
916 | config option from the A12 erratum due to the way errata are checked | |
917 | for and handled. | |
918 | ||
304009a1 DA |
919 | config ARM_ERRATA_857272 |
920 | bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" | |
921 | depends on CPU_V7 | |
922 | help | |
923 | This option enables the workaround for the 857272 Cortex-A17 erratum. | |
924 | This erratum is not known to be fixed in any A17 revision. | |
925 | This is identical to Cortex-A12 erratum 857271. It is a separate | |
926 | config option from the A12 erratum due to the way errata are checked | |
927 | for and handled. | |
928 | ||
1da177e4 LT |
929 | endmenu |
930 | ||
931 | source "arch/arm/common/Kconfig" | |
932 | ||
1da177e4 LT |
933 | menu "Bus support" |
934 | ||
1da177e4 LT |
935 | config ISA |
936 | bool | |
1da177e4 LT |
937 | help |
938 | Find out whether you have ISA slots on your motherboard. ISA is the | |
939 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
940 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
941 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
942 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
943 | ||
065909b9 | 944 | # Select ISA DMA interface |
5cae841b AV |
945 | config ISA_DMA_API |
946 | bool | |
5cae841b | 947 | |
779eb41c BG |
948 | config ARM_ERRATA_814220 |
949 | bool "ARM errata: Cache maintenance by set/way operations can execute out of order" | |
950 | depends on CPU_V7 | |
951 | help | |
952 | The v7 ARM states that all cache and branch predictor maintenance | |
953 | operations that do not specify an address execute, relative to | |
954 | each other, in program order. | |
955 | However, because of this erratum, an L2 set/way cache maintenance | |
956 | operation can overtake an L1 set/way cache maintenance operation. | |
957 | This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, | |
958 | r0p4, r0p5. | |
959 | ||
1da177e4 LT |
960 | endmenu |
961 | ||
962 | menu "Kernel Features" | |
963 | ||
3b55658a DM |
964 | config HAVE_SMP |
965 | bool | |
966 | help | |
967 | This option should be selected by machines which have an SMP- | |
968 | capable CPU. | |
969 | ||
970 | The only effect of this option is to make the SMP-related | |
971 | options available to the user for configuration. | |
972 | ||
1da177e4 | 973 | config SMP |
bb2d8130 | 974 | bool "Symmetric Multi-Processing" |
fbb4ddac | 975 | depends on CPU_V6K || CPU_V7 |
3b55658a | 976 | depends on HAVE_SMP |
801bb21c | 977 | depends on MMU || ARM_MPU |
0361748f | 978 | select IRQ_WORK |
1da177e4 LT |
979 | help |
980 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
981 | a system with only one CPU, say N. If you have a system with more |
982 | than one CPU, say Y. | |
1da177e4 | 983 | |
4a474157 | 984 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 985 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
986 | you say Y here, the kernel will run on many, but not all, |
987 | uniprocessor machines. On a uniprocessor machine, the kernel | |
988 | will run faster if you say N here. | |
1da177e4 | 989 | |
ff61f079 | 990 | See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, |
4f4cfa6c | 991 | <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at |
50a23e6e | 992 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
993 | |
994 | If you don't know what to do here, say N. | |
995 | ||
f00ec48f | 996 | config SMP_ON_UP |
5744ff43 | 997 | bool "Allow booting SMP kernel on uniprocessor systems" |
5408445b | 998 | depends on SMP && MMU |
f00ec48f RK |
999 | default y |
1000 | help | |
1001 | SMP kernels contain instructions which fail on non-SMP processors. | |
1002 | Enabling this option allows the kernel to modify itself to make | |
1003 | these instructions safe. Disabling it allows about 1K of space | |
1004 | savings. | |
1005 | ||
1006 | If you don't know what to do here, say Y. | |
1007 | ||
50596b75 AB |
1008 | |
1009 | config CURRENT_POINTER_IN_TPIDRURO | |
1010 | def_bool y | |
b87cf911 | 1011 | depends on CPU_32v6K && !CPU_V6 |
50596b75 | 1012 | |
d4664b6c AB |
1013 | config IRQSTACKS |
1014 | def_bool y | |
9974f857 AB |
1015 | select HAVE_IRQ_EXIT_ON_IRQ_STACK |
1016 | select HAVE_SOFTIRQ_ON_OWN_STACK | |
50596b75 | 1017 | |
c9018aab VG |
1018 | config ARM_CPU_TOPOLOGY |
1019 | bool "Support cpu topology definition" | |
1020 | depends on SMP && CPU_V7 | |
1021 | default y | |
1022 | help | |
1023 | Support ARM cpu topology definition. The MPIDR register defines | |
1024 | affinity between processors which is then used to describe the cpu | |
1025 | topology of an ARM System. | |
1026 | ||
1027 | config SCHED_MC | |
1028 | bool "Multi-core scheduler support" | |
1029 | depends on ARM_CPU_TOPOLOGY | |
1030 | help | |
1031 | Multi-core scheduler support improves the CPU scheduler's decision | |
1032 | making when dealing with multi-core CPU chips at a cost of slightly | |
1033 | increased overhead in some places. If unsure say N here. | |
1034 | ||
1035 | config SCHED_SMT | |
1036 | bool "SMT scheduler support" | |
1037 | depends on ARM_CPU_TOPOLOGY | |
1038 | help | |
1039 | Improves the CPU scheduler's decision making when dealing with | |
1040 | MultiThreading at a cost of slightly increased overhead in some | |
1041 | places. If unsure say N here. | |
1042 | ||
a8cbcd92 RK |
1043 | config HAVE_ARM_SCU |
1044 | bool | |
a8cbcd92 | 1045 | help |
8f433ec4 | 1046 | This option enables support for the ARM snoop control unit |
a8cbcd92 | 1047 | |
8a4da6e3 | 1048 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1049 | bool "Architected timer support" |
1050 | depends on CPU_V7 | |
8a4da6e3 | 1051 | select ARM_ARCH_TIMER |
022c03a2 MZ |
1052 | help |
1053 | This option enables support for the ARM architected timer | |
1054 | ||
f32f4ce2 RK |
1055 | config HAVE_ARM_TWD |
1056 | bool | |
f32f4ce2 RK |
1057 | help |
1058 | This options enables support for the ARM timer and watchdog unit | |
1059 | ||
e8db288e NP |
1060 | config MCPM |
1061 | bool "Multi-Cluster Power Management" | |
1062 | depends on CPU_V7 && SMP | |
1063 | help | |
1064 | This option provides the common power management infrastructure | |
1065 | for (multi-)cluster based systems, such as big.LITTLE based | |
1066 | systems. | |
1067 | ||
ebf4a5c5 HZ |
1068 | config MCPM_QUAD_CLUSTER |
1069 | bool | |
1070 | depends on MCPM | |
1071 | help | |
1072 | To avoid wasting resources unnecessarily, MCPM only supports up | |
1073 | to 2 clusters by default. | |
1074 | Platforms with 3 or 4 clusters that use MCPM must select this | |
1075 | option to allow the additional clusters to be managed. | |
1076 | ||
1c33be57 NP |
1077 | config BIG_LITTLE |
1078 | bool "big.LITTLE support (Experimental)" | |
1079 | depends on CPU_V7 && SMP | |
1080 | select MCPM | |
1081 | help | |
1082 | This option enables support selections for the big.LITTLE | |
1083 | system architecture. | |
1084 | ||
1085 | config BL_SWITCHER | |
1086 | bool "big.LITTLE switcher support" | |
6c044fec | 1087 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC |
51aaf81f | 1088 | select CPU_PM |
1c33be57 NP |
1089 | help |
1090 | The big.LITTLE "switcher" provides the core functionality to | |
1091 | transparently handle transition between a cluster of A15's | |
1092 | and a cluster of A7's in a big.LITTLE system. | |
1093 | ||
b22537c6 NP |
1094 | config BL_SWITCHER_DUMMY_IF |
1095 | tristate "Simple big.LITTLE switcher user interface" | |
1096 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1097 | help | |
1098 | This is a simple and dummy char dev interface to control | |
1099 | the big.LITTLE switcher core code. It is meant for | |
1100 | debugging purposes only. | |
1101 | ||
8d5796d2 LB |
1102 | choice |
1103 | prompt "Memory split" | |
006fa259 | 1104 | depends on MMU |
8d5796d2 LB |
1105 | default VMSPLIT_3G |
1106 | help | |
1107 | Select the desired split between kernel and user memory. | |
1108 | ||
1109 | If you are not absolutely sure what you are doing, leave this | |
1110 | option alone! | |
1111 | ||
1112 | config VMSPLIT_3G | |
1113 | bool "3G/1G user/kernel split" | |
63ce446c | 1114 | config VMSPLIT_3G_OPT |
bbeedfda | 1115 | depends on !ARM_LPAE |
63ce446c | 1116 | bool "3G/1G user/kernel split (for full 1G low memory)" |
8d5796d2 LB |
1117 | config VMSPLIT_2G |
1118 | bool "2G/2G user/kernel split" | |
1119 | config VMSPLIT_1G | |
1120 | bool "1G/3G user/kernel split" | |
1121 | endchoice | |
1122 | ||
1123 | config PAGE_OFFSET | |
1124 | hex | |
006fa259 | 1125 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1126 | default 0x40000000 if VMSPLIT_1G |
1127 | default 0x80000000 if VMSPLIT_2G | |
63ce446c | 1128 | default 0xB0000000 if VMSPLIT_3G_OPT |
8d5796d2 LB |
1129 | default 0xC0000000 |
1130 | ||
c12366ba LW |
1131 | config KASAN_SHADOW_OFFSET |
1132 | hex | |
1133 | depends on KASAN | |
1134 | default 0x1f000000 if PAGE_OFFSET=0x40000000 | |
1135 | default 0x5f000000 if PAGE_OFFSET=0x80000000 | |
1136 | default 0x9f000000 if PAGE_OFFSET=0xC0000000 | |
1137 | default 0x8f000000 if PAGE_OFFSET=0xB0000000 | |
1138 | default 0xffffffff | |
1139 | ||
1da177e4 LT |
1140 | config NR_CPUS |
1141 | int "Maximum number of CPUs (2-32)" | |
d624833f AB |
1142 | range 2 16 if DEBUG_KMAP_LOCAL |
1143 | range 2 32 if !DEBUG_KMAP_LOCAL | |
1da177e4 LT |
1144 | depends on SMP |
1145 | default "4" | |
d624833f AB |
1146 | help |
1147 | The maximum number of CPUs that the kernel can support. | |
1148 | Up to 32 CPUs can be supported, or up to 16 if kmap_local() | |
1149 | debugging is enabled, which uses half of the per-CPU fixmap | |
1150 | slots as guard regions. | |
1da177e4 | 1151 | |
a054a811 | 1152 | config HOTPLUG_CPU |
00b7dede | 1153 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1154 | depends on SMP |
1b5ba350 | 1155 | select GENERIC_IRQ_MIGRATION |
a054a811 RK |
1156 | help |
1157 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1158 | can be controlled through /sys/devices/system/cpu. | |
1159 | ||
2bdd424f WD |
1160 | config ARM_PSCI |
1161 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
e679660d | 1162 | depends on HAVE_ARM_SMCCC |
be120397 | 1163 | select ARM_PSCI_FW |
2bdd424f WD |
1164 | help |
1165 | Say Y here if you want Linux to communicate with system firmware | |
1166 | implementing the PSCI specification for CPU-centric power | |
1167 | management operations described in ARM document number ARM DEN | |
1168 | 0022A ("Power State Coordination Interface System Software on | |
1169 | ARM processors"). | |
1170 | ||
c9218b16 | 1171 | config HZ_FIXED |
f8065813 | 1172 | int |
1164f672 | 1173 | default 128 if SOC_AT91RM9200 |
47d84682 | 1174 | default 0 |
c9218b16 RK |
1175 | |
1176 | choice | |
47d84682 | 1177 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1178 | prompt "Timer frequency" |
1179 | ||
1180 | config HZ_100 | |
1181 | bool "100 Hz" | |
1182 | ||
1183 | config HZ_200 | |
1184 | bool "200 Hz" | |
1185 | ||
1186 | config HZ_250 | |
1187 | bool "250 Hz" | |
1188 | ||
1189 | config HZ_300 | |
1190 | bool "300 Hz" | |
1191 | ||
1192 | config HZ_500 | |
1193 | bool "500 Hz" | |
1194 | ||
1195 | config HZ_1000 | |
1196 | bool "1000 Hz" | |
1197 | ||
1198 | endchoice | |
1199 | ||
1200 | config HZ | |
1201 | int | |
47d84682 | 1202 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1203 | default 100 if HZ_100 |
1204 | default 200 if HZ_200 | |
1205 | default 250 if HZ_250 | |
1206 | default 300 if HZ_300 | |
1207 | default 500 if HZ_500 | |
1208 | default 1000 | |
1209 | ||
1210 | config SCHED_HRTICK | |
1211 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1212 | |
16c79651 | 1213 | config THUMB2_KERNEL |
bc7dea00 | 1214 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1215 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1216 | default y if CPU_THUMBONLY |
89bace65 | 1217 | select ARM_UNWIND |
16c79651 CM |
1218 | help |
1219 | By enabling this option, the kernel will be compiled in | |
75fea300 | 1220 | Thumb-2 mode. |
16c79651 CM |
1221 | |
1222 | If unsure, say N. | |
1223 | ||
42f25bdd NP |
1224 | config ARM_PATCH_IDIV |
1225 | bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" | |
5408445b | 1226 | depends on CPU_32v7 |
42f25bdd NP |
1227 | default y |
1228 | help | |
1229 | The ARM compiler inserts calls to __aeabi_idiv() and | |
1230 | __aeabi_uidiv() when it needs to perform division on signed | |
1231 | and unsigned integers. Some v7 CPUs have support for the sdiv | |
1232 | and udiv instructions that can be used to implement those | |
1233 | functions. | |
1234 | ||
1235 | Enabling this option allows the kernel to modify itself to | |
1236 | replace the first two instructions of these library functions | |
1237 | with the sdiv or udiv plus "bx lr" instructions when the CPU | |
1238 | it is running on supports them. Typically this will be faster | |
1239 | and less power intensive than running the original library | |
1240 | code to do integer division. | |
1241 | ||
704bdda0 | 1242 | config AEABI |
a05b9608 ND |
1243 | bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ |
1244 | !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG | |
1245 | default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG | |
704bdda0 NP |
1246 | help |
1247 | This option allows for the kernel to be compiled using the latest | |
1248 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1249 | space environment that is also compiled with EABI. | |
1250 | ||
1251 | Since there are major incompatibilities between the legacy ABI and | |
1252 | EABI, especially with regard to structure member alignment, this | |
1253 | option also changes the kernel syscall calling convention to | |
1254 | disambiguate both ABIs and allow for backward compatibility support | |
1255 | (selected with CONFIG_OABI_COMPAT). | |
1256 | ||
1257 | To use this you need GCC version 4.0.0 or later. | |
1258 | ||
6c90c872 | 1259 | config OABI_COMPAT |
a73a3ff1 | 1260 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1261 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1262 | help |
1263 | This option preserves the old syscall interface along with the | |
1264 | new (ARM EABI) one. It also provides a compatibility layer to | |
1265 | intercept syscalls that have structure arguments which layout | |
1266 | in memory differs between the legacy ABI and the new ARM EABI | |
1267 | (only for non "thumb" binaries). This option adds a tiny | |
1268 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1269 | |
1270 | The seccomp filter system will not be available when this is | |
1271 | selected, since there is no way yet to sensibly distinguish | |
1272 | between calling conventions during filtering. | |
1273 | ||
6c90c872 NP |
1274 | If you know you'll be using only pure EABI user space then you |
1275 | can say N here. If this option is not selected and you attempt | |
1276 | to execute a legacy ABI binary then the result will be | |
1277 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1278 | at all). If in doubt say N. |
6c90c872 | 1279 | |
fb597f2a | 1280 | config ARCH_SELECT_MEMORY_MODEL |
6fd09c9a | 1281 | def_bool y |
fb597f2a GF |
1282 | |
1283 | config ARCH_FLATMEM_ENABLE | |
6fd09c9a | 1284 | def_bool !(ARCH_RPC || ARCH_SA1100) |
05944d74 | 1285 | |
05944d74 | 1286 | config ARCH_SPARSEMEM_ENABLE |
6fd09c9a | 1287 | def_bool !ARCH_FOOTBRIDGE |
fb597f2a | 1288 | select SPARSEMEM_STATIC if SPARSEMEM |
07a2f737 | 1289 | |
053a96ca | 1290 | config HIGHMEM |
e8db89a2 RK |
1291 | bool "High Memory Support" |
1292 | depends on MMU | |
2a15ba82 | 1293 | select KMAP_LOCAL |
825c43f5 | 1294 | select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY |
053a96ca NP |
1295 | help |
1296 | The address space of ARM processors is only 4 Gigabytes large | |
1297 | and it has to accommodate user address space, kernel address | |
1298 | space as well as some memory mapped IO. That means that, if you | |
1299 | have a large amount of physical memory and/or IO, not all of the | |
1300 | memory can be "permanently mapped" by the kernel. The physical | |
1301 | memory that is not permanently mapped is called "high memory". | |
1302 | ||
1303 | Depending on the selected kernel/user memory split, minimum | |
1304 | vmalloc space and actual amount of RAM, you may not need this | |
1305 | option which should result in a slightly faster kernel. | |
1306 | ||
1307 | If unsure, say n. | |
1308 | ||
65cec8e3 | 1309 | config HIGHPTE |
9a431bd5 | 1310 | bool "Allocate 2nd-level pagetables from highmem" if EXPERT |
65cec8e3 | 1311 | depends on HIGHMEM |
9a431bd5 | 1312 | default y |
b4d103d1 RK |
1313 | help |
1314 | The VM uses one page of physical memory for each page table. | |
1315 | For systems with a lot of processes, this can use a lot of | |
1316 | precious low memory, eventually leading to low memory being | |
1317 | consumed by page tables. Setting this option will allow | |
1318 | user-space 2nd level page tables to reside in high memory. | |
65cec8e3 | 1319 | |
a5e090ac RK |
1320 | config CPU_SW_DOMAIN_PAN |
1321 | bool "Enable use of CPU domains to implement privileged no-access" | |
1322 | depends on MMU && !ARM_LPAE | |
1b8873a0 JI |
1323 | default y |
1324 | help | |
a5e090ac RK |
1325 | Increase kernel security by ensuring that normal kernel accesses |
1326 | are unable to access userspace addresses. This can help prevent | |
1327 | use-after-free bugs becoming an exploitable privilege escalation | |
1328 | by ensuring that magic values (such as LIST_POISON) will always | |
1329 | fault when dereferenced. | |
1330 | ||
1331 | CPUs with low-vector mappings use a best-efforts implementation. | |
1332 | Their lower 1MB needs to remain accessible for the vectors, but | |
1333 | the remainder of userspace will become appropriately inaccessible. | |
65cec8e3 | 1334 | |
1b8873a0 | 1335 | config HW_PERF_EVENTS |
fa8ad788 MR |
1336 | def_bool y |
1337 | depends on ARM_PMU | |
1b8873a0 | 1338 | |
7d485f64 AB |
1339 | config ARM_MODULE_PLTS |
1340 | bool "Use PLTs to allow module memory to spill over into vmalloc area" | |
1341 | depends on MODULES | |
8fa7ea40 | 1342 | select KASAN_VMALLOC if KASAN |
e7229f7d | 1343 | default y |
7d485f64 AB |
1344 | help |
1345 | Allocate PLTs when loading modules so that jumps and calls whose | |
1346 | targets are too far away for their relative offsets to be encoded | |
1347 | in the instructions themselves can be bounced via veneers in the | |
1348 | module's PLT. This allows modules to be allocated in the generic | |
1349 | vmalloc area after the dedicated module memory area has been | |
1350 | exhausted. The modules will use slightly more memory, but after | |
1351 | rounding up to page size, the actual memory footprint is usually | |
1352 | the same. | |
1353 | ||
e7229f7d AR |
1354 | Disabling this is usually safe for small single-platform |
1355 | configurations. If unsure, say y. | |
7d485f64 | 1356 | |
0192445c | 1357 | config ARCH_FORCE_MAX_ORDER |
8c907785 | 1358 | int "Order of maximal physically contiguous allocations" |
23baf831 KS |
1359 | default "11" if SOC_AM33XX |
1360 | default "8" if SA1111 | |
1361 | default "10" | |
c1b2d970 | 1362 | help |
8c907785 MRI |
1363 | The kernel page allocator limits the size of maximal physically |
1364 | contiguous allocations. The limit is called MAX_ORDER and it | |
1365 | defines the maximal power of two of number of pages that can be | |
1366 | allocated as a single contiguous block. This option allows | |
1367 | overriding the default setting when ability to allocate very | |
1368 | large blocks of physically contiguous memory is required. | |
1369 | ||
1370 | Don't change if unsure. | |
c1b2d970 | 1371 | |
1da177e4 | 1372 | config ALIGNMENT_TRAP |
3e3f354b | 1373 | def_bool CPU_CP15_MMU |
e119bfff | 1374 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1375 | help |
84eb8d06 | 1376 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1377 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1378 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1379 | fetch/store instructions will be emulated in software if you say | |
1380 | here, which has a severe performance impact. This is necessary for | |
1381 | correct operation of some network protocols. With an IP-only | |
1382 | configuration it is safe to say N, otherwise say Y. | |
1383 | ||
39ec58f3 | 1384 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1385 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1386 | depends on MMU | |
39ec58f3 LB |
1387 | default y if CPU_FEROCEON |
1388 | help | |
1389 | Implement faster copy_to_user and clear_user methods for CPU | |
1390 | cores where a 8-word STM instruction give significantly higher | |
1391 | memory write throughput than a sequence of individual 32bit stores. | |
1392 | ||
1393 | A possible side effect is a slight increase in scheduling latency | |
1394 | between threads sharing the same address space if they invoke | |
1395 | such copy operations with large buffers. | |
1396 | ||
1397 | However, if the CPU data cache is using a write-allocate mode, | |
1398 | this option is unlikely to provide any performance gain. | |
1399 | ||
02c2433b SS |
1400 | config PARAVIRT |
1401 | bool "Enable paravirtualization code" | |
1402 | help | |
1403 | This changes the kernel so it can modify itself when it is run | |
1404 | under a hypervisor, potentially improving performance significantly | |
1405 | over full virtualization. | |
1406 | ||
1407 | config PARAVIRT_TIME_ACCOUNTING | |
1408 | bool "Paravirtual steal time accounting" | |
1409 | select PARAVIRT | |
02c2433b SS |
1410 | help |
1411 | Select this option to enable fine granularity task steal time | |
1412 | accounting. Time spent executing other tasks in parallel with | |
1413 | the current vCPU is discounted from the vCPU power. To account for | |
1414 | that, there can be a small performance impact. | |
1415 | ||
1416 | If in doubt, say N here. | |
1417 | ||
eff8d644 SS |
1418 | config XEN_DOM0 |
1419 | def_bool y | |
1420 | depends on XEN | |
1421 | ||
1422 | config XEN | |
c2ba1f7d | 1423 | bool "Xen guest support on ARM" |
85323a99 | 1424 | depends on ARM && AEABI && OF |
f880b67d | 1425 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1426 | depends on !GENERIC_ATOMIC64 |
7693decc | 1427 | depends on MMU |
51aaf81f | 1428 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1429 | select ARM_PSCI |
f21254cd | 1430 | select SWIOTLB |
83862ccf | 1431 | select SWIOTLB_XEN |
02c2433b | 1432 | select PARAVIRT |
eff8d644 SS |
1433 | help |
1434 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1435 | ||
f05eb1d2 AB |
1436 | config CC_HAVE_STACKPROTECTOR_TLS |
1437 | def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) | |
1438 | ||
189af465 AB |
1439 | config STACKPROTECTOR_PER_TASK |
1440 | bool "Use a unique stack canary value for each task" | |
9c46929e | 1441 | depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA |
f05eb1d2 AB |
1442 | depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS |
1443 | select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS | |
189af465 AB |
1444 | default y |
1445 | help | |
1446 | Due to the fact that GCC uses an ordinary symbol reference from | |
1447 | which to load the value of the stack canary, this value can only | |
1448 | change at reboot time on SMP systems, and all tasks running in the | |
1449 | kernel's address space are forced to use the same canary value for | |
1450 | the entire duration that the system is up. | |
1451 | ||
1452 | Enable this option to switch to a different method that uses a | |
1453 | different canary value for each task. | |
1454 | ||
1da177e4 LT |
1455 | endmenu |
1456 | ||
1457 | menu "Boot options" | |
1458 | ||
9eb8f674 GL |
1459 | config USE_OF |
1460 | bool "Flattened Device Tree support" | |
b1b3f49c | 1461 | select IRQ_DOMAIN |
9eb8f674 | 1462 | select OF |
9eb8f674 GL |
1463 | help |
1464 | Include support for flattened device tree machine descriptions. | |
1465 | ||
6a1d798f RH |
1466 | config ARCH_WANT_FLAT_DTB_INSTALL |
1467 | def_bool y | |
1468 | ||
bd51e2f5 | 1469 | config ATAGS |
96a4ce30 | 1470 | bool "Support for the traditional ATAGS boot data passing" |
bd51e2f5 NP |
1471 | default y |
1472 | help | |
1473 | This is the traditional way of passing data to the kernel at boot | |
1474 | time. If you are solely relying on the flattened device tree (or | |
1475 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
acb926d6 AB |
1476 | to remove ATAGS support from your kernel binary. |
1477 | ||
bd51e2f5 NP |
1478 | config DEPRECATED_PARAM_STRUCT |
1479 | bool "Provide old way to pass kernel parameters" | |
1480 | depends on ATAGS | |
1481 | help | |
1482 | This was deprecated in 2001 and announced to live on for 5 years. | |
1483 | Some old boot loaders still use this way. | |
1484 | ||
1da177e4 LT |
1485 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1486 | # TEXT and BSS so we preserve their values in the config files. | |
1487 | config ZBOOT_ROM_TEXT | |
1488 | hex "Compressed ROM boot loader base address" | |
39c3e304 | 1489 | default 0x0 |
1da177e4 LT |
1490 | help |
1491 | The physical address at which the ROM-able zImage is to be | |
1492 | placed in the target. Platforms which normally make use of | |
1493 | ROM-able zImage formats normally set this to a suitable | |
1494 | value in their defconfig file. | |
1495 | ||
1496 | If ZBOOT_ROM is not enabled, this has no effect. | |
1497 | ||
1498 | config ZBOOT_ROM_BSS | |
1499 | hex "Compressed ROM boot loader BSS address" | |
39c3e304 | 1500 | default 0x0 |
1da177e4 | 1501 | help |
f8c440b2 DF |
1502 | The base address of an area of read/write memory in the target |
1503 | for the ROM-able zImage which must be available while the | |
1504 | decompressor is running. It must be large enough to hold the | |
1505 | entire decompressed kernel plus an additional 128 KiB. | |
1506 | Platforms which normally make use of ROM-able zImage formats | |
1507 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1508 | |
1509 | If ZBOOT_ROM is not enabled, this has no effect. | |
1510 | ||
1511 | config ZBOOT_ROM | |
1512 | bool "Compressed boot loader in ROM/flash" | |
1513 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1514 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1515 | help |
1516 | Say Y here if you intend to execute your compressed kernel image | |
1517 | (zImage) directly from ROM or flash. If unsure, say N. | |
1518 | ||
e2a6a3aa JB |
1519 | config ARM_APPENDED_DTB |
1520 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1521 | depends on OF |
e2a6a3aa JB |
1522 | help |
1523 | With this option, the boot code will look for a device tree binary | |
1524 | (DTB) appended to zImage | |
1525 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1526 | ||
1527 | This is meant as a backward compatibility convenience for those | |
1528 | systems with a bootloader that can't be upgraded to accommodate | |
1529 | the documented boot protocol using a device tree. | |
1530 | ||
1531 | Beware that there is very little in terms of protection against | |
1532 | this option being confused by leftover garbage in memory that might | |
1533 | look like a DTB header after a reboot if no actual DTB is appended | |
1534 | to zImage. Do not leave this option active in a production kernel | |
1535 | if you don't intend to always append a DTB. Proper passing of the | |
1536 | location into r2 of a bootloader provided DTB is always preferable | |
1537 | to this option. | |
1538 | ||
b90b9a38 NP |
1539 | config ARM_ATAG_DTB_COMPAT |
1540 | bool "Supplement the appended DTB with traditional ATAG information" | |
1541 | depends on ARM_APPENDED_DTB | |
1542 | help | |
1543 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1544 | they provide ATAGs with memory configuration, the ramdisk address, | |
1545 | the kernel cmdline string, etc. Such information is dynamically | |
1546 | provided by the bootloader and can't always be stored in a static | |
1547 | DTB. To allow a device tree enabled kernel to be used with such | |
1548 | bootloaders, this option allows zImage to extract the information | |
1549 | from the ATAG list and store it at run time into the appended DTB. | |
1550 | ||
d0f34a11 RG |
1551 | choice |
1552 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1553 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1554 | ||
1555 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1556 | bool "Use bootloader kernel arguments if available" | |
1557 | help | |
1558 | Uses the command-line options passed by the boot loader instead of | |
1559 | the device tree bootargs property. If the boot loader doesn't provide | |
1560 | any, the device tree bootargs property will be used. | |
1561 | ||
1562 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1563 | bool "Extend with bootloader kernel arguments" | |
1564 | help | |
1565 | The command-line arguments provided by the boot loader will be | |
1566 | appended to the the device tree bootargs property. | |
1567 | ||
1568 | endchoice | |
1569 | ||
1da177e4 LT |
1570 | config CMDLINE |
1571 | string "Default kernel command string" | |
1572 | default "" | |
1573 | help | |
3e3f354b | 1574 | On some architectures (e.g. CATS), there is currently no way |
1da177e4 LT |
1575 | for the boot loader to pass arguments to the kernel. For these |
1576 | architectures, you should supply some command-line options at build | |
1577 | time by entering them here. As a minimum, you should specify the | |
1578 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1579 | ||
4394c124 VB |
1580 | choice |
1581 | prompt "Kernel command line type" if CMDLINE != "" | |
1582 | default CMDLINE_FROM_BOOTLOADER | |
1583 | ||
1584 | config CMDLINE_FROM_BOOTLOADER | |
1585 | bool "Use bootloader kernel arguments if available" | |
1586 | help | |
1587 | Uses the command-line options passed by the boot loader. If | |
1588 | the boot loader doesn't provide any, the default kernel command | |
1589 | string provided in CMDLINE will be used. | |
1590 | ||
1591 | config CMDLINE_EXTEND | |
1592 | bool "Extend bootloader kernel arguments" | |
1593 | help | |
1594 | The command-line arguments provided by the boot loader will be | |
1595 | appended to the default kernel command string. | |
1596 | ||
92d2040d AH |
1597 | config CMDLINE_FORCE |
1598 | bool "Always use the default kernel command string" | |
92d2040d AH |
1599 | help |
1600 | Always use the default kernel command string, even if the boot | |
1601 | loader passes other arguments to the kernel. | |
1602 | This is useful if you cannot or don't want to change the | |
1603 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1604 | endchoice |
92d2040d | 1605 | |
1da177e4 LT |
1606 | config XIP_KERNEL |
1607 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1608 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
5408445b | 1609 | depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP |
1da177e4 LT |
1610 | help |
1611 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1612 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1613 | space since the text section of the kernel is not loaded from flash | |
1614 | to RAM. Read-write sections, such as the data section and stack, | |
1615 | are still copied to RAM. The XIP kernel is not compressed since | |
1616 | it has to run directly from flash, so it will take more space to | |
1617 | store it. The flash address used to link the kernel object files, | |
1618 | and for storing it, is configuration dependent. Therefore, if you | |
1619 | say Y here, you must know the proper physical address where to | |
1620 | store the kernel image depending on your own flash memory usage. | |
1621 | ||
1622 | Also note that the make target becomes "make xipImage" rather than | |
1623 | "make zImage" or "make Image". The final kernel binary to put in | |
1624 | ROM memory will be arch/arm/boot/xipImage. | |
1625 | ||
1626 | If unsure, say N. | |
1627 | ||
1628 | config XIP_PHYS_ADDR | |
1629 | hex "XIP Kernel Physical Location" | |
1630 | depends on XIP_KERNEL | |
1631 | default "0x00080000" | |
1632 | help | |
1633 | This is the physical address in your flash memory the kernel will | |
1634 | be linked for and stored to. This address is dependent on your | |
1635 | own flash usage. | |
1636 | ||
ca8b5d97 NP |
1637 | config XIP_DEFLATED_DATA |
1638 | bool "Store kernel .data section compressed in ROM" | |
1639 | depends on XIP_KERNEL | |
1640 | select ZLIB_INFLATE | |
1641 | help | |
1642 | Before the kernel is actually executed, its .data section has to be | |
1643 | copied to RAM from ROM. This option allows for storing that data | |
1644 | in compressed form and decompressed to RAM rather than merely being | |
1645 | copied, saving some precious ROM space. A possible drawback is a | |
1646 | slightly longer boot delay. | |
1647 | ||
c587e4a6 RP |
1648 | config KEXEC |
1649 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 1650 | depends on (!SMP || PM_SLEEP_SMP) |
76950f71 | 1651 | depends on MMU |
2965faa5 | 1652 | select KEXEC_CORE |
c587e4a6 RP |
1653 | help |
1654 | kexec is a system call that implements the ability to shutdown your | |
1655 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 1656 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
1657 | you can start any kernel with it, not just Linux. |
1658 | ||
1659 | It is an ongoing process to be certain the hardware in a machine | |
1660 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 1661 | initially work for you. |
c587e4a6 | 1662 | |
4cd9d6f7 RP |
1663 | config ATAGS_PROC |
1664 | bool "Export atags in procfs" | |
bd51e2f5 | 1665 | depends on ATAGS && KEXEC |
b98d7291 | 1666 | default y |
4cd9d6f7 RP |
1667 | help |
1668 | Should the atags used to boot the kernel be exported in an "atags" | |
1669 | file in procfs. Useful with kexec. | |
1670 | ||
cb5d39b3 MW |
1671 | config CRASH_DUMP |
1672 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
1673 | help |
1674 | Generate crash dump after being started by kexec. This should | |
1675 | be normally only set in special crash dump kernels which are | |
1676 | loaded in the main kernel with kexec-tools into a specially | |
1677 | reserved region and then later executed after a crash by | |
1678 | kdump/kexec. The crash dump kernel must be compiled to a | |
1679 | memory address not used by the main kernel | |
1680 | ||
330d4810 | 1681 | For more details see Documentation/admin-guide/kdump/kdump.rst |
cb5d39b3 | 1682 | |
e69edc79 | 1683 | config AUTO_ZRELADDR |
6fd09c9a AB |
1684 | bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM |
1685 | default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) | |
e69edc79 EM |
1686 | help |
1687 | ZRELADDR is the physical address where the decompressed kernel | |
1688 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
0673cb38 GU |
1689 | will be determined at run-time, either by masking the current IP |
1690 | with 0xf8000000, or, if invalid, from the DTB passed in r2. | |
1691 | This assumes the zImage being placed in the first 128MB from | |
1692 | start of memory. | |
e69edc79 | 1693 | |
81a0bc39 RF |
1694 | config EFI_STUB |
1695 | bool | |
1696 | ||
1697 | config EFI | |
1698 | bool "UEFI runtime support" | |
1699 | depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL | |
1700 | select UCS2_STRING | |
1701 | select EFI_PARAMS_FROM_FDT | |
1702 | select EFI_STUB | |
2e0eb483 | 1703 | select EFI_GENERIC_STUB |
81a0bc39 | 1704 | select EFI_RUNTIME_WRAPPERS |
a7f7f624 | 1705 | help |
81a0bc39 RF |
1706 | This option provides support for runtime services provided |
1707 | by UEFI firmware (such as non-volatile variables, realtime | |
1708 | clock, and platform reset). A UEFI stub is also provided to | |
1709 | allow the kernel to be booted as an EFI application. This | |
1710 | is only useful for kernels that may run on systems that have | |
1711 | UEFI firmware. | |
1712 | ||
bb817bef AB |
1713 | config DMI |
1714 | bool "Enable support for SMBIOS (DMI) tables" | |
1715 | depends on EFI | |
1716 | default y | |
1717 | help | |
1718 | This enables SMBIOS/DMI feature for systems. | |
1719 | ||
1720 | This option is only useful on systems that have UEFI firmware. | |
1721 | However, even with this option, the resultant kernel should | |
1722 | continue to boot on existing non-UEFI platforms. | |
1723 | ||
1724 | NOTE: This does *NOT* enable or encourage the use of DMI quirks, | |
1725 | i.e., the the practice of identifying the platform via DMI to | |
1726 | decide whether certain workarounds for buggy hardware and/or | |
1727 | firmware need to be enabled. This would require the DMI subsystem | |
1728 | to be enabled much earlier than we do on ARM, which is non-trivial. | |
1729 | ||
1da177e4 LT |
1730 | endmenu |
1731 | ||
ac9d7efc | 1732 | menu "CPU Power Management" |
1da177e4 | 1733 | |
1da177e4 | 1734 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 1735 | |
ac9d7efc RK |
1736 | source "drivers/cpuidle/Kconfig" |
1737 | ||
1738 | endmenu | |
1739 | ||
1da177e4 LT |
1740 | menu "Floating point emulation" |
1741 | ||
1742 | comment "At least one emulation must be selected" | |
1743 | ||
1744 | config FPE_NWFPE | |
1745 | bool "NWFPE math emulation" | |
593c252a | 1746 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
a7f7f624 | 1747 | help |
1da177e4 LT |
1748 | Say Y to include the NWFPE floating point emulator in the kernel. |
1749 | This is necessary to run most binaries. Linux does not currently | |
1750 | support floating point hardware so you need to say Y here even if | |
1751 | your machine has an FPA or floating point co-processor podule. | |
1752 | ||
1753 | You may say N here if you are going to load the Acorn FPEmulator | |
1754 | early in the bootup. | |
1755 | ||
1756 | config FPE_NWFPE_XP | |
1757 | bool "Support extended precision" | |
bedf142b | 1758 | depends on FPE_NWFPE |
1da177e4 LT |
1759 | help |
1760 | Say Y to include 80-bit support in the kernel floating-point | |
1761 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
1762 | Note that gcc does not generate 80-bit operations by default, | |
1763 | so in most cases this option only enlarges the size of the | |
1764 | floating point emulator without any good reason. | |
1765 | ||
1766 | You almost surely want to say N here. | |
1767 | ||
1768 | config FPE_FASTFPE | |
1769 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 1770 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
a7f7f624 | 1771 | help |
1da177e4 LT |
1772 | Say Y here to include the FAST floating point emulator in the kernel. |
1773 | This is an experimental much faster emulator which now also has full | |
1774 | precision for the mantissa. It does not support any exceptions. | |
1775 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
1776 | ||
1777 | It should be sufficient for most programs. It may be not suitable | |
1778 | for scientific calculations, but you have to check this for yourself. | |
1779 | If you do not feel you need a faster FP emulation you should better | |
1780 | choose NWFPE. | |
1781 | ||
1782 | config VFP | |
1783 | bool "VFP-format floating point maths" | |
e399b1a4 | 1784 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
1785 | help |
1786 | Say Y to include VFP support code in the kernel. This is needed | |
1787 | if your hardware includes a VFP unit. | |
1788 | ||
e318b36e | 1789 | Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for |
1da177e4 LT |
1790 | release notes and additional status information. |
1791 | ||
1792 | Say N if your target does not have VFP hardware. | |
1793 | ||
25ebee02 CM |
1794 | config VFPv3 |
1795 | bool | |
1796 | depends on VFP | |
1797 | default y if CPU_V7 | |
1798 | ||
b5872db4 CM |
1799 | config NEON |
1800 | bool "Advanced SIMD (NEON) Extension support" | |
1801 | depends on VFPv3 && CPU_V7 | |
1802 | help | |
1803 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
1804 | Extension. | |
1805 | ||
73c132c1 AB |
1806 | config KERNEL_MODE_NEON |
1807 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 1808 | depends on NEON && AEABI |
73c132c1 AB |
1809 | help |
1810 | Say Y to include support for NEON in kernel mode. | |
1811 | ||
1da177e4 LT |
1812 | endmenu |
1813 | ||
1da177e4 LT |
1814 | menu "Power management options" |
1815 | ||
eceab4ac | 1816 | source "kernel/power/Kconfig" |
1da177e4 | 1817 | |
f4cb5700 | 1818 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 1819 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 1820 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
1821 | def_bool y |
1822 | ||
15e0d9e3 | 1823 | config ARM_CPU_SUSPEND |
8b6f2499 | 1824 | def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW |
1b9bdf5c | 1825 | depends on ARCH_SUSPEND_POSSIBLE |
15e0d9e3 | 1826 | |
603fb42a SC |
1827 | config ARCH_HIBERNATION_POSSIBLE |
1828 | bool | |
1829 | depends on MMU | |
1830 | default y if ARCH_SUSPEND_POSSIBLE | |
1831 | ||
1da177e4 LT |
1832 | endmenu |
1833 | ||
2cbd1cc3 | 1834 | source "arch/arm/Kconfig.assembler" |