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Commit | Line | Data |
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dd84058d MY |
1 | menu "ARM architecture" |
2 | depends on ARM | |
3 | ||
4 | config SYS_ARCH | |
dd84058d MY |
5 | default "arm" |
6 | ||
016a954e MY |
7 | config ARM64 |
8 | bool | |
bb6b142f | 9 | select PHYS_64BIT |
067716ba | 10 | select SYS_CACHE_SHIFT_6 |
016a954e | 11 | |
49e93875 SW |
12 | if ARM64 |
13 | config POSITION_INDEPENDENT | |
14 | bool "Generate position-independent pre-relocation code" | |
f071cdab | 15 | select INIT_SP_RELATIVE |
49e93875 SW |
16 | help |
17 | U-Boot expects to be linked to a specific hard-coded address, and to | |
18 | be loaded to and run from that address. This option lifts that | |
19 | restriction, thus allowing the code to be loaded to and executed | |
20 | from almost any address. This logic relies on the relocation | |
e852b30b | 21 | information that is embedded in the binary to support U-Boot |
49e93875 | 22 | relocating itself to the top-of-RAM later during execution. |
e6c90448 | 23 | |
382de4a7 MY |
24 | config INIT_SP_RELATIVE |
25 | bool "Specify the early stack pointer relative to the .bss section" | |
e6c90448 SW |
26 | help |
27 | U-Boot typically uses a hard-coded value for the stack pointer | |
382de4a7 | 28 | before relocation. Enable this option to instead calculate the |
e6c90448 | 29 | initial SP at run-time. This is useful to avoid hard-coding addresses |
e852b30b | 30 | into U-Boot, so that it can be loaded and executed at arbitrary |
382de4a7 MY |
31 | addresses and thus avoid using arbitrary addresses at runtime. |
32 | ||
33 | If this option is enabled, the early stack pointer is set to | |
34 | &_bss_start with a offset value added. The offset is specified by | |
35 | SYS_INIT_SP_BSS_OFFSET. | |
36 | ||
37 | config SYS_INIT_SP_BSS_OFFSET | |
38 | int "Early stack offset from the .bss base address" | |
39 | depends on INIT_SP_RELATIVE | |
40 | default 524288 | |
41 | help | |
42 | This option's value is the offset added to &_bss_start in order to | |
e6c90448 SW |
43 | calculate the stack pointer. This offset should be large enough so |
44 | that the early malloc region, global data (gd), and early stack usage | |
45 | do not overlap any appended DTB. | |
8163faf9 SW |
46 | |
47 | config LINUX_KERNEL_IMAGE_HEADER | |
48 | bool | |
49 | help | |
50 | Place a Linux kernel image header at the start of the U-Boot binary. | |
51 | The format of the header is described in the Linux kernel source at | |
52 | Documentation/arm64/booting.txt. This feature is useful since the | |
53 | image header reports the amount of memory (BSS and similar) that | |
54 | U-Boot needs to use, but which isn't part of the binary. | |
55 | ||
56 | if LINUX_KERNEL_IMAGE_HEADER | |
57 | config LNX_KRNL_IMG_TEXT_OFFSET_BASE | |
58 | hex | |
59 | help | |
60 | The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the | |
e852b30b | 61 | TEXT_OFFSET value written to the Linux kernel image header. |
8163faf9 | 62 | endif |
49e93875 SW |
63 | endif |
64 | ||
0bc4356d BKRG |
65 | config GIC_V3_ITS |
66 | bool "ARM GICV3 ITS" | |
67 | help | |
68 | ARM GICV3 Interrupt translation service (ITS). | |
69 | Basic support for programming locality specific peripheral | |
70 | interrupts (LPI) configuration tables and enable LPI tables. | |
71 | LPI configuration table can be used by u-boot or Linux. | |
72 | ARM GICV3 has limitation, once the LPI table is enabled, LPI | |
73 | configuration table can not be re-programmed, unless GICV3 reset. | |
74 | ||
49e93875 SW |
75 | config STATIC_RELA |
76 | bool | |
77 | default y if ARM64 && !POSITION_INDEPENDENT | |
78 | ||
37217f0e LV |
79 | config DMA_ADDR_T_64BIT |
80 | bool | |
81 | default y if ARM64 | |
82 | ||
2e07c249 | 83 | config HAS_VBAR |
e009bfa4 | 84 | bool |
2e07c249 | 85 | |
62e92077 | 86 | config HAS_THUMB2 |
e009bfa4 | 87 | bool |
62e92077 | 88 | |
111a6af9 PE |
89 | # Used for compatibility with asm files copied from the kernel |
90 | config ARM_ASM_UNIFIED | |
91 | bool | |
92 | default y | |
93 | ||
94 | # Used for compatibility with asm files copied from the kernel | |
95 | config THUMB2_KERNEL | |
96 | bool | |
97 | ||
a0aba8a2 TW |
98 | config SYS_ICACHE_OFF |
99 | bool "Do not enable icache" | |
100 | default n | |
101 | help | |
102 | Do not enable instruction cache in U-Boot. | |
103 | ||
10015025 TW |
104 | config SPL_SYS_ICACHE_OFF |
105 | bool "Do not enable icache in SPL" | |
106 | depends on SPL | |
107 | default SYS_ICACHE_OFF | |
108 | help | |
109 | Do not enable instruction cache in SPL. | |
110 | ||
a0aba8a2 TW |
111 | config SYS_DCACHE_OFF |
112 | bool "Do not enable dcache" | |
113 | default n | |
114 | help | |
115 | Do not enable data cache in U-Boot. | |
116 | ||
10015025 TW |
117 | config SPL_SYS_DCACHE_OFF |
118 | bool "Do not enable dcache in SPL" | |
119 | depends on SPL | |
120 | default SYS_DCACHE_OFF | |
121 | help | |
122 | Do not enable data cache in SPL. | |
123 | ||
f4bcd767 LV |
124 | config SYS_ARM_CACHE_CP15 |
125 | bool "CP15 based cache enabling support" | |
126 | help | |
127 | Select this if your processor suports enabling caches by using | |
128 | CP15 registers. | |
129 | ||
7240b80e LV |
130 | config SYS_ARM_MMU |
131 | bool "MMU-based Paged Memory Management Support" | |
f4bcd767 | 132 | select SYS_ARM_CACHE_CP15 |
7240b80e LV |
133 | help |
134 | Select if you want MMU-based virtualised addressing space | |
e852b30b | 135 | support via paged memory management. |
7240b80e | 136 | |
f2ef2043 LV |
137 | config SYS_ARM_MPU |
138 | bool 'Use the ARM v7 PMSA Compliant MPU' | |
139 | help | |
140 | Some ARM systems without an MMU have instead a Memory Protection | |
141 | Unit (MPU) that defines the type and permissions for regions of | |
142 | memory. | |
143 | If your CPU has an MPU then you should choose 'y' here unless you | |
144 | know that you do not want to use the MPU. | |
145 | ||
8dda2e2f TR |
146 | # If set, the workarounds for these ARM errata are applied early during U-Boot |
147 | # startup. Note that in general these options force the workarounds to be | |
148 | # applied; no CPU-type/version detection exists, unlike the similar options in | |
149 | # the Linux kernel. Do not set these options unless they apply! Also note that | |
e852b30b RD |
150 | # the following can be machine-specific errata. These do have ability to |
151 | # provide rudimentary version and machine-specific checks, but expect no | |
8dda2e2f TR |
152 | # product checks: |
153 | # CONFIG_ARM_ERRATA_430973 | |
154 | # CONFIG_ARM_ERRATA_454179 | |
155 | # CONFIG_ARM_ERRATA_621766 | |
156 | # CONFIG_ARM_ERRATA_798870 | |
157 | # CONFIG_ARM_ERRATA_801819 | |
7b37a9c7 | 158 | # CONFIG_ARM_CORTEX_A8_CVE_2017_5715 |
c2ca3fdf | 159 | # CONFIG_ARM_CORTEX_A15_CVE_2017_5715 |
7b37a9c7 | 160 | |
8dda2e2f TR |
161 | config ARM_ERRATA_430973 |
162 | bool | |
163 | ||
164 | config ARM_ERRATA_454179 | |
165 | bool | |
166 | ||
167 | config ARM_ERRATA_621766 | |
168 | bool | |
169 | ||
170 | config ARM_ERRATA_716044 | |
171 | bool | |
172 | ||
19a75b8c SS |
173 | config ARM_ERRATA_725233 |
174 | bool | |
175 | ||
8dda2e2f TR |
176 | config ARM_ERRATA_742230 |
177 | bool | |
178 | ||
179 | config ARM_ERRATA_743622 | |
180 | bool | |
181 | ||
182 | config ARM_ERRATA_751472 | |
183 | bool | |
184 | ||
185 | config ARM_ERRATA_761320 | |
186 | bool | |
187 | ||
188 | config ARM_ERRATA_773022 | |
189 | bool | |
190 | ||
191 | config ARM_ERRATA_774769 | |
192 | bool | |
193 | ||
194 | config ARM_ERRATA_794072 | |
195 | bool | |
196 | ||
197 | config ARM_ERRATA_798870 | |
198 | bool | |
199 | ||
200 | config ARM_ERRATA_801819 | |
201 | bool | |
202 | ||
203 | config ARM_ERRATA_826974 | |
204 | bool | |
205 | ||
206 | config ARM_ERRATA_828024 | |
207 | bool | |
208 | ||
209 | config ARM_ERRATA_829520 | |
210 | bool | |
211 | ||
212 | config ARM_ERRATA_833069 | |
213 | bool | |
214 | ||
215 | config ARM_ERRATA_833471 | |
216 | bool | |
217 | ||
11d94319 | 218 | config ARM_ERRATA_845369 |
6e7bdde4 | 219 | bool |
11d94319 | 220 | |
8776350d NM |
221 | config ARM_ERRATA_852421 |
222 | bool | |
223 | ||
224 | config ARM_ERRATA_852423 | |
225 | bool | |
226 | ||
ab0ab54e AW |
227 | config ARM_ERRATA_855873 |
228 | bool | |
229 | ||
7b37a9c7 NM |
230 | config ARM_CORTEX_A8_CVE_2017_5715 |
231 | bool | |
232 | ||
c2ca3fdf NM |
233 | config ARM_CORTEX_A15_CVE_2017_5715 |
234 | bool | |
235 | ||
2e07c249 | 236 | config CPU_ARM720T |
e009bfa4 | 237 | bool |
067716ba | 238 | select SYS_CACHE_SHIFT_5 |
7240b80e | 239 | imply SYS_ARM_MMU |
2e07c249 GS |
240 | |
241 | config CPU_ARM920T | |
e009bfa4 | 242 | bool |
067716ba | 243 | select SYS_CACHE_SHIFT_5 |
7240b80e | 244 | imply SYS_ARM_MMU |
2e07c249 GS |
245 | |
246 | config CPU_ARM926EJS | |
e009bfa4 | 247 | bool |
067716ba | 248 | select SYS_CACHE_SHIFT_5 |
7240b80e | 249 | imply SYS_ARM_MMU |
2e07c249 GS |
250 | |
251 | config CPU_ARM946ES | |
e009bfa4 | 252 | bool |
067716ba | 253 | select SYS_CACHE_SHIFT_5 |
7240b80e | 254 | imply SYS_ARM_MMU |
2e07c249 GS |
255 | |
256 | config CPU_ARM1136 | |
e009bfa4 | 257 | bool |
067716ba | 258 | select SYS_CACHE_SHIFT_5 |
7240b80e | 259 | imply SYS_ARM_MMU |
2e07c249 GS |
260 | |
261 | config CPU_ARM1176 | |
e009bfa4 TR |
262 | bool |
263 | select HAS_VBAR | |
067716ba | 264 | select SYS_CACHE_SHIFT_5 |
7240b80e | 265 | imply SYS_ARM_MMU |
2e07c249 | 266 | |
acf15001 | 267 | config CPU_V7A |
e009bfa4 | 268 | bool |
e009bfa4 | 269 | select HAS_THUMB2 |
5ed063d1 | 270 | select HAS_VBAR |
067716ba | 271 | select SYS_CACHE_SHIFT_6 |
7240b80e | 272 | imply SYS_ARM_MMU |
2e07c249 | 273 | |
12d8a729 | 274 | config CPU_V7M |
275 | bool | |
e009bfa4 | 276 | select HAS_THUMB2 |
f2ef2043 | 277 | select SYS_ARM_MPU |
5ed063d1 | 278 | select SYS_CACHE_SHIFT_5 |
ea37f0b3 | 279 | select SYS_THUMB_BUILD |
5ed063d1 | 280 | select THUMB2_KERNEL |
12d8a729 | 281 | |
4bbd6b1d MS |
282 | config CPU_V7R |
283 | bool | |
284 | select HAS_THUMB2 | |
f2ef2043 | 285 | select SYS_ARM_CACHE_CP15 |
5ed063d1 MS |
286 | select SYS_ARM_MPU |
287 | select SYS_CACHE_SHIFT_6 | |
4bbd6b1d | 288 | |
2e07c249 | 289 | config CPU_PXA |
e009bfa4 | 290 | bool |
067716ba | 291 | select SYS_CACHE_SHIFT_5 |
7240b80e | 292 | imply SYS_ARM_MMU |
2e07c249 GS |
293 | |
294 | config CPU_SA1100 | |
e009bfa4 | 295 | bool |
067716ba | 296 | select SYS_CACHE_SHIFT_5 |
7240b80e | 297 | imply SYS_ARM_MMU |
2e07c249 GS |
298 | |
299 | config SYS_CPU | |
e009bfa4 TR |
300 | default "arm720t" if CPU_ARM720T |
301 | default "arm920t" if CPU_ARM920T | |
302 | default "arm926ejs" if CPU_ARM926EJS | |
303 | default "arm946es" if CPU_ARM946ES | |
304 | default "arm1136" if CPU_ARM1136 | |
305 | default "arm1176" if CPU_ARM1176 | |
acf15001 | 306 | default "armv7" if CPU_V7A |
4bbd6b1d | 307 | default "armv7" if CPU_V7R |
e009bfa4 TR |
308 | default "armv7m" if CPU_V7M |
309 | default "pxa" if CPU_PXA | |
310 | default "sa1100" if CPU_SA1100 | |
01541eec | 311 | default "armv8" if ARM64 |
2e07c249 | 312 | |
66020a67 MV |
313 | config SYS_ARM_ARCH |
314 | int | |
315 | default 4 if CPU_ARM720T | |
316 | default 4 if CPU_ARM920T | |
317 | default 5 if CPU_ARM926EJS | |
318 | default 5 if CPU_ARM946ES | |
319 | default 6 if CPU_ARM1136 | |
320 | default 6 if CPU_ARM1176 | |
acf15001 | 321 | default 7 if CPU_V7A |
66020a67 | 322 | default 7 if CPU_V7M |
4bbd6b1d | 323 | default 7 if CPU_V7R |
66020a67 MV |
324 | default 5 if CPU_PXA |
325 | default 4 if CPU_SA1100 | |
326 | default 8 if ARM64 | |
327 | ||
067716ba TR |
328 | config SYS_CACHE_SHIFT_5 |
329 | bool | |
330 | ||
331 | config SYS_CACHE_SHIFT_6 | |
332 | bool | |
333 | ||
334 | config SYS_CACHE_SHIFT_7 | |
335 | bool | |
336 | ||
337 | config SYS_CACHELINE_SIZE | |
338 | int | |
339 | default 128 if SYS_CACHE_SHIFT_7 | |
340 | default 64 if SYS_CACHE_SHIFT_6 | |
341 | default 32 if SYS_CACHE_SHIFT_5 | |
342 | ||
f8dc7f2f PD |
343 | choice |
344 | prompt "Select the ARM data write cache policy" | |
345 | default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ | |
346 | TARGET_BCMNSP || CPU_PXA || RZA1 | |
347 | default SYS_ARM_CACHE_WRITEBACK | |
348 | ||
349 | config SYS_ARM_CACHE_WRITEBACK | |
350 | bool "Write-back (WB)" | |
351 | help | |
352 | A write updates the cache only and marks the cache line as dirty. | |
353 | External memory is updated only when the line is evicted or explicitly | |
354 | cleaned. | |
355 | ||
356 | config SYS_ARM_CACHE_WRITETHROUGH | |
357 | bool "Write-through (WT)" | |
358 | help | |
359 | A write updates both the cache and the external memory system. | |
360 | This does not mark the cache line as dirty. | |
361 | ||
362 | config SYS_ARM_CACHE_WRITEALLOC | |
363 | bool "Write allocation (WA)" | |
364 | help | |
365 | A cache line is allocated on a write miss. This means that executing a | |
366 | store instruction on the processor might cause a burst read to occur. | |
367 | There is a linefill to obtain the data for the cache line, before the | |
368 | write is performed. | |
369 | endchoice | |
370 | ||
1bf33015 AF |
371 | config ARCH_CPU_INIT |
372 | bool "Enable ARCH_CPU_INIT" | |
373 | help | |
e852b30b | 374 | Some architectures require a call to arch_cpu_init(). |
1bf33015 AF |
375 | Say Y here to enable it |
376 | ||
7842b6a9 AP |
377 | config SYS_ARCH_TIMER |
378 | bool "ARM Generic Timer support" | |
acf15001 | 379 | depends on CPU_V7A || ARM64 |
7842b6a9 AP |
380 | default y if ARM64 |
381 | help | |
382 | The ARM Generic Timer (aka arch-timer) provides an architected | |
383 | interface to a timer source on an SoC. | |
e852b30b | 384 | It is mandatory for ARMv8 implementation and widely available |
7842b6a9 AP |
385 | on ARMv7 systems. |
386 | ||
c54bcf68 MY |
387 | config ARM_SMCCC |
388 | bool "Support for ARM SMC Calling Convention (SMCCC)" | |
acf15001 | 389 | depends on CPU_V7A || ARM64 |
573a3811 | 390 | select ARM_PSCI_FW |
c54bcf68 MY |
391 | help |
392 | Say Y here if you want to enable ARM SMC Calling Convention. | |
393 | This should be enabled if U-Boot needs to communicate with system | |
394 | firmware (for example, PSCI) according to SMCCC. | |
395 | ||
f91afc4d LW |
396 | config SEMIHOSTING |
397 | bool "support boot from semihosting" | |
398 | help | |
399 | In emulated environments, semihosting is a way for | |
400 | the hosted environment to call out to the emulator to | |
401 | retrieve files from the host machine. | |
402 | ||
3a649407 TR |
403 | config SYS_THUMB_BUILD |
404 | bool "Build U-Boot using the Thumb instruction set" | |
405 | depends on !ARM64 | |
406 | help | |
407 | Use this flag to build U-Boot using the Thumb instruction set for | |
408 | ARM architectures. Thumb instruction set provides better code | |
409 | density. For ARM architectures that support Thumb2 this flag will | |
410 | result in Thumb2 code generated by GCC. | |
411 | ||
412 | config SPL_SYS_THUMB_BUILD | |
413 | bool "Build SPL using the Thumb instruction set" | |
414 | default y if SYS_THUMB_BUILD | |
05705566 | 415 | depends on !ARM64 && SPL |
3a649407 TR |
416 | help |
417 | Use this flag to build SPL using the Thumb instruction set for | |
418 | ARM architectures. Thumb instruction set provides better code | |
419 | density. For ARM architectures that support Thumb2 this flag will | |
420 | result in Thumb2 code generated by GCC. | |
421 | ||
1e32c519 KY |
422 | config TPL_SYS_THUMB_BUILD |
423 | bool "Build TPL using the Thumb instruction set" | |
424 | default y if SYS_THUMB_BUILD | |
425 | depends on TPL && !ARM64 | |
426 | help | |
e852b30b | 427 | Use this flag to build TPL using the Thumb instruction set for |
1e32c519 KY |
428 | ARM architectures. Thumb instruction set provides better code |
429 | density. For ARM architectures that support Thumb2 this flag will | |
430 | result in Thumb2 code generated by GCC. | |
431 | ||
432 | ||
f3e9bec8 PF |
433 | config SYS_L2CACHE_OFF |
434 | bool "L2cache off" | |
435 | help | |
e852b30b | 436 | If SoC does not support L2CACHE or one does not want to enable |
f3e9bec8 PF |
437 | L2CACHE, choose this option. |
438 | ||
cdaa633f AP |
439 | config ENABLE_ARM_SOC_BOOT0_HOOK |
440 | bool "prepare BOOT0 header" | |
441 | help | |
442 | If the SoC's BOOT0 requires a header area filled with (magic) | |
7d531e8a SG |
443 | values, then choose this option, and create a file included as |
444 | <asm/arch/boot0.h> which contains the required assembler code. | |
cdaa633f | 445 | |
85db5831 AP |
446 | config ARM_CORTEX_CPU_IS_UP |
447 | bool | |
448 | default n | |
449 | ||
be72591b FE |
450 | config USE_ARCH_MEMCPY |
451 | bool "Use an assembly optimized implementation of memcpy" | |
40d5534c TR |
452 | default y |
453 | depends on !ARM64 | |
454 | help | |
455 | Enable the generation of an optimized version of memcpy. | |
e852b30b | 456 | Such an implementation may be faster under some conditions |
40d5534c TR |
457 | but may increase the binary size. |
458 | ||
459 | config SPL_USE_ARCH_MEMCPY | |
f8136e68 | 460 | bool "Use an assembly optimized implementation of memcpy for SPL" |
40d5534c | 461 | default y if USE_ARCH_MEMCPY |
05705566 | 462 | depends on !ARM64 && SPL |
be72591b FE |
463 | help |
464 | Enable the generation of an optimized version of memcpy. | |
e852b30b | 465 | Such an implementation may be faster under some conditions |
be72591b FE |
466 | but may increase the binary size. |
467 | ||
1e32c519 KY |
468 | config TPL_USE_ARCH_MEMCPY |
469 | bool "Use an assembly optimized implementation of memcpy for TPL" | |
470 | default y if USE_ARCH_MEMCPY | |
05705566 | 471 | depends on !ARM64 && TPL |
1e32c519 KY |
472 | help |
473 | Enable the generation of an optimized version of memcpy. | |
e852b30b | 474 | Such an implementation may be faster under some conditions |
1e32c519 KY |
475 | but may increase the binary size. |
476 | ||
be72591b FE |
477 | config USE_ARCH_MEMSET |
478 | bool "Use an assembly optimized implementation of memset" | |
40d5534c TR |
479 | default y |
480 | depends on !ARM64 | |
481 | help | |
482 | Enable the generation of an optimized version of memset. | |
e852b30b | 483 | Such an implementation may be faster under some conditions |
40d5534c TR |
484 | but may increase the binary size. |
485 | ||
486 | config SPL_USE_ARCH_MEMSET | |
f8136e68 | 487 | bool "Use an assembly optimized implementation of memset for SPL" |
40d5534c | 488 | default y if USE_ARCH_MEMSET |
05705566 | 489 | depends on !ARM64 && SPL |
be72591b FE |
490 | help |
491 | Enable the generation of an optimized version of memset. | |
e852b30b | 492 | Such an implementation may be faster under some conditions |
be72591b FE |
493 | but may increase the binary size. |
494 | ||
1e32c519 KY |
495 | config TPL_USE_ARCH_MEMSET |
496 | bool "Use an assembly optimized implementation of memset for TPL" | |
497 | default y if USE_ARCH_MEMSET | |
05705566 | 498 | depends on !ARM64 && TPL |
1e32c519 KY |
499 | help |
500 | Enable the generation of an optimized version of memset. | |
e852b30b | 501 | Such an implementation may be faster under some conditions |
1e32c519 KY |
502 | but may increase the binary size. |
503 | ||
085201c2 SDPP |
504 | config SET_STACK_SIZE |
505 | bool "Enable an option to set max stack size that can be used" | |
b72f4505 | 506 | default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ |
085201c2 SDPP |
507 | help |
508 | This will enable an option to set max stack size that can be | |
e852b30b | 509 | used by U-Boot. |
085201c2 SDPP |
510 | |
511 | config STACK_SIZE | |
e852b30b | 512 | hex "Define max stack size that can be used by U-Boot" |
085201c2 | 513 | depends on SET_STACK_SIZE |
a69814c8 | 514 | default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP |
b72f4505 | 515 | default 0x1000000 if ARCH_ZYNQ |
085201c2 | 516 | help |
e852b30b | 517 | Define Max stack size that can be used by U-Boot so that the |
085201c2 SDPP |
518 | initrd_high will be calculated as base stack pointer minus this |
519 | stack size. | |
520 | ||
ec6617c3 AW |
521 | config ARM64_SUPPORT_AARCH32 |
522 | bool "ARM64 system support AArch32 execution state" | |
05705566 AF |
523 | depends on ARM64 |
524 | default y if !TARGET_THUNDERX_88XX | |
ec6617c3 AW |
525 | help |
526 | This ARM64 system supports AArch32 execution state. | |
527 | ||
dd84058d MY |
528 | choice |
529 | prompt "Target select" | |
b928e658 | 530 | default TARGET_HIKEY |
dd84058d | 531 | |
4614b891 MY |
532 | config ARCH_AT91 |
533 | bool "Atmel AT91" | |
f58e9460 | 534 | select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB |
dd84058d MY |
535 | |
536 | config TARGET_EDB93XX | |
537 | bool "Support edb93xx" | |
2e07c249 | 538 | select CPU_ARM920T |
884f9013 | 539 | select PL010_SERIAL |
dd84058d | 540 | |
dd84058d MY |
541 | config TARGET_ASPENITE |
542 | bool "Support aspenite" | |
2e07c249 | 543 | select CPU_ARM926EJS |
dd84058d MY |
544 | |
545 | config TARGET_GPLUGD | |
546 | bool "Support gplugd" | |
2e07c249 | 547 | select CPU_ARM926EJS |
dd84058d | 548 | |
3491ba63 MY |
549 | config ARCH_DAVINCI |
550 | bool "TI DaVinci" | |
2e07c249 | 551 | select CPU_ARM926EJS |
15dc63d6 | 552 | imply CMD_SAVES |
3491ba63 MY |
553 | help |
554 | Support for TI's DaVinci platform. | |
dd84058d | 555 | |
bb0fb4c0 | 556 | config ARCH_KIRKWOOD |
47539e23 | 557 | bool "Marvell Kirkwood" |
4585601a | 558 | select ARCH_MISC_INIT |
5ed063d1 MS |
559 | select BOARD_EARLY_INIT_F |
560 | select CPU_ARM926EJS | |
dd84058d | 561 | |
c3d89140 | 562 | config ARCH_MVEBU |
21b29fc6 | 563 | bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" |
9cffb233 | 564 | select DM |
e3b9c98a | 565 | select DM_ETH |
1d51ea19 | 566 | select DM_SERIAL |
09a54c00 SR |
567 | select DM_SPI |
568 | select DM_SPI_FLASH | |
5ed063d1 MS |
569 | select OF_CONTROL |
570 | select OF_SEPARATE | |
f1b1f770 | 571 | select SPI |
08a00cba | 572 | imply CMD_DM |
a4884831 | 573 | |
dd84058d MY |
574 | config TARGET_APF27 |
575 | bool "Support apf27" | |
2e07c249 | 576 | select CPU_ARM926EJS |
02627356 | 577 | select SUPPORT_SPL |
dd84058d | 578 | |
b16a3316 | 579 | config ARCH_ORION5X |
22f2be7a | 580 | bool "Marvell Orion" |
2e07c249 | 581 | select CPU_ARM926EJS |
dd84058d | 582 | |
dd84058d MY |
583 | config TARGET_SPEAR300 |
584 | bool "Support spear300" | |
a5d67547 | 585 | select BOARD_EARLY_INIT_F |
5ed063d1 | 586 | select CPU_ARM926EJS |
d10fc50f | 587 | select PL011_SERIAL |
5ed063d1 | 588 | imply CMD_SAVES |
dd84058d MY |
589 | |
590 | config TARGET_SPEAR310 | |
591 | bool "Support spear310" | |
a5d67547 | 592 | select BOARD_EARLY_INIT_F |
5ed063d1 | 593 | select CPU_ARM926EJS |
d10fc50f | 594 | select PL011_SERIAL |
5ed063d1 | 595 | imply CMD_SAVES |
dd84058d MY |
596 | |
597 | config TARGET_SPEAR320 | |
598 | bool "Support spear320" | |
a5d67547 | 599 | select BOARD_EARLY_INIT_F |
5ed063d1 | 600 | select CPU_ARM926EJS |
d10fc50f | 601 | select PL011_SERIAL |
5ed063d1 | 602 | imply CMD_SAVES |
dd84058d MY |
603 | |
604 | config TARGET_SPEAR600 | |
605 | bool "Support spear600" | |
a5d67547 | 606 | select BOARD_EARLY_INIT_F |
5ed063d1 | 607 | select CPU_ARM926EJS |
d10fc50f | 608 | select PL011_SERIAL |
5ed063d1 | 609 | imply CMD_SAVES |
dd84058d | 610 | |
9fa32b12 VM |
611 | config TARGET_STV0991 |
612 | bool "Support stv0991" | |
acf15001 | 613 | select CPU_V7A |
cac0ca76 MY |
614 | select DM |
615 | select DM_SERIAL | |
e67abcaa VM |
616 | select DM_SPI |
617 | select DM_SPI_FLASH | |
5ed063d1 | 618 | select PL01X_SERIAL |
f1b1f770 | 619 | select SPI |
e67abcaa | 620 | select SPI_FLASH |
08a00cba | 621 | imply CMD_DM |
9fa32b12 | 622 | |
dd84058d MY |
623 | config TARGET_X600 |
624 | bool "Support x600" | |
e5ec4815 | 625 | select BOARD_LATE_INIT |
2e07c249 | 626 | select CPU_ARM926EJS |
d10fc50f | 627 | select PL011_SERIAL |
5ed063d1 | 628 | select SUPPORT_SPL |
dd84058d | 629 | |
dd84058d MY |
630 | config TARGET_FLEA3 |
631 | bool "Support flea3" | |
2e07c249 | 632 | select CPU_ARM1136 |
dd84058d MY |
633 | |
634 | config TARGET_MX35PDK | |
635 | bool "Support mx35pdk" | |
e5ec4815 | 636 | select BOARD_LATE_INIT |
2e07c249 | 637 | select CPU_ARM1136 |
dd84058d | 638 | |
ddf6bd48 MY |
639 | config ARCH_BCM283X |
640 | bool "Broadcom BCM283X family" | |
58d423b8 | 641 | select DM |
58d423b8 | 642 | select DM_GPIO |
5ed063d1 | 643 | select DM_SERIAL |
76709096 | 644 | select OF_CONTROL |
cf2c7784 | 645 | select PL01X_SERIAL |
ae5326a6 | 646 | select SERIAL_SEARCH_ALL |
08a00cba | 647 | imply CMD_DM |
91d27a17 | 648 | imply FAT_WRITE |
46414296 | 649 | |
ea1a7de5 PR |
650 | config ARCH_BCM63158 |
651 | bool "Broadcom BCM63158 family" | |
652 | select DM | |
653 | select OF_CONTROL | |
654 | imply CMD_DM | |
655 | ||
6454e95f PR |
656 | config ARCH_BCM68360 |
657 | bool "Broadcom BCM68360 family" | |
658 | select DM | |
659 | select OF_CONTROL | |
660 | imply CMD_DM | |
661 | ||
40b59b05 PR |
662 | config ARCH_BCM6858 |
663 | bool "Broadcom BCM6858 family" | |
664 | select DM | |
665 | select OF_CONTROL | |
666 | imply CMD_DM | |
667 | ||
dd84058d MY |
668 | config TARGET_VEXPRESS_CA15_TC2 |
669 | bool "Support vexpress_ca15_tc2" | |
acf15001 | 670 | select CPU_V7A |
ea624e19 HG |
671 | select CPU_V7_HAS_NONSEC |
672 | select CPU_V7_HAS_VIRT | |
d10fc50f | 673 | select PL011_SERIAL |
dd84058d | 674 | |
894c3ad2 TF |
675 | config ARCH_BCMSTB |
676 | bool "Broadcom BCM7XXX family" | |
677 | select CPU_V7A | |
678 | select DM | |
679 | select OF_CONTROL | |
680 | select OF_PRIOR_STAGE | |
08a00cba | 681 | imply CMD_DM |
894c3ad2 TF |
682 | help |
683 | This enables support for Broadcom ARM-based set-top box | |
684 | chipsets, including the 7445 family of chips. | |
685 | ||
dd84058d MY |
686 | config TARGET_VEXPRESS_CA5X2 |
687 | bool "Support vexpress_ca5x2" | |
acf15001 | 688 | select CPU_V7A |
d10fc50f | 689 | select PL011_SERIAL |
dd84058d MY |
690 | |
691 | config TARGET_VEXPRESS_CA9X4 | |
692 | bool "Support vexpress_ca9x4" | |
acf15001 | 693 | select CPU_V7A |
d10fc50f | 694 | select PL011_SERIAL |
dd84058d | 695 | |
43486e4c SR |
696 | config TARGET_BCM23550_W1D |
697 | bool "Support bcm23550_w1d" | |
acf15001 | 698 | select CPU_V7A |
221a949e | 699 | imply CRC32_VERIFY |
91d27a17 | 700 | imply FAT_WRITE |
43486e4c | 701 | |
dd84058d MY |
702 | config TARGET_BCM28155_AP |
703 | bool "Support bcm28155_ap" | |
acf15001 | 704 | select CPU_V7A |
221a949e | 705 | imply CRC32_VERIFY |
91d27a17 | 706 | imply FAT_WRITE |
dd84058d | 707 | |
abb1678c SR |
708 | config TARGET_BCMCYGNUS |
709 | bool "Support bcmcygnus" | |
acf15001 | 710 | select CPU_V7A |
5ed063d1 MS |
711 | imply BCM_SF2_ETH |
712 | imply BCM_SF2_ETH_GMAC | |
551c3934 | 713 | imply CMD_HASH |
5ed063d1 | 714 | imply CRC32_VERIFY |
91d27a17 | 715 | imply FAT_WRITE |
221a949e | 716 | imply HASH_VERIFY |
c89782dc | 717 | imply NETDEVICES |
9dec5270 | 718 | |
abb1678c SR |
719 | config TARGET_BCMNSP |
720 | bool "Support bcmnsp" | |
acf15001 | 721 | select CPU_V7A |
9dec5270 | 722 | |
274bced8 JM |
723 | config TARGET_BCMNS2 |
724 | bool "Support Broadcom Northstar2" | |
725 | select ARM64 | |
726 | help | |
727 | Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit | |
728 | ARMv8 Cortex-A57 processors targeting a broad range of networking | |
e852b30b | 729 | applications. |
274bced8 | 730 | |
72df68cc MY |
731 | config ARCH_EXYNOS |
732 | bool "Samsung EXYNOS" | |
58d423b8 | 733 | select DM |
5ed063d1 | 734 | select DM_GPIO |
fc47cf9d | 735 | select DM_I2C |
5ed063d1 | 736 | select DM_KEYBOARD |
58d423b8 MY |
737 | select DM_SERIAL |
738 | select DM_SPI | |
5ed063d1 | 739 | select DM_SPI_FLASH |
f1b1f770 | 740 | select SPI |
c96d9036 | 741 | imply SYS_THUMB_BUILD |
08a00cba | 742 | imply CMD_DM |
91d27a17 | 743 | imply FAT_WRITE |
dd84058d | 744 | |
311757be SG |
745 | config ARCH_S5PC1XX |
746 | bool "Samsung S5PC1XX" | |
acf15001 | 747 | select CPU_V7A |
58d423b8 | 748 | select DM |
58d423b8 | 749 | select DM_GPIO |
08848e9c | 750 | select DM_I2C |
5ed063d1 | 751 | select DM_SERIAL |
08a00cba | 752 | imply CMD_DM |
311757be | 753 | |
ef2b694c MY |
754 | config ARCH_HIGHBANK |
755 | bool "Calxeda Highbank" | |
acf15001 | 756 | select CPU_V7A |
d10fc50f | 757 | select PL011_SERIAL |
dd84058d | 758 | |
5cbbd9bd MY |
759 | config ARCH_INTEGRATOR |
760 | bool "ARM Ltd. Integrator family" | |
3f394e70 LW |
761 | select DM |
762 | select DM_SERIAL | |
cf2c7784 | 763 | select PL01X_SERIAL |
08a00cba | 764 | imply CMD_DM |
5cbbd9bd | 765 | |
c338f09e MY |
766 | config ARCH_KEYSTONE |
767 | bool "TI Keystone" | |
5ed063d1 | 768 | select CMD_POWEROFF |
acf15001 | 769 | select CPU_V7A |
02627356 | 770 | select SUPPORT_SPL |
7842b6a9 | 771 | select SYS_ARCH_TIMER |
5ed063d1 | 772 | select SYS_THUMB_BUILD |
d56b4b19 | 773 | imply CMD_MTDPARTS |
15dc63d6 | 774 | imply CMD_SAVES |
5ed063d1 | 775 | imply FIT |
dd84058d | 776 | |
586bde93 LV |
777 | config ARCH_K3 |
778 | bool "Texas Instruments' K3 Architecture" | |
779 | select SPL | |
780 | select SUPPORT_SPL | |
781 | select FIT | |
782 | ||
a93fbf4a MY |
783 | config ARCH_OMAP2PLUS |
784 | bool "TI OMAP2+" | |
acf15001 | 785 | select CPU_V7A |
0680f1b1 | 786 | select SPL_BOARD_INIT if SPL |
ff6c3125 | 787 | select SPL_STACK_R if SPL |
a93fbf4a MY |
788 | select SUPPORT_SPL |
789 | imply FIT | |
790 | ||
bfcef28a BG |
791 | config ARCH_MESON |
792 | bool "Amlogic Meson" | |
7325f6cf | 793 | imply DISTRO_DEFAULTS |
6da749d8 | 794 | imply DM_RNG |
bfcef28a BG |
795 | help |
796 | Support for the Meson SoC family developed by Amlogic Inc., | |
797 | targeted at media players and tablet computers. We currently | |
798 | support the S905 (GXBaby) 64-bit SoC. | |
799 | ||
cbd2fba1 RL |
800 | config ARCH_MEDIATEK |
801 | bool "MediaTek SoCs" | |
cbd2fba1 RL |
802 | select DM |
803 | select OF_CONTROL | |
804 | select SPL_DM if SPL | |
805 | select SPL_LIBCOMMON_SUPPORT if SPL | |
806 | select SPL_LIBGENERIC_SUPPORT if SPL | |
807 | select SPL_OF_CONTROL if SPL | |
808 | select SUPPORT_SPL | |
809 | help | |
810 | Support for the MediaTek SoCs family developed by MediaTek Inc. | |
811 | Please refer to doc/README.mediatek for more information. | |
812 | ||
ee54dfea VZ |
813 | config ARCH_LPC32XX |
814 | bool "NXP LPC32xx platform" | |
815 | select CPU_ARM926EJS | |
816 | select DM | |
817 | select DM_GPIO | |
818 | select DM_SERIAL | |
819 | select SPL_DM if SPL | |
820 | select SUPPORT_SPL | |
821 | imply CMD_DM | |
822 | ||
b2b8b9be PF |
823 | config ARCH_IMX8 |
824 | bool "NXP i.MX8 platform" | |
825 | select ARM64 | |
826 | select DM | |
827 | select OF_CONTROL | |
9a273858 | 828 | select ENABLE_ARM_SOC_BOOT0_HOOK |
b2b8b9be | 829 | |
cd357ad1 | 830 | config ARCH_IMX8M |
7a7391fd PF |
831 | bool "NXP i.MX8M platform" |
832 | select ARM64 | |
833 | select DM | |
834 | select SUPPORT_SPL | |
08a00cba | 835 | imply CMD_DM |
7a7391fd | 836 | |
77eb9a90 GB |
837 | config ARCH_IMXRT |
838 | bool "NXP i.MXRT platform" | |
839 | select CPU_V7M | |
840 | select DM | |
841 | select DM_SERIAL | |
842 | select SUPPORT_SPL | |
843 | imply CMD_DM | |
844 | ||
c5343d4e SA |
845 | config ARCH_MX23 |
846 | bool "NXP i.MX23 family" | |
847 | select CPU_ARM926EJS | |
848 | select PL011_SERIAL | |
849 | select SUPPORT_SPL | |
850 | ||
07df697e FE |
851 | config ARCH_MX25 |
852 | bool "NXP MX25" | |
853 | select CPU_ARM926EJS | |
8bbff6a7 | 854 | imply MXC_GPIO |
07df697e | 855 | |
25c5b4e1 SA |
856 | config ARCH_MX28 |
857 | bool "NXP i.MX28 family" | |
858 | select CPU_ARM926EJS | |
859 | select PL011_SERIAL | |
860 | select SUPPORT_SPL | |
861 | ||
3159ec64 ML |
862 | config ARCH_MX31 |
863 | bool "NXP i.MX31 family" | |
864 | select CPU_ARM1136 | |
865 | ||
e90a08da | 866 | config ARCH_MX7ULP |
6e7bdde4 | 867 | bool "NXP MX7ULP" |
acf15001 | 868 | select CPU_V7A |
e90a08da | 869 | select ROM_UNIFIED_SECTIONS |
8bbff6a7 | 870 | imply MXC_GPIO |
44ad4961 | 871 | imply SYS_THUMB_BUILD |
e90a08da | 872 | |
1a8150d4 AA |
873 | config ARCH_MX7 |
874 | bool "Freescale MX7" | |
5ed063d1 MS |
875 | select ARCH_MISC_INIT |
876 | select BOARD_EARLY_INIT_F | |
acf15001 | 877 | select CPU_V7A |
d714a75f | 878 | select SYS_FSL_HAS_SEC if IMX_HAB |
2c2e2c9e | 879 | select SYS_FSL_SEC_COMPAT_4 |
90b80386 | 880 | select SYS_FSL_SEC_LE |
8bbff6a7 | 881 | imply MXC_GPIO |
44ad4961 | 882 | imply SYS_THUMB_BUILD |
1a8150d4 | 883 | |
89ebc821 BB |
884 | config ARCH_MX6 |
885 | bool "Freescale MX6" | |
acf15001 | 886 | select CPU_V7A |
d714a75f | 887 | select SYS_FSL_HAS_SEC if IMX_HAB |
2c2e2c9e | 888 | select SYS_FSL_SEC_COMPAT_4 |
90b80386 | 889 | select SYS_FSL_SEC_LE |
8bbff6a7 | 890 | imply MXC_GPIO |
44ad4961 | 891 | imply SYS_THUMB_BUILD |
89ebc821 | 892 | |
b529993e PT |
893 | if ARCH_MX6 |
894 | config SPL_LDSCRIPT | |
6e7bdde4 | 895 | default "arch/arm/mach-omap2/u-boot-spl.lds" |
b529993e PT |
896 | endif |
897 | ||
424ee3d1 AR |
898 | config ARCH_MX5 |
899 | bool "Freescale MX5" | |
a5d67547 | 900 | select BOARD_EARLY_INIT_F |
5ed063d1 | 901 | select CPU_V7A |
8bbff6a7 | 902 | imply MXC_GPIO |
424ee3d1 | 903 | |
97775d26 MS |
904 | config ARCH_OWL |
905 | bool "Actions Semi OWL SoCs" | |
97775d26 MS |
906 | select DM |
907 | select DM_SERIAL | |
b1a6bb3b | 908 | select OWL_SERIAL |
8b520ac1 AST |
909 | select CLK |
910 | select CLK_OWL | |
97775d26 | 911 | select OF_CONTROL |
36c2f020 | 912 | select SYS_RELOC_GD_ENV_ADDR |
08a00cba | 913 | imply CMD_DM |
97775d26 | 914 | |
32f11829 TT |
915 | config ARCH_QEMU |
916 | bool "QEMU Virtual Platform" | |
70a64a07 | 917 | select ARCH_SUPPORT_TFABOOT |
32f11829 TT |
918 | select DM |
919 | select DM_SERIAL | |
920 | select OF_CONTROL | |
cf2c7784 | 921 | select PL01X_SERIAL |
08a00cba | 922 | imply CMD_DM |
a47c1b5b AT |
923 | imply DM_RTC |
924 | imply RTC_PL031 | |
32f11829 | 925 | |
1cc95f6e | 926 | config ARCH_RMOBILE |
f40b9898 | 927 | bool "Renesas ARM SoCs" |
35295964 | 928 | select BOARD_EARLY_INIT_F if !RZA1 |
1cc95f6e NI |
929 | select DM |
930 | select DM_SERIAL | |
08a00cba | 931 | imply CMD_DM |
91d27a17 | 932 | imply FAT_WRITE |
3a649407 | 933 | imply SYS_THUMB_BUILD |
00e4b57e | 934 | imply ARCH_MISC_INIT if DISPLAY_CPUINFO |
dd84058d | 935 | |
9702ec00 EP |
936 | config TARGET_S32V234EVB |
937 | bool "Support s32v234evb" | |
938 | select ARM64 | |
c01e4a1a | 939 | select SYS_FSL_ERRATUM_ESDHC111 |
9702ec00 | 940 | |
08592136 MK |
941 | config ARCH_SNAPDRAGON |
942 | bool "Qualcomm Snapdragon SoCs" | |
943 | select ARM64 | |
944 | select DM | |
945 | select DM_GPIO | |
946 | select DM_SERIAL | |
5ed063d1 | 947 | select MSM_SMEM |
08592136 MK |
948 | select OF_CONTROL |
949 | select OF_SEPARATE | |
654dd4a8 | 950 | select SMEM |
5ed063d1 | 951 | select SPMI |
08a00cba | 952 | imply CMD_DM |
08592136 | 953 | |
7865f4b0 MY |
954 | config ARCH_SOCFPGA |
955 | bool "Altera SOCFPGA family" | |
48befc00 | 956 | select ARCH_EARLY_INIT_R |
d6a61da4 | 957 | select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 |
a76b711d | 958 | select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX |
a684729a | 959 | select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 |
1d9aa3e5 | 960 | select DM |
73172753 | 961 | select DM_SERIAL |
a684729a | 962 | select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 |
48befc00 | 963 | select OF_CONTROL |
00057eea | 964 | select SPL_DM_RESET if DM_RESET |
5ed063d1 | 965 | select SPL_DM_SERIAL |
48befc00 | 966 | select SPL_LIBCOMMON_SUPPORT |
48befc00 | 967 | select SPL_LIBGENERIC_SUPPORT |
48befc00 MV |
968 | select SPL_NAND_SUPPORT if SPL_NAND_DENALI |
969 | select SPL_OF_CONTROL | |
a76b711d | 970 | select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX |
48befc00 | 971 | select SPL_SERIAL_SUPPORT |
ef72ba0b | 972 | select SPL_SYSRESET |
48befc00 MV |
973 | select SPL_WATCHDOG_SUPPORT |
974 | select SUPPORT_SPL | |
73172753 | 975 | select SYS_NS16550 |
a684729a | 976 | select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 |
ef72ba0b SG |
977 | select SYSRESET |
978 | select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 | |
63b312d8 | 979 | select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10 |
08a00cba | 980 | imply CMD_DM |
d56b4b19 | 981 | imply CMD_MTDPARTS |
221a949e | 982 | imply CRC32_VERIFY |
fef4a545 SG |
983 | imply DM_SPI |
984 | imply DM_SPI_FLASH | |
91d27a17 | 985 | imply FAT_WRITE |
aef44283 SG |
986 | imply SPL |
987 | imply SPL_DM | |
a9024dc1 SG |
988 | imply SPL_LIBDISK_SUPPORT |
989 | imply SPL_MMC_SUPPORT | |
fef4a545 | 990 | imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION |
f48db4ed | 991 | imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE |
a9024dc1 SG |
992 | imply SPL_SPI_FLASH_SUPPORT |
993 | imply SPL_SPI_SUPPORT | |
aaa64803 | 994 | imply L2X0_CACHE |
dd84058d | 995 | |
2c7e3b90 IC |
996 | config ARCH_SUNXI |
997 | bool "Support sunxi (Allwinner) SoCs" | |
d6a0c78a | 998 | select BINMAN |
88bb800d | 999 | select CMD_GPIO |
0878a8a7 | 1000 | select CMD_MMC if MMC |
2997ee50 | 1001 | select CMD_USB if DISTRO_DEFAULTS |
e236ff0a | 1002 | select CLK |
b6006baf | 1003 | select DM |
45368827 | 1004 | select DM_ETH |
211d57a4 HG |
1005 | select DM_GPIO |
1006 | select DM_KEYBOARD | |
bb3362b0 JT |
1007 | select DM_MMC if MMC |
1008 | select DM_SCSI if SCSI | |
45368827 | 1009 | select DM_SERIAL |
2997ee50 | 1010 | select DM_USB if DISTRO_DEFAULTS |
d75111a7 | 1011 | select OF_BOARD_SETUP |
b6006baf HG |
1012 | select OF_CONTROL |
1013 | select OF_SEPARATE | |
6f6b7cfa | 1014 | select SPECIFY_CONSOLE_INDEX |
ab43de80 TR |
1015 | select SPL_STACK_R if SPL |
1016 | select SPL_SYS_MALLOC_SIMPLE if SPL | |
3a649407 | 1017 | select SPL_SYS_THUMB_BUILD if !ARM64 |
10cfbaab | 1018 | select SUNXI_GPIO |
5ed063d1 | 1019 | select SYS_NS16550 |
ce2e44d8 | 1020 | select SYS_THUMB_BUILD if !ARM64 |
2997ee50 | 1021 | select USB if DISTRO_DEFAULTS |
2997ee50 | 1022 | select USB_KEYBOARD if DISTRO_DEFAULTS |
5ed063d1 | 1023 | select USB_STORAGE if DISTRO_DEFAULTS |
27084c03 | 1024 | select SPL_USE_TINY_PRINTF |
48313fe5 AP |
1025 | select USE_PREBOOT |
1026 | select SYS_RELOC_GD_ENV_ADDR | |
08a00cba | 1027 | imply CMD_DM |
a12fb0e3 | 1028 | imply CMD_GPT |
88718be3 | 1029 | imply CMD_UBI if MTD_RAW_NAND |
7325f6cf | 1030 | imply DISTRO_DEFAULTS |
91d27a17 | 1031 | imply FAT_WRITE |
2f13cf35 | 1032 | imply FIT |
eff264d7 | 1033 | imply OF_LIBFDT_OVERLAY |
af83a604 MY |
1034 | imply PRE_CONSOLE_BUFFER |
1035 | imply SPL_GPIO_SUPPORT | |
1036 | imply SPL_LIBCOMMON_SUPPORT | |
af83a604 | 1037 | imply SPL_LIBGENERIC_SUPPORT |
4aa2ba3a | 1038 | imply SPL_MMC_SUPPORT if MMC |
af83a604 MY |
1039 | imply SPL_POWER_SUPPORT |
1040 | imply SPL_SERIAL_SUPPORT | |
654b02b1 | 1041 | imply USB_GADGET |
8ebe4f42 | 1042 | |
689088f9 SG |
1043 | config ARCH_U8500 |
1044 | bool "ST-Ericsson U8500 Series" | |
1045 | select CPU_V7A | |
1046 | select DM | |
1047 | select DM_GPIO | |
1048 | select DM_MMC if MMC | |
1049 | select DM_SERIAL | |
1050 | select DM_USB if USB | |
1051 | select OF_CONTROL | |
1052 | select SYSRESET | |
1053 | select TIMER | |
1054 | imply ARM_PL180_MMCI | |
1055 | imply DM_RTC | |
1056 | imply NOMADIK_MTU_TIMER | |
1057 | imply PL01X_SERIAL | |
1058 | imply RTC_PL031 | |
1059 | imply SYSRESET_SYSCON | |
1060 | ||
ec48b6c9 MS |
1061 | config ARCH_VERSAL |
1062 | bool "Support Xilinx Versal Platform" | |
1063 | select ARM64 | |
1064 | select CLK | |
1065 | select DM | |
fa797157 MS |
1066 | select DM_ETH if NET |
1067 | select DM_MMC if MMC | |
ec48b6c9 MS |
1068 | select DM_SERIAL |
1069 | select OF_CONTROL | |
bfd092f9 | 1070 | imply BOARD_LATE_INIT |
ec48b6c9 | 1071 | |
7966b437 SA |
1072 | config ARCH_VF610 |
1073 | bool "Freescale Vybrid" | |
acf15001 | 1074 | select CPU_V7A |
c01e4a1a | 1075 | select SYS_FSL_ERRATUM_ESDHC111 |
d56b4b19 | 1076 | imply CMD_MTDPARTS |
88718be3 | 1077 | imply MTD_RAW_NAND |
e7b860fa | 1078 | |
5ca269a4 | 1079 | config ARCH_ZYNQ |
b8d4497f | 1080 | bool "Xilinx Zynq based platform" |
5ed063d1 MS |
1081 | select CLK |
1082 | select CLK_ZYNQ | |
acf15001 | 1083 | select CPU_V7A |
8981f05c | 1084 | select DM |
c4a142f4 | 1085 | select DM_ETH if NET |
c4a142f4 | 1086 | select DM_MMC if MMC |
42800ffa | 1087 | select DM_SERIAL |
5ed063d1 | 1088 | select DM_SPI |
9f7a4502 | 1089 | select DM_SPI_FLASH |
dec49e86 | 1090 | select DM_USB if USB |
5ed063d1 | 1091 | select OF_CONTROL |
f1b1f770 | 1092 | select SPI |
5ed063d1 MS |
1093 | select SPL_BOARD_INIT if SPL |
1094 | select SPL_CLK if SPL | |
1095 | select SPL_DM if SPL | |
1096 | select SPL_OF_CONTROL if SPL | |
1097 | select SPL_SEPARATE_BSS if SPL | |
1098 | select SUPPORT_SPL | |
1099 | imply ARCH_EARLY_INIT_R | |
8eb55e19 | 1100 | imply BOARD_LATE_INIT |
d315628e | 1101 | imply CMD_CLK |
08a00cba | 1102 | imply CMD_DM |
72c3033f | 1103 | imply CMD_SPL |
5ed063d1 | 1104 | imply FAT_WRITE |
dd84058d | 1105 | |
1d6c54ec MS |
1106 | config ARCH_ZYNQMP_R5 |
1107 | bool "Xilinx ZynqMP R5 based platform" | |
5ed063d1 | 1108 | select CLK |
1d6c54ec | 1109 | select CPU_V7R |
1d6c54ec | 1110 | select DM |
6f96fb50 MS |
1111 | select DM_ETH if NET |
1112 | select DM_MMC if MMC | |
1d6c54ec | 1113 | select DM_SERIAL |
5ed063d1 | 1114 | select OF_CONTROL |
08a00cba | 1115 | imply CMD_DM |
687ab545 | 1116 | imply DM_USB_GADGET |
1d6c54ec | 1117 | |
0b54a9dd | 1118 | config ARCH_ZYNQMP |
b8d4497f | 1119 | bool "Xilinx ZynqMP based platform" |
84c7204b | 1120 | select ARM64 |
5ed063d1 | 1121 | select CLK |
c2490bf5 | 1122 | select DM |
fb693108 | 1123 | select DM_ETH if NET |
1327d167 | 1124 | select DM_MAILBOX |
fb693108 | 1125 | select DM_MMC if MMC |
c2490bf5 | 1126 | select DM_SERIAL |
088f83ee MS |
1127 | select DM_SPI if SPI |
1128 | select DM_SPI_FLASH if DM_SPI | |
5ed063d1 | 1129 | select DM_USB if USB |
325a22dc | 1130 | select FIRMWARE |
5ed063d1 | 1131 | select OF_CONTROL |
0680f1b1 | 1132 | select SPL_BOARD_INIT if SPL |
2f03968e | 1133 | select SPL_CLK if SPL |
325a22dc IE |
1134 | select SPL_DM_MAILBOX if SPL |
1135 | select SPL_FIRMWARE if SPL | |
850e7795 | 1136 | select SPL_SEPARATE_BSS if SPL |
5ed063d1 | 1137 | select SUPPORT_SPL |
1327d167 | 1138 | select ZYNQMP_IPI |
8eb55e19 | 1139 | imply BOARD_LATE_INIT |
08a00cba | 1140 | imply CMD_DM |
91d27a17 | 1141 | imply FAT_WRITE |
22270ca0 | 1142 | imply MP |
687ab545 | 1143 | imply DM_USB_GADGET |
84c7204b | 1144 | |
18138ab2 | 1145 | config ARCH_TEGRA |
ddd960e6 | 1146 | bool "NVIDIA Tegra" |
7325f6cf | 1147 | imply DISTRO_DEFAULTS |
91d27a17 | 1148 | imply FAT_WRITE |
dd84058d | 1149 | |
f91afc4d | 1150 | config TARGET_VEXPRESS64_AEMV8A |
dd84058d | 1151 | bool "Support vexpress_aemv8a" |
016a954e | 1152 | select ARM64 |
cf2c7784 | 1153 | select PL01X_SERIAL |
dd84058d | 1154 | |
f91afc4d LW |
1155 | config TARGET_VEXPRESS64_BASE_FVP |
1156 | bool "Support Versatile Express ARMv8a FVP BASE model" | |
1157 | select ARM64 | |
cf2c7784 | 1158 | select PL01X_SERIAL |
5ed063d1 | 1159 | select SEMIHOSTING |
f91afc4d | 1160 | |
ffc10373 LW |
1161 | config TARGET_VEXPRESS64_JUNO |
1162 | bool "Support Versatile Express Juno Development Platform" | |
1163 | select ARM64 | |
cf2c7784 | 1164 | select PL01X_SERIAL |
b3270e91 AP |
1165 | select DM |
1166 | select OF_CONTROL | |
1167 | select OF_BOARD | |
1168 | select CLK | |
1169 | select DM_SERIAL | |
be0d0969 AP |
1170 | select ARM_PSCI_FW |
1171 | select PSCI_RESET | |
56e403d9 AP |
1172 | select DM |
1173 | select BLK | |
1174 | select USB | |
1175 | select DM_USB | |
ffc10373 | 1176 | |
44937214 PK |
1177 | config TARGET_LS2080A_EMU |
1178 | bool "Support ls2080a_emu" | |
fb2bf8c2 | 1179 | select ARCH_LS2080A |
016a954e | 1180 | select ARM64 |
23b5877c | 1181 | select ARMV8_MULTIENTRY |
32413125 | 1182 | select FSL_DDR_SYNC_REFRESH |
44937214 | 1183 | help |
e852b30b RD |
1184 | Support for Freescale LS2080A_EMU platform. |
1185 | The LS2080A Development System (EMULATOR) is a pre-silicon | |
44937214 PK |
1186 | development platform that supports the QorIQ LS2080A |
1187 | Layerscape Architecture processor. | |
dd84058d | 1188 | |
44937214 PK |
1189 | config TARGET_LS2080A_SIMU |
1190 | bool "Support ls2080a_simu" | |
fb2bf8c2 | 1191 | select ARCH_LS2080A |
016a954e | 1192 | select ARM64 |
23b5877c | 1193 | select ARMV8_MULTIENTRY |
acf40f50 | 1194 | select BOARD_LATE_INIT |
44937214 | 1195 | help |
e852b30b | 1196 | Support for Freescale LS2080A_SIMU platform. |
44937214 PK |
1197 | The LS2080A Development System (QDS) is a pre silicon |
1198 | development platform that supports the QorIQ LS2080A | |
1199 | Layerscape Architecture processor. | |
dd84058d | 1200 | |
7769776a AK |
1201 | config TARGET_LS1088AQDS |
1202 | bool "Support ls1088aqds" | |
1203 | select ARCH_LS1088A | |
1204 | select ARM64 | |
1205 | select ARMV8_MULTIENTRY | |
6324d506 | 1206 | select ARCH_SUPPORT_TFABOOT |
7769776a | 1207 | select BOARD_LATE_INIT |
91fded62 | 1208 | select SUPPORT_SPL |
32413125 | 1209 | select FSL_DDR_INTERACTIVE if !SD_BOOT |
7769776a | 1210 | help |
e852b30b | 1211 | Support for NXP LS1088AQDS platform. |
7769776a AK |
1212 | The LS1088A Development System (QDS) is a high-performance |
1213 | development platform that supports the QorIQ LS1088A | |
1214 | Layerscape Architecture processor. | |
1215 | ||
44937214 PK |
1216 | config TARGET_LS2080AQDS |
1217 | bool "Support ls2080aqds" | |
fb2bf8c2 | 1218 | select ARCH_LS2080A |
7288c2c2 YS |
1219 | select ARM64 |
1220 | select ARMV8_MULTIENTRY | |
6324d506 | 1221 | select ARCH_SUPPORT_TFABOOT |
e5ec4815 | 1222 | select BOARD_LATE_INIT |
b2d5ac59 | 1223 | select SUPPORT_SPL |
fedb428c | 1224 | imply SCSI |
9fd95ef0 | 1225 | imply SCSI_AHCI |
32413125 RB |
1226 | select FSL_DDR_BIST |
1227 | select FSL_DDR_INTERACTIVE if !SPL | |
7288c2c2 | 1228 | help |
e852b30b | 1229 | Support for Freescale LS2080AQDS platform. |
44937214 PK |
1230 | The LS2080A Development System (QDS) is a high-performance |
1231 | development platform that supports the QorIQ LS2080A | |
7288c2c2 YS |
1232 | Layerscape Architecture processor. |
1233 | ||
44937214 PK |
1234 | config TARGET_LS2080ARDB |
1235 | bool "Support ls2080ardb" | |
fb2bf8c2 | 1236 | select ARCH_LS2080A |
e2b65ea9 YS |
1237 | select ARM64 |
1238 | select ARMV8_MULTIENTRY | |
6324d506 | 1239 | select ARCH_SUPPORT_TFABOOT |
e5ec4815 | 1240 | select BOARD_LATE_INIT |
32eda7cc | 1241 | select SUPPORT_SPL |
32413125 RB |
1242 | select FSL_DDR_BIST |
1243 | select FSL_DDR_INTERACTIVE if !SPL | |
fedb428c | 1244 | imply SCSI |
9fd95ef0 | 1245 | imply SCSI_AHCI |
e2b65ea9 | 1246 | help |
44937214 PK |
1247 | Support for Freescale LS2080ARDB platform. |
1248 | The LS2080A Reference design board (RDB) is a high-performance | |
1249 | development platform that supports the QorIQ LS2080A | |
e2b65ea9 YS |
1250 | Layerscape Architecture processor. |
1251 | ||
3049a583 PJ |
1252 | config TARGET_LS2081ARDB |
1253 | bool "Support ls2081ardb" | |
1254 | select ARCH_LS2080A | |
1255 | select ARM64 | |
1256 | select ARMV8_MULTIENTRY | |
1257 | select BOARD_LATE_INIT | |
1258 | select SUPPORT_SPL | |
3049a583 PJ |
1259 | help |
1260 | Support for Freescale LS2081ARDB platform. | |
1261 | The LS2081A Reference design board (RDB) is a high-performance | |
1262 | development platform that supports the QorIQ LS2081A/LS2041A | |
1263 | Layerscape Architecture processor. | |
1264 | ||
58c3e620 PJ |
1265 | config TARGET_LX2160ARDB |
1266 | bool "Support lx2160ardb" | |
1267 | select ARCH_LX2160A | |
58c3e620 PJ |
1268 | select ARM64 |
1269 | select ARMV8_MULTIENTRY | |
6324d506 | 1270 | select ARCH_SUPPORT_TFABOOT |
58c3e620 PJ |
1271 | select BOARD_LATE_INIT |
1272 | help | |
1273 | Support for NXP LX2160ARDB platform. | |
1274 | The lx2160ardb (LX2160A Reference design board (RDB) | |
1275 | is a high-performance development platform that supports the | |
1276 | QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. | |
1277 | ||
1eba723c PB |
1278 | config TARGET_LX2160AQDS |
1279 | bool "Support lx2160aqds" | |
1280 | select ARCH_LX2160A | |
1eba723c PB |
1281 | select ARM64 |
1282 | select ARMV8_MULTIENTRY | |
6324d506 | 1283 | select ARCH_SUPPORT_TFABOOT |
1eba723c PB |
1284 | select BOARD_LATE_INIT |
1285 | help | |
1286 | Support for NXP LX2160AQDS platform. | |
1287 | The lx2160aqds (LX2160A QorIQ Development System (QDS) | |
1288 | is a high-performance development platform that supports the | |
1289 | QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. | |
1290 | ||
11ac2363 PG |
1291 | config TARGET_HIKEY |
1292 | bool "Support HiKey 96boards Consumer Edition Platform" | |
1293 | select ARM64 | |
efd7b60a PG |
1294 | select DM |
1295 | select DM_GPIO | |
9c71bcdc | 1296 | select DM_SERIAL |
cd593ed6 | 1297 | select OF_CONTROL |
cf2c7784 | 1298 | select PL01X_SERIAL |
6f6b7cfa | 1299 | select SPECIFY_CONSOLE_INDEX |
08a00cba | 1300 | imply CMD_DM |
11ac2363 PG |
1301 | help |
1302 | Support for HiKey 96boards platform. It features a HI6220 | |
1303 | SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. | |
1304 | ||
c62c7ef7 MS |
1305 | config TARGET_HIKEY960 |
1306 | bool "Support HiKey960 96boards Consumer Edition Platform" | |
1307 | select ARM64 | |
1308 | select DM | |
1309 | select DM_SERIAL | |
1310 | select OF_CONTROL | |
1311 | select PL01X_SERIAL | |
1312 | imply CMD_DM | |
1313 | help | |
1314 | Support for HiKey960 96boards platform. It features a HI3660 | |
1315 | SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM. | |
1316 | ||
d754254f JRO |
1317 | config TARGET_POPLAR |
1318 | bool "Support Poplar 96boards Enterprise Edition Platform" | |
1319 | select ARM64 | |
1320 | select DM | |
d754254f JRO |
1321 | select DM_SERIAL |
1322 | select DM_USB | |
5ed063d1 | 1323 | select OF_CONTROL |
cf2c7784 | 1324 | select PL01X_SERIAL |
08a00cba | 1325 | imply CMD_DM |
d754254f JRO |
1326 | help |
1327 | Support for Poplar 96boards EE platform. It features a HI3798cv200 | |
1328 | SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU | |
1329 | making it capable of running any commercial set-top solution based on | |
1330 | Linux or Android. | |
1331 | ||
9d044fcb PK |
1332 | config TARGET_LS1012AQDS |
1333 | bool "Support ls1012aqds" | |
9533acf3 | 1334 | select ARCH_LS1012A |
9d044fcb | 1335 | select ARM64 |
6324d506 | 1336 | select ARCH_SUPPORT_TFABOOT |
e5ec4815 | 1337 | select BOARD_LATE_INIT |
9d044fcb PK |
1338 | help |
1339 | Support for Freescale LS1012AQDS platform. | |
1340 | The LS1012A Development System (QDS) is a high-performance | |
1341 | development platform that supports the QorIQ LS1012A | |
1342 | Layerscape Architecture processor. | |
1343 | ||
3b6e3898 PK |
1344 | config TARGET_LS1012ARDB |
1345 | bool "Support ls1012ardb" | |
9533acf3 | 1346 | select ARCH_LS1012A |
3b6e3898 | 1347 | select ARM64 |
6324d506 | 1348 | select ARCH_SUPPORT_TFABOOT |
e5ec4815 | 1349 | select BOARD_LATE_INIT |
fedb428c | 1350 | imply SCSI |
9fd95ef0 | 1351 | imply SCSI_AHCI |
3b6e3898 PK |
1352 | help |
1353 | Support for Freescale LS1012ARDB platform. | |
1354 | The LS1012A Reference design board (RDB) is a high-performance | |
1355 | development platform that supports the QorIQ LS1012A | |
1356 | Layerscape Architecture processor. | |
1357 | ||
b0ce187b BU |
1358 | config TARGET_LS1012A2G5RDB |
1359 | bool "Support ls1012a2g5rdb" | |
1360 | select ARCH_LS1012A | |
1361 | select ARM64 | |
6324d506 | 1362 | select ARCH_SUPPORT_TFABOOT |
b0ce187b BU |
1363 | select BOARD_LATE_INIT |
1364 | imply SCSI | |
1365 | help | |
1366 | Support for Freescale LS1012A2G5RDB platform. | |
1367 | The LS1012A 2G5 Reference design board (RDB) is a high-performance | |
1368 | development platform that supports the QorIQ LS1012A | |
1369 | Layerscape Architecture processor. | |
1370 | ||
9629ccdd BU |
1371 | config TARGET_LS1012AFRWY |
1372 | bool "Support ls1012afrwy" | |
1373 | select ARCH_LS1012A | |
1374 | select ARM64 | |
6324d506 | 1375 | select ARCH_SUPPORT_TFABOOT |
5ed063d1 | 1376 | select BOARD_LATE_INIT |
9629ccdd BU |
1377 | imply SCSI |
1378 | imply SCSI_AHCI | |
1379 | help | |
1380 | Support for Freescale LS1012AFRWY platform. | |
1381 | The LS1012A FRWY board (FRWY) is a high-performance | |
1382 | development platform that supports the QorIQ LS1012A | |
1383 | Layerscape Architecture processor. | |
1384 | ||
ff78aa2b PK |
1385 | config TARGET_LS1012AFRDM |
1386 | bool "Support ls1012afrdm" | |
9533acf3 | 1387 | select ARCH_LS1012A |
ff78aa2b | 1388 | select ARM64 |
6324d506 | 1389 | select ARCH_SUPPORT_TFABOOT |
ff78aa2b PK |
1390 | help |
1391 | Support for Freescale LS1012AFRDM platform. | |
1392 | The LS1012A Freedom board (FRDM) is a high-performance | |
1393 | development platform that supports the QorIQ LS1012A | |
1394 | Layerscape Architecture processor. | |
1395 | ||
f278a217 YT |
1396 | config TARGET_LS1028AQDS |
1397 | bool "Support ls1028aqds" | |
1398 | select ARCH_LS1028A | |
1399 | select ARM64 | |
1400 | select ARMV8_MULTIENTRY | |
6324d506 | 1401 | select ARCH_SUPPORT_TFABOOT |
acf40f50 | 1402 | select BOARD_LATE_INIT |
f278a217 YT |
1403 | help |
1404 | Support for Freescale LS1028AQDS platform | |
1405 | The LS1028A Development System (QDS) is a high-performance | |
1406 | development platform that supports the QorIQ LS1028A | |
1407 | Layerscape Architecture processor. | |
1408 | ||
353f36d9 YT |
1409 | config TARGET_LS1028ARDB |
1410 | bool "Support ls1028ardb" | |
1411 | select ARCH_LS1028A | |
1412 | select ARM64 | |
1413 | select ARMV8_MULTIENTRY | |
6324d506 | 1414 | select ARCH_SUPPORT_TFABOOT |
c40ebf7e | 1415 | select BOARD_LATE_INIT |
353f36d9 YT |
1416 | help |
1417 | Support for Freescale LS1028ARDB platform | |
1418 | The LS1028A Development System (RDB) is a high-performance | |
1419 | development platform that supports the QorIQ LS1028A | |
1420 | Layerscape Architecture processor. | |
1421 | ||
e84a324b AK |
1422 | config TARGET_LS1088ARDB |
1423 | bool "Support ls1088ardb" | |
1424 | select ARCH_LS1088A | |
1425 | select ARM64 | |
1426 | select ARMV8_MULTIENTRY | |
6324d506 | 1427 | select ARCH_SUPPORT_TFABOOT |
e84a324b | 1428 | select BOARD_LATE_INIT |
099f4093 | 1429 | select SUPPORT_SPL |
32413125 | 1430 | select FSL_DDR_INTERACTIVE if !SD_BOOT |
e84a324b AK |
1431 | help |
1432 | Support for NXP LS1088ARDB platform. | |
1433 | The LS1088A Reference design board (RDB) is a high-performance | |
1434 | development platform that supports the QorIQ LS1088A | |
1435 | Layerscape Architecture processor. | |
1436 | ||
550e3dc0 | 1437 | config TARGET_LS1021AQDS |
0de15707 | 1438 | bool "Support ls1021aqds" |
5ed063d1 MS |
1439 | select ARCH_LS1021A |
1440 | select ARCH_SUPPORT_PSCI | |
1441 | select BOARD_EARLY_INIT_F | |
e5ec4815 | 1442 | select BOARD_LATE_INIT |
acf15001 | 1443 | select CPU_V7A |
adee1d4c HZ |
1444 | select CPU_V7_HAS_NONSEC |
1445 | select CPU_V7_HAS_VIRT | |
5e8bd7e1 | 1446 | select LS1_DEEP_SLEEP |
5ed063d1 | 1447 | select SUPPORT_SPL |
d26e34c4 | 1448 | select SYS_FSL_DDR |
32413125 | 1449 | select FSL_DDR_INTERACTIVE |
fedb428c | 1450 | imply SCSI |
217f92bb | 1451 | |
c8a7d9da | 1452 | config TARGET_LS1021ATWR |
0de15707 | 1453 | bool "Support ls1021atwr" |
5ed063d1 MS |
1454 | select ARCH_LS1021A |
1455 | select ARCH_SUPPORT_PSCI | |
1456 | select BOARD_EARLY_INIT_F | |
e5ec4815 | 1457 | select BOARD_LATE_INIT |
acf15001 | 1458 | select CPU_V7A |
adee1d4c HZ |
1459 | select CPU_V7_HAS_NONSEC |
1460 | select CPU_V7_HAS_VIRT | |
5e8bd7e1 | 1461 | select LS1_DEEP_SLEEP |
5ed063d1 | 1462 | select SUPPORT_SPL |
fedb428c | 1463 | imply SCSI |
c8a7d9da | 1464 | |
87821220 JW |
1465 | config TARGET_LS1021ATSN |
1466 | bool "Support ls1021atsn" | |
1467 | select ARCH_LS1021A | |
1468 | select ARCH_SUPPORT_PSCI | |
1469 | select BOARD_EARLY_INIT_F | |
1470 | select BOARD_LATE_INIT | |
1471 | select CPU_V7A | |
1472 | select CPU_V7_HAS_NONSEC | |
1473 | select CPU_V7_HAS_VIRT | |
1474 | select LS1_DEEP_SLEEP | |
1475 | select SUPPORT_SPL | |
1476 | imply SCSI | |
1477 | ||
20c700f8 FL |
1478 | config TARGET_LS1021AIOT |
1479 | bool "Support ls1021aiot" | |
5ed063d1 MS |
1480 | select ARCH_LS1021A |
1481 | select ARCH_SUPPORT_PSCI | |
e5ec4815 | 1482 | select BOARD_LATE_INIT |
acf15001 | 1483 | select CPU_V7A |
20c700f8 FL |
1484 | select CPU_V7_HAS_NONSEC |
1485 | select CPU_V7_HAS_VIRT | |
1486 | select SUPPORT_SPL | |
fedb428c | 1487 | imply SCSI |
20c700f8 FL |
1488 | help |
1489 | Support for Freescale LS1021AIOT platform. | |
1490 | The LS1021A Freescale board (IOT) is a high-performance | |
1491 | development platform that supports the QorIQ LS1021A | |
1492 | Layerscape Architecture processor. | |
1493 | ||
02b5d2ed SX |
1494 | config TARGET_LS1043AQDS |
1495 | bool "Support ls1043aqds" | |
0a37cf8f | 1496 | select ARCH_LS1043A |
02b5d2ed SX |
1497 | select ARM64 |
1498 | select ARMV8_MULTIENTRY | |
6324d506 | 1499 | select ARCH_SUPPORT_TFABOOT |
5ed063d1 | 1500 | select BOARD_EARLY_INIT_F |
e5ec4815 | 1501 | select BOARD_LATE_INIT |
02b5d2ed | 1502 | select SUPPORT_SPL |
32413125 | 1503 | select FSL_DDR_INTERACTIVE if !SPL |
fedb428c | 1504 | imply SCSI |
f11e492a | 1505 | imply SCSI_AHCI |
02b5d2ed SX |
1506 | help |
1507 | Support for Freescale LS1043AQDS platform. | |
1508 | ||
f3a8e2b7 MH |
1509 | config TARGET_LS1043ARDB |
1510 | bool "Support ls1043ardb" | |
0a37cf8f | 1511 | select ARCH_LS1043A |
f3a8e2b7 | 1512 | select ARM64 |
831c068f | 1513 | select ARMV8_MULTIENTRY |
6324d506 | 1514 | select ARCH_SUPPORT_TFABOOT |
5ed063d1 | 1515 | select BOARD_EARLY_INIT_F |
e5ec4815 | 1516 | select BOARD_LATE_INIT |
3ad44729 | 1517 | select SUPPORT_SPL |
f3a8e2b7 MH |
1518 | help |
1519 | Support for Freescale LS1043ARDB platform. | |
1520 | ||
126fe70d SX |
1521 | config TARGET_LS1046AQDS |
1522 | bool "Support ls1046aqds" | |
da28e58a | 1523 | select ARCH_LS1046A |
126fe70d SX |
1524 | select ARM64 |
1525 | select ARMV8_MULTIENTRY | |
6324d506 | 1526 | select ARCH_SUPPORT_TFABOOT |
5ed063d1 | 1527 | select BOARD_EARLY_INIT_F |
e5ec4815 | 1528 | select BOARD_LATE_INIT |
126fe70d | 1529 | select DM_SPI_FLASH if DM_SPI |
5ed063d1 | 1530 | select SUPPORT_SPL |
32413125 RB |
1531 | select FSL_DDR_BIST if !SPL |
1532 | select FSL_DDR_INTERACTIVE if !SPL | |
1533 | select FSL_DDR_INTERACTIVE if !SPL | |
fedb428c | 1534 | imply SCSI |
126fe70d SX |
1535 | help |
1536 | Support for Freescale LS1046AQDS platform. | |
1537 | The LS1046A Development System (QDS) is a high-performance | |
1538 | development platform that supports the QorIQ LS1046A | |
1539 | Layerscape Architecture processor. | |
1540 | ||
dd02936f MH |
1541 | config TARGET_LS1046ARDB |
1542 | bool "Support ls1046ardb" | |
da28e58a | 1543 | select ARCH_LS1046A |
dd02936f MH |
1544 | select ARM64 |
1545 | select ARMV8_MULTIENTRY | |
6324d506 | 1546 | select ARCH_SUPPORT_TFABOOT |
5ed063d1 | 1547 | select BOARD_EARLY_INIT_F |
e5ec4815 | 1548 | select BOARD_LATE_INIT |
dd02936f | 1549 | select DM_SPI_FLASH if DM_SPI |
dccef2ec | 1550 | select POWER_MC34VR500 |
5ed063d1 | 1551 | select SUPPORT_SPL |
32413125 RB |
1552 | select FSL_DDR_BIST |
1553 | select FSL_DDR_INTERACTIVE if !SPL | |
fedb428c | 1554 | imply SCSI |
dd02936f MH |
1555 | help |
1556 | Support for Freescale LS1046ARDB platform. | |
1557 | The LS1046A Reference Design Board (RDB) is a high-performance | |
1558 | development platform that supports the QorIQ LS1046A | |
1559 | Layerscape Architecture processor. | |
1560 | ||
d90c7ac7 VS |
1561 | config TARGET_LS1046AFRWY |
1562 | bool "Support ls1046afrwy" | |
1563 | select ARCH_LS1046A | |
1564 | select ARM64 | |
1565 | select ARMV8_MULTIENTRY | |
6324d506 | 1566 | select ARCH_SUPPORT_TFABOOT |
d90c7ac7 VS |
1567 | select BOARD_EARLY_INIT_F |
1568 | select BOARD_LATE_INIT | |
1569 | select DM_SPI_FLASH if DM_SPI | |
1570 | imply SCSI | |
1571 | help | |
1572 | Support for Freescale LS1046AFRWY platform. | |
1573 | The LS1046A Freeway Board (FRWY) is a high-performance | |
1574 | development platform that supports the QorIQ LS1046A | |
1575 | Layerscape Architecture processor. | |
dd84058d | 1576 | |
dd84058d MY |
1577 | config TARGET_COLIBRI_PXA270 |
1578 | bool "Support colibri_pxa270" | |
2e07c249 | 1579 | select CPU_PXA |
dd84058d | 1580 | |
66cba041 | 1581 | config ARCH_UNIPHIER |
b6ef3a3f | 1582 | bool "Socionext UniPhier SoCs" |
e5ec4815 | 1583 | select BOARD_LATE_INIT |
4e819950 | 1584 | select DM |
1517126f | 1585 | select DM_ETH |
b800cbde | 1586 | select DM_GPIO |
4e819950 | 1587 | select DM_I2C |
4aceb3f8 | 1588 | select DM_MMC |
407b01b3 | 1589 | select DM_MTD |
4fb96c48 | 1590 | select DM_RESET |
b5550e49 | 1591 | select DM_SERIAL |
47a79f65 | 1592 | select DM_USB |
65fce763 | 1593 | select OF_BOARD_SETUP |
b5550e49 MY |
1594 | select OF_CONTROL |
1595 | select OF_LIBFDT | |
27350c92 | 1596 | select PINCTRL |
0680f1b1 | 1597 | select SPL_BOARD_INIT if SPL |
561ca649 MY |
1598 | select SPL_DM if SPL |
1599 | select SPL_LIBCOMMON_SUPPORT if SPL | |
1600 | select SPL_LIBGENERIC_SUPPORT if SPL | |
1601 | select SPL_OF_CONTROL if SPL | |
1602 | select SPL_PINCTRL if SPL | |
b5550e49 | 1603 | select SUPPORT_SPL |
08a00cba | 1604 | imply CMD_DM |
7ef5b1e7 | 1605 | imply DISTRO_DEFAULTS |
91d27a17 | 1606 | imply FAT_WRITE |
b6ef3a3f MY |
1607 | help |
1608 | Support for UniPhier SoC family developed by Socionext Inc. | |
1609 | (formerly, System LSI Business Division of Panasonic Corporation) | |
66cba041 | 1610 | |
71f6354b | 1611 | config ARCH_STM32 |
2514c2d0 | 1612 | bool "Support STMicroelectronics STM32 MCU with cortex M" |
ed09a554 | 1613 | select CPU_V7M |
66562414 KL |
1614 | select DM |
1615 | select DM_SERIAL | |
08a00cba | 1616 | imply CMD_DM |
ed09a554 | 1617 | |
94e9a4ef PC |
1618 | config ARCH_STI |
1619 | bool "Support STMicrolectronics SoCs" | |
5ed063d1 | 1620 | select BLK |
acf15001 | 1621 | select CPU_V7A |
214a17e6 | 1622 | select DM |
eee20f81 | 1623 | select DM_MMC |
584861ff | 1624 | select DM_RESET |
5ed063d1 | 1625 | select DM_SERIAL |
08a00cba | 1626 | imply CMD_DM |
94e9a4ef PC |
1627 | help |
1628 | Support for STMicroelectronics STiH407/10 SoC family. | |
1629 | This SoC is used on Linaro 96Board STiH410-B2260 | |
1630 | ||
2514c2d0 PD |
1631 | config ARCH_STM32MP |
1632 | bool "Support STMicroelectronics STM32MP Socs with cortex A" | |
08772f6e | 1633 | select ARCH_MISC_INIT |
654706be | 1634 | select ARCH_SUPPORT_TFABOOT |
2514c2d0 PD |
1635 | select BOARD_LATE_INIT |
1636 | select CLK | |
1637 | select DM | |
1638 | select DM_GPIO | |
1639 | select DM_RESET | |
1640 | select DM_SERIAL | |
5ed063d1 | 1641 | select MISC |
2514c2d0 PD |
1642 | select OF_CONTROL |
1643 | select OF_LIBFDT | |
05d36936 | 1644 | select OF_SYSTEM_SETUP |
2514c2d0 PD |
1645 | select PINCTRL |
1646 | select REGMAP | |
1647 | select SUPPORT_SPL | |
1648 | select SYSCON | |
86634a93 | 1649 | select SYSRESET |
2514c2d0 | 1650 | select SYS_THUMB_BUILD |
09259fce | 1651 | imply SPL_SYSRESET |
08a00cba | 1652 | imply CMD_DM |
c16cc4f6 | 1653 | imply CMD_POWEROFF |
f219361d | 1654 | imply OF_LIBFDT_OVERLAY |
b4ae34b6 | 1655 | imply ENV_VARS_UBOOT_RUNTIME_CONFIG |
ce3772ca | 1656 | imply USE_PREBOOT |
2514c2d0 PD |
1657 | help |
1658 | Support for STM32MP SoC family developed by STMicroelectronics, | |
1659 | MPUs based on ARM cortex A core | |
abf2678f PD |
1660 | U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL). |
1661 | FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot | |
1662 | chain. | |
1663 | SPL is the unsecure FSBL for the basic boot chain. | |
2514c2d0 | 1664 | |
2444dae5 SG |
1665 | config ARCH_ROCKCHIP |
1666 | bool "Support Rockchip SoCs" | |
aa15038c | 1667 | select BLK |
79030a48 | 1668 | select BINMAN if !ARM64 |
2444dae5 | 1669 | select DM |
aa15038c SG |
1670 | select DM_GPIO |
1671 | select DM_I2C | |
1672 | select DM_MMC | |
5ed063d1 MS |
1673 | select DM_PWM |
1674 | select DM_REGULATOR | |
aa15038c SG |
1675 | select DM_SERIAL |
1676 | select DM_SPI | |
1677 | select DM_SPI_FLASH | |
892742df | 1678 | select DM_USB if USB |
14ad6eb2 | 1679 | select ENABLE_ARM_SOC_BOOT0_HOOK |
5ed063d1 | 1680 | select OF_CONTROL |
f1b1f770 | 1681 | select SPI |
5ed063d1 | 1682 | select SPL_DM if SPL |
5ed063d1 MS |
1683 | select SYS_MALLOC_F |
1684 | select SYS_THUMB_BUILD if !ARM64 | |
1685 | imply ADC | |
08a00cba | 1686 | imply CMD_DM |
b0a569da | 1687 | imply DEBUG_UART_BOARD_INIT |
7325f6cf | 1688 | imply DISTRO_DEFAULTS |
91d27a17 | 1689 | imply FAT_WRITE |
8e8bcccc | 1690 | imply SARADC_ROCKCHIP |
5ed063d1 | 1691 | imply SPL_SYSRESET |
64eff47c | 1692 | imply SPL_SYS_MALLOC_SIMPLE |
c3c0331d | 1693 | imply SYS_NS16550 |
5ed063d1 MS |
1694 | imply TPL_SYSRESET |
1695 | imply USB_FUNCTION_FASTBOOT | |
2444dae5 | 1696 | |
746f985a ST |
1697 | config TARGET_THUNDERX_88XX |
1698 | bool "Support ThunderX 88xx" | |
b4ba1693 | 1699 | select ARM64 |
746f985a | 1700 | select OF_CONTROL |
cf2c7784 | 1701 | select PL01X_SERIAL |
5ed063d1 | 1702 | select SYS_CACHE_SHIFT_7 |
746f985a | 1703 | |
4697abea | 1704 | config ARCH_ASPEED |
1705 | bool "Support Aspeed SoCs" | |
4697abea | 1706 | select DM |
5ed063d1 | 1707 | select OF_CONTROL |
08a00cba | 1708 | imply CMD_DM |
4697abea | 1709 | |
e3aafef4 | 1710 | config TARGET_DURIAN |
1711 | bool "Support Phytium Durian Platform" | |
1712 | select ARM64 | |
1713 | help | |
1714 | Support for durian platform. | |
1715 | It has 2GB Sdram, uart and pcie. | |
1716 | ||
7d706a88 AN |
1717 | config TARGET_PRESIDIO_ASIC |
1718 | bool "Support Cortina Presidio ASIC Platform" | |
1719 | select ARM64 | |
1720 | ||
dd84058d MY |
1721 | endchoice |
1722 | ||
6324d506 AT |
1723 | config ARCH_SUPPORT_TFABOOT |
1724 | bool | |
1725 | ||
1726 | config TFABOOT | |
1727 | bool "Support for booting from TF-A" | |
1728 | depends on ARCH_SUPPORT_TFABOOT | |
1729 | default n | |
1730 | help | |
1731 | Enabling this will make a U-Boot binary that is capable of being | |
e852b30b | 1732 | booted via TF-A (Trusted Firmware for Cortex-A). |
6324d506 | 1733 | |
5fbed8f2 AD |
1734 | config TI_SECURE_DEVICE |
1735 | bool "HS Device Type Support" | |
3a543a80 | 1736 | depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3 |
5fbed8f2 AD |
1737 | help |
1738 | If a high secure (HS) device type is being used, this config | |
1739 | must be set. This option impacts various aspects of the | |
1740 | build system (to create signed boot images that can be | |
1741 | authenticated) and the code. See the doc/README.ti-secure | |
1742 | file for further details. | |
1743 | ||
9c4b0131 TR |
1744 | if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE |
1745 | config ISW_ENTRY_ADDR | |
1746 | hex "Address in memory or XIP address of bootloader entry point" | |
1747 | default 0x402F4000 if AM43XX | |
1748 | default 0x402F0400 if AM33XX | |
1749 | default 0x40301350 if OMAP54XX | |
1750 | help | |
1751 | After any reset, the boot ROM searches the boot media for a valid | |
1752 | boot image. For non-XIP devices, the ROM then copies the image into | |
1753 | internal memory. For all boot modes, after the ROM processes the | |
1754 | boot image it eventually computes the entry point address depending | |
1755 | on the device type (secure/non-secure), boot media (xip/non-xip) and | |
1756 | image headers. | |
1757 | endif | |
1758 | ||
4697abea | 1759 | source "arch/arm/mach-aspeed/Kconfig" |
1760 | ||
4614b891 MY |
1761 | source "arch/arm/mach-at91/Kconfig" |
1762 | ||
ddf6bd48 | 1763 | source "arch/arm/mach-bcm283x/Kconfig" |
3491ba63 | 1764 | |
894c3ad2 TF |
1765 | source "arch/arm/mach-bcmstb/Kconfig" |
1766 | ||
ddf6bd48 | 1767 | source "arch/arm/mach-davinci/Kconfig" |
34e609ca | 1768 | |
77b55e8c | 1769 | source "arch/arm/mach-exynos/Kconfig" |
72df68cc | 1770 | |
72a8ff4b | 1771 | source "arch/arm/mach-highbank/Kconfig" |
ef2b694c | 1772 | |
5cbbd9bd MY |
1773 | source "arch/arm/mach-integrator/Kconfig" |
1774 | ||
586bde93 LV |
1775 | source "arch/arm/mach-k3/Kconfig" |
1776 | ||
39a72345 | 1777 | source "arch/arm/mach-keystone/Kconfig" |
c338f09e | 1778 | |
56f86e39 | 1779 | source "arch/arm/mach-kirkwood/Kconfig" |
47539e23 | 1780 | |
b3d9a8b1 | 1781 | source "arch/arm/mach-lpc32xx/Kconfig" |
ee54dfea | 1782 | |
c3d89140 SR |
1783 | source "arch/arm/mach-mvebu/Kconfig" |
1784 | ||
0a37cf8f YS |
1785 | source "arch/arm/cpu/armv7/ls102xa/Kconfig" |
1786 | ||
07df697e FE |
1787 | source "arch/arm/mach-imx/mx2/Kconfig" |
1788 | ||
3159ec64 ML |
1789 | source "arch/arm/mach-imx/mx3/Kconfig" |
1790 | ||
7a7391fd PF |
1791 | source "arch/arm/mach-imx/mx5/Kconfig" |
1792 | ||
1793 | source "arch/arm/mach-imx/mx6/Kconfig" | |
e90a08da | 1794 | |
552a848e | 1795 | source "arch/arm/mach-imx/mx7/Kconfig" |
1a8150d4 | 1796 | |
7a7391fd | 1797 | source "arch/arm/mach-imx/mx7ulp/Kconfig" |
89ebc821 | 1798 | |
b2b8b9be PF |
1799 | source "arch/arm/mach-imx/imx8/Kconfig" |
1800 | ||
cd357ad1 | 1801 | source "arch/arm/mach-imx/imx8m/Kconfig" |
424ee3d1 | 1802 | |
77eb9a90 GB |
1803 | source "arch/arm/mach-imx/imxrt/Kconfig" |
1804 | ||
c5343d4e SA |
1805 | source "arch/arm/mach-imx/mxs/Kconfig" |
1806 | ||
983e3700 | 1807 | source "arch/arm/mach-omap2/Kconfig" |
6384726d | 1808 | |
da28e58a YS |
1809 | source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig" |
1810 | ||
3e93b4e6 | 1811 | source "arch/arm/mach-orion5x/Kconfig" |
22f2be7a | 1812 | |
97775d26 MS |
1813 | source "arch/arm/mach-owl/Kconfig" |
1814 | ||
badbb63c | 1815 | source "arch/arm/mach-rmobile/Kconfig" |
f40b9898 | 1816 | |
bfcef28a BG |
1817 | source "arch/arm/mach-meson/Kconfig" |
1818 | ||
cbd2fba1 RL |
1819 | source "arch/arm/mach-mediatek/Kconfig" |
1820 | ||
32f11829 TT |
1821 | source "arch/arm/mach-qemu/Kconfig" |
1822 | ||
2444dae5 SG |
1823 | source "arch/arm/mach-rockchip/Kconfig" |
1824 | ||
225f5eec | 1825 | source "arch/arm/mach-s5pc1xx/Kconfig" |
311757be | 1826 | |
08592136 MK |
1827 | source "arch/arm/mach-snapdragon/Kconfig" |
1828 | ||
7865f4b0 MY |
1829 | source "arch/arm/mach-socfpga/Kconfig" |
1830 | ||
94e9a4ef PC |
1831 | source "arch/arm/mach-sti/Kconfig" |
1832 | ||
0a61ee88 VM |
1833 | source "arch/arm/mach-stm32/Kconfig" |
1834 | ||
2514c2d0 PD |
1835 | source "arch/arm/mach-stm32mp/Kconfig" |
1836 | ||
3abfd887 MY |
1837 | source "arch/arm/mach-sunxi/Kconfig" |
1838 | ||
09f455dc | 1839 | source "arch/arm/mach-tegra/Kconfig" |
ddd960e6 | 1840 | |
689088f9 SG |
1841 | source "arch/arm/mach-u8500/Kconfig" |
1842 | ||
4c425570 | 1843 | source "arch/arm/mach-uniphier/Kconfig" |
66cba041 | 1844 | |
7966b437 SA |
1845 | source "arch/arm/cpu/armv7/vf610/Kconfig" |
1846 | ||
0107f240 | 1847 | source "arch/arm/mach-zynq/Kconfig" |
ddd960e6 | 1848 | |
274ccb5b MS |
1849 | source "arch/arm/mach-zynqmp/Kconfig" |
1850 | ||
ec48b6c9 MS |
1851 | source "arch/arm/mach-versal/Kconfig" |
1852 | ||
1d6c54ec MS |
1853 | source "arch/arm/mach-zynqmp-r5/Kconfig" |
1854 | ||
ea624e19 HG |
1855 | source "arch/arm/cpu/armv7/Kconfig" |
1856 | ||
23b5877c LW |
1857 | source "arch/arm/cpu/armv8/Kconfig" |
1858 | ||
552a848e | 1859 | source "arch/arm/mach-imx/Kconfig" |
a05a6045 | 1860 | |
d8ccbe93 | 1861 | source "board/bosch/shc/Kconfig" |
45123804 | 1862 | source "board/bosch/guardian/Kconfig" |
dd84058d | 1863 | source "board/CarMediaLab/flea3/Kconfig" |
dd84058d | 1864 | source "board/Marvell/aspenite/Kconfig" |
dd84058d | 1865 | source "board/Marvell/gplugd/Kconfig" |
dd84058d | 1866 | source "board/armadeus/apf27/Kconfig" |
dd84058d MY |
1867 | source "board/armltd/vexpress/Kconfig" |
1868 | source "board/armltd/vexpress64/Kconfig" | |
7d706a88 | 1869 | source "board/cortina/presidio-asic/Kconfig" |
43486e4c | 1870 | source "board/broadcom/bcm23550_w1d/Kconfig" |
dd84058d | 1871 | source "board/broadcom/bcm28155_ap/Kconfig" |
be2fc084 | 1872 | source "board/broadcom/bcm963158/Kconfig" |
645b7ec5 | 1873 | source "board/broadcom/bcm968360bg/Kconfig" |
40b59b05 | 1874 | source "board/broadcom/bcm968580xref/Kconfig" |
abb1678c SR |
1875 | source "board/broadcom/bcmcygnus/Kconfig" |
1876 | source "board/broadcom/bcmnsp/Kconfig" | |
274bced8 | 1877 | source "board/broadcom/bcmns2/Kconfig" |
746f985a | 1878 | source "board/cavium/thunderx/Kconfig" |
dd84058d | 1879 | source "board/cirrus/edb93xx/Kconfig" |
85ab0452 | 1880 | source "board/eets/pdu001/Kconfig" |
6f332765 | 1881 | source "board/emulation/qemu-arm/Kconfig" |
44937214 PK |
1882 | source "board/freescale/ls2080a/Kconfig" |
1883 | source "board/freescale/ls2080aqds/Kconfig" | |
1884 | source "board/freescale/ls2080ardb/Kconfig" | |
e84a324b | 1885 | source "board/freescale/ls1088a/Kconfig" |
353f36d9 | 1886 | source "board/freescale/ls1028a/Kconfig" |
550e3dc0 | 1887 | source "board/freescale/ls1021aqds/Kconfig" |
02b5d2ed | 1888 | source "board/freescale/ls1043aqds/Kconfig" |
c8a7d9da | 1889 | source "board/freescale/ls1021atwr/Kconfig" |
87821220 | 1890 | source "board/freescale/ls1021atsn/Kconfig" |
20c700f8 | 1891 | source "board/freescale/ls1021aiot/Kconfig" |
126fe70d | 1892 | source "board/freescale/ls1046aqds/Kconfig" |
f3a8e2b7 | 1893 | source "board/freescale/ls1043ardb/Kconfig" |
dd02936f | 1894 | source "board/freescale/ls1046ardb/Kconfig" |
d90c7ac7 | 1895 | source "board/freescale/ls1046afrwy/Kconfig" |
9d044fcb | 1896 | source "board/freescale/ls1012aqds/Kconfig" |
3b6e3898 | 1897 | source "board/freescale/ls1012ardb/Kconfig" |
ff78aa2b | 1898 | source "board/freescale/ls1012afrdm/Kconfig" |
58c3e620 | 1899 | source "board/freescale/lx2160a/Kconfig" |
dd84058d | 1900 | source "board/freescale/mx35pdk/Kconfig" |
9702ec00 | 1901 | source "board/freescale/s32v234evb/Kconfig" |
ab38bf6a | 1902 | source "board/grinn/chiliboard/Kconfig" |
dd84058d | 1903 | source "board/gumstix/pepper/Kconfig" |
345243ed | 1904 | source "board/hisilicon/hikey/Kconfig" |
c62c7ef7 | 1905 | source "board/hisilicon/hikey960/Kconfig" |
d754254f | 1906 | source "board/hisilicon/poplar/Kconfig" |
a96c08f5 | 1907 | source "board/isee/igep003x/Kconfig" |
dd84058d | 1908 | source "board/phytec/pcm051/Kconfig" |
dd84058d | 1909 | source "board/silica/pengwyn/Kconfig" |
dd84058d MY |
1910 | source "board/spear/spear300/Kconfig" |
1911 | source "board/spear/spear310/Kconfig" | |
1912 | source "board/spear/spear320/Kconfig" | |
1913 | source "board/spear/spear600/Kconfig" | |
1914 | source "board/spear/x600/Kconfig" | |
9fa32b12 | 1915 | source "board/st/stv0991/Kconfig" |
9d1b2987 | 1916 | source "board/tcl/sl50/Kconfig" |
a2bc4321 | 1917 | source "board/birdland/bav335x/Kconfig" |
dd84058d | 1918 | source "board/toradex/colibri_pxa270/Kconfig" |
d8d33b6d | 1919 | source "board/variscite/dart_6ul/Kconfig" |
6ce89324 | 1920 | source "board/vscom/baltos/Kconfig" |
6da4f67a | 1921 | source "board/xilinx/Kconfig" |
37e3a36a | 1922 | source "board/xilinx/zynq/Kconfig" |
c436bf92 | 1923 | source "board/xilinx/zynqmp/Kconfig" |
e3aafef4 | 1924 | source "board/phytium/durian/Kconfig" |
dd84058d | 1925 | |
51b17d49 MY |
1926 | source "arch/arm/Kconfig.debug" |
1927 | ||
dd84058d | 1928 | endmenu |
b529993e PT |
1929 | |
1930 | config SPL_LDSCRIPT | |
6e7bdde4 MS |
1931 | default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK |
1932 | default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 | |
b529993e PT |
1933 | default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 |
1934 | ||
1935 |