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dd84058d
MY
1menu "ARM architecture"
2 depends on ARM
3
4config SYS_ARCH
dd84058d
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5 default "arm"
6
016a954e
MY
7config ARM64
8 bool
bb6b142f 9 select PHYS_64BIT
067716ba 10 select SYS_CACHE_SHIFT_6
016a954e 11
49e93875
SW
12if ARM64
13config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
f071cdab 15 select INIT_SP_RELATIVE
49e93875
SW
16 help
17 U-Boot expects to be linked to a specific hard-coded address, and to
18 be loaded to and run from that address. This option lifts that
19 restriction, thus allowing the code to be loaded to and executed
20 from almost any address. This logic relies on the relocation
e852b30b 21 information that is embedded in the binary to support U-Boot
49e93875 22 relocating itself to the top-of-RAM later during execution.
e6c90448 23
382de4a7
MY
24config INIT_SP_RELATIVE
25 bool "Specify the early stack pointer relative to the .bss section"
e6c90448
SW
26 help
27 U-Boot typically uses a hard-coded value for the stack pointer
382de4a7 28 before relocation. Enable this option to instead calculate the
e6c90448 29 initial SP at run-time. This is useful to avoid hard-coding addresses
e852b30b 30 into U-Boot, so that it can be loaded and executed at arbitrary
382de4a7
MY
31 addresses and thus avoid using arbitrary addresses at runtime.
32
33 If this option is enabled, the early stack pointer is set to
34 &_bss_start with a offset value added. The offset is specified by
35 SYS_INIT_SP_BSS_OFFSET.
36
37config SYS_INIT_SP_BSS_OFFSET
38 int "Early stack offset from the .bss base address"
39 depends on INIT_SP_RELATIVE
40 default 524288
41 help
42 This option's value is the offset added to &_bss_start in order to
e6c90448
SW
43 calculate the stack pointer. This offset should be large enough so
44 that the early malloc region, global data (gd), and early stack usage
45 do not overlap any appended DTB.
8163faf9
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46
47config LINUX_KERNEL_IMAGE_HEADER
48 bool
49 help
50 Place a Linux kernel image header at the start of the U-Boot binary.
51 The format of the header is described in the Linux kernel source at
52 Documentation/arm64/booting.txt. This feature is useful since the
53 image header reports the amount of memory (BSS and similar) that
54 U-Boot needs to use, but which isn't part of the binary.
55
56if LINUX_KERNEL_IMAGE_HEADER
57config LNX_KRNL_IMG_TEXT_OFFSET_BASE
58 hex
59 help
60 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
e852b30b 61 TEXT_OFFSET value written to the Linux kernel image header.
8163faf9 62endif
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SW
63endif
64
0bc4356d
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65config GIC_V3_ITS
66 bool "ARM GICV3 ITS"
67 help
68 ARM GICV3 Interrupt translation service (ITS).
69 Basic support for programming locality specific peripheral
70 interrupts (LPI) configuration tables and enable LPI tables.
71 LPI configuration table can be used by u-boot or Linux.
72 ARM GICV3 has limitation, once the LPI table is enabled, LPI
73 configuration table can not be re-programmed, unless GICV3 reset.
74
49e93875
SW
75config STATIC_RELA
76 bool
77 default y if ARM64 && !POSITION_INDEPENDENT
78
37217f0e
LV
79config DMA_ADDR_T_64BIT
80 bool
81 default y if ARM64
82
2e07c249 83config HAS_VBAR
e009bfa4 84 bool
2e07c249 85
62e92077 86config HAS_THUMB2
e009bfa4 87 bool
62e92077 88
111a6af9
PE
89# Used for compatibility with asm files copied from the kernel
90config ARM_ASM_UNIFIED
91 bool
92 default y
93
94# Used for compatibility with asm files copied from the kernel
95config THUMB2_KERNEL
96 bool
97
a0aba8a2
TW
98config SYS_ICACHE_OFF
99 bool "Do not enable icache"
100 default n
101 help
102 Do not enable instruction cache in U-Boot.
103
10015025
TW
104config SPL_SYS_ICACHE_OFF
105 bool "Do not enable icache in SPL"
106 depends on SPL
107 default SYS_ICACHE_OFF
108 help
109 Do not enable instruction cache in SPL.
110
a0aba8a2
TW
111config SYS_DCACHE_OFF
112 bool "Do not enable dcache"
113 default n
114 help
115 Do not enable data cache in U-Boot.
116
10015025
TW
117config SPL_SYS_DCACHE_OFF
118 bool "Do not enable dcache in SPL"
119 depends on SPL
120 default SYS_DCACHE_OFF
121 help
122 Do not enable data cache in SPL.
123
f4bcd767
LV
124config SYS_ARM_CACHE_CP15
125 bool "CP15 based cache enabling support"
126 help
127 Select this if your processor suports enabling caches by using
128 CP15 registers.
129
7240b80e
LV
130config SYS_ARM_MMU
131 bool "MMU-based Paged Memory Management Support"
f4bcd767 132 select SYS_ARM_CACHE_CP15
7240b80e
LV
133 help
134 Select if you want MMU-based virtualised addressing space
e852b30b 135 support via paged memory management.
7240b80e 136
f2ef2043
LV
137config SYS_ARM_MPU
138 bool 'Use the ARM v7 PMSA Compliant MPU'
139 help
140 Some ARM systems without an MMU have instead a Memory Protection
141 Unit (MPU) that defines the type and permissions for regions of
142 memory.
143 If your CPU has an MPU then you should choose 'y' here unless you
144 know that you do not want to use the MPU.
145
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146# If set, the workarounds for these ARM errata are applied early during U-Boot
147# startup. Note that in general these options force the workarounds to be
148# applied; no CPU-type/version detection exists, unlike the similar options in
149# the Linux kernel. Do not set these options unless they apply! Also note that
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150# the following can be machine-specific errata. These do have ability to
151# provide rudimentary version and machine-specific checks, but expect no
8dda2e2f
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152# product checks:
153# CONFIG_ARM_ERRATA_430973
154# CONFIG_ARM_ERRATA_454179
155# CONFIG_ARM_ERRATA_621766
156# CONFIG_ARM_ERRATA_798870
157# CONFIG_ARM_ERRATA_801819
7b37a9c7 158# CONFIG_ARM_CORTEX_A8_CVE_2017_5715
c2ca3fdf 159# CONFIG_ARM_CORTEX_A15_CVE_2017_5715
7b37a9c7 160
8dda2e2f
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161config ARM_ERRATA_430973
162 bool
163
164config ARM_ERRATA_454179
165 bool
166
167config ARM_ERRATA_621766
168 bool
169
170config ARM_ERRATA_716044
171 bool
172
19a75b8c
SS
173config ARM_ERRATA_725233
174 bool
175
8dda2e2f
TR
176config ARM_ERRATA_742230
177 bool
178
179config ARM_ERRATA_743622
180 bool
181
182config ARM_ERRATA_751472
183 bool
184
185config ARM_ERRATA_761320
186 bool
187
188config ARM_ERRATA_773022
189 bool
190
191config ARM_ERRATA_774769
192 bool
193
194config ARM_ERRATA_794072
195 bool
196
197config ARM_ERRATA_798870
198 bool
199
200config ARM_ERRATA_801819
201 bool
202
203config ARM_ERRATA_826974
204 bool
205
206config ARM_ERRATA_828024
207 bool
208
209config ARM_ERRATA_829520
210 bool
211
212config ARM_ERRATA_833069
213 bool
214
215config ARM_ERRATA_833471
216 bool
217
11d94319 218config ARM_ERRATA_845369
6e7bdde4 219 bool
11d94319 220
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NM
221config ARM_ERRATA_852421
222 bool
223
224config ARM_ERRATA_852423
225 bool
226
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AW
227config ARM_ERRATA_855873
228 bool
229
7b37a9c7
NM
230config ARM_CORTEX_A8_CVE_2017_5715
231 bool
232
c2ca3fdf
NM
233config ARM_CORTEX_A15_CVE_2017_5715
234 bool
235
2e07c249 236config CPU_ARM720T
e009bfa4 237 bool
067716ba 238 select SYS_CACHE_SHIFT_5
7240b80e 239 imply SYS_ARM_MMU
2e07c249
GS
240
241config CPU_ARM920T
e009bfa4 242 bool
067716ba 243 select SYS_CACHE_SHIFT_5
7240b80e 244 imply SYS_ARM_MMU
2e07c249
GS
245
246config CPU_ARM926EJS
e009bfa4 247 bool
067716ba 248 select SYS_CACHE_SHIFT_5
7240b80e 249 imply SYS_ARM_MMU
2e07c249
GS
250
251config CPU_ARM946ES
e009bfa4 252 bool
067716ba 253 select SYS_CACHE_SHIFT_5
7240b80e 254 imply SYS_ARM_MMU
2e07c249
GS
255
256config CPU_ARM1136
e009bfa4 257 bool
067716ba 258 select SYS_CACHE_SHIFT_5
7240b80e 259 imply SYS_ARM_MMU
2e07c249
GS
260
261config CPU_ARM1176
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262 bool
263 select HAS_VBAR
067716ba 264 select SYS_CACHE_SHIFT_5
7240b80e 265 imply SYS_ARM_MMU
2e07c249 266
acf15001 267config CPU_V7A
e009bfa4 268 bool
e009bfa4 269 select HAS_THUMB2
5ed063d1 270 select HAS_VBAR
067716ba 271 select SYS_CACHE_SHIFT_6
7240b80e 272 imply SYS_ARM_MMU
2e07c249 273
12d8a729 274config CPU_V7M
275 bool
e009bfa4 276 select HAS_THUMB2
f2ef2043 277 select SYS_ARM_MPU
5ed063d1 278 select SYS_CACHE_SHIFT_5
ea37f0b3 279 select SYS_THUMB_BUILD
5ed063d1 280 select THUMB2_KERNEL
12d8a729 281
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MS
282config CPU_V7R
283 bool
284 select HAS_THUMB2
f2ef2043 285 select SYS_ARM_CACHE_CP15
5ed063d1
MS
286 select SYS_ARM_MPU
287 select SYS_CACHE_SHIFT_6
4bbd6b1d 288
2e07c249 289config CPU_PXA
e009bfa4 290 bool
067716ba 291 select SYS_CACHE_SHIFT_5
7240b80e 292 imply SYS_ARM_MMU
2e07c249
GS
293
294config CPU_SA1100
e009bfa4 295 bool
067716ba 296 select SYS_CACHE_SHIFT_5
7240b80e 297 imply SYS_ARM_MMU
2e07c249
GS
298
299config SYS_CPU
e009bfa4
TR
300 default "arm720t" if CPU_ARM720T
301 default "arm920t" if CPU_ARM920T
302 default "arm926ejs" if CPU_ARM926EJS
303 default "arm946es" if CPU_ARM946ES
304 default "arm1136" if CPU_ARM1136
305 default "arm1176" if CPU_ARM1176
acf15001 306 default "armv7" if CPU_V7A
4bbd6b1d 307 default "armv7" if CPU_V7R
e009bfa4
TR
308 default "armv7m" if CPU_V7M
309 default "pxa" if CPU_PXA
310 default "sa1100" if CPU_SA1100
01541eec 311 default "armv8" if ARM64
2e07c249 312
66020a67
MV
313config SYS_ARM_ARCH
314 int
315 default 4 if CPU_ARM720T
316 default 4 if CPU_ARM920T
317 default 5 if CPU_ARM926EJS
318 default 5 if CPU_ARM946ES
319 default 6 if CPU_ARM1136
320 default 6 if CPU_ARM1176
acf15001 321 default 7 if CPU_V7A
66020a67 322 default 7 if CPU_V7M
4bbd6b1d 323 default 7 if CPU_V7R
66020a67
MV
324 default 5 if CPU_PXA
325 default 4 if CPU_SA1100
326 default 8 if ARM64
327
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TR
328config SYS_CACHE_SHIFT_5
329 bool
330
331config SYS_CACHE_SHIFT_6
332 bool
333
334config SYS_CACHE_SHIFT_7
335 bool
336
337config SYS_CACHELINE_SIZE
338 int
339 default 128 if SYS_CACHE_SHIFT_7
340 default 64 if SYS_CACHE_SHIFT_6
341 default 32 if SYS_CACHE_SHIFT_5
342
1bf33015
AF
343config ARCH_CPU_INIT
344 bool "Enable ARCH_CPU_INIT"
345 help
e852b30b 346 Some architectures require a call to arch_cpu_init().
1bf33015
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347 Say Y here to enable it
348
7842b6a9
AP
349config SYS_ARCH_TIMER
350 bool "ARM Generic Timer support"
acf15001 351 depends on CPU_V7A || ARM64
7842b6a9
AP
352 default y if ARM64
353 help
354 The ARM Generic Timer (aka arch-timer) provides an architected
355 interface to a timer source on an SoC.
e852b30b 356 It is mandatory for ARMv8 implementation and widely available
7842b6a9
AP
357 on ARMv7 systems.
358
c54bcf68
MY
359config ARM_SMCCC
360 bool "Support for ARM SMC Calling Convention (SMCCC)"
acf15001 361 depends on CPU_V7A || ARM64
573a3811 362 select ARM_PSCI_FW
c54bcf68
MY
363 help
364 Say Y here if you want to enable ARM SMC Calling Convention.
365 This should be enabled if U-Boot needs to communicate with system
366 firmware (for example, PSCI) according to SMCCC.
367
f91afc4d
LW
368config SEMIHOSTING
369 bool "support boot from semihosting"
370 help
371 In emulated environments, semihosting is a way for
372 the hosted environment to call out to the emulator to
373 retrieve files from the host machine.
374
3a649407
TR
375config SYS_THUMB_BUILD
376 bool "Build U-Boot using the Thumb instruction set"
377 depends on !ARM64
378 help
379 Use this flag to build U-Boot using the Thumb instruction set for
380 ARM architectures. Thumb instruction set provides better code
381 density. For ARM architectures that support Thumb2 this flag will
382 result in Thumb2 code generated by GCC.
383
384config SPL_SYS_THUMB_BUILD
385 bool "Build SPL using the Thumb instruction set"
386 default y if SYS_THUMB_BUILD
05705566 387 depends on !ARM64 && SPL
3a649407
TR
388 help
389 Use this flag to build SPL using the Thumb instruction set for
390 ARM architectures. Thumb instruction set provides better code
391 density. For ARM architectures that support Thumb2 this flag will
392 result in Thumb2 code generated by GCC.
393
1e32c519
KY
394config TPL_SYS_THUMB_BUILD
395 bool "Build TPL using the Thumb instruction set"
396 default y if SYS_THUMB_BUILD
397 depends on TPL && !ARM64
398 help
e852b30b 399 Use this flag to build TPL using the Thumb instruction set for
1e32c519
KY
400 ARM architectures. Thumb instruction set provides better code
401 density. For ARM architectures that support Thumb2 this flag will
402 result in Thumb2 code generated by GCC.
403
404
f3e9bec8
PF
405config SYS_L2CACHE_OFF
406 bool "L2cache off"
407 help
e852b30b 408 If SoC does not support L2CACHE or one does not want to enable
f3e9bec8
PF
409 L2CACHE, choose this option.
410
cdaa633f
AP
411config ENABLE_ARM_SOC_BOOT0_HOOK
412 bool "prepare BOOT0 header"
413 help
414 If the SoC's BOOT0 requires a header area filled with (magic)
7d531e8a
SG
415 values, then choose this option, and create a file included as
416 <asm/arch/boot0.h> which contains the required assembler code.
cdaa633f 417
85db5831
AP
418config ARM_CORTEX_CPU_IS_UP
419 bool
420 default n
421
be72591b
FE
422config USE_ARCH_MEMCPY
423 bool "Use an assembly optimized implementation of memcpy"
40d5534c
TR
424 default y
425 depends on !ARM64
426 help
427 Enable the generation of an optimized version of memcpy.
e852b30b 428 Such an implementation may be faster under some conditions
40d5534c
TR
429 but may increase the binary size.
430
431config SPL_USE_ARCH_MEMCPY
f8136e68 432 bool "Use an assembly optimized implementation of memcpy for SPL"
40d5534c 433 default y if USE_ARCH_MEMCPY
05705566 434 depends on !ARM64 && SPL
be72591b
FE
435 help
436 Enable the generation of an optimized version of memcpy.
e852b30b 437 Such an implementation may be faster under some conditions
be72591b
FE
438 but may increase the binary size.
439
1e32c519
KY
440config TPL_USE_ARCH_MEMCPY
441 bool "Use an assembly optimized implementation of memcpy for TPL"
442 default y if USE_ARCH_MEMCPY
05705566 443 depends on !ARM64 && TPL
1e32c519
KY
444 help
445 Enable the generation of an optimized version of memcpy.
e852b30b 446 Such an implementation may be faster under some conditions
1e32c519
KY
447 but may increase the binary size.
448
be72591b
FE
449config USE_ARCH_MEMSET
450 bool "Use an assembly optimized implementation of memset"
40d5534c
TR
451 default y
452 depends on !ARM64
453 help
454 Enable the generation of an optimized version of memset.
e852b30b 455 Such an implementation may be faster under some conditions
40d5534c
TR
456 but may increase the binary size.
457
458config SPL_USE_ARCH_MEMSET
f8136e68 459 bool "Use an assembly optimized implementation of memset for SPL"
40d5534c 460 default y if USE_ARCH_MEMSET
05705566 461 depends on !ARM64 && SPL
be72591b
FE
462 help
463 Enable the generation of an optimized version of memset.
e852b30b 464 Such an implementation may be faster under some conditions
be72591b
FE
465 but may increase the binary size.
466
1e32c519
KY
467config TPL_USE_ARCH_MEMSET
468 bool "Use an assembly optimized implementation of memset for TPL"
469 default y if USE_ARCH_MEMSET
05705566 470 depends on !ARM64 && TPL
1e32c519
KY
471 help
472 Enable the generation of an optimized version of memset.
e852b30b 473 Such an implementation may be faster under some conditions
1e32c519
KY
474 but may increase the binary size.
475
085201c2
SDPP
476config SET_STACK_SIZE
477 bool "Enable an option to set max stack size that can be used"
a69814c8 478 default y if ARCH_VERSAL || ARCH_ZYNQMP
085201c2
SDPP
479 help
480 This will enable an option to set max stack size that can be
e852b30b 481 used by U-Boot.
085201c2
SDPP
482
483config STACK_SIZE
e852b30b 484 hex "Define max stack size that can be used by U-Boot"
085201c2 485 depends on SET_STACK_SIZE
a69814c8 486 default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
085201c2 487 help
e852b30b 488 Define Max stack size that can be used by U-Boot so that the
085201c2
SDPP
489 initrd_high will be calculated as base stack pointer minus this
490 stack size.
491
ec6617c3
AW
492config ARM64_SUPPORT_AARCH32
493 bool "ARM64 system support AArch32 execution state"
05705566
AF
494 depends on ARM64
495 default y if !TARGET_THUNDERX_88XX
ec6617c3
AW
496 help
497 This ARM64 system supports AArch32 execution state.
498
dd84058d
MY
499choice
500 prompt "Target select"
b928e658 501 default TARGET_HIKEY
dd84058d 502
4614b891
MY
503config ARCH_AT91
504 bool "Atmel AT91"
f58e9460 505 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
dd84058d
MY
506
507config TARGET_EDB93XX
508 bool "Support edb93xx"
2e07c249 509 select CPU_ARM920T
884f9013 510 select PL010_SERIAL
dd84058d 511
dd84058d
MY
512config TARGET_ASPENITE
513 bool "Support aspenite"
2e07c249 514 select CPU_ARM926EJS
dd84058d
MY
515
516config TARGET_GPLUGD
517 bool "Support gplugd"
2e07c249 518 select CPU_ARM926EJS
dd84058d 519
3491ba63
MY
520config ARCH_DAVINCI
521 bool "TI DaVinci"
2e07c249 522 select CPU_ARM926EJS
15dc63d6 523 imply CMD_SAVES
3491ba63
MY
524 help
525 Support for TI's DaVinci platform.
dd84058d 526
47539e23
MY
527config KIRKWOOD
528 bool "Marvell Kirkwood"
4585601a 529 select ARCH_MISC_INIT
5ed063d1
MS
530 select BOARD_EARLY_INIT_F
531 select CPU_ARM926EJS
dd84058d 532
c3d89140 533config ARCH_MVEBU
21b29fc6 534 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
9cffb233 535 select DM
e3b9c98a 536 select DM_ETH
1d51ea19 537 select DM_SERIAL
09a54c00
SR
538 select DM_SPI
539 select DM_SPI_FLASH
5ed063d1
MS
540 select OF_CONTROL
541 select OF_SEPARATE
f1b1f770 542 select SPI
08a00cba 543 imply CMD_DM
a4884831 544
dd84058d
MY
545config TARGET_APF27
546 bool "Support apf27"
2e07c249 547 select CPU_ARM926EJS
02627356 548 select SUPPORT_SPL
dd84058d 549
22f2be7a
MY
550config ORION5X
551 bool "Marvell Orion"
2e07c249 552 select CPU_ARM926EJS
dd84058d 553
dd84058d
MY
554config TARGET_SPEAR300
555 bool "Support spear300"
a5d67547 556 select BOARD_EARLY_INIT_F
5ed063d1 557 select CPU_ARM926EJS
d10fc50f 558 select PL011_SERIAL
5ed063d1 559 imply CMD_SAVES
dd84058d
MY
560
561config TARGET_SPEAR310
562 bool "Support spear310"
a5d67547 563 select BOARD_EARLY_INIT_F
5ed063d1 564 select CPU_ARM926EJS
d10fc50f 565 select PL011_SERIAL
5ed063d1 566 imply CMD_SAVES
dd84058d
MY
567
568config TARGET_SPEAR320
569 bool "Support spear320"
a5d67547 570 select BOARD_EARLY_INIT_F
5ed063d1 571 select CPU_ARM926EJS
d10fc50f 572 select PL011_SERIAL
5ed063d1 573 imply CMD_SAVES
dd84058d
MY
574
575config TARGET_SPEAR600
576 bool "Support spear600"
a5d67547 577 select BOARD_EARLY_INIT_F
5ed063d1 578 select CPU_ARM926EJS
d10fc50f 579 select PL011_SERIAL
5ed063d1 580 imply CMD_SAVES
dd84058d 581
9fa32b12
VM
582config TARGET_STV0991
583 bool "Support stv0991"
acf15001 584 select CPU_V7A
cac0ca76
MY
585 select DM
586 select DM_SERIAL
e67abcaa
VM
587 select DM_SPI
588 select DM_SPI_FLASH
5ed063d1 589 select PL01X_SERIAL
f1b1f770 590 select SPI
e67abcaa 591 select SPI_FLASH
08a00cba 592 imply CMD_DM
9fa32b12 593
dd84058d
MY
594config TARGET_X600
595 bool "Support x600"
e5ec4815 596 select BOARD_LATE_INIT
2e07c249 597 select CPU_ARM926EJS
d10fc50f 598 select PL011_SERIAL
5ed063d1 599 select SUPPORT_SPL
dd84058d 600
dd84058d
MY
601config TARGET_FLEA3
602 bool "Support flea3"
2e07c249 603 select CPU_ARM1136
dd84058d
MY
604
605config TARGET_MX35PDK
606 bool "Support mx35pdk"
e5ec4815 607 select BOARD_LATE_INIT
2e07c249 608 select CPU_ARM1136
dd84058d 609
ddf6bd48
MY
610config ARCH_BCM283X
611 bool "Broadcom BCM283X family"
58d423b8 612 select DM
58d423b8 613 select DM_GPIO
5ed063d1 614 select DM_SERIAL
76709096 615 select OF_CONTROL
cf2c7784 616 select PL01X_SERIAL
ae5326a6 617 select SERIAL_SEARCH_ALL
08a00cba 618 imply CMD_DM
91d27a17 619 imply FAT_WRITE
46414296 620
ea1a7de5
PR
621config ARCH_BCM63158
622 bool "Broadcom BCM63158 family"
623 select DM
624 select OF_CONTROL
625 imply CMD_DM
626
6454e95f
PR
627config ARCH_BCM68360
628 bool "Broadcom BCM68360 family"
629 select DM
630 select OF_CONTROL
631 imply CMD_DM
632
40b59b05
PR
633config ARCH_BCM6858
634 bool "Broadcom BCM6858 family"
635 select DM
636 select OF_CONTROL
637 imply CMD_DM
638
dd84058d
MY
639config TARGET_VEXPRESS_CA15_TC2
640 bool "Support vexpress_ca15_tc2"
acf15001 641 select CPU_V7A
ea624e19
HG
642 select CPU_V7_HAS_NONSEC
643 select CPU_V7_HAS_VIRT
d10fc50f 644 select PL011_SERIAL
dd84058d 645
894c3ad2
TF
646config ARCH_BCMSTB
647 bool "Broadcom BCM7XXX family"
648 select CPU_V7A
649 select DM
650 select OF_CONTROL
651 select OF_PRIOR_STAGE
08a00cba 652 imply CMD_DM
894c3ad2
TF
653 help
654 This enables support for Broadcom ARM-based set-top box
655 chipsets, including the 7445 family of chips.
656
dd84058d
MY
657config TARGET_VEXPRESS_CA5X2
658 bool "Support vexpress_ca5x2"
acf15001 659 select CPU_V7A
d10fc50f 660 select PL011_SERIAL
dd84058d
MY
661
662config TARGET_VEXPRESS_CA9X4
663 bool "Support vexpress_ca9x4"
acf15001 664 select CPU_V7A
d10fc50f 665 select PL011_SERIAL
dd84058d 666
43486e4c
SR
667config TARGET_BCM23550_W1D
668 bool "Support bcm23550_w1d"
acf15001 669 select CPU_V7A
221a949e 670 imply CRC32_VERIFY
91d27a17 671 imply FAT_WRITE
43486e4c 672
dd84058d
MY
673config TARGET_BCM28155_AP
674 bool "Support bcm28155_ap"
acf15001 675 select CPU_V7A
221a949e 676 imply CRC32_VERIFY
91d27a17 677 imply FAT_WRITE
dd84058d 678
abb1678c
SR
679config TARGET_BCMCYGNUS
680 bool "Support bcmcygnus"
acf15001 681 select CPU_V7A
5ed063d1
MS
682 imply BCM_SF2_ETH
683 imply BCM_SF2_ETH_GMAC
551c3934 684 imply CMD_HASH
5ed063d1 685 imply CRC32_VERIFY
91d27a17 686 imply FAT_WRITE
221a949e 687 imply HASH_VERIFY
c89782dc 688 imply NETDEVICES
9dec5270 689
abb1678c
SR
690config TARGET_BCMNSP
691 bool "Support bcmnsp"
acf15001 692 select CPU_V7A
9dec5270 693
274bced8
JM
694config TARGET_BCMNS2
695 bool "Support Broadcom Northstar2"
696 select ARM64
697 help
698 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
699 ARMv8 Cortex-A57 processors targeting a broad range of networking
e852b30b 700 applications.
274bced8 701
72df68cc
MY
702config ARCH_EXYNOS
703 bool "Samsung EXYNOS"
58d423b8 704 select DM
5ed063d1 705 select DM_GPIO
fc47cf9d 706 select DM_I2C
5ed063d1 707 select DM_KEYBOARD
58d423b8
MY
708 select DM_SERIAL
709 select DM_SPI
5ed063d1 710 select DM_SPI_FLASH
f1b1f770 711 select SPI
c96d9036 712 imply SYS_THUMB_BUILD
08a00cba 713 imply CMD_DM
91d27a17 714 imply FAT_WRITE
dd84058d 715
311757be
SG
716config ARCH_S5PC1XX
717 bool "Samsung S5PC1XX"
acf15001 718 select CPU_V7A
58d423b8 719 select DM
58d423b8 720 select DM_GPIO
08848e9c 721 select DM_I2C
5ed063d1 722 select DM_SERIAL
08a00cba 723 imply CMD_DM
311757be 724
ef2b694c
MY
725config ARCH_HIGHBANK
726 bool "Calxeda Highbank"
acf15001 727 select CPU_V7A
d10fc50f 728 select PL011_SERIAL
dd84058d 729
5cbbd9bd
MY
730config ARCH_INTEGRATOR
731 bool "ARM Ltd. Integrator family"
3f394e70
LW
732 select DM
733 select DM_SERIAL
cf2c7784 734 select PL01X_SERIAL
08a00cba 735 imply CMD_DM
5cbbd9bd 736
c338f09e
MY
737config ARCH_KEYSTONE
738 bool "TI Keystone"
5ed063d1 739 select CMD_POWEROFF
acf15001 740 select CPU_V7A
02627356 741 select SUPPORT_SPL
7842b6a9 742 select SYS_ARCH_TIMER
5ed063d1 743 select SYS_THUMB_BUILD
d56b4b19 744 imply CMD_MTDPARTS
15dc63d6 745 imply CMD_SAVES
5ed063d1 746 imply FIT
dd84058d 747
586bde93
LV
748config ARCH_K3
749 bool "Texas Instruments' K3 Architecture"
750 select SPL
751 select SUPPORT_SPL
752 select FIT
753
a93fbf4a
MY
754config ARCH_OMAP2PLUS
755 bool "TI OMAP2+"
acf15001 756 select CPU_V7A
0680f1b1 757 select SPL_BOARD_INIT if SPL
ff6c3125 758 select SPL_STACK_R if SPL
a93fbf4a
MY
759 select SUPPORT_SPL
760 imply FIT
761
bfcef28a
BG
762config ARCH_MESON
763 bool "Amlogic Meson"
7325f6cf 764 imply DISTRO_DEFAULTS
bfcef28a
BG
765 help
766 Support for the Meson SoC family developed by Amlogic Inc.,
767 targeted at media players and tablet computers. We currently
768 support the S905 (GXBaby) 64-bit SoC.
769
cbd2fba1
RL
770config ARCH_MEDIATEK
771 bool "MediaTek SoCs"
cbd2fba1
RL
772 select DM
773 select OF_CONTROL
774 select SPL_DM if SPL
775 select SPL_LIBCOMMON_SUPPORT if SPL
776 select SPL_LIBGENERIC_SUPPORT if SPL
777 select SPL_OF_CONTROL if SPL
778 select SUPPORT_SPL
779 help
780 Support for the MediaTek SoCs family developed by MediaTek Inc.
781 Please refer to doc/README.mediatek for more information.
782
ee54dfea
VZ
783config ARCH_LPC32XX
784 bool "NXP LPC32xx platform"
785 select CPU_ARM926EJS
786 select DM
787 select DM_GPIO
788 select DM_SERIAL
789 select SPL_DM if SPL
790 select SUPPORT_SPL
791 imply CMD_DM
792
b2b8b9be
PF
793config ARCH_IMX8
794 bool "NXP i.MX8 platform"
795 select ARM64
796 select DM
797 select OF_CONTROL
9a273858 798 select ENABLE_ARM_SOC_BOOT0_HOOK
b2b8b9be 799
cd357ad1 800config ARCH_IMX8M
7a7391fd
PF
801 bool "NXP i.MX8M platform"
802 select ARM64
803 select DM
804 select SUPPORT_SPL
08a00cba 805 imply CMD_DM
7a7391fd 806
77eb9a90
GB
807config ARCH_IMXRT
808 bool "NXP i.MXRT platform"
809 select CPU_V7M
810 select DM
811 select DM_SERIAL
812 select SUPPORT_SPL
813 imply CMD_DM
814
c5343d4e
SA
815config ARCH_MX23
816 bool "NXP i.MX23 family"
817 select CPU_ARM926EJS
818 select PL011_SERIAL
819 select SUPPORT_SPL
820
07df697e
FE
821config ARCH_MX25
822 bool "NXP MX25"
823 select CPU_ARM926EJS
8bbff6a7 824 imply MXC_GPIO
07df697e 825
25c5b4e1
SA
826config ARCH_MX28
827 bool "NXP i.MX28 family"
828 select CPU_ARM926EJS
829 select PL011_SERIAL
830 select SUPPORT_SPL
831
3159ec64
ML
832config ARCH_MX31
833 bool "NXP i.MX31 family"
834 select CPU_ARM1136
835
e90a08da 836config ARCH_MX7ULP
6e7bdde4 837 bool "NXP MX7ULP"
acf15001 838 select CPU_V7A
e90a08da 839 select ROM_UNIFIED_SECTIONS
8bbff6a7 840 imply MXC_GPIO
44ad4961 841 imply SYS_THUMB_BUILD
e90a08da 842
1a8150d4
AA
843config ARCH_MX7
844 bool "Freescale MX7"
5ed063d1
MS
845 select ARCH_MISC_INIT
846 select BOARD_EARLY_INIT_F
acf15001 847 select CPU_V7A
d714a75f 848 select SYS_FSL_HAS_SEC if IMX_HAB
2c2e2c9e 849 select SYS_FSL_SEC_COMPAT_4
90b80386 850 select SYS_FSL_SEC_LE
8bbff6a7 851 imply MXC_GPIO
44ad4961 852 imply SYS_THUMB_BUILD
1a8150d4 853
89ebc821
BB
854config ARCH_MX6
855 bool "Freescale MX6"
acf15001 856 select CPU_V7A
d714a75f 857 select SYS_FSL_HAS_SEC if IMX_HAB
2c2e2c9e 858 select SYS_FSL_SEC_COMPAT_4
90b80386 859 select SYS_FSL_SEC_LE
8bbff6a7 860 imply MXC_GPIO
44ad4961 861 imply SYS_THUMB_BUILD
89ebc821 862
b529993e
PT
863if ARCH_MX6
864config SPL_LDSCRIPT
6e7bdde4 865 default "arch/arm/mach-omap2/u-boot-spl.lds"
b529993e
PT
866endif
867
424ee3d1
AR
868config ARCH_MX5
869 bool "Freescale MX5"
a5d67547 870 select BOARD_EARLY_INIT_F
5ed063d1 871 select CPU_V7A
8bbff6a7 872 imply MXC_GPIO
424ee3d1 873
97775d26
MS
874config ARCH_OWL
875 bool "Actions Semi OWL SoCs"
876 select ARM64
877 select DM
878 select DM_SERIAL
879 select OF_CONTROL
08a00cba 880 imply CMD_DM
97775d26 881
32f11829
TT
882config ARCH_QEMU
883 bool "QEMU Virtual Platform"
70a64a07 884 select ARCH_SUPPORT_TFABOOT
32f11829
TT
885 select DM
886 select DM_SERIAL
887 select OF_CONTROL
cf2c7784 888 select PL01X_SERIAL
08a00cba 889 imply CMD_DM
a47c1b5b
AT
890 imply DM_RTC
891 imply RTC_PL031
32f11829 892
1cc95f6e 893config ARCH_RMOBILE
f40b9898 894 bool "Renesas ARM SoCs"
35295964 895 select BOARD_EARLY_INIT_F if !RZA1
1cc95f6e
NI
896 select DM
897 select DM_SERIAL
08a00cba 898 imply CMD_DM
91d27a17 899 imply FAT_WRITE
3a649407 900 imply SYS_THUMB_BUILD
00e4b57e 901 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
dd84058d 902
9702ec00
EP
903config TARGET_S32V234EVB
904 bool "Support s32v234evb"
905 select ARM64
c01e4a1a 906 select SYS_FSL_ERRATUM_ESDHC111
9702ec00 907
08592136
MK
908config ARCH_SNAPDRAGON
909 bool "Qualcomm Snapdragon SoCs"
910 select ARM64
911 select DM
912 select DM_GPIO
913 select DM_SERIAL
5ed063d1 914 select MSM_SMEM
08592136
MK
915 select OF_CONTROL
916 select OF_SEPARATE
654dd4a8 917 select SMEM
5ed063d1 918 select SPMI
08a00cba 919 imply CMD_DM
08592136 920
7865f4b0
MY
921config ARCH_SOCFPGA
922 bool "Altera SOCFPGA family"
48befc00 923 select ARCH_EARLY_INIT_R
d6a61da4 924 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
a76b711d 925 select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
a684729a 926 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1d9aa3e5 927 select DM
73172753 928 select DM_SERIAL
a684729a 929 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
48befc00 930 select OF_CONTROL
00057eea 931 select SPL_DM_RESET if DM_RESET
5ed063d1 932 select SPL_DM_SERIAL
48befc00 933 select SPL_LIBCOMMON_SUPPORT
48befc00 934 select SPL_LIBGENERIC_SUPPORT
48befc00
MV
935 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
936 select SPL_OF_CONTROL
a76b711d 937 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
48befc00 938 select SPL_SERIAL_SUPPORT
ef72ba0b 939 select SPL_SYSRESET
48befc00
MV
940 select SPL_WATCHDOG_SUPPORT
941 select SUPPORT_SPL
73172753 942 select SYS_NS16550
a684729a 943 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
ef72ba0b
SG
944 select SYSRESET
945 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
63b312d8 946 select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
08a00cba 947 imply CMD_DM
d56b4b19 948 imply CMD_MTDPARTS
221a949e 949 imply CRC32_VERIFY
fef4a545
SG
950 imply DM_SPI
951 imply DM_SPI_FLASH
91d27a17 952 imply FAT_WRITE
aef44283
SG
953 imply SPL
954 imply SPL_DM
a9024dc1
SG
955 imply SPL_LIBDISK_SUPPORT
956 imply SPL_MMC_SUPPORT
fef4a545 957 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
f48db4ed 958 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
a9024dc1
SG
959 imply SPL_SPI_FLASH_SUPPORT
960 imply SPL_SPI_SUPPORT
aaa64803 961 imply L2X0_CACHE
dd84058d 962
2c7e3b90
IC
963config ARCH_SUNXI
964 bool "Support sunxi (Allwinner) SoCs"
d6a0c78a 965 select BINMAN
88bb800d 966 select CMD_GPIO
0878a8a7 967 select CMD_MMC if MMC
2997ee50 968 select CMD_USB if DISTRO_DEFAULTS
e236ff0a 969 select CLK
b6006baf 970 select DM
45368827 971 select DM_ETH
211d57a4
HG
972 select DM_GPIO
973 select DM_KEYBOARD
bb3362b0
JT
974 select DM_MMC if MMC
975 select DM_SCSI if SCSI
45368827 976 select DM_SERIAL
2997ee50 977 select DM_USB if DISTRO_DEFAULTS
d75111a7 978 select OF_BOARD_SETUP
b6006baf
HG
979 select OF_CONTROL
980 select OF_SEPARATE
6f6b7cfa 981 select SPECIFY_CONSOLE_INDEX
ab43de80
TR
982 select SPL_STACK_R if SPL
983 select SPL_SYS_MALLOC_SIMPLE if SPL
3a649407 984 select SPL_SYS_THUMB_BUILD if !ARM64
10cfbaab 985 select SUNXI_GPIO
5ed063d1 986 select SYS_NS16550
ce2e44d8 987 select SYS_THUMB_BUILD if !ARM64
2997ee50 988 select USB if DISTRO_DEFAULTS
2997ee50 989 select USB_KEYBOARD if DISTRO_DEFAULTS
5ed063d1 990 select USB_STORAGE if DISTRO_DEFAULTS
27084c03 991 select SPL_USE_TINY_PRINTF
48313fe5
AP
992 select USE_PREBOOT
993 select SYS_RELOC_GD_ENV_ADDR
08a00cba 994 imply CMD_DM
a12fb0e3 995 imply CMD_GPT
88718be3 996 imply CMD_UBI if MTD_RAW_NAND
7325f6cf 997 imply DISTRO_DEFAULTS
91d27a17 998 imply FAT_WRITE
2f13cf35 999 imply FIT
eff264d7 1000 imply OF_LIBFDT_OVERLAY
af83a604
MY
1001 imply PRE_CONSOLE_BUFFER
1002 imply SPL_GPIO_SUPPORT
1003 imply SPL_LIBCOMMON_SUPPORT
af83a604 1004 imply SPL_LIBGENERIC_SUPPORT
4aa2ba3a 1005 imply SPL_MMC_SUPPORT if MMC
af83a604
MY
1006 imply SPL_POWER_SUPPORT
1007 imply SPL_SERIAL_SUPPORT
654b02b1 1008 imply USB_GADGET
8ebe4f42 1009
689088f9
SG
1010config ARCH_U8500
1011 bool "ST-Ericsson U8500 Series"
1012 select CPU_V7A
1013 select DM
1014 select DM_GPIO
1015 select DM_MMC if MMC
1016 select DM_SERIAL
1017 select DM_USB if USB
1018 select OF_CONTROL
1019 select SYSRESET
1020 select TIMER
1021 imply ARM_PL180_MMCI
1022 imply DM_RTC
1023 imply NOMADIK_MTU_TIMER
1024 imply PL01X_SERIAL
1025 imply RTC_PL031
1026 imply SYSRESET_SYSCON
1027
ec48b6c9
MS
1028config ARCH_VERSAL
1029 bool "Support Xilinx Versal Platform"
1030 select ARM64
1031 select CLK
1032 select DM
fa797157
MS
1033 select DM_ETH if NET
1034 select DM_MMC if MMC
ec48b6c9
MS
1035 select DM_SERIAL
1036 select OF_CONTROL
bfd092f9 1037 imply BOARD_LATE_INIT
ec48b6c9 1038
7966b437
SA
1039config ARCH_VF610
1040 bool "Freescale Vybrid"
acf15001 1041 select CPU_V7A
c01e4a1a 1042 select SYS_FSL_ERRATUM_ESDHC111
d56b4b19 1043 imply CMD_MTDPARTS
88718be3 1044 imply MTD_RAW_NAND
e7b860fa 1045
5ca269a4 1046config ARCH_ZYNQ
b8d4497f 1047 bool "Xilinx Zynq based platform"
5ed063d1
MS
1048 select CLK
1049 select CLK_ZYNQ
acf15001 1050 select CPU_V7A
8981f05c 1051 select DM
c4a142f4 1052 select DM_ETH if NET
c4a142f4 1053 select DM_MMC if MMC
42800ffa 1054 select DM_SERIAL
5ed063d1 1055 select DM_SPI
9f7a4502 1056 select DM_SPI_FLASH
dec49e86 1057 select DM_USB if USB
5ed063d1 1058 select OF_CONTROL
f1b1f770 1059 select SPI
5ed063d1
MS
1060 select SPL_BOARD_INIT if SPL
1061 select SPL_CLK if SPL
1062 select SPL_DM if SPL
1063 select SPL_OF_CONTROL if SPL
1064 select SPL_SEPARATE_BSS if SPL
1065 select SUPPORT_SPL
1066 imply ARCH_EARLY_INIT_R
8eb55e19 1067 imply BOARD_LATE_INIT
d315628e 1068 imply CMD_CLK
08a00cba 1069 imply CMD_DM
72c3033f 1070 imply CMD_SPL
5ed063d1 1071 imply FAT_WRITE
dd84058d 1072
1d6c54ec
MS
1073config ARCH_ZYNQMP_R5
1074 bool "Xilinx ZynqMP R5 based platform"
5ed063d1 1075 select CLK
1d6c54ec 1076 select CPU_V7R
1d6c54ec 1077 select DM
6f96fb50
MS
1078 select DM_ETH if NET
1079 select DM_MMC if MMC
1d6c54ec 1080 select DM_SERIAL
5ed063d1 1081 select OF_CONTROL
08a00cba 1082 imply CMD_DM
687ab545 1083 imply DM_USB_GADGET
1d6c54ec 1084
0b54a9dd 1085config ARCH_ZYNQMP
b8d4497f 1086 bool "Xilinx ZynqMP based platform"
84c7204b 1087 select ARM64
5ed063d1 1088 select CLK
c2490bf5 1089 select DM
fb693108 1090 select DM_ETH if NET
1327d167 1091 select DM_MAILBOX
fb693108 1092 select DM_MMC if MMC
c2490bf5 1093 select DM_SERIAL
088f83ee
MS
1094 select DM_SPI if SPI
1095 select DM_SPI_FLASH if DM_SPI
5ed063d1 1096 select DM_USB if USB
325a22dc 1097 select FIRMWARE
5ed063d1 1098 select OF_CONTROL
0680f1b1 1099 select SPL_BOARD_INIT if SPL
2f03968e 1100 select SPL_CLK if SPL
325a22dc
IE
1101 select SPL_DM_MAILBOX if SPL
1102 select SPL_FIRMWARE if SPL
850e7795 1103 select SPL_SEPARATE_BSS if SPL
5ed063d1 1104 select SUPPORT_SPL
1327d167 1105 select ZYNQMP_IPI
8eb55e19 1106 imply BOARD_LATE_INIT
08a00cba 1107 imply CMD_DM
91d27a17 1108 imply FAT_WRITE
22270ca0 1109 imply MP
687ab545 1110 imply DM_USB_GADGET
84c7204b 1111
ddd960e6
MY
1112config TEGRA
1113 bool "NVIDIA Tegra"
7325f6cf 1114 imply DISTRO_DEFAULTS
91d27a17 1115 imply FAT_WRITE
dd84058d 1116
f91afc4d 1117config TARGET_VEXPRESS64_AEMV8A
dd84058d 1118 bool "Support vexpress_aemv8a"
016a954e 1119 select ARM64
cf2c7784 1120 select PL01X_SERIAL
dd84058d 1121
f91afc4d
LW
1122config TARGET_VEXPRESS64_BASE_FVP
1123 bool "Support Versatile Express ARMv8a FVP BASE model"
1124 select ARM64
cf2c7784 1125 select PL01X_SERIAL
5ed063d1 1126 select SEMIHOSTING
f91afc4d 1127
ffc10373
LW
1128config TARGET_VEXPRESS64_JUNO
1129 bool "Support Versatile Express Juno Development Platform"
1130 select ARM64
cf2c7784 1131 select PL01X_SERIAL
ffc10373 1132
44937214
PK
1133config TARGET_LS2080A_EMU
1134 bool "Support ls2080a_emu"
fb2bf8c2 1135 select ARCH_LS2080A
016a954e 1136 select ARM64
23b5877c 1137 select ARMV8_MULTIENTRY
32413125 1138 select FSL_DDR_SYNC_REFRESH
44937214 1139 help
e852b30b
RD
1140 Support for Freescale LS2080A_EMU platform.
1141 The LS2080A Development System (EMULATOR) is a pre-silicon
44937214
PK
1142 development platform that supports the QorIQ LS2080A
1143 Layerscape Architecture processor.
dd84058d 1144
44937214
PK
1145config TARGET_LS2080A_SIMU
1146 bool "Support ls2080a_simu"
fb2bf8c2 1147 select ARCH_LS2080A
016a954e 1148 select ARM64
23b5877c 1149 select ARMV8_MULTIENTRY
acf40f50 1150 select BOARD_LATE_INIT
44937214 1151 help
e852b30b 1152 Support for Freescale LS2080A_SIMU platform.
44937214
PK
1153 The LS2080A Development System (QDS) is a pre silicon
1154 development platform that supports the QorIQ LS2080A
1155 Layerscape Architecture processor.
dd84058d 1156
7769776a
AK
1157config TARGET_LS1088AQDS
1158 bool "Support ls1088aqds"
1159 select ARCH_LS1088A
1160 select ARM64
1161 select ARMV8_MULTIENTRY
6324d506 1162 select ARCH_SUPPORT_TFABOOT
7769776a 1163 select BOARD_LATE_INIT
91fded62 1164 select SUPPORT_SPL
32413125 1165 select FSL_DDR_INTERACTIVE if !SD_BOOT
7769776a 1166 help
e852b30b 1167 Support for NXP LS1088AQDS platform.
7769776a
AK
1168 The LS1088A Development System (QDS) is a high-performance
1169 development platform that supports the QorIQ LS1088A
1170 Layerscape Architecture processor.
1171
44937214
PK
1172config TARGET_LS2080AQDS
1173 bool "Support ls2080aqds"
fb2bf8c2 1174 select ARCH_LS2080A
7288c2c2
YS
1175 select ARM64
1176 select ARMV8_MULTIENTRY
6324d506 1177 select ARCH_SUPPORT_TFABOOT
e5ec4815 1178 select BOARD_LATE_INIT
b2d5ac59 1179 select SUPPORT_SPL
fedb428c 1180 imply SCSI
9fd95ef0 1181 imply SCSI_AHCI
32413125
RB
1182 select FSL_DDR_BIST
1183 select FSL_DDR_INTERACTIVE if !SPL
7288c2c2 1184 help
e852b30b 1185 Support for Freescale LS2080AQDS platform.
44937214
PK
1186 The LS2080A Development System (QDS) is a high-performance
1187 development platform that supports the QorIQ LS2080A
7288c2c2
YS
1188 Layerscape Architecture processor.
1189
44937214
PK
1190config TARGET_LS2080ARDB
1191 bool "Support ls2080ardb"
fb2bf8c2 1192 select ARCH_LS2080A
e2b65ea9
YS
1193 select ARM64
1194 select ARMV8_MULTIENTRY
6324d506 1195 select ARCH_SUPPORT_TFABOOT
e5ec4815 1196 select BOARD_LATE_INIT
32eda7cc 1197 select SUPPORT_SPL
32413125
RB
1198 select FSL_DDR_BIST
1199 select FSL_DDR_INTERACTIVE if !SPL
fedb428c 1200 imply SCSI
9fd95ef0 1201 imply SCSI_AHCI
e2b65ea9 1202 help
44937214
PK
1203 Support for Freescale LS2080ARDB platform.
1204 The LS2080A Reference design board (RDB) is a high-performance
1205 development platform that supports the QorIQ LS2080A
e2b65ea9
YS
1206 Layerscape Architecture processor.
1207
3049a583
PJ
1208config TARGET_LS2081ARDB
1209 bool "Support ls2081ardb"
1210 select ARCH_LS2080A
1211 select ARM64
1212 select ARMV8_MULTIENTRY
1213 select BOARD_LATE_INIT
1214 select SUPPORT_SPL
3049a583
PJ
1215 help
1216 Support for Freescale LS2081ARDB platform.
1217 The LS2081A Reference design board (RDB) is a high-performance
1218 development platform that supports the QorIQ LS2081A/LS2041A
1219 Layerscape Architecture processor.
1220
58c3e620
PJ
1221config TARGET_LX2160ARDB
1222 bool "Support lx2160ardb"
1223 select ARCH_LX2160A
58c3e620
PJ
1224 select ARM64
1225 select ARMV8_MULTIENTRY
6324d506 1226 select ARCH_SUPPORT_TFABOOT
58c3e620
PJ
1227 select BOARD_LATE_INIT
1228 help
1229 Support for NXP LX2160ARDB platform.
1230 The lx2160ardb (LX2160A Reference design board (RDB)
1231 is a high-performance development platform that supports the
1232 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1233
1eba723c
PB
1234config TARGET_LX2160AQDS
1235 bool "Support lx2160aqds"
1236 select ARCH_LX2160A
1eba723c
PB
1237 select ARM64
1238 select ARMV8_MULTIENTRY
6324d506 1239 select ARCH_SUPPORT_TFABOOT
1eba723c
PB
1240 select BOARD_LATE_INIT
1241 help
1242 Support for NXP LX2160AQDS platform.
1243 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1244 is a high-performance development platform that supports the
1245 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1246
11ac2363
PG
1247config TARGET_HIKEY
1248 bool "Support HiKey 96boards Consumer Edition Platform"
1249 select ARM64
efd7b60a
PG
1250 select DM
1251 select DM_GPIO
9c71bcdc 1252 select DM_SERIAL
cd593ed6 1253 select OF_CONTROL
cf2c7784 1254 select PL01X_SERIAL
6f6b7cfa 1255 select SPECIFY_CONSOLE_INDEX
08a00cba 1256 imply CMD_DM
11ac2363
PG
1257 help
1258 Support for HiKey 96boards platform. It features a HI6220
1259 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1260
c62c7ef7
MS
1261config TARGET_HIKEY960
1262 bool "Support HiKey960 96boards Consumer Edition Platform"
1263 select ARM64
1264 select DM
1265 select DM_SERIAL
1266 select OF_CONTROL
1267 select PL01X_SERIAL
1268 imply CMD_DM
1269 help
1270 Support for HiKey960 96boards platform. It features a HI3660
1271 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1272
d754254f
JRO
1273config TARGET_POPLAR
1274 bool "Support Poplar 96boards Enterprise Edition Platform"
1275 select ARM64
1276 select DM
d754254f
JRO
1277 select DM_SERIAL
1278 select DM_USB
5ed063d1 1279 select OF_CONTROL
cf2c7784 1280 select PL01X_SERIAL
08a00cba 1281 imply CMD_DM
d754254f
JRO
1282 help
1283 Support for Poplar 96boards EE platform. It features a HI3798cv200
1284 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1285 making it capable of running any commercial set-top solution based on
1286 Linux or Android.
1287
9d044fcb
PK
1288config TARGET_LS1012AQDS
1289 bool "Support ls1012aqds"
9533acf3 1290 select ARCH_LS1012A
9d044fcb 1291 select ARM64
6324d506 1292 select ARCH_SUPPORT_TFABOOT
e5ec4815 1293 select BOARD_LATE_INIT
9d044fcb
PK
1294 help
1295 Support for Freescale LS1012AQDS platform.
1296 The LS1012A Development System (QDS) is a high-performance
1297 development platform that supports the QorIQ LS1012A
1298 Layerscape Architecture processor.
1299
3b6e3898
PK
1300config TARGET_LS1012ARDB
1301 bool "Support ls1012ardb"
9533acf3 1302 select ARCH_LS1012A
3b6e3898 1303 select ARM64
6324d506 1304 select ARCH_SUPPORT_TFABOOT
e5ec4815 1305 select BOARD_LATE_INIT
fedb428c 1306 imply SCSI
9fd95ef0 1307 imply SCSI_AHCI
3b6e3898
PK
1308 help
1309 Support for Freescale LS1012ARDB platform.
1310 The LS1012A Reference design board (RDB) is a high-performance
1311 development platform that supports the QorIQ LS1012A
1312 Layerscape Architecture processor.
1313
b0ce187b
BU
1314config TARGET_LS1012A2G5RDB
1315 bool "Support ls1012a2g5rdb"
1316 select ARCH_LS1012A
1317 select ARM64
6324d506 1318 select ARCH_SUPPORT_TFABOOT
b0ce187b
BU
1319 select BOARD_LATE_INIT
1320 imply SCSI
1321 help
1322 Support for Freescale LS1012A2G5RDB platform.
1323 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1324 development platform that supports the QorIQ LS1012A
1325 Layerscape Architecture processor.
1326
9629ccdd
BU
1327config TARGET_LS1012AFRWY
1328 bool "Support ls1012afrwy"
1329 select ARCH_LS1012A
1330 select ARM64
6324d506 1331 select ARCH_SUPPORT_TFABOOT
5ed063d1 1332 select BOARD_LATE_INIT
9629ccdd
BU
1333 imply SCSI
1334 imply SCSI_AHCI
1335 help
1336 Support for Freescale LS1012AFRWY platform.
1337 The LS1012A FRWY board (FRWY) is a high-performance
1338 development platform that supports the QorIQ LS1012A
1339 Layerscape Architecture processor.
1340
ff78aa2b
PK
1341config TARGET_LS1012AFRDM
1342 bool "Support ls1012afrdm"
9533acf3 1343 select ARCH_LS1012A
ff78aa2b 1344 select ARM64
6324d506 1345 select ARCH_SUPPORT_TFABOOT
ff78aa2b
PK
1346 help
1347 Support for Freescale LS1012AFRDM platform.
1348 The LS1012A Freedom board (FRDM) is a high-performance
1349 development platform that supports the QorIQ LS1012A
1350 Layerscape Architecture processor.
1351
f278a217
YT
1352config TARGET_LS1028AQDS
1353 bool "Support ls1028aqds"
1354 select ARCH_LS1028A
1355 select ARM64
1356 select ARMV8_MULTIENTRY
6324d506 1357 select ARCH_SUPPORT_TFABOOT
acf40f50 1358 select BOARD_LATE_INIT
f278a217
YT
1359 help
1360 Support for Freescale LS1028AQDS platform
1361 The LS1028A Development System (QDS) is a high-performance
1362 development platform that supports the QorIQ LS1028A
1363 Layerscape Architecture processor.
1364
353f36d9
YT
1365config TARGET_LS1028ARDB
1366 bool "Support ls1028ardb"
1367 select ARCH_LS1028A
1368 select ARM64
1369 select ARMV8_MULTIENTRY
6324d506 1370 select ARCH_SUPPORT_TFABOOT
c40ebf7e 1371 select BOARD_LATE_INIT
353f36d9
YT
1372 help
1373 Support for Freescale LS1028ARDB platform
1374 The LS1028A Development System (RDB) is a high-performance
1375 development platform that supports the QorIQ LS1028A
1376 Layerscape Architecture processor.
1377
e84a324b
AK
1378config TARGET_LS1088ARDB
1379 bool "Support ls1088ardb"
1380 select ARCH_LS1088A
1381 select ARM64
1382 select ARMV8_MULTIENTRY
6324d506 1383 select ARCH_SUPPORT_TFABOOT
e84a324b 1384 select BOARD_LATE_INIT
099f4093 1385 select SUPPORT_SPL
32413125 1386 select FSL_DDR_INTERACTIVE if !SD_BOOT
e84a324b
AK
1387 help
1388 Support for NXP LS1088ARDB platform.
1389 The LS1088A Reference design board (RDB) is a high-performance
1390 development platform that supports the QorIQ LS1088A
1391 Layerscape Architecture processor.
1392
550e3dc0 1393config TARGET_LS1021AQDS
0de15707 1394 bool "Support ls1021aqds"
5ed063d1
MS
1395 select ARCH_LS1021A
1396 select ARCH_SUPPORT_PSCI
1397 select BOARD_EARLY_INIT_F
e5ec4815 1398 select BOARD_LATE_INIT
acf15001 1399 select CPU_V7A
adee1d4c
HZ
1400 select CPU_V7_HAS_NONSEC
1401 select CPU_V7_HAS_VIRT
5e8bd7e1 1402 select LS1_DEEP_SLEEP
5ed063d1 1403 select SUPPORT_SPL
d26e34c4 1404 select SYS_FSL_DDR
32413125 1405 select FSL_DDR_INTERACTIVE
fedb428c 1406 imply SCSI
217f92bb 1407
c8a7d9da 1408config TARGET_LS1021ATWR
0de15707 1409 bool "Support ls1021atwr"
5ed063d1
MS
1410 select ARCH_LS1021A
1411 select ARCH_SUPPORT_PSCI
1412 select BOARD_EARLY_INIT_F
e5ec4815 1413 select BOARD_LATE_INIT
acf15001 1414 select CPU_V7A
adee1d4c
HZ
1415 select CPU_V7_HAS_NONSEC
1416 select CPU_V7_HAS_VIRT
5e8bd7e1 1417 select LS1_DEEP_SLEEP
5ed063d1 1418 select SUPPORT_SPL
fedb428c 1419 imply SCSI
c8a7d9da 1420
87821220
JW
1421config TARGET_LS1021ATSN
1422 bool "Support ls1021atsn"
1423 select ARCH_LS1021A
1424 select ARCH_SUPPORT_PSCI
1425 select BOARD_EARLY_INIT_F
1426 select BOARD_LATE_INIT
1427 select CPU_V7A
1428 select CPU_V7_HAS_NONSEC
1429 select CPU_V7_HAS_VIRT
1430 select LS1_DEEP_SLEEP
1431 select SUPPORT_SPL
1432 imply SCSI
1433
20c700f8
FL
1434config TARGET_LS1021AIOT
1435 bool "Support ls1021aiot"
5ed063d1
MS
1436 select ARCH_LS1021A
1437 select ARCH_SUPPORT_PSCI
e5ec4815 1438 select BOARD_LATE_INIT
acf15001 1439 select CPU_V7A
20c700f8
FL
1440 select CPU_V7_HAS_NONSEC
1441 select CPU_V7_HAS_VIRT
1442 select SUPPORT_SPL
fedb428c 1443 imply SCSI
20c700f8
FL
1444 help
1445 Support for Freescale LS1021AIOT platform.
1446 The LS1021A Freescale board (IOT) is a high-performance
1447 development platform that supports the QorIQ LS1021A
1448 Layerscape Architecture processor.
1449
02b5d2ed
SX
1450config TARGET_LS1043AQDS
1451 bool "Support ls1043aqds"
0a37cf8f 1452 select ARCH_LS1043A
02b5d2ed
SX
1453 select ARM64
1454 select ARMV8_MULTIENTRY
6324d506 1455 select ARCH_SUPPORT_TFABOOT
5ed063d1 1456 select BOARD_EARLY_INIT_F
e5ec4815 1457 select BOARD_LATE_INIT
02b5d2ed 1458 select SUPPORT_SPL
32413125 1459 select FSL_DDR_INTERACTIVE if !SPL
fedb428c 1460 imply SCSI
f11e492a 1461 imply SCSI_AHCI
02b5d2ed
SX
1462 help
1463 Support for Freescale LS1043AQDS platform.
1464
f3a8e2b7
MH
1465config TARGET_LS1043ARDB
1466 bool "Support ls1043ardb"
0a37cf8f 1467 select ARCH_LS1043A
f3a8e2b7 1468 select ARM64
831c068f 1469 select ARMV8_MULTIENTRY
6324d506 1470 select ARCH_SUPPORT_TFABOOT
5ed063d1 1471 select BOARD_EARLY_INIT_F
e5ec4815 1472 select BOARD_LATE_INIT
3ad44729 1473 select SUPPORT_SPL
f3a8e2b7
MH
1474 help
1475 Support for Freescale LS1043ARDB platform.
1476
126fe70d
SX
1477config TARGET_LS1046AQDS
1478 bool "Support ls1046aqds"
da28e58a 1479 select ARCH_LS1046A
126fe70d
SX
1480 select ARM64
1481 select ARMV8_MULTIENTRY
6324d506 1482 select ARCH_SUPPORT_TFABOOT
5ed063d1 1483 select BOARD_EARLY_INIT_F
e5ec4815 1484 select BOARD_LATE_INIT
126fe70d 1485 select DM_SPI_FLASH if DM_SPI
5ed063d1 1486 select SUPPORT_SPL
32413125
RB
1487 select FSL_DDR_BIST if !SPL
1488 select FSL_DDR_INTERACTIVE if !SPL
1489 select FSL_DDR_INTERACTIVE if !SPL
fedb428c 1490 imply SCSI
126fe70d
SX
1491 help
1492 Support for Freescale LS1046AQDS platform.
1493 The LS1046A Development System (QDS) is a high-performance
1494 development platform that supports the QorIQ LS1046A
1495 Layerscape Architecture processor.
1496
dd02936f
MH
1497config TARGET_LS1046ARDB
1498 bool "Support ls1046ardb"
da28e58a 1499 select ARCH_LS1046A
dd02936f
MH
1500 select ARM64
1501 select ARMV8_MULTIENTRY
6324d506 1502 select ARCH_SUPPORT_TFABOOT
5ed063d1 1503 select BOARD_EARLY_INIT_F
e5ec4815 1504 select BOARD_LATE_INIT
dd02936f 1505 select DM_SPI_FLASH if DM_SPI
dccef2ec 1506 select POWER_MC34VR500
5ed063d1 1507 select SUPPORT_SPL
32413125
RB
1508 select FSL_DDR_BIST
1509 select FSL_DDR_INTERACTIVE if !SPL
fedb428c 1510 imply SCSI
dd02936f
MH
1511 help
1512 Support for Freescale LS1046ARDB platform.
1513 The LS1046A Reference Design Board (RDB) is a high-performance
1514 development platform that supports the QorIQ LS1046A
1515 Layerscape Architecture processor.
1516
d90c7ac7
VS
1517config TARGET_LS1046AFRWY
1518 bool "Support ls1046afrwy"
1519 select ARCH_LS1046A
1520 select ARM64
1521 select ARMV8_MULTIENTRY
6324d506 1522 select ARCH_SUPPORT_TFABOOT
d90c7ac7
VS
1523 select BOARD_EARLY_INIT_F
1524 select BOARD_LATE_INIT
1525 select DM_SPI_FLASH if DM_SPI
1526 imply SCSI
1527 help
1528 Support for Freescale LS1046AFRWY platform.
1529 The LS1046A Freeway Board (FRWY) is a high-performance
1530 development platform that supports the QorIQ LS1046A
1531 Layerscape Architecture processor.
dd84058d 1532
dd84058d
MY
1533config TARGET_COLIBRI_PXA270
1534 bool "Support colibri_pxa270"
2e07c249 1535 select CPU_PXA
dd84058d 1536
66cba041 1537config ARCH_UNIPHIER
b6ef3a3f 1538 bool "Socionext UniPhier SoCs"
e5ec4815 1539 select BOARD_LATE_INIT
4e819950 1540 select DM
b800cbde 1541 select DM_GPIO
4e819950 1542 select DM_I2C
4aceb3f8 1543 select DM_MMC
407b01b3 1544 select DM_MTD
4fb96c48 1545 select DM_RESET
b5550e49 1546 select DM_SERIAL
47a79f65 1547 select DM_USB
65fce763 1548 select OF_BOARD_SETUP
b5550e49
MY
1549 select OF_CONTROL
1550 select OF_LIBFDT
27350c92 1551 select PINCTRL
0680f1b1 1552 select SPL_BOARD_INIT if SPL
561ca649
MY
1553 select SPL_DM if SPL
1554 select SPL_LIBCOMMON_SUPPORT if SPL
1555 select SPL_LIBGENERIC_SUPPORT if SPL
1556 select SPL_OF_CONTROL if SPL
1557 select SPL_PINCTRL if SPL
b5550e49 1558 select SUPPORT_SPL
08a00cba 1559 imply CMD_DM
7ef5b1e7 1560 imply DISTRO_DEFAULTS
91d27a17 1561 imply FAT_WRITE
b6ef3a3f
MY
1562 help
1563 Support for UniPhier SoC family developed by Socionext Inc.
1564 (formerly, System LSI Business Division of Panasonic Corporation)
66cba041 1565
0a61ee88 1566config STM32
2514c2d0 1567 bool "Support STMicroelectronics STM32 MCU with cortex M"
ed09a554 1568 select CPU_V7M
66562414
KL
1569 select DM
1570 select DM_SERIAL
08a00cba 1571 imply CMD_DM
ed09a554 1572
94e9a4ef
PC
1573config ARCH_STI
1574 bool "Support STMicrolectronics SoCs"
5ed063d1 1575 select BLK
acf15001 1576 select CPU_V7A
214a17e6 1577 select DM
eee20f81 1578 select DM_MMC
584861ff 1579 select DM_RESET
5ed063d1 1580 select DM_SERIAL
08a00cba 1581 imply CMD_DM
94e9a4ef
PC
1582 help
1583 Support for STMicroelectronics STiH407/10 SoC family.
1584 This SoC is used on Linaro 96Board STiH410-B2260
1585
2514c2d0
PD
1586config ARCH_STM32MP
1587 bool "Support STMicroelectronics STM32MP Socs with cortex A"
08772f6e 1588 select ARCH_MISC_INIT
2514c2d0
PD
1589 select BOARD_LATE_INIT
1590 select CLK
1591 select DM
1592 select DM_GPIO
1593 select DM_RESET
1594 select DM_SERIAL
5ed063d1 1595 select MISC
2514c2d0
PD
1596 select OF_CONTROL
1597 select OF_LIBFDT
05d36936 1598 select OF_SYSTEM_SETUP
2514c2d0
PD
1599 select PINCTRL
1600 select REGMAP
1601 select SUPPORT_SPL
1602 select SYSCON
86634a93 1603 select SYSRESET
2514c2d0 1604 select SYS_THUMB_BUILD
09259fce 1605 imply SPL_SYSRESET
08a00cba 1606 imply CMD_DM
c16cc4f6 1607 imply CMD_POWEROFF
f219361d 1608 imply OF_LIBFDT_OVERLAY
b4ae34b6 1609 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
ce3772ca 1610 imply USE_PREBOOT
2514c2d0
PD
1611 help
1612 Support for STM32MP SoC family developed by STMicroelectronics,
1613 MPUs based on ARM cortex A core
abf2678f
PD
1614 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1615 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1616 chain.
1617 SPL is the unsecure FSBL for the basic boot chain.
2514c2d0 1618
2444dae5
SG
1619config ARCH_ROCKCHIP
1620 bool "Support Rockchip SoCs"
aa15038c 1621 select BLK
79030a48 1622 select BINMAN if !ARM64
2444dae5 1623 select DM
aa15038c
SG
1624 select DM_GPIO
1625 select DM_I2C
1626 select DM_MMC
5ed063d1
MS
1627 select DM_PWM
1628 select DM_REGULATOR
aa15038c
SG
1629 select DM_SERIAL
1630 select DM_SPI
1631 select DM_SPI_FLASH
892742df 1632 select DM_USB if USB
14ad6eb2 1633 select ENABLE_ARM_SOC_BOOT0_HOOK
5ed063d1 1634 select OF_CONTROL
f1b1f770 1635 select SPI
5ed063d1 1636 select SPL_DM if SPL
5ed063d1
MS
1637 select SYS_MALLOC_F
1638 select SYS_THUMB_BUILD if !ARM64
1639 imply ADC
08a00cba 1640 imply CMD_DM
b0a569da 1641 imply DEBUG_UART_BOARD_INIT
7325f6cf 1642 imply DISTRO_DEFAULTS
91d27a17 1643 imply FAT_WRITE
8e8bcccc 1644 imply SARADC_ROCKCHIP
5ed063d1 1645 imply SPL_SYSRESET
64eff47c 1646 imply SPL_SYS_MALLOC_SIMPLE
c3c0331d 1647 imply SYS_NS16550
5ed063d1
MS
1648 imply TPL_SYSRESET
1649 imply USB_FUNCTION_FASTBOOT
2444dae5 1650
746f985a
ST
1651config TARGET_THUNDERX_88XX
1652 bool "Support ThunderX 88xx"
b4ba1693 1653 select ARM64
746f985a 1654 select OF_CONTROL
cf2c7784 1655 select PL01X_SERIAL
5ed063d1 1656 select SYS_CACHE_SHIFT_7
746f985a 1657
4697abea 1658config ARCH_ASPEED
1659 bool "Support Aspeed SoCs"
4697abea 1660 select DM
5ed063d1 1661 select OF_CONTROL
08a00cba 1662 imply CMD_DM
4697abea 1663
e3aafef4 1664config TARGET_DURIAN
1665 bool "Support Phytium Durian Platform"
1666 select ARM64
1667 help
1668 Support for durian platform.
1669 It has 2GB Sdram, uart and pcie.
1670
7d706a88
AN
1671config TARGET_PRESIDIO_ASIC
1672 bool "Support Cortina Presidio ASIC Platform"
1673 select ARM64
1674
dd84058d
MY
1675endchoice
1676
6324d506
AT
1677config ARCH_SUPPORT_TFABOOT
1678 bool
1679
1680config TFABOOT
1681 bool "Support for booting from TF-A"
1682 depends on ARCH_SUPPORT_TFABOOT
1683 default n
1684 help
1685 Enabling this will make a U-Boot binary that is capable of being
e852b30b 1686 booted via TF-A (Trusted Firmware for Cortex-A).
6324d506 1687
5fbed8f2
AD
1688config TI_SECURE_DEVICE
1689 bool "HS Device Type Support"
3a543a80 1690 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
5fbed8f2
AD
1691 help
1692 If a high secure (HS) device type is being used, this config
1693 must be set. This option impacts various aspects of the
1694 build system (to create signed boot images that can be
1695 authenticated) and the code. See the doc/README.ti-secure
1696 file for further details.
1697
9c4b0131
TR
1698if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1699config ISW_ENTRY_ADDR
1700 hex "Address in memory or XIP address of bootloader entry point"
1701 default 0x402F4000 if AM43XX
1702 default 0x402F0400 if AM33XX
1703 default 0x40301350 if OMAP54XX
1704 help
1705 After any reset, the boot ROM searches the boot media for a valid
1706 boot image. For non-XIP devices, the ROM then copies the image into
1707 internal memory. For all boot modes, after the ROM processes the
1708 boot image it eventually computes the entry point address depending
1709 on the device type (secure/non-secure), boot media (xip/non-xip) and
1710 image headers.
1711endif
1712
4697abea 1713source "arch/arm/mach-aspeed/Kconfig"
1714
4614b891
MY
1715source "arch/arm/mach-at91/Kconfig"
1716
ddf6bd48 1717source "arch/arm/mach-bcm283x/Kconfig"
3491ba63 1718
894c3ad2
TF
1719source "arch/arm/mach-bcmstb/Kconfig"
1720
ddf6bd48 1721source "arch/arm/mach-davinci/Kconfig"
34e609ca 1722
77b55e8c 1723source "arch/arm/mach-exynos/Kconfig"
72df68cc 1724
72a8ff4b 1725source "arch/arm/mach-highbank/Kconfig"
ef2b694c 1726
5cbbd9bd
MY
1727source "arch/arm/mach-integrator/Kconfig"
1728
586bde93
LV
1729source "arch/arm/mach-k3/Kconfig"
1730
39a72345 1731source "arch/arm/mach-keystone/Kconfig"
c338f09e 1732
56f86e39 1733source "arch/arm/mach-kirkwood/Kconfig"
47539e23 1734
ee54dfea
VZ
1735source "arch/arm/cpu/arm926ejs/lpc32xx/Kconfig"
1736
c3d89140
SR
1737source "arch/arm/mach-mvebu/Kconfig"
1738
0a37cf8f
YS
1739source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1740
07df697e
FE
1741source "arch/arm/mach-imx/mx2/Kconfig"
1742
3159ec64
ML
1743source "arch/arm/mach-imx/mx3/Kconfig"
1744
7a7391fd
PF
1745source "arch/arm/mach-imx/mx5/Kconfig"
1746
1747source "arch/arm/mach-imx/mx6/Kconfig"
e90a08da 1748
552a848e 1749source "arch/arm/mach-imx/mx7/Kconfig"
1a8150d4 1750
7a7391fd 1751source "arch/arm/mach-imx/mx7ulp/Kconfig"
89ebc821 1752
b2b8b9be
PF
1753source "arch/arm/mach-imx/imx8/Kconfig"
1754
cd357ad1 1755source "arch/arm/mach-imx/imx8m/Kconfig"
424ee3d1 1756
77eb9a90
GB
1757source "arch/arm/mach-imx/imxrt/Kconfig"
1758
c5343d4e
SA
1759source "arch/arm/mach-imx/mxs/Kconfig"
1760
983e3700 1761source "arch/arm/mach-omap2/Kconfig"
6384726d 1762
da28e58a
YS
1763source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
1764
3e93b4e6 1765source "arch/arm/mach-orion5x/Kconfig"
22f2be7a 1766
97775d26
MS
1767source "arch/arm/mach-owl/Kconfig"
1768
badbb63c 1769source "arch/arm/mach-rmobile/Kconfig"
f40b9898 1770
bfcef28a
BG
1771source "arch/arm/mach-meson/Kconfig"
1772
cbd2fba1
RL
1773source "arch/arm/mach-mediatek/Kconfig"
1774
32f11829
TT
1775source "arch/arm/mach-qemu/Kconfig"
1776
2444dae5
SG
1777source "arch/arm/mach-rockchip/Kconfig"
1778
225f5eec 1779source "arch/arm/mach-s5pc1xx/Kconfig"
311757be 1780
08592136
MK
1781source "arch/arm/mach-snapdragon/Kconfig"
1782
7865f4b0
MY
1783source "arch/arm/mach-socfpga/Kconfig"
1784
94e9a4ef
PC
1785source "arch/arm/mach-sti/Kconfig"
1786
0a61ee88
VM
1787source "arch/arm/mach-stm32/Kconfig"
1788
2514c2d0
PD
1789source "arch/arm/mach-stm32mp/Kconfig"
1790
3abfd887
MY
1791source "arch/arm/mach-sunxi/Kconfig"
1792
09f455dc 1793source "arch/arm/mach-tegra/Kconfig"
ddd960e6 1794
689088f9
SG
1795source "arch/arm/mach-u8500/Kconfig"
1796
4c425570 1797source "arch/arm/mach-uniphier/Kconfig"
66cba041 1798
7966b437
SA
1799source "arch/arm/cpu/armv7/vf610/Kconfig"
1800
0107f240 1801source "arch/arm/mach-zynq/Kconfig"
ddd960e6 1802
274ccb5b
MS
1803source "arch/arm/mach-zynqmp/Kconfig"
1804
ec48b6c9
MS
1805source "arch/arm/mach-versal/Kconfig"
1806
1d6c54ec
MS
1807source "arch/arm/mach-zynqmp-r5/Kconfig"
1808
ea624e19
HG
1809source "arch/arm/cpu/armv7/Kconfig"
1810
23b5877c
LW
1811source "arch/arm/cpu/armv8/Kconfig"
1812
552a848e 1813source "arch/arm/mach-imx/Kconfig"
a05a6045 1814
d8ccbe93 1815source "board/bosch/shc/Kconfig"
45123804 1816source "board/bosch/guardian/Kconfig"
dd84058d 1817source "board/CarMediaLab/flea3/Kconfig"
dd84058d 1818source "board/Marvell/aspenite/Kconfig"
dd84058d 1819source "board/Marvell/gplugd/Kconfig"
dd84058d 1820source "board/armadeus/apf27/Kconfig"
dd84058d
MY
1821source "board/armltd/vexpress/Kconfig"
1822source "board/armltd/vexpress64/Kconfig"
7d706a88 1823source "board/cortina/presidio-asic/Kconfig"
43486e4c 1824source "board/broadcom/bcm23550_w1d/Kconfig"
dd84058d 1825source "board/broadcom/bcm28155_ap/Kconfig"
be2fc084 1826source "board/broadcom/bcm963158/Kconfig"
645b7ec5 1827source "board/broadcom/bcm968360bg/Kconfig"
40b59b05 1828source "board/broadcom/bcm968580xref/Kconfig"
abb1678c
SR
1829source "board/broadcom/bcmcygnus/Kconfig"
1830source "board/broadcom/bcmnsp/Kconfig"
274bced8 1831source "board/broadcom/bcmns2/Kconfig"
746f985a 1832source "board/cavium/thunderx/Kconfig"
dd84058d 1833source "board/cirrus/edb93xx/Kconfig"
85ab0452 1834source "board/eets/pdu001/Kconfig"
6f332765 1835source "board/emulation/qemu-arm/Kconfig"
44937214
PK
1836source "board/freescale/ls2080a/Kconfig"
1837source "board/freescale/ls2080aqds/Kconfig"
1838source "board/freescale/ls2080ardb/Kconfig"
e84a324b 1839source "board/freescale/ls1088a/Kconfig"
353f36d9 1840source "board/freescale/ls1028a/Kconfig"
550e3dc0 1841source "board/freescale/ls1021aqds/Kconfig"
02b5d2ed 1842source "board/freescale/ls1043aqds/Kconfig"
c8a7d9da 1843source "board/freescale/ls1021atwr/Kconfig"
87821220 1844source "board/freescale/ls1021atsn/Kconfig"
20c700f8 1845source "board/freescale/ls1021aiot/Kconfig"
126fe70d 1846source "board/freescale/ls1046aqds/Kconfig"
f3a8e2b7 1847source "board/freescale/ls1043ardb/Kconfig"
dd02936f 1848source "board/freescale/ls1046ardb/Kconfig"
d90c7ac7 1849source "board/freescale/ls1046afrwy/Kconfig"
9d044fcb 1850source "board/freescale/ls1012aqds/Kconfig"
3b6e3898 1851source "board/freescale/ls1012ardb/Kconfig"
ff78aa2b 1852source "board/freescale/ls1012afrdm/Kconfig"
58c3e620 1853source "board/freescale/lx2160a/Kconfig"
dd84058d 1854source "board/freescale/mx35pdk/Kconfig"
9702ec00 1855source "board/freescale/s32v234evb/Kconfig"
ab38bf6a 1856source "board/grinn/chiliboard/Kconfig"
dd84058d 1857source "board/gumstix/pepper/Kconfig"
345243ed 1858source "board/hisilicon/hikey/Kconfig"
c62c7ef7 1859source "board/hisilicon/hikey960/Kconfig"
d754254f 1860source "board/hisilicon/poplar/Kconfig"
a96c08f5 1861source "board/isee/igep003x/Kconfig"
dd84058d 1862source "board/phytec/pcm051/Kconfig"
dd84058d 1863source "board/silica/pengwyn/Kconfig"
dd84058d
MY
1864source "board/spear/spear300/Kconfig"
1865source "board/spear/spear310/Kconfig"
1866source "board/spear/spear320/Kconfig"
1867source "board/spear/spear600/Kconfig"
1868source "board/spear/x600/Kconfig"
9fa32b12 1869source "board/st/stv0991/Kconfig"
9d1b2987 1870source "board/tcl/sl50/Kconfig"
eba6589f 1871source "board/ucRobotics/bubblegum_96/Kconfig"
a2bc4321 1872source "board/birdland/bav335x/Kconfig"
dd84058d 1873source "board/toradex/colibri_pxa270/Kconfig"
d8d33b6d 1874source "board/variscite/dart_6ul/Kconfig"
6ce89324 1875source "board/vscom/baltos/Kconfig"
6da4f67a 1876source "board/xilinx/Kconfig"
37e3a36a 1877source "board/xilinx/zynq/Kconfig"
c436bf92 1878source "board/xilinx/zynqmp/Kconfig"
e3aafef4 1879source "board/phytium/durian/Kconfig"
dd84058d 1880
51b17d49
MY
1881source "arch/arm/Kconfig.debug"
1882
dd84058d 1883endmenu
b529993e
PT
1884
1885config SPL_LDSCRIPT
6e7bdde4
MS
1886 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
1887 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
b529993e
PT
1888 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
1889
1890