[thirdparty/linux.git] / arch / arm / boot / dts / bcm63138.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Broadcom BCM63138 DSL SoCs Device Tree
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "skeleton.dtsi"

/ {
	compatible = "brcm,bcm63138";
	model = "Broadcom BCM63138 DSL SoC";
	interrupt-parent = <&gic>;

	aliases {
		uart0 = &serial0;
		uart1 = &serial1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0>;
			enable-method = "brcm,bcm63138";
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <1>;
			enable-method = "brcm,bcm63138";
			resets = <&pmb0 4 1>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		/* UBUS peripheral clock */
		periph_clk: periph_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
			clock-output-names = "periph";
		};

		/* peripheral clock for system timer */
		axi_clk: axi_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&armpll>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		/* APB bus clock */
		apb_clk: apb_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&armpll>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	/* ARM bus */
	axi@80000000 {
		compatible = "simple-bus";
		ranges = <0 0x80000000 0x784000>;
		#address-cells = <1>;
		#size-cells = <1>;

		L2: cache-controller@1d000 {
			compatible = "arm,pl310-cache";
			reg = <0x1d000 0x1000>;
			cache-unified;
			cache-level = <2>;
			cache-size = <524288>;
			cache-sets = <1024>;
			cache-line-size = <32>;
			interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
		};

		scu: scu@1e000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0x1e000 0x100>;
		};

		gic: interrupt-controller@1e100 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x1f000 0x1000
				0x1e100 0x100>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
		};

		global_timer: timer@1e200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x1e200 0x20>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&axi_clk>;
		};

		local_timer: local-timer@1e600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x1e600 0x20>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&axi_clk>;
		};

		twd_watchdog: watchdog@1e620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x1e620 0x20>;
			interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
		};

		armpll: armpll {
			#clock-cells = <0>;
			compatible = "brcm,bcm63138-armpll";
			clocks = <&periph_clk>;
			reg = <0x20000 0xf00>;
		};

		pmb0: reset-controller@4800c0 {
			compatible = "brcm,bcm63138-pmb";
			reg = <0x4800c0 0x10>;
			#reset-cells = <2>;
		};

		pmb1: reset-controller@4800e0 {
			compatible = "brcm,bcm63138-pmb";
			reg = <0x4800e0 0x10>;
			#reset-cells = <2>;
		};
	};

	/* Legacy UBUS base */
	ubus@fffe8000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xfffe8000 0x8100>;

		timer: timer@80 {
			compatible = "brcm,bcm6328-timer", "syscon";
			reg = <0x80 0x3c>;
		};

		serial0: serial@600 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x600 0x1b>;
			interrupts = <GIC_SPI 32 0>;
			clocks = <&periph_clk>;
			clock-names = "periph";
			status = "disabled";
		};

		serial1: serial@620 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x620 0x1b>;
			interrupts = <GIC_SPI 33 0>;
			clocks = <&periph_clk>;
			clock-names = "periph";
			status = "disabled";
		};

		nand: nand@2000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
			reg = <0x2000 0x600>, <0xf0 0x10>;
			reg-names = "nand", "nand-int-base";
			status = "disabled";
			interrupts = <GIC_SPI 38 0>;
			interrupt-names = "nand";
		};

		bootlut: bootlut@8000 {
			compatible = "brcm,bcm63138-bootlut";
			reg = <0x8000 0x50>;
		};

		reboot {
			compatible = "syscon-reboot";
			regmap = <&timer>;
			offset = <0x34>;
			mask = <1>;
		};
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
46d4bca0 FF	2	/*
	3	* Broadcom BCM63138 DSL SoCs Device Tree
	4	*/
	5
	6	#include <dt-bindings/interrupt-controller/arm-gic.h>
	7	#include <dt-bindings/interrupt-controller/irq.h>
	8
	9	#include "skeleton.dtsi"
	10
	11	/ {
	12	compatible = "brcm,bcm63138";
	13	model = "Broadcom BCM63138 DSL SoC";
	14	interrupt-parent = <&gic>;
	15
	16	aliases {
	17	uart0 = &serial0;
	18	uart1 = &serial1;
	19	};
	20
	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	cpu@0 {
	26	device_type = "cpu";
	27	compatible = "arm,cortex-a9";
	28	next-level-cache = <&L2>;
	29	reg = <0>;
9f988029	30	enable-method = "brcm,bcm63138";
46d4bca0 FF	31	};
	32
	33	cpu@1 {
	34	device_type = "cpu";
	35	compatible = "arm,cortex-a9";
	36	next-level-cache = <&L2>;
	37	reg = <1>;
9f988029 FF	38	enable-method = "brcm,bcm63138";
9f988029 FF	39	resets = <&pmb0 4 1>;
46d4bca0 FF	40	};
	41	};
	42
	43	clocks {
	44	#address-cells = <1>;
	45	#size-cells = <0>;
	46
511d3044	47	/* UBUS peripheral clock */
46d4bca0 FF	48	periph_clk: periph_clk {
	49	#clock-cells = <0>;
	50	compatible = "fixed-clock";
	51	clock-frequency = <50000000>;
	52	clock-output-names = "periph";
	53	};
511d3044 FF	54
	55	/* peripheral clock for system timer */
	56	axi_clk: axi_clk {
	57	#clock-cells = <0>;
	58	compatible = "fixed-factor-clock";
	59	clocks = <&armpll>;
	60	clock-div = <2>;
	61	clock-mult = <1>;
	62	};
	63
	64	/* APB bus clock */
	65	apb_clk: apb_clk {
	66	#clock-cells = <0>;
	67	compatible = "fixed-factor-clock";
	68	clocks = <&armpll>;
	69	clock-div = <4>;
	70	clock-mult = <1>;
	71	};
46d4bca0 FF	72	};
	73
	74	/* ARM bus */
	75	axi@80000000 {
	76	compatible = "simple-bus";
	77	ranges = <0 0x80000000 0x784000>;
	78	#address-cells = <1>;
	79	#size-cells = <1>;
	80
	81	L2: cache-controller@1d000 {
	82	compatible = "arm,pl310-cache";
	83	reg = <0x1d000 0x1000>;
	84	cache-unified;
	85	cache-level = <2>;
9df11828 FF	86	cache-size = <524288>;
	87	cache-sets = <1024>;
	88	cache-line-size = <32>;
46d4bca0 FF	89	interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
	90	};
	91
	92	scu: scu@1e000 {
	93	compatible = "arm,cortex-a9-scu";
	94	reg = <0x1e000 0x100>;
	95	};
	96
	97	gic: interrupt-controller@1e100 {
	98	compatible = "arm,cortex-a9-gic";
	99	reg = <0x1f000 0x1000
	100	0x1e100 0x100>;
	101	#interrupt-cells = <3>;
	102	#address-cells = <0>;
	103	interrupt-controller;
	104	};
	105
	106	global_timer: timer@1e200 {
	107	compatible = "arm,cortex-a9-global-timer";
	108	reg = <0x1e200 0x20>;
	109	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
511d3044	110	clocks = <&axi_clk>;
46d4bca0 FF	111	};
	112
	113	local_timer: local-timer@1e600 {
	114	compatible = "arm,cortex-a9-twd-timer";
	115	reg = <0x1e600 0x20>;
	116	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
511d3044	117	clocks = <&axi_clk>;
46d4bca0 FF	118	};
	119
	120	twd_watchdog: watchdog@1e620 {
	121	compatible = "arm,cortex-a9-twd-wdt";
	122	reg = <0x1e620 0x20>;
cbd25516	123	interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
46d4bca0	124	};
39afb980	125
511d3044 FF	126	armpll: armpll {
	127	#clock-cells = <0>;
	128	compatible = "brcm,bcm63138-armpll";
	129	clocks = <&periph_clk>;
	130	reg = <0x20000 0xf00>;
	131	};
	132
39afb980 FF	133	pmb0: reset-controller@4800c0 {
	134	compatible = "brcm,bcm63138-pmb";
	135	reg = <0x4800c0 0x10>;
	136	#reset-cells = <2>;
	137	};
	138
	139	pmb1: reset-controller@4800e0 {
	140	compatible = "brcm,bcm63138-pmb";
	141	reg = <0x4800e0 0x10>;
	142	#reset-cells = <2>;
	143	};
46d4bca0 FF	144	};
	145
	146	/* Legacy UBUS base */
	147	ubus@fffe8000 {
	148	compatible = "simple-bus";
	149	#address-cells = <1>;
	150	#size-cells = <1>;
	151	ranges = <0 0xfffe8000 0x8100>;
	152
8ab14288 FF	153	timer: timer@80 {
	154	compatible = "brcm,bcm6328-timer", "syscon";
	155	reg = <0x80 0x3c>;
	156	};
	157
46d4bca0 FF	158	serial0: serial@600 {
	159	compatible = "brcm,bcm6345-uart";
	160	reg = <0x600 0x1b>;
	161	interrupts = <GIC_SPI 32 0>;
	162	clocks = <&periph_clk>;
	163	clock-names = "periph";
	164	status = "disabled";
	165	};
	166
	167	serial1: serial@620 {
	168	compatible = "brcm,bcm6345-uart";
	169	reg = <0x620 0x1b>;
	170	interrupts = <GIC_SPI 33 0>;
	171	clocks = <&periph_clk>;
	172	clock-names = "periph";
	173	status = "disabled";
	174	};
9f988029	175
9d7ef1b7 FF	176	nand: nand@2000 {
	177	#address-cells = <1>;
	178	#size-cells = <0>;
	179	compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
	180	reg = <0x2000 0x600>, <0xf0 0x10>;
	181	reg-names = "nand", "nand-int-base";
	182	status = "disabled";
	183	interrupts = <GIC_SPI 38 0>;
	184	interrupt-names = "nand";
	185	};
	186
9f988029 FF	187	bootlut: bootlut@8000 {
	188	compatible = "brcm,bcm63138-bootlut";
	189	reg = <0x8000 0x50>;
	190	};
8ab14288 FF	191
	192	reboot {
	193	compatible = "syscon-reboot";
	194	regmap = <&timer>;
	195	offset = <0x34>;
	196	mask = <1>;
	197	};
46d4bca0 FF	198	};
46d4bca0 FF	199	};