[thirdparty/kernel/stable.git] / arch / arm / boot / dts / dra72-evm-common.dtsi

/*
 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>

/ {
	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";

	aliases {
		display0 = &hdmi0;
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_5v0: fixedregulator-evm5v0 {
		/* Output 1 of TPS43351QDAPRQ1 */
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output 2 of TPS43351QDAPRQ1 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_3v3_sw: fixedregulator-evm_3v3 {
		/* TPS22965DSG */
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vsys_3v3>;
		regulator-always-on;
		regulator-boot-on;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		/* TPS77018DBVT */
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd";
		vin-supply = <&evm_3v3_sw>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	evm_3v3_sd: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_3v3_sw>;
		enable-active-high;
		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
	};

	extcon_usb1: extcon_usb1 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
	};

	extcon_usb2: extcon_usb2 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
	};

	hdmi0: connector {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tpd12s015_out>;
			};
		};
	};

	tpd12s015: encoder {
		compatible = "ti,tpd12s015";

		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tpd12s015_in: endpoint {
					remote-endpoint = <&hdmi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tpd12s015_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

	sound0: sound0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-EVM";
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line Out",
			"Microphone", "Mic Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",       "HPLOUT",
			"Headphone Jack",       "HPROUT",
			"Line Out",		"LLOUT",
			"Line Out",		"RLOUT",
			"MIC3L",		"Mic Jack",
			"MIC3R",		"Mic Jack",
			"Mic Jack",		"Mic Bias",
			"LINE1L",               "Line In",
			"LINE1R",               "Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&sound0_master>;
		simple-audio-card,frame-master = <&sound0_master>;
		simple-audio-card,bitclock-inversion;

		sound0_master: simple-audio-card,cpu {
			sound-dai = <&mcasp3>;
			system-clock-frequency = <5644800>;
		};

		simple-audio-card,codec {
			sound-dai = <&tlv320aic3106>;
			clocks = <&atl_clkin2_ck>;
		};
	};
};

&dra7_pmx_core {
	mmc1_pins_default: mmc1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)	/* mmc1sdcd.gpio219 */
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};

	mmc2_pins_default: mmc2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	dcan1_pins_default: dcan1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
			DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
		>;
	};

	dcan1_pins_sleep: dcan1_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
			DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP)	/* wakeup0.off */
		>;
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	pcf_gpio_21: gpio@21 {
		compatible = "ti,pcf8575", "nxp,pcf8575";
		reg = <0x21>;
		lines-initial-states = <0x1408>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	tlv320aic3106: tlv320aic3106@19 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x19>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		/* 2.0V */
		status = "okay";

		/* Regulators */
		AVDD-supply = <&evm_3v3_sw>;
		IOVDD-supply = <&evm_3v3_sw>;
		DRVDD-supply = <&evm_3v3_sw>;
		DVDD-supply = <&aic_dvdd>;
	};
};

&i2c5 {
	status = "okay";
	clock-frequency = <400000>;

	pcf_hdmi: pcf8575@26 {
		compatible = "ti,pcf8575", "nxp,pcf8575";
		reg = <0x26>;
		gpio-controller;
		#gpio-cells = <2>;
		/*
		 * initial state is used here to keep the mdio interface
		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
		 * VIN2_S0 driven high otherwise Ethernet stops working
		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
		 */
		lines-initial-states = <0x0f2b>;

		p1 {
			/* vin6_sel_s0: high: VIN6, low: audio */
			gpio-hog;
			gpios = <1 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "vin6_sel_s0";
		};
	};
};

&uart1 {
	status = "okay";
	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
			      <&dra7_pmx_core 0x3e0>;
};

&elm {
	status = "okay";
};

&gpmc {
	status = "okay";
	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		/* To use NAND, DIP switch SW5 must be set like so:
		 * SW5.1 (NAND_SELn) = ON (LOW)
		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
		 */
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;		/* device IO registers */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <80>;
		gpmc,cs-wr-off-ns = <80>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <60>;
		gpmc,adv-wr-off-ns = <60>;
		gpmc,we-on-ns = <10>;
		gpmc,we-off-ns = <50>;
		gpmc,oe-on-ns = <4>;
		gpmc,oe-off-ns = <40>;
		gpmc,access-ns = <40>;
		gpmc,wr-access-ns = <80>;
		gpmc,rd-cycle-ns = <80>;
		gpmc,wr-cycle-ns = <80>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x000020000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00020000 0x00020000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00040000 0x00020000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x00060000 0x00020000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00080000 0x00040000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x000c0000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x001c0000 0x00020000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x001e0000 0x00020000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00200000 0x00800000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x0f600000>;
		};
	};
};

&omap_dwc3_1 {
	extcon = <&extcon_usb1>;
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&usb1 {
	dr_mode = "peripheral";
};

&usb2 {
	dr_mode = "host";
};

&mmc1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins_default>;
	vmmc-supply = <&evm_3v3_sd>;
	bus-width = <4>;
	/*
	 * SDCD signal is not being used here - using the fact that GPIO mode
	 * is a viable alternative
	 */
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	max-frequency = <192000000>;
};

&mmc2 {
	/* SW5-3 in ON position */
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins_default>;

	vmmc-supply = <&evm_3v3_sw>;
	bus-width = <8>;
	ti,non-removable;
	max-frequency = <192000000>;
};

&mac {
	status = "okay";
};

&dcan1 {
	status = "ok";
	pinctrl-names = "default", "sleep", "active";
	pinctrl-0 = <&dcan1_pins_sleep>;
	pinctrl-1 = <&dcan1_pins_sleep>;
	pinctrl-2 = <&dcan1_pins_default>;
};

&qspi {
	status = "okay";

	spi-max-frequency = <76800000>;
	m25p80@0 {
		compatible = "s25fl256s1";
		spi-max-frequency = <76800000>;
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x000010000>;
		};
		partition@1 {
			label = "QSPI.SPL.backup1";
			reg = <0x00010000 0x00010000>;
		};
		partition@2 {
			label = "QSPI.SPL.backup2";
			reg = <0x00020000 0x00010000>;
		};
		partition@3 {
			label = "QSPI.SPL.backup3";
			reg = <0x00030000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@5 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@6 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@7 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@8 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@9 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x01620000>;
		};
	};
};

&dss {
	status = "ok";
};

&hdmi {
	status = "ok";

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&tpd12s015_in>;
		};
	};
};

&atl {
	assigned-clocks = <&abe_dpll_sys_clk_mux>,
			  <&atl_gfclk_mux>,
			  <&dpll_abe_ck>,
			  <&dpll_abe_m2x2_ck>,
			  <&atl_clkin2_ck>;
	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;

	status = "okay";

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};

&mcasp3 {
	#sound-dai-cells = <0>;

	assigned-clocks = <&mcasp3_ahclkx_mux>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	status = "okay";

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializer */
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "okay";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		status = "okay";
	};
};
Commit	Line	Data
a4240d3a NM	1	/*
	2	* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8	/dts-v1/;
	9
	10	#include "dra72x.dtsi"
	11	#include <dt-bindings/gpio/gpio.h>
	12	#include <dt-bindings/clk/ti-dra7-atl.h>
	13
	14	/ {
	15	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
	16
	17	aliases {
	18	display0 = &hdmi0;
	19	};
	20
e9a05fbd LV	21	evm_12v0: fixedregulator-evm12v0 {
	22	/* main supply */
	23	compatible = "regulator-fixed";
	24	regulator-name = "evm_12v0";
	25	regulator-min-microvolt = <12000000>;
	26	regulator-max-microvolt = <12000000>;
	27	regulator-always-on;
	28	regulator-boot-on;
	29	};
	30
	31	evm_5v0: fixedregulator-evm5v0 {
	32	/* Output 1 of TPS43351QDAPRQ1 */
	33	compatible = "regulator-fixed";
	34	regulator-name = "evm_5v0";
	35	regulator-min-microvolt = <5000000>;
	36	regulator-max-microvolt = <5000000>;
	37	vin-supply = <&evm_12v0>;
	38	regulator-always-on;
	39	regulator-boot-on;
	40	};
	41
	42	vsys_3v3: fixedregulator-vsys3v3 {
	43	/* Output 2 of TPS43351QDAPRQ1 */
	44	compatible = "regulator-fixed";
	45	regulator-name = "vsys_3v3";
	46	regulator-min-microvolt = <3300000>;
	47	regulator-max-microvolt = <3300000>;
	48	vin-supply = <&evm_12v0>;
	49	regulator-always-on;
	50	regulator-boot-on;
	51	};
	52
7172e745	53	evm_3v3_sw: fixedregulator-evm_3v3 {
e9a05fbd	54	/* TPS22965DSG */
a4240d3a NM	55	compatible = "regulator-fixed";
	56	regulator-name = "evm_3v3";
	57	regulator-min-microvolt = <3300000>;
	58	regulator-max-microvolt = <3300000>;
e9a05fbd LV	59	vin-supply = <&vsys_3v3>;
	60	regulator-always-on;
	61	regulator-boot-on;
a4240d3a NM	62	};
	63
	64	aic_dvdd: fixedregulator-aic_dvdd {
	65	/* TPS77018DBVT */
	66	compatible = "regulator-fixed";
	67	regulator-name = "aic_dvdd";
7172e745	68	vin-supply = <&evm_3v3_sw>;
a4240d3a NM	69	regulator-min-microvolt = <1800000>;
	70	regulator-max-microvolt = <1800000>;
	71	};
	72
	73	evm_3v3_sd: fixedregulator-sd {
	74	compatible = "regulator-fixed";
	75	regulator-name = "evm_3v3_sd";
	76	regulator-min-microvolt = <3300000>;
	77	regulator-max-microvolt = <3300000>;
e9a05fbd	78	vin-supply = <&evm_3v3_sw>;
a4240d3a NM	79	enable-active-high;
	80	gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
	81	};
	82
	83	extcon_usb1: extcon_usb1 {
	84	compatible = "linux,extcon-usb-gpio";
	85	id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
	86	};
	87
	88	extcon_usb2: extcon_usb2 {
	89	compatible = "linux,extcon-usb-gpio";
	90	id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
	91	};
	92
	93	hdmi0: connector {
	94	compatible = "hdmi-connector";
	95	label = "hdmi";
	96
	97	type = "a";
	98
	99	port {
	100	hdmi_connector_in: endpoint {
	101	remote-endpoint = <&tpd12s015_out>;
	102	};
	103	};
	104	};
	105
	106	tpd12s015: encoder {
	107	compatible = "ti,tpd12s015";
	108
a4240d3a NM	109	gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
	110	<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
	111	<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
	112
	113	ports {
	114	#address-cells = <1>;
	115	#size-cells = <0>;
	116
	117	port@0 {
	118	reg = <0>;
	119
	120	tpd12s015_in: endpoint {
	121	remote-endpoint = <&hdmi_out>;
	122	};
	123	};
	124
	125	port@1 {
	126	reg = <1>;
	127
	128	tpd12s015_out: endpoint {
	129	remote-endpoint = <&hdmi_connector_in>;
	130	};
	131	};
	132	};
	133	};
	134
	135	sound0: sound0 {
	136	compatible = "simple-audio-card";
	137	simple-audio-card,name = "DRA7xx-EVM";
	138	simple-audio-card,widgets =
	139	"Headphone", "Headphone Jack",
	140	"Line", "Line Out",
	141	"Microphone", "Mic Jack",
	142	"Line", "Line In";
	143	simple-audio-card,routing =
	144	"Headphone Jack", "HPLOUT",
	145	"Headphone Jack", "HPROUT",
	146	"Line Out", "LLOUT",
	147	"Line Out", "RLOUT",
	148	"MIC3L", "Mic Jack",
	149	"MIC3R", "Mic Jack",
	150	"Mic Jack", "Mic Bias",
	151	"LINE1L", "Line In",
	152	"LINE1R", "Line In";
	153	simple-audio-card,format = "dsp_b";
	154	simple-audio-card,bitclock-master = <&sound0_master>;
	155	simple-audio-card,frame-master = <&sound0_master>;
	156	simple-audio-card,bitclock-inversion;
	157
	158	sound0_master: simple-audio-card,cpu {
	159	sound-dai = <&mcasp3>;
	160	system-clock-frequency = <5644800>;
	161	};
	162
	163	simple-audio-card,codec {
	164	sound-dai = <&tlv320aic3106>;
	165	clocks = <&atl_clkin2_ck>;
	166	};
	167	};
	168	};
	169
	170	&dra7_pmx_core {
a4240d3a NM	171	mmc1_pins_default: mmc1_pins_default {
	172	pinctrl-single,pins = <
	173	DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT \| MUX_MODE14) /* mmc1sdcd.gpio219 */
	174	DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_clk.clk */
	175	DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_cmd.cmd */
	176	DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat0.dat0 */
	177	DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat1.dat1 */
	178	DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat2.dat2 */
	179	DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat3.dat3 */
	180	>;
	181	};
	182
	183	mmc2_pins_default: mmc2_pins_default {
	184	pinctrl-single,pins = <
	185	DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a23.mmc2_clk */
	186	DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
	187	DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
	188	DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
	189	DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
	190	DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
	191	DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
	192	DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
	193	DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
	194	DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
	195	>;
	196	};
	197
	198	dcan1_pins_default: dcan1_pins_default {
	199	pinctrl-single,pins = <
	200	DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* dcan1_tx */
	201	DRA7XX_CORE_IOPAD(0x3818, PULL_UP \| MUX_MODE1) /* wakeup0.dcan1_rx */
	202	>;
	203	};
	204
	205	dcan1_pins_sleep: dcan1_pins_sleep {
	206	pinctrl-single,pins = <
	207	DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 \| PULL_UP) /* dcan1_tx.off */
	208	DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 \| PULL_UP) /* wakeup0.off */
	209	>;
	210	};
a4240d3a NM	211	};
	212
	213	&i2c1 {
	214	status = "okay";
a4240d3a NM	215	clock-frequency = <400000>;
a4240d3a NM	216
a4240d3a	217	pcf_gpio_21: gpio@21 {
86f196f8	218	compatible = "ti,pcf8575", "nxp,pcf8575";
a4240d3a NM	219	reg = <0x21>;
	220	lines-initial-states = <0x1408>;
	221	gpio-controller;
	222	#gpio-cells = <2>;
	223	interrupt-controller;
	224	#interrupt-cells = <2>;
	225	};
	226
	227	tlv320aic3106: tlv320aic3106@19 {
	228	#sound-dai-cells = <0>;
	229	compatible = "ti,tlv320aic3106";
	230	reg = <0x19>;
	231	adc-settle-ms = <40>;
	232	ai3x-micbias-vg = <1>; /* 2.0V */
	233	status = "okay";
	234
	235	/* Regulators */
7172e745 MLC	236	AVDD-supply = <&evm_3v3_sw>;
	237	IOVDD-supply = <&evm_3v3_sw>;
	238	DRVDD-supply = <&evm_3v3_sw>;
a4240d3a NM	239	DVDD-supply = <&aic_dvdd>;
	240	};
	241	};
	242
	243	&i2c5 {
	244	status = "okay";
a4240d3a NM	245	clock-frequency = <400000>;
	246
	247	pcf_hdmi: pcf8575@26 {
86f196f8	248	compatible = "ti,pcf8575", "nxp,pcf8575";
a4240d3a NM	249	reg = <0x26>;
	250	gpio-controller;
	251	#gpio-cells = <2>;
	252	/*
	253	* initial state is used here to keep the mdio interface
	254	* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
	255	* VIN2_S0 driven high otherwise Ethernet stops working
	256	* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
	257	*/
	258	lines-initial-states = <0x0f2b>;
	259
	260	p1 {
	261	/* vin6_sel_s0: high: VIN6, low: audio */
	262	gpio-hog;
	263	gpios = <1 GPIO_ACTIVE_HIGH>;
	264	output-low;
	265	line-name = "vin6_sel_s0";
	266	};
	267	};
	268	};
	269
	270	&uart1 {
	271	status = "okay";
	272	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	273	<&dra7_pmx_core 0x3e0>;
	274	};
	275
	276	&elm {
	277	status = "okay";
	278	};
	279
	280	&gpmc {
	281	status = "okay";
a4240d3a NM	282	ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
	283	nand@0,0 {
	284	/* To use NAND, DIP switch SW5 must be set like so:
	285	* SW5.1 (NAND_SELn) = ON (LOW)
	286	* SW5.9 (GPMC_WPN) = OFF (HIGH)
	287	*/
	288	compatible = "ti,omap2-nand";
	289	reg = <0 0 4>; /* device IO registers */
	290	interrupt-parent = <&gpmc>;
	291	interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
	292	<1 IRQ_TYPE_NONE>; /* termcount */
	293	rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
	294	ti,nand-ecc-opt = "bch8";
	295	ti,elm-id = <&elm>;
	296	nand-bus-width = <16>;
	297	gpmc,device-width = <2>;
	298	gpmc,sync-clk-ps = <0>;
	299	gpmc,cs-on-ns = <0>;
	300	gpmc,cs-rd-off-ns = <80>;
	301	gpmc,cs-wr-off-ns = <80>;
	302	gpmc,adv-on-ns = <0>;
	303	gpmc,adv-rd-off-ns = <60>;
	304	gpmc,adv-wr-off-ns = <60>;
	305	gpmc,we-on-ns = <10>;
	306	gpmc,we-off-ns = <50>;
	307	gpmc,oe-on-ns = <4>;
	308	gpmc,oe-off-ns = <40>;
	309	gpmc,access-ns = <40>;
	310	gpmc,wr-access-ns = <80>;
	311	gpmc,rd-cycle-ns = <80>;
	312	gpmc,wr-cycle-ns = <80>;
	313	gpmc,bus-turnaround-ns = <0>;
	314	gpmc,cycle2cycle-delay-ns = <0>;
	315	gpmc,clk-activation-ns = <0>;
	316	gpmc,wr-data-mux-bus-ns = <0>;
	317	/* MTD partition table */
	318	/* All SPL-* partitions are sized to minimal length
	319	* which can be independently programmable. For
	320	* NAND flash this is equal to size of erase-block */
	321	#address-cells = <1>;
	322	#size-cells = <1>;
	323	partition@0 {
	324	label = "NAND.SPL";
	325	reg = <0x00000000 0x000020000>;
	326	};
	327	partition@1 {
	328	label = "NAND.SPL.backup1";
	329	reg = <0x00020000 0x00020000>;
	330	};
	331	partition@2 {
	332	label = "NAND.SPL.backup2";
	333	reg = <0x00040000 0x00020000>;
	334	};
	335	partition@3 {
	336	label = "NAND.SPL.backup3";
	337	reg = <0x00060000 0x00020000>;
	338	};
	339	partition@4 {
	340	label = "NAND.u-boot-spl-os";
	341	reg = <0x00080000 0x00040000>;
	342	};
	343	partition@5 {
	344	label = "NAND.u-boot";
	345	reg = <0x000c0000 0x00100000>;
346	};
347	partition@6 {
348	label = "NAND.u-boot-env";
349	reg = <0x001c0000 0x00020000>;
350	};
351	partition@7 {
352	label = "NAND.u-boot-env.backup1";
353	reg = <0x001e0000 0x00020000>;
354	};
355	partition@8 {
356	label = "NAND.kernel";
357	reg = <0x00200000 0x00800000>;
358	};
359	partition@9 {
360	label = "NAND.file-system";
361	reg = <0x00a00000 0x0f600000>;
362	};
363	};
364	};
365
a4240d3a NM	366	&omap_dwc3_1 {
	367	extcon = <&extcon_usb1>;
	368	};
	369
	370	&omap_dwc3_2 {
	371	extcon = <&extcon_usb2>;
	372	};
	373
	374	&usb1 {
	375	dr_mode = "peripheral";
a4240d3a NM	376	};
	377
	378	&usb2 {
	379	dr_mode = "host";
a4240d3a NM	380	};
	381
	382	&mmc1 {
	383	status = "okay";
	384	pinctrl-names = "default";
	385	pinctrl-0 = <&mmc1_pins_default>;
	386	vmmc-supply = <&evm_3v3_sd>;
a4240d3a NM	387	bus-width = <4>;
	388	/*
	389	* SDCD signal is not being used here - using the fact that GPIO mode
	390	* is a viable alternative
	391	*/
	392	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	393	max-frequency = <192000000>;
	394	};
	395
	396	&mmc2 {
	397	/* SW5-3 in ON position */
	398	status = "okay";
	399	pinctrl-names = "default";
	400	pinctrl-0 = <&mmc2_pins_default>;
	401
7172e745	402	vmmc-supply = <&evm_3v3_sw>;
a4240d3a NM	403	bus-width = <8>;
	404	ti,non-removable;
	405	max-frequency = <192000000>;
	406	};
	407
a4240d3a NM	408	&mac {
a4240d3a NM	409	status = "okay";
a4240d3a NM	410	};
	411
	412	&dcan1 {
	413	status = "ok";
	414	pinctrl-names = "default", "sleep", "active";
	415	pinctrl-0 = <&dcan1_pins_sleep>;
	416	pinctrl-1 = <&dcan1_pins_sleep>;
	417	pinctrl-2 = <&dcan1_pins_default>;
	418	};
	419
	420	&qspi {
	421	status = "okay";
a4240d3a	422
a0b83af0	423	spi-max-frequency = <76800000>;
a4240d3a NM	424	m25p80@0 {
a4240d3a NM	425	compatible = "s25fl256s1";
a0b83af0	426	spi-max-frequency = <76800000>;
a4240d3a NM	427	reg = <0>;
	428	spi-tx-bus-width = <1>;
	429	spi-rx-bus-width = <4>;
a4240d3a NM	430	#address-cells = <1>;
	431	#size-cells = <1>;
	432
	433	/* MTD partition table.
	434	* The ROM checks the first four physical blocks
	435	* for a valid file to boot and the flash here is
	436	* 64KiB block size.
	437	*/
	438	partition@0 {
	439	label = "QSPI.SPL";
	440	reg = <0x00000000 0x000010000>;
	441	};
	442	partition@1 {
	443	label = "QSPI.SPL.backup1";
	444	reg = <0x00010000 0x00010000>;
	445	};
	446	partition@2 {
	447	label = "QSPI.SPL.backup2";
	448	reg = <0x00020000 0x00010000>;
	449	};
	450	partition@3 {
	451	label = "QSPI.SPL.backup3";
	452	reg = <0x00030000 0x00010000>;
	453	};
	454	partition@4 {
	455	label = "QSPI.u-boot";
	456	reg = <0x00040000 0x00100000>;
	457	};
	458	partition@5 {
	459	label = "QSPI.u-boot-spl-os";
	460	reg = <0x00140000 0x00080000>;
	461	};
	462	partition@6 {
	463	label = "QSPI.u-boot-env";
	464	reg = <0x001c0000 0x00010000>;
	465	};
	466	partition@7 {
	467	label = "QSPI.u-boot-env.backup1";
	468	reg = <0x001d0000 0x0010000>;
	469	};
	470	partition@8 {
	471	label = "QSPI.kernel";
	472	reg = <0x001e0000 0x0800000>;
	473	};
	474	partition@9 {
	475	label = "QSPI.file-system";
	476	reg = <0x009e0000 0x01620000>;
	477	};
	478	};
	479	};
	480
	481	&dss {
	482	status = "ok";
a4240d3a NM	483	};
	484
	485	&hdmi {
	486	status = "ok";
	487
a4240d3a NM	488	port {
	489	hdmi_out: endpoint {
	490	remote-endpoint = <&tpd12s015_in>;
	491	};
	492	};
	493	};
	494
	495	&atl {
a4240d3a NM	496	assigned-clocks = <&abe_dpll_sys_clk_mux>,
	497	<&atl_gfclk_mux>,
	498	<&dpll_abe_ck>,
	499	<&dpll_abe_m2x2_ck>,
	500	<&atl_clkin2_ck>;
	501	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	502	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
	503
	504	status = "okay";
	505
	506	atl2 {
	507	bws = <DRA7_ATL_WS_MCASP2_FSX>;
	508	aws = <DRA7_ATL_WS_MCASP3_FSX>;
	509	};
	510	};
	511
	512	&mcasp3 {
	513	#sound-dai-cells = <0>;
a4240d3a NM	514
	515	assigned-clocks = <&mcasp3_ahclkx_mux>;
	516	assigned-clock-parents = <&atl_clkin2_ck>;
	517
	518	status = "okay";
	519
	520	op-mode = <0>; /* MCASP_IIS_MODE */
	521	tdm-slots = <2>;
	522	/* 4 serializer */
	523	serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
	524	1 2 0 0
	525	>;
	526	tx-num-evt = <32>;
	527	rx-num-evt = <32>;
	528	};
	529
	530	&mailbox5 {
	531	status = "okay";
	532	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
	533	status = "okay";
	534	};
	535	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
	536	status = "okay";
	537	};
	538	};
	539
	540	&mailbox6 {
	541	status = "okay";
	542	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
	543	status = "okay";
	544	};
	545	};