projects / thirdparty / kernel / stable.git / blame
| Commit | Line | Data |
|---|---|---|
| d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 56a9c909 WL |
2 | /* |
| 3 | * Hisilicon Ltd. HiP01 SoC | |
| 4 | * | |
| 5 | * Copyright (c) 2014 Hisilicon Ltd. | |
| 6 | * Copyright (c) 2014 Huawei Ltd. | |
| 7 | * | |
| 8 | * Author: Wang Long <long.wanglong@huawei.com> | |
| 56a9c909 WL |
9 | */ |
| 10 | ||
| 56a9c909 WL |
11 | / { |
| 12 | interrupt-parent = <&gic>; | |
| 13 | #address-cells = <1>; | |
| 14 | #size-cells = <1>; | |
| 15 | ||
| 16 | gic: interrupt-controller@1e001000 { | |
| 17 | compatible = "arm,cortex-a9-gic"; | |
| 18 | #interrupt-cells = <3>; | |
| 19 | #address-cells = <0>; | |
| 20 | interrupt-controller; | |
| 21 | reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>; | |
| 22 | }; | |
| 23 | ||
| 24 | hisi_refclk144mhz: refclk144mkhz { | |
| 25 | compatible = "fixed-clock"; | |
| 26 | #clock-cells = <0>; | |
| 27 | clock-frequency = <144000000>; | |
| 28 | clock-output-names = "hisi:refclk144khz"; | |
| 29 | }; | |
| 30 | ||
| 31 | soc { | |
| 32 | #address-cells = <1>; | |
| 33 | #size-cells = <1>; | |
| 34 | compatible = "simple-bus"; | |
| 35 | interrupt-parent = <&gic>; | |
| 36 | ranges = <0 0x10000000 0x20000000>; | |
| 37 | ||
| 38 | amba { | |
| 39 | #address-cells = <1>; | |
| 40 | #size-cells = <1>; | |
| 2ef7d5f3 | 41 | compatible = "simple-bus"; |
| 56a9c909 WL |
42 | ranges; |
| 43 | ||
| 44 | uart0: uart@10001000 { | |
| 45 | compatible = "snps,dw-apb-uart"; | |
| 46 | reg = <0x10001000 0x1000>; | |
| 47 | clocks = <&hisi_refclk144mhz>; | |
| 48 | clock-names = "apb_pclk"; | |
| 49 | reg-shift = <2>; | |
| 50 | interrupts = <0 32 4>; | |
| 51 | status = "disabled"; | |
| 52 | }; | |
| 53 | ||
| 54 | uart1: uart@10002000 { | |
| 55 | compatible = "snps,dw-apb-uart"; | |
| 56 | reg = <0x10002000 0x1000>; | |
| 57 | clocks = <&hisi_refclk144mhz>; | |
| 58 | clock-names = "apb_pclk"; | |
| 59 | reg-shift = <2>; | |
| 60 | interrupts = <0 33 4>; | |
| 61 | status = "disabled"; | |
| 62 | }; | |
| 63 | ||
| 64 | uart2: uart@10003000 { | |
| 65 | compatible = "snps,dw-apb-uart"; | |
| 66 | reg = <0x10003000 0x1000>; | |
| 67 | clocks = <&hisi_refclk144mhz>; | |
| 68 | clock-names = "apb_pclk"; | |
| 69 | reg-shift = <2>; | |
| 70 | interrupts = <0 34 4>; | |
| 71 | status = "disabled"; | |
| 72 | }; | |
| 73 | ||
| 74 | uart3: uart@10006000 { | |
| 75 | compatible = "snps,dw-apb-uart"; | |
| 76 | reg = <0x10006000 0x1000>; | |
| 77 | clocks = <&hisi_refclk144mhz>; | |
| 78 | clock-names = "apb_pclk"; | |
| 79 | reg-shift = <2>; | |
| 80 | interrupts = <0 4 4>; | |
| 81 | status = "disabled"; | |
| 82 | }; | |
| 83 | }; | |
| 84 | ||
| 85 | system-controller@10000000 { | |
| 86 | compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; | |
| 87 | reg = <0x10000000 0x1000>; | |
| 88 | reboot-offset = <0x4>; | |
| 89 | }; | |
| 90 | ||
| 8dccafaa | 91 | global_timer@a000200 { |
| 56a9c909 WL |
92 | compatible = "arm,cortex-a9-global-timer"; |
| 93 | reg = <0x0a000200 0x100>; | |
| 94 | interrupts = <1 11 0xf04>; | |
| 95 | clocks = <&hisi_refclk144mhz>; | |
| 96 | }; | |
| 97 | ||
| 8dccafaa | 98 | local_timer@a000600 { |
| 56a9c909 WL |
99 | compatible = "arm,cortex-a9-twd-timer"; |
| 100 | reg = <0x0a000600 0x100>; | |
| 101 | interrupts = <1 13 0xf04>; | |
| 102 | clocks = <&hisi_refclk144mhz>; | |
| 103 | }; | |
| 104 | }; | |
| 105 | }; |