[thirdparty/linux.git] / arch / arm / boot / dts / imx25-pdk.dts

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2013 Freescale Semiconductor, Inc.

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx25.dtsi"

/ {
	model = "Freescale i.MX25 Product Development Kit";
	compatible = "fsl,imx25-pdk", "fsl,imx25";

	memory@80000000 {
		reg = <0x80000000 0x4000000>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_fec_3v3: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "fec-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio2 3 0>;
			enable-active-high;
		};

		reg_2p5v: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "2P5V";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
		};

		reg_3p3v: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

		reg_can_3v3: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "can-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 6 0>;
		};
	};

	sound {
		compatible = "fsl,imx25-pdk-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx25-pdk-sgtl5000";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <4>;
	};

	wvga: display {
		model = "CLAA057VC01CW";
		bits-per-pixel = <16>;
		fsl,pcr = <0xfa208b80>;
		bus-width = <18>;
		native-mode = <&wvga_timings>;
		display-timings {
			wvga_timings: 640x480 {
				hactive = <640>;
				vactive = <480>;
				hback-porch = <45>;
				hfront-porch = <114>;
				hsync-len = <1>;
				vback-porch = <33>;
				vfront-porch = <11>;
				vsync-len = <1>;
				clock-frequency = <25200000>;
			};
		};
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1>;
	xceiver-supply = <&reg_can_3v3>;
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&fec {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-supply = <&reg_fec_3v3>;
	phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks 129>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};
};

&iomuxc {
	imx25-pdk {
		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX25_PAD_RW__AUD4_TXFS			0xe0
				MX25_PAD_OE__AUD4_TXC			0xe0
				MX25_PAD_EB0__AUD4_TXD			0xe0
				MX25_PAD_EB1__AUD4_RXD			0xe0
			>;
		};

		pinctrl_can1: can1grp {
			fsl,pins = <
				MX25_PAD_GPIO_A__CAN1_TX		0x0
				MX25_PAD_GPIO_B__CAN1_RX		0x0
				MX25_PAD_D14__GPIO_4_6 			0x80000000
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				MX25_PAD_SD1_CMD__ESDHC1_CMD		0x80000000
				MX25_PAD_SD1_CLK__ESDHC1_CLK		0x80000000
				MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x80000000
				MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x80000000
				MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x80000000
				MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x80000000
				MX25_PAD_A14__GPIO_2_0			0x80000000
				MX25_PAD_A15__GPIO_2_1			0x80000000
			>;
		};

		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
				MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
				MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
				MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
				MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
				MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
				MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
				MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
				MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
				MX25_PAD_A17__GPIO_2_3			0x80000000
				MX25_PAD_D12__GPIO_4_8			0x80000000
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
				MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
			>;
		};

		pinctrl_kpp: kppgrp {
			fsl,pins = <
				MX25_PAD_KPP_ROW0__KPP_ROW0	0x80000000
				MX25_PAD_KPP_ROW1__KPP_ROW1	0x80000000
				MX25_PAD_KPP_ROW2__KPP_ROW2	0x80000000
				MX25_PAD_KPP_ROW3__KPP_ROW3	0x80000000
				MX25_PAD_KPP_COL0__KPP_COL0	0x80000000
				MX25_PAD_KPP_COL1__KPP_COL1	0x80000000
				MX25_PAD_KPP_COL2__KPP_COL2	0x80000000
				MX25_PAD_KPP_COL3__KPP_COL3	0x80000000
			>;
		};

		pinctrl_lcd: lcdgrp {
			fsl,pins = <
				MX25_PAD_LD0__LD0		0xe0
				MX25_PAD_LD1__LD1		0xe0
				MX25_PAD_LD2__LD2		0xe0
				MX25_PAD_LD3__LD3		0xe0
				MX25_PAD_LD4__LD4		0xe0
				MX25_PAD_LD5__LD5		0xe0
				MX25_PAD_LD6__LD6		0xe0
				MX25_PAD_LD7__LD7		0xe0
				MX25_PAD_LD8__LD8		0xe0
				MX25_PAD_LD9__LD9		0xe0
				MX25_PAD_LD10__LD10		0xe0
				MX25_PAD_LD11__LD11		0xe0
				MX25_PAD_LD12__LD12		0xe0
				MX25_PAD_LD13__LD13		0xe0
				MX25_PAD_LD14__LD14		0xe0
				MX25_PAD_LD15__LD15		0xe0
				MX25_PAD_GPIO_E__LD16		0xe0
				MX25_PAD_GPIO_F__LD17		0xe0
				MX25_PAD_HSYNC__HSYNC		0xe0
				MX25_PAD_VSYNC__VSYNC		0xe0
				MX25_PAD_LSCLK__LSCLK		0xe0
				MX25_PAD_OE_ACD__OE_ACD		0xe0
				MX25_PAD_CONTRAST__CONTRAST	0xe0
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX25_PAD_UART1_RTS__UART1_RTS		0xe0
				MX25_PAD_UART1_CTS__UART1_CTS		0xe0
				MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
				MX25_PAD_UART1_RXD__UART1_RXD		0xc0
			>;
		};
	};
};

&lcdc {
	display = <&wvga>;
	fsl,lpccr = <0x00a903ff>;
	fsl,lscr1 = <0x00120300>;
	fsl,dmacr = <0x00020010>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd>;
	status = "okay";
};

&nfc {
	nand-on-flash-bbt;
	status = "okay";
};

&kpp {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_kpp>;
	linux,keymap = <
			MATRIX_KEY(0x0, 0x0, KEY_UP)
			MATRIX_KEY(0x0, 0x1, KEY_DOWN)
			MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
			MATRIX_KEY(0x0, 0x3, KEY_HOME)
			MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
			MATRIX_KEY(0x1, 0x1, KEY_LEFT)
			MATRIX_KEY(0x1, 0x2, KEY_ENTER)
			MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
			MATRIX_KEY(0x2, 0x0, KEY_F6)
			MATRIX_KEY(0x2, 0x1, KEY_F8)
			MATRIX_KEY(0x2, 0x2, KEY_F9)
			MATRIX_KEY(0x2, 0x3, KEY_F10)
			MATRIX_KEY(0x3, 0x0, KEY_F1)
			MATRIX_KEY(0x3, 0x1, KEY_F2)
			MATRIX_KEY(0x3, 0x2, KEY_F3)
			MATRIX_KEY(0x3, 0x2, KEY_POWER)
	>;
	status = "okay";
};

&ssi1 {
	status = "okay";
};

&tsc {
	status = "okay";
};

&tscadc {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	uart-has-rtscts;
	status = "okay";
};

&usbhost1 {
	phy_type = "serial";
	dr_mode = "host";
	status = "okay";
};

&usbotg {
	external-vbus-divider;
	status = "okay";
};
Commit	Line	Data
1f31e253 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright 2013 Freescale Semiconductor, Inc.
860c06f6 FE	4
860c06f6 FE	5	/dts-v1/;
cf75eb15	6	#include <dt-bindings/gpio/gpio.h>
9223dd87	7	#include <dt-bindings/input/input.h>
36dffd8f	8	#include "imx25.dtsi"
860c06f6 FE	9
	10	/ {
	11	model = "Freescale i.MX25 Product Development Kit";
	12	compatible = "fsl,imx25-pdk", "fsl,imx25";
	13
ad00e080	14	memory@80000000 {
860c06f6 FE	15	reg = <0x80000000 0x4000000>;
860c06f6 FE	16	};
6e3ef2f6 FE	17
	18	regulators {
	19	compatible = "simple-bus";
	20	#address-cells = <1>;
	21	#size-cells = <0>;
	22
	23	reg_fec_3v3: regulator@0 {
	24	compatible = "regulator-fixed";
	25	reg = <0>;
	26	regulator-name = "fec-3v3";
	27	regulator-min-microvolt = <3300000>;
	28	regulator-max-microvolt = <3300000>;
	29	gpio = <&gpio2 3 0>;
	30	enable-active-high;
	31	};
35d2bc8c FE	32
	33	reg_2p5v: regulator@1 {
	34	compatible = "regulator-fixed";
	35	reg = <1>;
	36	regulator-name = "2P5V";
	37	regulator-min-microvolt = <2500000>;
	38	regulator-max-microvolt = <2500000>;
	39	};
	40
	41	reg_3p3v: regulator@2 {
	42	compatible = "regulator-fixed";
	43	reg = <2>;
	44	regulator-name = "3P3V";
	45	regulator-min-microvolt = <3300000>;
	46	regulator-max-microvolt = <3300000>;
	47	};
	48
b04415cf FE	49	reg_can_3v3: regulator@3 {
	50	compatible = "regulator-fixed";
	51	reg = <3>;
	52	regulator-name = "can-3v3";
	53	regulator-min-microvolt = <3300000>;
	54	regulator-max-microvolt = <3300000>;
	55	gpio = <&gpio4 6 0>;
	56	};
35d2bc8c FE	57	};
	58
	59	sound {
	60	compatible = "fsl,imx25-pdk-sgtl5000",
	61	"fsl,imx-audio-sgtl5000";
	62	model = "imx25-pdk-sgtl5000";
	63	ssi-controller = <&ssi1>;
	64	audio-codec = <&codec>;
	65	audio-routing =
	66	"MIC_IN", "Mic Jack",
	67	"Mic Jack", "Mic Bias",
	68	"Headphone Jack", "HP_OUT";
	69	mux-int-port = <1>;
	70	mux-ext-port = <4>;
6e3ef2f6	71	};
fc26d5f2 FE	72
	73	wvga: display {
	74	model = "CLAA057VC01CW";
	75	bits-per-pixel = <16>;
	76	fsl,pcr = <0xfa208b80>;
	77	bus-width = <18>;
	78	native-mode = <&wvga_timings>;
	79	display-timings {
	80	wvga_timings: 640x480 {
	81	hactive = <640>;
	82	vactive = <480>;
	83	hback-porch = <45>;
	84	hfront-porch = <114>;
	85	hsync-len = <1>;
	86	vback-porch = <33>;
	87	vfront-porch = <11>;
	88	vsync-len = <1>;
	89	clock-frequency = <25200000>;
	90	};
	91	};
	92	};
860c06f6 FE	93	};
860c06f6 FE	94
35d2bc8c FE	95	&audmux {
	96	pinctrl-names = "default";
	97	pinctrl-0 = <&pinctrl_audmux>;
	98	status = "okay";
	99	};
	100
b04415cf FE	101	&can1 {
	102	pinctrl-names = "default";
	103	pinctrl-0 = <&pinctrl_can1>;
	104	xceiver-supply = <&reg_can_3v3>;
	105	status = "okay";
	106	};
	107
707e6906 FE	108	&esdhc1 {
	109	pinctrl-names = "default";
	110	pinctrl-0 = <&pinctrl_esdhc1>;
cf75eb15 DA	111	cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
cf75eb15 DA	112	wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
707e6906 FE	113	status = "okay";
	114	};
	115
860c06f6 FE	116	&fec {
860c06f6 FE	117	phy-mode = "rmii";
f0bd6881 FE	118	pinctrl-names = "default";
f0bd6881 FE	119	pinctrl-0 = <&pinctrl_fec>;
6e3ef2f6	120	phy-supply = <&reg_fec_3v3>;
12de44f5	121	phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
860c06f6 FE	122	status = "okay";
	123	};
	124
35d2bc8c FE	125	&i2c1 {
	126	clock-frequency = <100000>;
	127	pinctrl-names = "default";
	128	pinctrl-0 = <&pinctrl_i2c1>;
	129	status = "okay";
	130
8dccafaa	131	codec: sgtl5000@a {
35d2bc8c FE	132	compatible = "fsl,sgtl5000";
	133	reg = <0x0a>;
	134	clocks = <&clks 129>;
	135	VDDA-supply = <&reg_2p5v>;
	136	VDDIO-supply = <&reg_3p3v>;
	137	};
	138	};
	139
53ba9c70 FE	140	&iomuxc {
53ba9c70 FE	141	imx25-pdk {
35d2bc8c FE	142	pinctrl_audmux: audmuxgrp {
	143	fsl,pins = <
	144	MX25_PAD_RW__AUD4_TXFS 0xe0
	145	MX25_PAD_OE__AUD4_TXC 0xe0
	146	MX25_PAD_EB0__AUD4_TXD 0xe0
	147	MX25_PAD_EB1__AUD4_RXD 0xe0
	148	>;
	149	};
	150
b04415cf FE	151	pinctrl_can1: can1grp {
	152	fsl,pins = <
	153	MX25_PAD_GPIO_A__CAN1_TX 0x0
	154	MX25_PAD_GPIO_B__CAN1_RX 0x0
	155	MX25_PAD_D14__GPIO_4_6 0x80000000
	156	>;
	157	};
	158
707e6906 FE	159	pinctrl_esdhc1: esdhc1grp {
707e6906 FE	160	fsl,pins = <
d1bf7b44 BT	161	MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
	162	MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
	163	MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
	164	MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
	165	MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
	166	MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
707e6906 FE	167	MX25_PAD_A14__GPIO_2_0 0x80000000
	168	MX25_PAD_A15__GPIO_2_1 0x80000000
	169	>;
	170	};
	171
f0bd6881 FE	172	pinctrl_fec: fecgrp {
	173	fsl,pins = <
	174	MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
	175	MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
	176	MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
	177	MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
	178	MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
	179	MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
	180	MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
	181	MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
	182	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
6e3ef2f6	183	MX25_PAD_A17__GPIO_2_3 0x80000000
c7b15c28	184	MX25_PAD_D12__GPIO_4_8 0x80000000
f0bd6881 FE	185	>;
	186	};
	187
35d2bc8c FE	188	pinctrl_i2c1: i2c1grp {
	189	fsl,pins = <
	190	MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
	191	MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
	192	>;
	193	};
	194
9223dd87 FE	195	pinctrl_kpp: kppgrp {
	196	fsl,pins = <
	197	MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000
	198	MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000
	199	MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000
	200	MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000
	201	MX25_PAD_KPP_COL0__KPP_COL0 0x80000000
	202	MX25_PAD_KPP_COL1__KPP_COL1 0x80000000
	203	MX25_PAD_KPP_COL2__KPP_COL2 0x80000000
	204	MX25_PAD_KPP_COL3__KPP_COL3 0x80000000
	205	>;
	206	};
	207
fc26d5f2 FE	208	pinctrl_lcd: lcdgrp {
	209	fsl,pins = <
	210	MX25_PAD_LD0__LD0 0xe0
	211	MX25_PAD_LD1__LD1 0xe0
	212	MX25_PAD_LD2__LD2 0xe0
	213	MX25_PAD_LD3__LD3 0xe0
	214	MX25_PAD_LD4__LD4 0xe0
	215	MX25_PAD_LD5__LD5 0xe0
	216	MX25_PAD_LD6__LD6 0xe0
	217	MX25_PAD_LD7__LD7 0xe0
	218	MX25_PAD_LD8__LD8 0xe0
	219	MX25_PAD_LD9__LD9 0xe0
	220	MX25_PAD_LD10__LD10 0xe0
	221	MX25_PAD_LD11__LD11 0xe0
	222	MX25_PAD_LD12__LD12 0xe0
	223	MX25_PAD_LD13__LD13 0xe0
	224	MX25_PAD_LD14__LD14 0xe0
	225	MX25_PAD_LD15__LD15 0xe0
	226	MX25_PAD_GPIO_E__LD16 0xe0
	227	MX25_PAD_GPIO_F__LD17 0xe0
	228	MX25_PAD_HSYNC__HSYNC 0xe0
	229	MX25_PAD_VSYNC__VSYNC 0xe0
	230	MX25_PAD_LSCLK__LSCLK 0xe0
	231	MX25_PAD_OE_ACD__OE_ACD 0xe0
	232	MX25_PAD_CONTRAST__CONTRAST 0xe0
	233	>;
	234	};
9223dd87	235
53ba9c70 FE	236	pinctrl_uart1: uart1grp {
	237	fsl,pins = <
	238	MX25_PAD_UART1_RTS__UART1_RTS 0xe0
	239	MX25_PAD_UART1_CTS__UART1_CTS 0xe0
	240	MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
	241	MX25_PAD_UART1_RXD__UART1_RXD 0xc0
	242	>;
	243	};
	244	};
	245	};
	246
fc26d5f2 FE	247	&lcdc {
	248	display = <&wvga>;
	249	fsl,lpccr = <0x00a903ff>;
	250	fsl,lscr1 = <0x00120300>;
	251	fsl,dmacr = <0x00020010>;
	252	pinctrl-names = "default";
	253	pinctrl-0 = <&pinctrl_lcd>;
	254	status = "okay";
	255	};
	256
860c06f6 FE	257	&nfc {
	258	nand-on-flash-bbt;
	259	status = "okay";
	260	};
8617cb0b	261
9223dd87 FE	262	&kpp {
	263	pinctrl-names = "default";
	264	pinctrl-0 = <&pinctrl_kpp>;
	265	linux,keymap = <
	266	MATRIX_KEY(0x0, 0x0, KEY_UP)
	267	MATRIX_KEY(0x0, 0x1, KEY_DOWN)
	268	MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
	269	MATRIX_KEY(0x0, 0x3, KEY_HOME)
	270	MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
	271	MATRIX_KEY(0x1, 0x1, KEY_LEFT)
	272	MATRIX_KEY(0x1, 0x2, KEY_ENTER)
	273	MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
	274	MATRIX_KEY(0x2, 0x0, KEY_F6)
	275	MATRIX_KEY(0x2, 0x1, KEY_F8)
	276	MATRIX_KEY(0x2, 0x2, KEY_F9)
	277	MATRIX_KEY(0x2, 0x3, KEY_F10)
	278	MATRIX_KEY(0x3, 0x0, KEY_F1)
	279	MATRIX_KEY(0x3, 0x1, KEY_F2)
	280	MATRIX_KEY(0x3, 0x2, KEY_F3)
	281	MATRIX_KEY(0x3, 0x2, KEY_POWER)
	282	>;
	283	status = "okay";
	284	};
	285
35d2bc8c	286	&ssi1 {
35d2bc8c FE	287	status = "okay";
	288	};
	289
4a5b479b FE	290	&tsc {
	291	status = "okay";
	292	};
	293
	294	&tscadc {
	295	status = "okay";
	296	};
	297
8617cb0b	298	&uart1 {
53ba9c70 FE	299	pinctrl-names = "default";
53ba9c70 FE	300	pinctrl-0 = <&pinctrl_uart1>;
2e7c416c	301	uart-has-rtscts;
8617cb0b FE	302	status = "okay";
8617cb0b FE	303	};
f0ee0450 FE	304
	305	&usbhost1 {
	306	phy_type = "serial";
	307	dr_mode = "host";
	308	status = "okay";
	309	};
e60e9461 FE	310
e60e9461 FE	311	&usbotg {
e60e9461 FE	312	external-vbus-divider;
	313	status = "okay";
	314	};