[thirdparty/linux.git] / arch / arm / boot / dts / r7s9210.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R7S9210 SoC
 *
 * Copyright (C) 2018 Renesas Electronics Corporation
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r7s9210-cpg-mssr.h>

/ {
	compatible = "renesas,r7s9210";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	/* External clocks */
	extal_clk: extal {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* Value must be set by board */
		clock-frequency = <0>;
	};

	rtc_x1_clk: rtc_x1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* If clk present, value (32678) must be set by board */
		clock-frequency = <0>;
	};

	usb_x1_clk: usb_x1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* If clk present, value (48000000) must be set by board */
		clock-frequency = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <528000000>;
			next-level-cache = <&L2>;
		};
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		L2: cache-controller@1f003000 {
			compatible = "arm,pl310-cache";
			reg = <0x1f003000 0x1000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			arm,early-bresp-disable;
			arm,full-line-zero-disable;
			cache-unified;
			cache-level = <2>;
		};

		scif0: serial@e8007000 {
			compatible = "renesas,scif-r7s9210";
			reg = <0xe8007000 0x18>;
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD 47>;
			clock-names = "fck";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif1: serial@e8007800 {
			compatible = "renesas,scif-r7s9210";
			reg = <0xe8007800 0x18>;
			interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD 46>;
			clock-names = "fck";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif2: serial@e8008000 {
			compatible = "renesas,scif-r7s9210";
			reg = <0xe8008000 0x18>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD 45>;
			clock-names = "fck";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif3: serial@e8008800 {
			compatible = "renesas,scif-r7s9210";
			reg = <0xe8008800 0x18>;
			interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD 44>;
			clock-names = "fck";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif4: serial@e8009000 {
			compatible = "renesas,scif-r7s9210";
			reg = <0xe8009000 0x18>;
			interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD 43>;
			clock-names = "fck";
			power-domains = <&cpg>;
			status = "disabled";
		};

		spi0: spi@e800c800 {
			compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
			reg = <0xe800c800 0x24>;
			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD 97>;
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@e800d000 {
			compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
			reg = <0xe800d000 0x24>;
			interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD 96>;
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@e800d800 {
			compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
			reg = <0xe800d800 0x24>;
			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD 95>;
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ether0: ethernet@e8204000 {
			compatible = "renesas,ether-r7s9210";
			reg = <0xe8204000 0x200>;
			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 65>;
			power-domains = <&cpg>;

			phy-mode = "rmii";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ether1: ethernet@e8204200 {
			compatible = "renesas,ether-r7s9210";
			reg = <0xe8204200 0x200>;
			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 64>;
			power-domains = <&cpg>;
			phy-mode = "rmii";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c0: i2c@e803a000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
			reg = <0xe803a000 0x44>;
			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 87>;
			power-domains = <&cpg>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c1: i2c@e803a400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
			reg = <0xe803a400 0x44>;
			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 86>;
			power-domains = <&cpg>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c2: i2c@e803a800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
			reg = <0xe803a800 0x44>;
			interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 85>;
			power-domains = <&cpg>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c3: i2c@e803ac00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
			reg = <0xe803ac00 0x44>;
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 84>;
			power-domains = <&cpg>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		ostm0: timer@e803b000 {
			compatible = "renesas,r7s9210-ostm", "renesas,ostm";
			reg = <0xe803b000 0x30>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 36>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm1: timer@e803c000 {
			compatible = "renesas,r7s9210-ostm", "renesas,ostm";
			reg = <0xe803c000 0x30>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 35>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm2: timer@e803d000 {
			compatible = "renesas,r7s9210-ostm", "renesas,ostm";
			reg = <0xe803d000 0x30>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 34>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ohci0: usb@e8218000 {
			compatible = "generic-ohci";
			reg = <0xe8218000 0x100>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 61>;
			phys = <&usb2_phy0>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		ehci0: usb@e8218100 {
			compatible = "generic-ehci";
			reg = <0xe8218100 0x100>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 61>;
			phys = <&usb2_phy0>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		usb2_phy0: usb-phy@e8218200 {
			compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
			reg = <0xe8218200 0x700>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>;
			clock-names = "fck", "usb_x1";
			power-domains = <&cpg>;
			#phy-cells = <0>;
			status = "disabled";
		};

		usbhs0: usb@e8219000 {
			compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
			reg = <0xe8219000 0x724>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 61>;
			renesas,buswait = <7>;
			phys = <&usb2_phy0>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		ohci1: usb@e821a000 {
			compatible = "generic-ohci";
			reg = <0xe821a000 0x100>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 60>;
			phys = <&usb2_phy1>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		ehci1: usb@e821a100 {
			compatible = "generic-ehci";
			reg = <0xe821a100 0x100>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 60>;
			phys = <&usb2_phy1>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		usb2_phy1: usb-phy@e821a200 {
			compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
			reg = <0xe821a200 0x700>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>;
			clock-names = "fck", "usb_x1";
			power-domains = <&cpg>;
			#phy-cells = <0>;
			status = "disabled";
		};

		usbhs1: usb@e821b000 {
			compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
			reg = <0xe821b000 0x724>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 60>;
			renesas,buswait = <7>;
			phys = <&usb2_phy1>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		sdhi0: sd@e8228000 {
			compatible = "renesas,sdhi-r7s9210";
			reg = <0xe8228000 0x8c0>;
			interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>;
			clock-names = "core", "cd";
			power-domains = <&cpg>;
			cap-sd-highspeed;
			cap-sdio-irq;
			status = "disabled";
		};

		sdhi1: sd@e822a000 {
			compatible = "renesas,sdhi-r7s9210";
			reg = <0xe822a000 0x8c0>;
			interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>;
			clock-names = "core", "cd";
			power-domains = <&cpg>;
			cap-sd-highspeed;
			cap-sdio-irq;
			status = "disabled";
		};

		gic: interrupt-controller@e8221000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0xe8221000 0x1000>,
			      <0xe8222000 0x1000>;
		};

		cpg: clock-controller@fcfe0010 {
			compatible = "renesas,r7s9210-cpg-mssr";
			reg = <0xfcfe0010 0x455>;
			clocks = <&extal_clk>;
			clock-names = "extal";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
		};

		wdt: watchdog@fcfe7000 {
			compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
			reg = <0xfcfe7000 0x26>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
		};

		bsid: chipid@fcfe8004 {
			compatible = "renesas,bsid";
			reg = <0xfcfe8004 4>;
		};

		irqc: interrupt-controller@fcfef800 {
			compatible = "renesas,r7s9210-irqc",
				     "renesas,rza1-irqc";
			#interrupt-cells = <2>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0xfcfef800 0x6>;
			interrupt-map =
				<0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				<1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
				<2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				<3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
				<4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				<5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				<6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				<7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-map-mask = <7 0>;
		};

		pinctrl: pin-controller@fcffe000 {
			compatible = "renesas,r7s9210-pinctrl";
			reg = <0xfcffe000 0x1000>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 176>;
		};
	};
};
Commit	Line	Data
bbbcd02b CB	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Device Tree Source for the R7S9210 SoC
	4	*
	5	* Copyright (C) 2018 Renesas Electronics Corporation
	6	*
	7	*/
	8
	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
	10	#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
	11
	12	/ {
	13	compatible = "renesas,r7s9210";
	14	interrupt-parent = <&gic>;
	15	#address-cells = <1>;
	16	#size-cells = <1>;
	17
	18	/* External clocks */
	19	extal_clk: extal {
	20	#clock-cells = <0>;
	21	compatible = "fixed-clock";
	22	/* Value must be set by board */
	23	clock-frequency = <0>;
	24	};
	25
	26	rtc_x1_clk: rtc_x1 {
	27	#clock-cells = <0>;
	28	compatible = "fixed-clock";
	29	/* If clk present, value (32678) must be set by board */
	30	clock-frequency = <0>;
283f881a CB	31	};
	32
	33	usb_x1_clk: usb_x1 {
	34	#clock-cells = <0>;
	35	compatible = "fixed-clock";
	36	/* If clk present, value (48000000) must be set by board */
	37	clock-frequency = <0>;
bbbcd02b CB	38	};
	39
	40	cpus {
	41	#address-cells = <1>;
	42	#size-cells = <0>;
	43
	44	cpu@0 {
	45	device_type = "cpu";
	46	compatible = "arm,cortex-a9";
	47	reg = <0>;
	48	clock-frequency = <528000000>;
	49	next-level-cache = <&L2>;
	50	};
	51	};
	52
	53	soc {
	54	compatible = "simple-bus";
	55	interrupt-parent = <&gic>;
	56
	57	#address-cells = <1>;
	58	#size-cells = <1>;
	59	ranges;
	60
	61	L2: cache-controller@1f003000 {
	62	compatible = "arm,pl310-cache";
	63	reg = <0x1f003000 0x1000>;
	64	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	65	arm,early-bresp-disable;
	66	arm,full-line-zero-disable;
	67	cache-unified;
	68	cache-level = <2>;
	69	};
	70
	71	scif0: serial@e8007000 {
	72	compatible = "renesas,scif-r7s9210";
	73	reg = <0xe8007000 0x18>;
	74	interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
	75	<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
	76	<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
	77	<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
	78	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
	79	<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	80	interrupt-names = "eri", "rxi", "txi",
	81	"bri", "dri", "tei";
	82	clocks = <&cpg CPG_MOD 47>;
	83	clock-names = "fck";
	84	power-domains = <&cpg>;
	85	status = "disabled";
	86	};
	87
	88	scif1: serial@e8007800 {
	89	compatible = "renesas,scif-r7s9210";
	90	reg = <0xe8007800 0x18>;
	91	interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
	92	<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
	93	<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
	94	<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
	95	<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
	96	<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
	97	interrupt-names = "eri", "rxi", "txi",
	98	"bri", "dri", "tei";
	99	clocks = <&cpg CPG_MOD 46>;
	100	clock-names = "fck";
	101	power-domains = <&cpg>;
102	status = "disabled";
103	};
104
105	scif2: serial@e8008000 {
106	compatible = "renesas,scif-r7s9210";
107	reg = <0xe8008000 0x18>;
108	interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
109	<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
110	<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
111	<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
112	<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
113	<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
114	interrupt-names = "eri", "rxi", "txi",
115	"bri", "dri", "tei";
116	clocks = <&cpg CPG_MOD 45>;
117	clock-names = "fck";
118	power-domains = <&cpg>;
119	status = "disabled";
120	};
121
122	scif3: serial@e8008800 {
123	compatible = "renesas,scif-r7s9210";
124	reg = <0xe8008800 0x18>;
125	interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
126	<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
127	<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
128	<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
129	<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
130	<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
131	interrupt-names = "eri", "rxi", "txi",
132	"bri", "dri", "tei";
133	clocks = <&cpg CPG_MOD 44>;
134	clock-names = "fck";
135	power-domains = <&cpg>;
136	status = "disabled";
137	};
138
139	scif4: serial@e8009000 {
140	compatible = "renesas,scif-r7s9210";
141	reg = <0xe8009000 0x18>;
142	interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
143	<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
144	<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
145	<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
146	<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
147	<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
148	interrupt-names = "eri", "rxi", "txi",
149	"bri", "dri", "tei";
150	clocks = <&cpg CPG_MOD 43>;
151	clock-names = "fck";
152	power-domains = <&cpg>;
153	status = "disabled";
154	};
155
9105996b CB	156	spi0: spi@e800c800 {
	157	compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
	158	reg = <0xe800c800 0x24>;
	159	interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
	160	<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
	161	<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
	162	interrupt-names = "error", "rx", "tx";
	163	clocks = <&cpg CPG_MOD 97>;
	164	power-domains = <&cpg>;
	165	num-cs = <1>;
	166	#address-cells = <1>;
	167	#size-cells = <0>;
	168	status = "disabled";
	169	};
	170
	171	spi1: spi@e800d000 {
	172	compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
	173	reg = <0xe800d000 0x24>;
	174	interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	175	<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	176	<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
	177	interrupt-names = "error", "rx", "tx";
	178	clocks = <&cpg CPG_MOD 96>;
	179	power-domains = <&cpg>;
	180	num-cs = <1>;
	181	#address-cells = <1>;
	182	#size-cells = <0>;
	183	status = "disabled";
	184	};
	185
	186	spi2: spi@e800d800 {
	187	compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
	188	reg = <0xe800d800 0x24>;
	189	interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	190	<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
	191	<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
	192	interrupt-names = "error", "rx", "tx";
	193	clocks = <&cpg CPG_MOD 95>;
	194	power-domains = <&cpg>;
	195	num-cs = <1>;
	196	#address-cells = <1>;
	197	#size-cells = <0>;
	198	status = "disabled";
	199	};
	200
cbcb6391 CB	201	ether0: ethernet@e8204000 {
	202	compatible = "renesas,ether-r7s9210";
	203	reg = <0xe8204000 0x200>;
	204	interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
	205	clocks = <&cpg CPG_MOD 65>;
	206	power-domains = <&cpg>;
	207
	208	phy-mode = "rmii";
	209	#address-cells = <1>;
	210	#size-cells = <0>;
	211	status = "disabled";
	212	};
	213
	214	ether1: ethernet@e8204200 {
	215	compatible = "renesas,ether-r7s9210";
	216	reg = <0xe8204200 0x200>;
	217	interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
	218	clocks = <&cpg CPG_MOD 64>;
	219	power-domains = <&cpg>;
	220	phy-mode = "rmii";
	221	#address-cells = <1>;
	222	#size-cells = <0>;
	223	status = "disabled";
	224	};
	225
49da03c6 CB	226	i2c0: i2c@e803a000 {
	227	#address-cells = <1>;
	228	#size-cells = <0>;
	229	compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
	230	reg = <0xe803a000 0x44>;
	231	interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
	232	<GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
	233	<GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
	234	<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
	235	<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
	236	<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
	237	<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
	238	<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
	239	clocks = <&cpg CPG_MOD 87>;
	240	power-domains = <&cpg>;
	241	clock-frequency = <100000>;
	242	status = "disabled";
	243	};
	244
	245	i2c1: i2c@e803a400 {
	246	#address-cells = <1>;
	247	#size-cells = <0>;
	248	compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
	249	reg = <0xe803a400 0x44>;
	250	interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
	251	<GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
	252	<GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
	253	<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
	254	<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
	255	<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
	256	<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
	257	<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
	258	clocks = <&cpg CPG_MOD 86>;
	259	power-domains = <&cpg>;
	260	clock-frequency = <100000>;
	261	status = "disabled";
	262	};
	263
	264	i2c2: i2c@e803a800 {
	265	#address-cells = <1>;
	266	#size-cells = <0>;
	267	compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
	268	reg = <0xe803a800 0x44>;
	269	interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
	270	<GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
	271	<GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
	272	<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
	273	<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
	274	<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
	275	<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
	276	<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
	277	clocks = <&cpg CPG_MOD 85>;
	278	power-domains = <&cpg>;
	279	clock-frequency = <100000>;
	280	status = "disabled";
	281	};
	282
	283	i2c3: i2c@e803ac00 {
	284	#address-cells = <1>;
	285	#size-cells = <0>;
	286	compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
	287	reg = <0xe803ac00 0x44>;
	288	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	289	<GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
290	<GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
291	<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
292	<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
293	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
294	<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
295	<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
296	clocks = <&cpg CPG_MOD 84>;
297	power-domains = <&cpg>;
298	clock-frequency = <100000>;
299	status = "disabled";
300	};
301
bbbcd02b CB	302	ostm0: timer@e803b000 {
	303	compatible = "renesas,r7s9210-ostm", "renesas,ostm";
	304	reg = <0xe803b000 0x30>;
	305	interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
	306	clocks = <&cpg CPG_MOD 36>;
bbbcd02b CB	307	power-domains = <&cpg>;
	308	status = "disabled";
	309	};
	310
	311	ostm1: timer@e803c000 {
	312	compatible = "renesas,r7s9210-ostm", "renesas,ostm";
	313	reg = <0xe803c000 0x30>;
	314	interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
	315	clocks = <&cpg CPG_MOD 35>;
bbbcd02b CB	316	power-domains = <&cpg>;
	317	status = "disabled";
	318	};
	319
	320	ostm2: timer@e803d000 {
	321	compatible = "renesas,r7s9210-ostm", "renesas,ostm";
	322	reg = <0xe803d000 0x30>;
	323	interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
	324	clocks = <&cpg CPG_MOD 34>;
bbbcd02b CB	325	power-domains = <&cpg>;
	326	status = "disabled";
	327	};
	328
9d8c794e CB	329	ohci0: usb@e8218000 {
	330	compatible = "generic-ohci";
	331	reg = <0xe8218000 0x100>;
	332	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	333	clocks = <&cpg CPG_MOD 61>;
	334	phys = <&usb2_phy0>;
	335	phy-names = "usb";
	336	power-domains = <&cpg>;
	337	status = "disabled";
	338	};
	339
	340	ehci0: usb@e8218100 {
	341	compatible = "generic-ehci";
	342	reg = <0xe8218100 0x100>;
	343	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	344	clocks = <&cpg CPG_MOD 61>;
	345	phys = <&usb2_phy0>;
	346	phy-names = "usb";
	347	power-domains = <&cpg>;
	348	status = "disabled";
	349	};
	350
	351	usb2_phy0: usb-phy@e8218200 {
	352	compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
	353	reg = <0xe8218200 0x700>;
	354	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	355	clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>;
	356	clock-names = "fck", "usb_x1";
	357	power-domains = <&cpg>;
	358	#phy-cells = <0>;
	359	status = "disabled";
	360	};
	361
f56e674d CB	362	usbhs0: usb@e8219000 {
	363	compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
	364	reg = <0xe8219000 0x724>;
	365	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	366	clocks = <&cpg CPG_MOD 61>;
	367	renesas,buswait = <7>;
	368	phys = <&usb2_phy0>;
	369	phy-names = "usb";
	370	power-domains = <&cpg>;
	371	status = "disabled";
	372	};
	373
9d8c794e CB	374	ohci1: usb@e821a000 {
	375	compatible = "generic-ohci";
	376	reg = <0xe821a000 0x100>;
	377	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	378	clocks = <&cpg CPG_MOD 60>;
	379	phys = <&usb2_phy1>;
	380	phy-names = "usb";
	381	power-domains = <&cpg>;
	382	status = "disabled";
	383	};
	384
	385	ehci1: usb@e821a100 {
	386	compatible = "generic-ehci";
	387	reg = <0xe821a100 0x100>;
	388	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	389	clocks = <&cpg CPG_MOD 60>;
	390	phys = <&usb2_phy1>;
	391	phy-names = "usb";
	392	power-domains = <&cpg>;
	393	status = "disabled";
	394	};
	395
	396	usb2_phy1: usb-phy@e821a200 {
	397	compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
	398	reg = <0xe821a200 0x700>;
	399	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	400	clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>;
	401	clock-names = "fck", "usb_x1";
	402	power-domains = <&cpg>;
	403	#phy-cells = <0>;
	404	status = "disabled";
	405	};
	406
f56e674d CB	407	usbhs1: usb@e821b000 {
	408	compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
	409	reg = <0xe821b000 0x724>;
	410	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	411	clocks = <&cpg CPG_MOD 60>;
	412	renesas,buswait = <7>;
	413	phys = <&usb2_phy1>;
	414	phy-names = "usb";
	415	power-domains = <&cpg>;
	416	status = "disabled";
	417	};
	418
a49f76cd CB	419	sdhi0: sd@e8228000 {
	420	compatible = "renesas,sdhi-r7s9210";
	421	reg = <0xe8228000 0x8c0>;
	422	interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
	423	clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>;
	424	clock-names = "core", "cd";
	425	power-domains = <&cpg>;
	426	cap-sd-highspeed;
	427	cap-sdio-irq;
	428	status = "disabled";
	429	};
	430
	431	sdhi1: sd@e822a000 {
	432	compatible = "renesas,sdhi-r7s9210";
	433	reg = <0xe822a000 0x8c0>;
	434	interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
	435	clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>;
	436	clock-names = "core", "cd";
	437	power-domains = <&cpg>;
	438	cap-sd-highspeed;
	439	cap-sdio-irq;
	440	status = "disabled";
	441	};
	442
bbbcd02b CB	443	gic: interrupt-controller@e8221000 {
	444	compatible = "arm,gic-400";
	445	#interrupt-cells = <3>;
	446	#address-cells = <0>;
	447	interrupt-controller;
	448	reg = <0xe8221000 0x1000>,
	449	<0xe8222000 0x1000>;
	450	};
	451
	452	cpg: clock-controller@fcfe0010 {
	453	compatible = "renesas,r7s9210-cpg-mssr";
	454	reg = <0xfcfe0010 0x455>;
	455	clocks = <&extal_clk>;
	456	clock-names = "extal";
	457	#clock-cells = <2>;
	458	#power-domain-cells = <0>;
	459	};
	460
	461	wdt: watchdog@fcfe7000 {
	462	compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
	463	reg = <0xfcfe7000 0x26>;
	464	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	465	clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
	466	};
	467
	468	bsid: chipid@fcfe8004 {
	469	compatible = "renesas,bsid";
	470	reg = <0xfcfe8004 4>;
	471	};
	472
e23391f3 CB	473	irqc: interrupt-controller@fcfef800 {
	474	compatible = "renesas,r7s9210-irqc",
	475	"renesas,rza1-irqc";
	476	#interrupt-cells = <2>;
	477	#address-cells = <0>;
	478	interrupt-controller;
	479	reg = <0xfcfef800 0x6>;
	480	interrupt-map =
	481	<0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	482	<1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	483	<2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	484	<3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	485	<4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	486	<5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	487	<6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	488	<7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	489	interrupt-map-mask = <7 0>;
	490	};
	491
bbbcd02b CB	492	pinctrl: pin-controller@fcffe000 {
	493	compatible = "renesas,r7s9210-pinctrl";
	494	reg = <0xfcffe000 0x1000>;
	495
	496	gpio-controller;
	497	#gpio-cells = <2>;
	498	gpio-ranges = <&pinctrl 0 0 176>;
	499	};
	500	};
	501	};