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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / arch / arm / boot / dts / r8a73a4.dtsi
CommitLineData
cdbfaf64 1// SPDX-License-Identifier: GPL-2.0
eccf0607
MD		 2/*
3 * Device Tree Source for the r8a73a4 SoC
4 *
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Magnus Damm
eccf0607
MD		 7 */
8
a76809a3 9#include <dt-bindings/clock/r8a73a4-clock.h>
5f75e73c
LP		 10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
eccf0607
MD		 13/ {
14 compatible = "renesas,r8a73a4";
15 interrupt-parent = <&gic>;
26a0d2d4
TY		 16 #address-cells = <2>;
17 #size-cells = <2>;
eccf0607
MD		 18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu0: cpu@0 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a15";
26 reg = <0>;
a7869a5b 27 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
eccf0607 28 clock-frequency = <1500000000>;
7b9ad9a0 29 power-domains = <&pd_a2sl>;
c86a4b62 30 next-level-cache = <&L2_CA15>;
eccf0607 31 };
b0da45c6 32
cdaf6417 33 L2_CA15: cache-controller-0 {
b0da45c6 34 compatible = "cache";
b0da45c6
GU		 35 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
36 power-domains = <&pd_a3sm>;
37 cache-unified;
38 cache-level = <2>;
39 };
40
cdaf6417 41 L2_CA7: cache-controller-1 {
b0da45c6 42 compatible = "cache";
b0da45c6
GU		 43 clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
44 power-domains = <&pd_a3km>;
45 cache-unified;
46 cache-level = <2>;
47 };
eccf0607
MD		 48 };
49
7b9ad9a0
GU		 50 ptm {
51 compatible = "arm,coresight-etm3x";
52 power-domains = <&pd_d4>;
53 };
54
eccf0607
MD		 55 timer {
56 compatible = "arm,armv7-timer";
45e75c42
GU		 57 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
58 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
59 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
60 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
eccf0607 61 };
984ca295 62
35dd549c
GU		 63 dbsc1: memory-controller@e6790000 {
64 compatible = "renesas,dbsc-r8a73a4";
65 reg = <0 0xe6790000 0 0x10000>;
7b9ad9a0 66 power-domains = <&pd_a3bc>;
35dd549c
GU		 67 };
68
69 dbsc2: memory-controller@e67a0000 {
70 compatible = "renesas,dbsc-r8a73a4";
71 reg = <0 0xe67a0000 0 0x10000>;
7b9ad9a0 72 power-domains = <&pd_a3bc>;
35dd549c
GU		 73 };
74
7300505a
UH		 75 dmac: dma-multiplexer {
76 compatible = "renesas,shdma-mux";
77 #dma-cells = <1>;
78 dma-channels = <20>;
79 dma-requests = <256>;
80 #address-cells = <2>;
81 #size-cells = <2>;
82 ranges;
83
84 dma0: dma-controller@e6700020 {
85 compatible = "renesas,shdma-r8a73a4";
86 reg = <0 0xe6700020 0 0x89e0>;
c2e952ef
GU		 87 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
7300505a
UH		 108 interrupt-names = "error",
109 "ch0", "ch1", "ch2", "ch3",
110 "ch4", "ch5", "ch6", "ch7",
111 "ch8", "ch9", "ch10", "ch11",
112 "ch12", "ch13", "ch14", "ch15",
113 "ch16", "ch17", "ch18", "ch19";
662dd64f 114 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
7b9ad9a0 115 power-domains = <&pd_a3sp>;
7300505a
UH		 116 };
117 };
118
7300505a
UH		 119 i2c5: i2c@e60b0000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
7e9ad4d0 122 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
7300505a 123 reg = <0 0xe60b0000 0 0x428>;
4d5746a3 124 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 125 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
7b9ad9a0 126 power-domains = <&pd_a3sp>;
f7b65230
SH		 127
128 status = "disabled";
129 };
130
131 cmt1: timer@e6130000 {
86656e9c 132 compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
f7b65230 133 reg = <0 0xe6130000 0 0x1004>;
0f739fdf
GU		 134 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
662dd64f
UH		 142 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
143 clock-names = "fck";
7b9ad9a0 144 power-domains = <&pd_c5>;
7300505a
UH		 145 status = "disabled";
146 };
147
984ca295 148 irqc0: interrupt-controller@e61c0000 {
34abee39 149 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
984ca295
MD		 150 #interrupt-cells = <2>;
151 interrupt-controller;
26a0d2d4 152 reg = <0 0xe61c0000 0 0x200>;
4d5746a3
SH		 153 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1c2a7eb7 185 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
7b9ad9a0 186 power-domains = <&pd_c4>;
984ca295
MD		 187 };
188
189 irqc1: interrupt-controller@e61c0200 {
34abee39 190 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
984ca295
MD		 191 #interrupt-cells = <2>;
192 interrupt-controller;
26a0d2d4 193 reg = <0 0xe61c0200 0 0x200>;
4d5746a3
SH		 194 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1c2a7eb7 220 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
7b9ad9a0 221 power-domains = <&pd_c4>;
984ca295
MD		 222 };
223
5b9906c9 224 pfc: pin-controller@e6050000 {
e4ba0a9b
GU		 225 compatible = "renesas,pfc-r8a73a4";
226 reg = <0 0xe6050000 0 0x9000>;
227 gpio-controller;
228 #gpio-cells = <2>;
17ccec50
GU		 229 gpio-ranges =
230 <&pfc 0 0 31>, <&pfc 32 32 9>,
231 <&pfc 64 64 22>, <&pfc 96 96 31>,
232 <&pfc 128 128 7>, <&pfc 160 160 19>,
233 <&pfc 192 192 31>, <&pfc 224 224 27>,
234 <&pfc 256 256 28>, <&pfc 288 288 21>,
235 <&pfc 320 320 10>;
e4ba0a9b
GU		 236 interrupts-extended =
237 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
238 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
239 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
240 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
241 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
242 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
243 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
244 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
245 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
246 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
247 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
248 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
249 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
250 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
251 <&irqc1 24 0>, <&irqc1 25 0>;
7b9ad9a0 252 power-domains = <&pd_c5>;
e4ba0a9b
GU		 253 };
254
c91cf2fa 255 thermal@e61f0000 {
a2cfaa74 256 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
26a0d2d4
TY		 257 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
258 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
4d5746a3 259 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 260 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
7b9ad9a0 261 power-domains = <&pd_c5>;
c91cf2fa 262 };
f98c1069
GL		 263
264 i2c0: i2c@e6500000 {
265 #address-cells = <1>;
266 #size-cells = <0>;
7e9ad4d0 267 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 268 reg = <0 0xe6500000 0 0x428>;
4d5746a3 269 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 270 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
7b9ad9a0 271 power-domains = <&pd_a3sp>;
eda3a4fa 272 status = "disabled";
f98c1069
GL		 273 };
274
275 i2c1: i2c@e6510000 {
276 #address-cells = <1>;
277 #size-cells = <0>;
7e9ad4d0 278 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 279 reg = <0 0xe6510000 0 0x428>;
4d5746a3 280 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 281 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
7b9ad9a0 282 power-domains = <&pd_a3sp>;
eda3a4fa 283 status = "disabled";
f98c1069
GL		 284 };
285
286 i2c2: i2c@e6520000 {
287 #address-cells = <1>;
288 #size-cells = <0>;
7e9ad4d0 289 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 290 reg = <0 0xe6520000 0 0x428>;
4d5746a3 291 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 292 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
7b9ad9a0 293 power-domains = <&pd_a3sp>;
eda3a4fa 294 status = "disabled";
f98c1069
GL		 295 };
296
297 i2c3: i2c@e6530000 {
298 #address-cells = <1>;
299 #size-cells = <0>;
7e9ad4d0 300 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 301 reg = <0 0xe6530000 0 0x428>;
4d5746a3 302 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 303 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
7b9ad9a0 304 power-domains = <&pd_a3sp>;
eda3a4fa 305 status = "disabled";
f98c1069
GL		 306 };
307
308 i2c4: i2c@e6540000 {
309 #address-cells = <1>;
310 #size-cells = <0>;
7e9ad4d0 311 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 312 reg = <0 0xe6540000 0 0x428>;
4d5746a3 313 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 314 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
7b9ad9a0 315 power-domains = <&pd_a3sp>;
eda3a4fa 316 status = "disabled";
f98c1069
GL		 317 };
318
f98c1069
GL		 319 i2c6: i2c@e6550000 {
320 #address-cells = <1>;
321 #size-cells = <0>;
7e9ad4d0 322 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 323 reg = <0 0xe6550000 0 0x428>;
4d5746a3 324 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 325 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
7b9ad9a0 326 power-domains = <&pd_a3sp>;
eda3a4fa 327 status = "disabled";
f98c1069
GL		 328 };
329
330 i2c7: i2c@e6560000 {
331 #address-cells = <1>;
332 #size-cells = <0>;
7e9ad4d0 333 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 334 reg = <0 0xe6560000 0 0x428>;
4d5746a3 335 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 336 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
7b9ad9a0 337 power-domains = <&pd_a3sp>;
eda3a4fa 338 status = "disabled";
f98c1069
GL		 339 };
340
341 i2c8: i2c@e6570000 {
342 #address-cells = <1>;
343 #size-cells = <0>;
7e9ad4d0 344 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 345 reg = <0 0xe6570000 0 0x428>;
4d5746a3 346 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 347 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
7b9ad9a0 348 power-domains = <&pd_a3sp>;
94f1a03d
SH		 349 status = "disabled";
350 };
351
0b3a0ef6 352 scifb0: serial@e6c20000 {
94f1a03d
SH		 353 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
354 reg = <0 0xe6c20000 0 0x100>;
4d5746a3 355 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 356 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
d4be2f1b 357 clock-names = "fck";
7b9ad9a0 358 power-domains = <&pd_a3sp>;
94f1a03d
SH		 359 status = "disabled";
360 };
361
0b3a0ef6 362 scifb1: serial@e6c30000 {
94f1a03d
SH		 363 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
364 reg = <0 0xe6c30000 0 0x100>;
4d5746a3 365 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 366 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
d4be2f1b 367 clock-names = "fck";
7b9ad9a0 368 power-domains = <&pd_a3sp>;
94f1a03d
SH		 369 status = "disabled";
370 };
371
7300505a
UH		 372 scifa0: serial@e6c40000 {
373 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
374 reg = <0 0xe6c40000 0 0x100>;
4d5746a3 375 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 376 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
d4be2f1b 377 clock-names = "fck";
7b9ad9a0 378 power-domains = <&pd_a3sp>;
7300505a
UH		 379 status = "disabled";
380 };
381
382 scifa1: serial@e6c50000 {
383 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
384 reg = <0 0xe6c50000 0 0x100>;
4d5746a3 385 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 386 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
d4be2f1b 387 clock-names = "fck";
7b9ad9a0 388 power-domains = <&pd_a3sp>;
7300505a
UH		 389 status = "disabled";
390 };
391
0b3a0ef6 392 scifb2: serial@e6ce0000 {
94f1a03d
SH		 393 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
394 reg = <0 0xe6ce0000 0 0x100>;
4d5746a3 395 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 396 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
d4be2f1b 397 clock-names = "fck";
7b9ad9a0 398 power-domains = <&pd_a3sp>;
94f1a03d
SH		 399 status = "disabled";
400 };
401
0b3a0ef6 402 scifb3: serial@e6cf0000 {
94f1a03d
SH		 403 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
404 reg = <0 0xe6cf0000 0 0x100>;
4d5746a3 405 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 406 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
d4be2f1b 407 clock-names = "fck";
7b9ad9a0 408 power-domains = <&pd_c4>;
eda3a4fa 409 status = "disabled";
f98c1069 410 };
369ee2db 411
43304a5f 412 sdhi0: sd@ee100000 {
df1d0584 413 compatible = "renesas,sdhi-r8a73a4";
369ee2db 414 reg = <0 0xee100000 0 0x100>;
4d5746a3 415 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 416 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
7b9ad9a0 417 power-domains = <&pd_a3sp>;
369ee2db
GL		 418 cap-sd-highspeed;
419 status = "disabled";
420 };
421
43304a5f 422 sdhi1: sd@ee120000 {
df1d0584 423 compatible = "renesas,sdhi-r8a73a4";
369ee2db 424 reg = <0 0xee120000 0 0x100>;
4d5746a3 425 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 426 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
7b9ad9a0 427 power-domains = <&pd_a3sp>;
369ee2db
GL		 428 cap-sd-highspeed;
429 status = "disabled";
430 };
431
43304a5f 432 sdhi2: sd@ee140000 {
df1d0584 433 compatible = "renesas,sdhi-r8a73a4";
369ee2db 434 reg = <0 0xee140000 0 0x100>;
4d5746a3 435 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 436 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
7b9ad9a0 437 power-domains = <&pd_a3sp>;
369ee2db
GL		 438 cap-sd-highspeed;
439 status = "disabled";
440 };
7300505a
UH		 441
442 mmcif0: mmc@ee200000 {
5b016174 443 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
7300505a 444 reg = <0 0xee200000 0 0x80>;
4d5746a3 445 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 446 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
7b9ad9a0 447 power-domains = <&pd_a3sp>;
7300505a
UH		 448 reg-io-width = <4>;
449 status = "disabled";
450 };
451
452 mmcif1: mmc@ee220000 {
5b016174 453 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
7300505a 454 reg = <0 0xee220000 0 0x80>;
4d5746a3 455 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 456 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
7b9ad9a0 457 power-domains = <&pd_a3sp>;
7300505a
UH		 458 reg-io-width = <4>;
459 status = "disabled";
460 };
461
462 gic: interrupt-controller@f1001000 {
eaec1d67 463 compatible = "arm,gic-400";
7300505a
UH		 464 #interrupt-cells = <3>;
465 #address-cells = <0>;
466 interrupt-controller;
467 reg = <0 0xf1001000 0 0x1000>,
387720c9 468 <0 0xf1002000 0 0x2000>,
7300505a
UH		 469 <0 0xf1004000 0 0x2000>,
470 <0 0xf1006000 0 0x2000>;
45e75c42 471 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
c11333cc
GU		 472 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
473 clock-names = "clk";
474 power-domains = <&pd_c4>;
7300505a 475 };
a76809a3 476
271b3ad2
GU		 477 bsc: bus@fec10000 {
478 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
479 "simple-pm-bus";
480 #address-cells = <1>;
481 #size-cells = <1>;
482 ranges = <0 0 0 0x20000000>;
483 reg = <0 0xfec10000 0 0x400>;
484 clocks = <&zb_clk>;
7b9ad9a0 485 power-domains = <&pd_c4>;
271b3ad2
GU		 486 };
487
a76809a3
UH		 488 clocks {
489 #address-cells = <2>;
490 #size-cells = <2>;
491 ranges;
492
493 /* External root clocks */
57c75d1e 494 extalr_clk: extalr {
a76809a3
UH		 495 compatible = "fixed-clock";
496 #clock-cells = <0>;
497 clock-frequency = <32768>;
a76809a3 498 };
57c75d1e 499 extal1_clk: extal1 {
a76809a3
UH		 500 compatible = "fixed-clock";
501 #clock-cells = <0>;
502 clock-frequency = <25000000>;
a76809a3 503 };
57c75d1e 504 extal2_clk: extal2 {
a76809a3
UH		 505 compatible = "fixed-clock";
506 #clock-cells = <0>;
507 clock-frequency = <48000000>;
a76809a3 508 };
57c75d1e 509 fsiack_clk: fsiack {
a76809a3
UH		 510 compatible = "fixed-clock";
511 #clock-cells = <0>;
512 /* This value must be overridden by the board. */
513 clock-frequency = <0>;
a76809a3 514 };
57c75d1e 515 fsibck_clk: fsibck {
a76809a3
UH		 516 compatible = "fixed-clock";
517 #clock-cells = <0>;
518 /* This value must be overridden by the board. */
519 clock-frequency = <0>;
a76809a3
UH		 520 };
521
522 /* Special CPG clocks */
523 cpg_clocks: cpg_clocks@e6150000 {
524 compatible = "renesas,r8a73a4-cpg-clocks";
525 reg = <0 0xe6150000 0 0x10000>;
526 clocks = <&extal1_clk>, <&extal2_clk>;
527 #clock-cells = <1>;
528 clock-output-names = "main", "pll0", "pll1", "pll2",
529 "pll2s", "pll2h", "z", "z2",
530 "i", "m3", "b", "m1", "m2",
531 "zx", "zs", "hp";
532 };
533
534 /* Variable factor clocks (DIV6) */
535 zb_clk: zb_clk@e6150010 {
536 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
537 reg = <0 0xe6150010 0 4>;
538 clocks = <&pll1_div2_clk>, <0>,
539 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
540 #clock-cells = <0>;
541 clock-output-names = "zb";
542 };
57c75d1e 543 sdhi0_clk: sdhi0ck@e6150074 {
a76809a3
UH		 544 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
545 reg = <0 0xe6150074 0 4>;
546 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
547 <0>, <&extal2_clk>;
548 #clock-cells = <0>;
a76809a3 549 };
57c75d1e 550 sdhi1_clk: sdhi1ck@e6150078 {
a76809a3
UH		 551 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
552 reg = <0 0xe6150078 0 4>;
553 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
554 <0>, <&extal2_clk>;
555 #clock-cells = <0>;
a76809a3 556 };
57c75d1e 557 sdhi2_clk: sdhi2ck@e615007c {
a76809a3
UH		 558 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
559 reg = <0 0xe615007c 0 4>;
560 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
561 <0>, <&extal2_clk>;
562 #clock-cells = <0>;
a76809a3 563 };
57c75d1e 564 mmc0_clk: mmc0@e6150240 {
a76809a3
UH		 565 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
566 reg = <0 0xe6150240 0 4>;
567 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
568 <0>, <&extal2_clk>;
569 #clock-cells = <0>;
a76809a3 570 };
57c75d1e 571 mmc1_clk: mmc1@e6150244 {
a76809a3
UH		 572 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
573 reg = <0 0xe6150244 0 4>;
574 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
575 <0>, <&extal2_clk>;
576 #clock-cells = <0>;
a76809a3 577 };
57c75d1e 578 vclk1_clk: vclk1@e6150008 {
a76809a3
UH		 579 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
580 reg = <0 0xe6150008 0 4>;
581 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
582 <0>, <&extal2_clk>, <&main_div2_clk>,
583 <&extalr_clk>, <0>, <0>;
584 #clock-cells = <0>;
a76809a3 585 };
57c75d1e 586 vclk2_clk: vclk2@e615000c {
a76809a3
UH		 587 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
588 reg = <0 0xe615000c 0 4>;
589 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
590 <0>, <&extal2_clk>, <&main_div2_clk>,
591 <&extalr_clk>, <0>, <0>;
592 #clock-cells = <0>;
a76809a3 593 };
57c75d1e 594 vclk3_clk: vclk3@e615001c {
a76809a3
UH		 595 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
596 reg = <0 0xe615001c 0 4>;
597 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
598 <0>, <&extal2_clk>, <&main_div2_clk>,
599 <&extalr_clk>, <0>, <0>;
600 #clock-cells = <0>;
a76809a3 601 };
57c75d1e 602 vclk4_clk: vclk4@e6150014 {
a76809a3
UH		 603 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
604 reg = <0 0xe6150014 0 4>;
605 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
606 <0>, <&extal2_clk>, <&main_div2_clk>,
607 <&extalr_clk>, <0>, <0>;
608 #clock-cells = <0>;
a76809a3 609 };
57c75d1e 610 vclk5_clk: vclk5@e6150034 {
a76809a3
UH		 611 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
612 reg = <0 0xe6150034 0 4>;
613 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
614 <0>, <&extal2_clk>, <&main_div2_clk>,
615 <&extalr_clk>, <0>, <0>;
616 #clock-cells = <0>;
a76809a3 617 };
57c75d1e 618 fsia_clk: fsia@e6150018 {
a76809a3
UH		 619 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
620 reg = <0 0xe6150018 0 4>;
621 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
622 <&fsiack_clk>, <0>;
623 #clock-cells = <0>;
a76809a3 624 };
57c75d1e 625 fsib_clk: fsib@e6150090 {
a76809a3
UH		 626 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
627 reg = <0 0xe6150090 0 4>;
628 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
629 <&fsibck_clk>, <0>;
630 #clock-cells = <0>;
a76809a3 631 };
57c75d1e 632 mp_clk: mp@e6150080 {
a76809a3
UH		 633 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
634 reg = <0 0xe6150080 0 4>;
635 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
636 <&extal2_clk>, <&extal2_clk>;
637 #clock-cells = <0>;
a76809a3 638 };
57c75d1e 639 m4_clk: m4@e6150098 {
a76809a3
UH		 640 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
641 reg = <0 0xe6150098 0 4>;
642 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
643 #clock-cells = <0>;
a76809a3 644 };
57c75d1e 645 hsi_clk: hsi@e615026c {
a76809a3
UH		 646 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
647 reg = <0 0xe615026c 0 4>;
648 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
649 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
650 #clock-cells = <0>;
a76809a3 651 };
57c75d1e 652 spuv_clk: spuv@e6150094 {
a76809a3
UH		 653 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
654 reg = <0 0xe6150094 0 4>;
655 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
656 <&extal2_clk>, <&extal2_clk>;
657 #clock-cells = <0>;
a76809a3
UH		 658 };
659
660 /* Fixed factor clocks */
57c75d1e 661 main_div2_clk: main_div2 {
a76809a3
UH		 662 compatible = "fixed-factor-clock";
663 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
664 #clock-cells = <0>;
665 clock-div = <2>;
666 clock-mult = <1>;
a76809a3 667 };
57c75d1e 668 pll0_div2_clk: pll0_div2 {
a76809a3
UH		 669 compatible = "fixed-factor-clock";
670 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
671 #clock-cells = <0>;
672 clock-div = <2>;
673 clock-mult = <1>;
a76809a3 674 };
57c75d1e 675 pll1_div2_clk: pll1_div2 {
a76809a3
UH		 676 compatible = "fixed-factor-clock";
677 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
678 #clock-cells = <0>;
679 clock-div = <2>;
680 clock-mult = <1>;
a76809a3 681 };
57c75d1e 682 extal1_div2_clk: extal1_div2 {
a76809a3
UH		 683 compatible = "fixed-factor-clock";
684 clocks = <&extal1_clk>;
685 #clock-cells = <0>;
686 clock-div = <2>;
687 clock-mult = <1>;
a76809a3
UH		 688 };
689
690 /* Gate clocks */
691 mstp2_clks: mstp2_clks@e6150138 {
692 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
693 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
694 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
695 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
696 #clock-cells = <1>;
697 clock-indices = <
698 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
699 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
700 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
701 R8A73A4_CLK_DMAC
702 >;
703 clock-output-names =
704 "scifa0", "scifa1", "scifb0", "scifb1",
705 "scifb2", "scifb3", "dmac";
706 };
707 mstp3_clks: mstp3_clks@e615013c {
708 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
709 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
710 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
711 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
712 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
713 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
714 R8A73A4_CLK_HP>, <&cpg_clocks
715 R8A73A4_CLK_HP>, <&extalr_clk>;
716 #clock-cells = <1>;
717 clock-indices = <
718 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
719 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
720 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
721 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
722 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
723 R8A73A4_CLK_CMT1
724 >;
725 clock-output-names =
726 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
727 "mmcif0", "iic6", "iic7", "iic0", "iic1",
728 "cmt1";
729 };
730 mstp4_clks: mstp4_clks@e6150140 {
731 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
732 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
c11333cc
GU		 733 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
734 <&main_div2_clk>,
1c2a7eb7 735 <&cpg_clocks R8A73A4_CLK_HP>,
a76809a3
UH		 736 <&cpg_clocks R8A73A4_CLK_HP>;
737 #clock-cells = <1>;
738 clock-indices = <
c11333cc
GU		 739 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
740 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
741 R8A73A4_CLK_IIC3
a76809a3
UH		 742 >;
743 clock-output-names =
c11333cc 744 "irqc", "intc-sys", "iic5", "iic4", "iic3";
a76809a3
UH		 745 };
746 mstp5_clks: mstp5_clks@e6150144 {
747 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
748 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
749 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
750 #clock-cells = <1>;
751 clock-indices = <
752 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
753 >;
754 clock-output-names =
755 "thermal", "iic8";
756 };
757 };
7b9ad9a0 758
f0270332
GU		 759 prr: chipid@ff000044 {
760 compatible = "renesas,prr";
761 reg = <0 0xff000044 0 4>;
762 };
763
7b9ad9a0
GU		 764 sysc: system-controller@e6180000 {
765 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
766 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
767
768 pm-domains {
769 pd_c5: c5 {
770 #address-cells = <1>;
771 #size-cells = <0>;
772 #power-domain-cells = <0>;
773
774 pd_c4: c4@0 {
775 reg = <0>;
776 #address-cells = <1>;
777 #size-cells = <0>;
778 #power-domain-cells = <0>;
779
780 pd_a3sg: a3sg@16 {
781 reg = <16>;
782 #power-domain-cells = <0>;
783 };
784
785 pd_a3ex: a3ex@17 {
786 reg = <17>;
787 #power-domain-cells = <0>;
788 };
789
790 pd_a3sp: a3sp@18 {
791 reg = <18>;
792 #address-cells = <1>;
793 #size-cells = <0>;
794 #power-domain-cells = <0>;
795
796 pd_a2us: a2us@19 {
797 reg = <19>;
798 #power-domain-cells = <0>;
799 };
800 };
801
802 pd_a3sm: a3sm@20 {
803 reg = <20>;
804 #address-cells = <1>;
805 #size-cells = <0>;
806 #power-domain-cells = <0>;
807
808 pd_a2sl: a2sl@21 {
809 reg = <21>;
810 #power-domain-cells = <0>;
811 };
812 };
813
814 pd_a3km: a3km@22 {
815 reg = <22>;
816 #address-cells = <1>;
817 #size-cells = <0>;
818 #power-domain-cells = <0>;
819
820 pd_a2kl: a2kl@23 {
821 reg = <23>;
822 #power-domain-cells = <0>;
823 };
824 };
825 };
826
827 pd_c4ma: c4ma@1 {
828 reg = <1>;
829 #power-domain-cells = <0>;
830 };
831
832 pd_c4cl: c4cl@2 {
833 reg = <2>;
834 #power-domain-cells = <0>;
835 };
836
837 pd_d4: d4@3 {
838 reg = <3>;
839 #power-domain-cells = <0>;
840 };
841
842 pd_a4bc: a4bc@4 {
843 reg = <4>;
844 #address-cells = <1>;
845 #size-cells = <0>;
846 #power-domain-cells = <0>;
847
848 pd_a3bc: a3bc@5 {
849 reg = <5>;
850 #power-domain-cells = <0>;
851 };
852 };
853
854 pd_a4l: a4l@6 {
855 reg = <6>;
856 #power-domain-cells = <0>;
857 };
858
859 pd_a4lc: a4lc@7 {
860 reg = <7>;
861 #power-domain-cells = <0>;
862 };
863
864 pd_a4mp: a4mp@8 {
865 reg = <8>;
866 #address-cells = <1>;
867 #size-cells = <0>;
868 #power-domain-cells = <0>;
869
870 pd_a3mp: a3mp@9 {
871 reg = <9>;
872 #power-domain-cells = <0>;
873 };
874
875 pd_a3vc: a3vc@10 {
876 reg = <10>;
877 #power-domain-cells = <0>;
878 };
879 };
880
881 pd_a4sf: a4sf@11 {
882 reg = <11>;
883 #power-domain-cells = <0>;
884 };
885
886 pd_a3r: a3r@12 {
887 reg = <12>;
888 #address-cells = <1>;
889 #size-cells = <0>;
890 #power-domain-cells = <0>;
891
892 pd_a2rv: a2rv@13 {
893 reg = <13>;
894 #power-domain-cells = <0>;
895 };
896
897 pd_a2is: a2is@14 {
898 reg = <14>;
899 #power-domain-cells = <0>;
900 };
901 };
902 };
903 };
904 };
eccf0607 905};
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