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fce152a6 | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
f75efdd7 HS |
2 | /* |
3 | * Copyright (c) 2013 MundoReader S.L. | |
4 | * Author: Heiko Stuebner <heiko@sntech.de> | |
f75efdd7 HS |
5 | */ |
6 | ||
7 | #include <dt-bindings/interrupt-controller/irq.h> | |
8 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
b60ab70b | 9 | #include <dt-bindings/soc/rockchip,boot-mode.h> |
f75efdd7 HS |
10 | |
11 | / { | |
80f6defc JMC |
12 | #address-cells = <1>; |
13 | #size-cells = <1>; | |
14 | ||
f75efdd7 HS |
15 | interrupt-parent = <&gic>; |
16 | ||
9cdffd8c | 17 | aliases { |
b3e4b953 | 18 | ethernet0 = &emac; |
9cdffd8c HS |
19 | i2c0 = &i2c0; |
20 | i2c1 = &i2c1; | |
21 | i2c2 = &i2c2; | |
22 | i2c3 = &i2c3; | |
23 | i2c4 = &i2c4; | |
4ff4ae12 HS |
24 | mshc0 = &emmc; |
25 | mshc1 = &mmc0; | |
26 | mshc2 = &mmc1; | |
e5b0deda JC |
27 | serial0 = &uart0; |
28 | serial1 = &uart1; | |
29 | serial2 = &uart2; | |
30 | serial3 = &uart3; | |
39c2bd78 HS |
31 | spi0 = &spi0; |
32 | spi1 = &spi1; | |
9cdffd8c HS |
33 | }; |
34 | ||
0c1cb8b0 | 35 | amba: bus { |
2ef7d5f3 | 36 | compatible = "simple-bus"; |
ac42f481 HS |
37 | #address-cells = <1>; |
38 | #size-cells = <1>; | |
39 | ranges; | |
40 | ||
41 | dmac1_s: dma-controller@20018000 { | |
42 | compatible = "arm,pl330", "arm,primecell"; | |
43 | reg = <0x20018000 0x4000>; | |
44 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
45 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
46 | #dma-cells = <1>; | |
9bed8b41 | 47 | arm,pl330-broken-no-flushp; |
ac42f481 HS |
48 | clocks = <&cru ACLK_DMA1>; |
49 | clock-names = "apb_pclk"; | |
50 | }; | |
51 | ||
52 | dmac1_ns: dma-controller@2001c000 { | |
53 | compatible = "arm,pl330", "arm,primecell"; | |
54 | reg = <0x2001c000 0x4000>; | |
55 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
56 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
57 | #dma-cells = <1>; | |
9bed8b41 | 58 | arm,pl330-broken-no-flushp; |
ac42f481 HS |
59 | clocks = <&cru ACLK_DMA1>; |
60 | clock-names = "apb_pclk"; | |
61 | status = "disabled"; | |
62 | }; | |
63 | ||
64 | dmac2: dma-controller@20078000 { | |
65 | compatible = "arm,pl330", "arm,primecell"; | |
66 | reg = <0x20078000 0x4000>; | |
67 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
68 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
69 | #dma-cells = <1>; | |
9bed8b41 | 70 | arm,pl330-broken-no-flushp; |
ac42f481 HS |
71 | clocks = <&cru ACLK_DMA2>; |
72 | clock-names = "apb_pclk"; | |
73 | }; | |
74 | }; | |
75 | ||
560106c1 HS |
76 | xin24m: oscillator { |
77 | compatible = "fixed-clock"; | |
78 | clock-frequency = <24000000>; | |
79 | #clock-cells = <0>; | |
80 | clock-output-names = "xin24m"; | |
81 | }; | |
82 | ||
4fcac83b HS |
83 | gpu: gpu@10090000 { |
84 | compatible = "arm,mali-400"; | |
85 | reg = <0x10090000 0x10000>; | |
86 | clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; | |
b14f3898 | 87 | clock-names = "bus", "core"; |
4fcac83b HS |
88 | assigned-clocks = <&cru ACLK_GPU>; |
89 | assigned-clock-rates = <100000000>; | |
90 | resets = <&cru SRST_GPU>; | |
91 | status = "disabled"; | |
92 | }; | |
93 | ||
c0044dc7 | 94 | L2: cache-controller@10138000 { |
c3030d30 HS |
95 | compatible = "arm,pl310-cache"; |
96 | reg = <0x10138000 0x1000>; | |
97 | cache-unified; | |
98 | cache-level = <2>; | |
99 | }; | |
100 | ||
ff84b90e HS |
101 | scu@1013c000 { |
102 | compatible = "arm,cortex-a9-scu"; | |
103 | reg = <0x1013c000 0x100>; | |
104 | }; | |
105 | ||
e40b43d6 | 106 | global_timer: global-timer@1013c200 { |
c3030d30 HS |
107 | compatible = "arm,cortex-a9-global-timer"; |
108 | reg = <0x1013c200 0x20>; | |
2e1aa605 | 109 | interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; |
c3030d30 HS |
110 | clocks = <&cru CORE_PERI>; |
111 | }; | |
112 | ||
e40b43d6 | 113 | local_timer: local-timer@1013c600 { |
c3030d30 HS |
114 | compatible = "arm,cortex-a9-twd-timer"; |
115 | reg = <0x1013c600 0x20>; | |
2e1aa605 | 116 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; |
c3030d30 HS |
117 | clocks = <&cru CORE_PERI>; |
118 | }; | |
119 | ||
ff84b90e HS |
120 | gic: interrupt-controller@1013d000 { |
121 | compatible = "arm,cortex-a9-gic"; | |
122 | interrupt-controller; | |
123 | #interrupt-cells = <3>; | |
124 | reg = <0x1013d000 0x1000>, | |
125 | <0x1013c100 0x0100>; | |
126 | }; | |
127 | ||
c3030d30 HS |
128 | uart0: serial@10124000 { |
129 | compatible = "snps,dw-apb-uart"; | |
130 | reg = <0x10124000 0x400>; | |
131 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
132 | reg-shift = <2>; | |
133 | reg-io-width = <1>; | |
69667ca2 HS |
134 | clock-names = "baudclk", "apb_pclk"; |
135 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
c3030d30 HS |
136 | status = "disabled"; |
137 | }; | |
138 | ||
139 | uart1: serial@10126000 { | |
140 | compatible = "snps,dw-apb-uart"; | |
141 | reg = <0x10126000 0x400>; | |
142 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
143 | reg-shift = <2>; | |
144 | reg-io-width = <1>; | |
69667ca2 HS |
145 | clock-names = "baudclk", "apb_pclk"; |
146 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
c3030d30 HS |
147 | status = "disabled"; |
148 | }; | |
149 | ||
3e712a03 HS |
150 | qos_gpu: qos@1012d000 { |
151 | compatible = "syscon"; | |
152 | reg = <0x1012d000 0x20>; | |
153 | }; | |
154 | ||
155 | qos_vpu: qos@1012e000 { | |
156 | compatible = "syscon"; | |
157 | reg = <0x1012e000 0x20>; | |
158 | }; | |
159 | ||
160 | qos_lcdc0: qos@1012f000 { | |
161 | compatible = "syscon"; | |
162 | reg = <0x1012f000 0x20>; | |
163 | }; | |
164 | ||
165 | qos_cif0: qos@1012f080 { | |
166 | compatible = "syscon"; | |
167 | reg = <0x1012f080 0x20>; | |
168 | }; | |
169 | ||
170 | qos_ipp: qos@1012f100 { | |
171 | compatible = "syscon"; | |
172 | reg = <0x1012f100 0x20>; | |
173 | }; | |
174 | ||
175 | qos_lcdc1: qos@1012f180 { | |
176 | compatible = "syscon"; | |
177 | reg = <0x1012f180 0x20>; | |
178 | }; | |
179 | ||
180 | qos_cif1: qos@1012f200 { | |
181 | compatible = "syscon"; | |
182 | reg = <0x1012f200 0x20>; | |
183 | }; | |
184 | ||
185 | qos_rga: qos@1012f280 { | |
186 | compatible = "syscon"; | |
187 | reg = <0x1012f280 0x20>; | |
188 | }; | |
189 | ||
fd14e6f9 HS |
190 | usb_otg: usb@10180000 { |
191 | compatible = "rockchip,rk3066-usb", "snps,dwc2"; | |
192 | reg = <0x10180000 0x40000>; | |
193 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
194 | clocks = <&cru HCLK_OTG0>; | |
195 | clock-names = "otg"; | |
ec32bd9f HS |
196 | dr_mode = "otg"; |
197 | g-np-tx-fifo-size = <16>; | |
198 | g-rx-fifo-size = <275>; | |
199 | g-tx-fifo-size = <256 128 128 64 64 32>; | |
760bb977 HS |
200 | phys = <&usbphy0>; |
201 | phy-names = "usb2-phy"; | |
fd14e6f9 HS |
202 | status = "disabled"; |
203 | }; | |
204 | ||
205 | usb_host: usb@101c0000 { | |
206 | compatible = "snps,dwc2"; | |
207 | reg = <0x101c0000 0x40000>; | |
208 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
209 | clocks = <&cru HCLK_OTG1>; | |
210 | clock-names = "otg"; | |
ec32bd9f | 211 | dr_mode = "host"; |
760bb977 HS |
212 | phys = <&usbphy1>; |
213 | phy-names = "usb2-phy"; | |
fd14e6f9 HS |
214 | status = "disabled"; |
215 | }; | |
216 | ||
18ec91e1 RP |
217 | emac: ethernet@10204000 { |
218 | compatible = "snps,arc-emac"; | |
219 | reg = <0x10204000 0x3c>; | |
220 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
221 | #address-cells = <1>; | |
222 | #size-cells = <0>; | |
223 | ||
224 | rockchip,grf = <&grf>; | |
225 | ||
226 | clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; | |
227 | clock-names = "hclk", "macref"; | |
228 | max-speed = <100>; | |
229 | phy-mode = "rmii"; | |
230 | ||
231 | status = "disabled"; | |
232 | }; | |
233 | ||
fed1fc51 | 234 | mmc0: mmc@10214000 { |
c3030d30 HS |
235 | compatible = "rockchip,rk2928-dw-mshc"; |
236 | reg = <0x10214000 0x1000>; | |
237 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
c3030d30 HS |
238 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; |
239 | clock-names = "biu", "ciu"; | |
94bbdd77 AK |
240 | dmas = <&dmac2 1>; |
241 | dma-names = "rx-tx"; | |
4c1e3ff7 | 242 | fifo-depth = <256>; |
ee0024fd HS |
243 | resets = <&cru SRST_SDMMC>; |
244 | reset-names = "reset"; | |
c3030d30 HS |
245 | status = "disabled"; |
246 | }; | |
247 | ||
fed1fc51 | 248 | mmc1: mmc@10218000 { |
c3030d30 HS |
249 | compatible = "rockchip,rk2928-dw-mshc"; |
250 | reg = <0x10218000 0x1000>; | |
251 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
c3030d30 HS |
252 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; |
253 | clock-names = "biu", "ciu"; | |
94bbdd77 AK |
254 | dmas = <&dmac2 3>; |
255 | dma-names = "rx-tx"; | |
4c1e3ff7 | 256 | fifo-depth = <256>; |
ee0024fd HS |
257 | resets = <&cru SRST_SDIO>; |
258 | reset-names = "reset"; | |
c3030d30 | 259 | status = "disabled"; |
f75efdd7 | 260 | }; |
ff84b90e | 261 | |
fed1fc51 | 262 | emmc: mmc@1021c000 { |
4ff4ae12 HS |
263 | compatible = "rockchip,rk2928-dw-mshc"; |
264 | reg = <0x1021c000 0x1000>; | |
265 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
4ff4ae12 HS |
266 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; |
267 | clock-names = "biu", "ciu"; | |
94bbdd77 AK |
268 | dmas = <&dmac2 4>; |
269 | dma-names = "rx-tx"; | |
4c1e3ff7 | 270 | fifo-depth = <256>; |
ee0024fd HS |
271 | resets = <&cru SRST_EMMC>; |
272 | reset-names = "reset"; | |
4ff4ae12 HS |
273 | status = "disabled"; |
274 | }; | |
275 | ||
ff84b90e | 276 | pmu: pmu@20004000 { |
b60ab70b | 277 | compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; |
ff84b90e | 278 | reg = <0x20004000 0x100>; |
b60ab70b AY |
279 | |
280 | reboot-mode { | |
281 | compatible = "syscon-reboot-mode"; | |
282 | offset = <0x40>; | |
283 | mode-normal = <BOOT_NORMAL>; | |
284 | mode-recovery = <BOOT_RECOVERY>; | |
285 | mode-bootloader = <BOOT_FASTBOOT>; | |
286 | mode-loader = <BOOT_BL_DOWNLOAD>; | |
287 | }; | |
ff84b90e HS |
288 | }; |
289 | ||
290 | grf: grf@20008000 { | |
291 | compatible = "syscon"; | |
292 | reg = <0x20008000 0x200>; | |
293 | }; | |
294 | ||
9cdffd8c HS |
295 | i2c0: i2c@2002d000 { |
296 | compatible = "rockchip,rk3066-i2c"; | |
297 | reg = <0x2002d000 0x1000>; | |
298 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
299 | #address-cells = <1>; | |
300 | #size-cells = <0>; | |
301 | ||
302 | rockchip,grf = <&grf>; | |
9cdffd8c HS |
303 | |
304 | clock-names = "i2c"; | |
305 | clocks = <&cru PCLK_I2C0>; | |
306 | ||
307 | status = "disabled"; | |
308 | }; | |
309 | ||
310 | i2c1: i2c@2002f000 { | |
311 | compatible = "rockchip,rk3066-i2c"; | |
312 | reg = <0x2002f000 0x1000>; | |
313 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
314 | #address-cells = <1>; | |
315 | #size-cells = <0>; | |
316 | ||
317 | rockchip,grf = <&grf>; | |
318 | ||
319 | clocks = <&cru PCLK_I2C1>; | |
320 | clock-names = "i2c"; | |
321 | ||
322 | status = "disabled"; | |
323 | }; | |
324 | ||
550c7f4e BG |
325 | pwm0: pwm@20030000 { |
326 | compatible = "rockchip,rk2928-pwm"; | |
327 | reg = <0x20030000 0x10>; | |
328 | #pwm-cells = <2>; | |
329 | clocks = <&cru PCLK_PWM01>; | |
330 | status = "disabled"; | |
331 | }; | |
332 | ||
333 | pwm1: pwm@20030010 { | |
334 | compatible = "rockchip,rk2928-pwm"; | |
335 | reg = <0x20030010 0x10>; | |
336 | #pwm-cells = <2>; | |
337 | clocks = <&cru PCLK_PWM01>; | |
338 | status = "disabled"; | |
339 | }; | |
340 | ||
eb2b9d47 HS |
341 | wdt: watchdog@2004c000 { |
342 | compatible = "snps,dw-wdt"; | |
343 | reg = <0x2004c000 0x100>; | |
344 | clocks = <&cru PCLK_WDT>; | |
345 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
346 | status = "disabled"; | |
347 | }; | |
348 | ||
550c7f4e BG |
349 | pwm2: pwm@20050020 { |
350 | compatible = "rockchip,rk2928-pwm"; | |
351 | reg = <0x20050020 0x10>; | |
352 | #pwm-cells = <2>; | |
353 | clocks = <&cru PCLK_PWM23>; | |
354 | status = "disabled"; | |
355 | }; | |
356 | ||
357 | pwm3: pwm@20050030 { | |
358 | compatible = "rockchip,rk2928-pwm"; | |
359 | reg = <0x20050030 0x10>; | |
360 | #pwm-cells = <2>; | |
361 | clocks = <&cru PCLK_PWM23>; | |
362 | status = "disabled"; | |
363 | }; | |
364 | ||
9cdffd8c HS |
365 | i2c2: i2c@20056000 { |
366 | compatible = "rockchip,rk3066-i2c"; | |
367 | reg = <0x20056000 0x1000>; | |
368 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
369 | #address-cells = <1>; | |
370 | #size-cells = <0>; | |
371 | ||
372 | rockchip,grf = <&grf>; | |
373 | ||
374 | clocks = <&cru PCLK_I2C2>; | |
375 | clock-names = "i2c"; | |
376 | ||
377 | status = "disabled"; | |
378 | }; | |
379 | ||
380 | i2c3: i2c@2005a000 { | |
381 | compatible = "rockchip,rk3066-i2c"; | |
382 | reg = <0x2005a000 0x1000>; | |
383 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
384 | #address-cells = <1>; | |
385 | #size-cells = <0>; | |
386 | ||
387 | rockchip,grf = <&grf>; | |
388 | ||
389 | clocks = <&cru PCLK_I2C3>; | |
390 | clock-names = "i2c"; | |
391 | ||
392 | status = "disabled"; | |
393 | }; | |
394 | ||
395 | i2c4: i2c@2005e000 { | |
396 | compatible = "rockchip,rk3066-i2c"; | |
397 | reg = <0x2005e000 0x1000>; | |
398 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
399 | #address-cells = <1>; | |
400 | #size-cells = <0>; | |
401 | ||
402 | rockchip,grf = <&grf>; | |
403 | ||
404 | clocks = <&cru PCLK_I2C4>; | |
405 | clock-names = "i2c"; | |
406 | ||
407 | status = "disabled"; | |
408 | }; | |
409 | ||
ff84b90e HS |
410 | uart2: serial@20064000 { |
411 | compatible = "snps,dw-apb-uart"; | |
412 | reg = <0x20064000 0x400>; | |
413 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
414 | reg-shift = <2>; | |
415 | reg-io-width = <1>; | |
69667ca2 HS |
416 | clock-names = "baudclk", "apb_pclk"; |
417 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
ff84b90e HS |
418 | status = "disabled"; |
419 | }; | |
420 | ||
421 | uart3: serial@20068000 { | |
422 | compatible = "snps,dw-apb-uart"; | |
423 | reg = <0x20068000 0x400>; | |
424 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
425 | reg-shift = <2>; | |
426 | reg-io-width = <1>; | |
69667ca2 HS |
427 | clock-names = "baudclk", "apb_pclk"; |
428 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
ff84b90e HS |
429 | status = "disabled"; |
430 | }; | |
f23a6179 HS |
431 | |
432 | saradc: saradc@2006c000 { | |
433 | compatible = "rockchip,saradc"; | |
434 | reg = <0x2006c000 0x100>; | |
435 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
436 | #io-channel-cells = <1>; | |
437 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | |
438 | clock-names = "saradc", "apb_pclk"; | |
3d4267a5 CW |
439 | resets = <&cru SRST_SARADC>; |
440 | reset-names = "saradc-apb"; | |
f23a6179 HS |
441 | status = "disabled"; |
442 | }; | |
39c2bd78 HS |
443 | |
444 | spi0: spi@20070000 { | |
445 | compatible = "rockchip,rk3066-spi"; | |
446 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
447 | clock-names = "spiclk", "apb_pclk"; | |
448 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
449 | reg = <0x20070000 0x1000>; | |
450 | #address-cells = <1>; | |
451 | #size-cells = <0>; | |
b3e3a7b2 JC |
452 | dmas = <&dmac2 10>, <&dmac2 11>; |
453 | dma-names = "tx", "rx"; | |
39c2bd78 HS |
454 | status = "disabled"; |
455 | }; | |
456 | ||
457 | spi1: spi@20074000 { | |
458 | compatible = "rockchip,rk3066-spi"; | |
459 | clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; | |
460 | clock-names = "spiclk", "apb_pclk"; | |
461 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
462 | reg = <0x20074000 0x1000>; | |
463 | #address-cells = <1>; | |
464 | #size-cells = <0>; | |
b3e3a7b2 JC |
465 | dmas = <&dmac2 12>, <&dmac2 13>; |
466 | dma-names = "tx", "rx"; | |
39c2bd78 HS |
467 | status = "disabled"; |
468 | }; | |
f75efdd7 | 469 | }; |